Low-voltage ESD protection device adopting SELBOX structure and implementation method of low-voltage ESD protection device

Abstract

The invention discloses a low-voltage ESD protection device adopting an SELBOX structure and an implementation method of the low-voltage ESD protection device. N + on the leftmost side and P + on the rightmost side of the protection device are highly doped active regions. The middle N + / P- / N + is an NMOS transistor, N + is highly doped, and P-is lowly doped. And the STI is an oxide layer for isolating the NMOS from the active region. And a coupling resistor is added on the NMOS. And the two N + parts on the left side and the resistor are connected to the cathode through metal. The right N + and P + are together connected to the anode. An etched oxide layer, called SELBOX, is arranged below the NMOS, and the etched region is doped with P <->. The two well regions are respectively a P-well region and an N-well region, and the P-well region and the N-well region adopt middle doping. And a P-sub substrate is adopted on the lowermost side. And carrying out P-sub low doping. According to the ESD protection device, the trigger voltage of the ESD protection device under low-voltage application can be reduced, meanwhile, the capacity of discharging current is improved, the GCCNMOS device on the buried oxide layer is used for assisting a trigger SCR, the excellent discharging current performance is achieved, and the low adjustable trigger voltage is achieved.

Description

Technical Field

[0001] The invention relates to a low-voltage ESD protection device adopting a SELBOX structure and a realization method thereof, belonging to the technical field of flexible electronics. Background Art

[0002] As the process nodes of integrated circuits shrink, traditional MOSFETs are reaching their scaling limits, and silicon-on-insulator (SOI MOSFET) devices are considered to be one of the best alternatives to traditional MOSFETs in sub-micron regions in IoT, mobile, and server technologies. However, in fully depleted silicon-on-insulator (FDSOI) technology, the low thermal conductivity of the buried oxide layer (BOX) greatly reduces its inherent ESD robustness. In addition, the ultra-thin silicon layer also limits the ability to discharge large currents.

[0003] Scholars have proposed different solutions for ESD protection of FDSOI devices. 2 -FET, FED and other devices build ESD paths in thin silicon layers through potential barrier modulation of electrons and holes, which can quickly conduct ESD current. However, the silicon volume is too small and is easily broken down by large currents. For example, although the combined devices GDNMOS and GDBIMOS are built in the lateral silicon layer, they have good integration and performance, but external configuration is required to further reduce the trigger voltage. For example, through local silicon etching technology, a thin silicon layer device is used to trigger the main SCR path under the BOX layer to discharge large currents. However, this structure needs to be further optimized to meet CDM requirements. For example, GGNMOS is used as a trigger structure to reduce the trigger voltage, but due to the etching of the STI in the source and drain regions, the static leakage current is increased to a certain extent. Summary of the invention

[0004] The purpose of the present invention is to address the defects and shortcomings of the above-mentioned prior art and propose a low-voltage ESD protection device using a SELBOX structure and a method for implementing the same, which can reduce the trigger voltage of the ESD protection device under low-voltage applications and improve the ability to discharge current. The present invention uses a GCNMOS device on a buried oxide layer to assist in triggering the body SCR, which not only has excellent discharge current performance, but also achieves a low adjustable trigger voltage.

[0005] The technical solution adopted by the present invention to solve its technical problem is: a low-voltage ESD protection device using a SELBOX structure, which is mainly aimed at electrostatic discharge protection of chips under advanced processes (28nm FDSOI process). The leftmost N+ and the rightmost P+ of the protection device are highly doped active areas. The middle N+ / P- / N+ is an NMOS transistor, in which N+ is highly doped and P- is low doped. STI is an oxide layer used to isolate NMOS and the active area. A coupling resistor is added to NMOS. The two N+ and the resistor on the left are connected to the cathode through metal. The right N+ and P+ are connected to the anode together. Below NMOS is an etched oxide layer called SELBOX, and the etched area is doped with P-. Below are two well areas, P-well and N-well, respectively, and P-well and N-well are medium doped. The bottom uses a P-sub substrate. P-sub is low doped. (N type refers to doping with phosphorus elements and P type refers to doping with boron elements).

[0006] The present invention also provides a method for implementing a low-voltage ESD protection device using a SELBOX structure. The device can be placed at the chip IO port and automatically performs ESD (electrostatic discharge) protection as a protection device. The protection device has two working modes. One is that the Anode anode is in a closed state under a normal working voltage of 0.9V to reduce unnecessary power consumption. Under normal pressure, the gate has no coupling voltage, the nmos channel is in a closed state, and at the same time, Nwell and Pwell are in reverse bias, and the anode voltage is not enough to open the discharge channel of the entire device.

[0007] Another is that electrostatic discharge occurs at the anode end, and a large current flows through the anode and flows to the cathode. The protection device is turned on. The entire conduction process is divided into the following steps:

[0008] Step 1: When an ESD event occurs, the voltage at the Anode rises rapidly. The voltage increase increases the local electric field of the N+ and P- reverse-biased junctions. The high electric field increases the carrier collision mobility in this area until avalanche breakdown occurs.

[0009] Step 2: After avalanche breakdown occurs, the holes generated by the collision move directly to the cathode through the channel, and some holes flow to the cathode through P- / Pwell / N+. This behavior increases the P-well potential and promotes the conduction of the Pwell / N+ junction.

[0010] Step 3: The continuously raised anode voltage further passes through the channel, gate capacitance, and resistor to couple a certain voltage value at the gate, which promotes the opening of NMOS. Electrons flow from the cathode through the channel to the anode. In this process, electrons also flow through the open P- through N-well / P+ to the anode anode. The process of electron flow promotes the conduction of the P+ / N-well junction.

[0011] Step 4: With the assistance of holes and electrons generated by GCNOMS, the P+ / N-well and P-well / N+ junctions on the anode and cathode sides are quickly turned on. N-well and P-well are in a reverse bias state, and the P+ / N-well / P-well transistors and N-well / pwell / N+ transistors form a positive feedback loop, resulting in a conductivity modulation effect. The on-resistance decreases rapidly, and the anode voltage decreases as the current increases, resulting in hysteresis.

[0012] Step 5: After the hysteresis reaches the lowest voltage (called the holding voltage), the on-resistance drops to the lowest. At this time, the P+ / N-well / P-well / N+ path serves as the main path for discharging the large current generated by the anode. Until the protection device reaches thermal failure, the device loses its protection function.

[0013] Beneficial effects:

[0014] 1. The present invention can reduce the trigger voltage of ESD protection devices under low voltage applications and improve the ability of discharge current. The present invention uses GCNMOS devices on the buried oxide layer to assist in triggering the body SCR, which not only has excellent discharge current performance, but also achieves a low adjustable trigger voltage.

[0015] 2. The present invention adopts the SELBOX structure to enable GCNMOS to assist in triggering the opening of the main SCR, thereby reducing the trigger voltage and increasing the discharge current. AD simulation shows that compared with the traditional structure, the trigger voltage of the present invention is as low as 2.06V, and the discharge current is increased from 0.125A to 1.84A. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the cross section of a traditional GCNMOS.

[0017] Figure 2 It is a cross-sectional schematic diagram of the SBO-GCSCR of the present invention.

[0018] Figure 3 It is the TLP IV characteristic curve diagram of the present invention.

[0019] Figure 4 This is the impact ionization density distribution diagram of the present invention.

[0020] Figure 5 This is the carrier distribution diagram of the auxiliary opening process of the present invention.

[0021] in, Figure 5 (a) is the hole injection density distribution diagram; Figure 5 (b) is the electron injection density distribution diagram.

[0022] Figure 6 This is the current density distribution diagram after the present invention is fully turned on.

[0023] Figure 7 FIG. 4 is a graph showing the I_V characteristic curves of SBO-GCSCR under different gate lengths of the present invention.

[0024] Figure 8 It is a static leakage current curve diagram under different gate lengths of the present invention.

[0025] Fig. 9 It is the IV characteristic curve diagram of the device under different opening lengths of the present invention.

[0026] Fig.10 This is a graph showing the IV characteristic curves of the device under different gate resistances of the present invention. DETAILED DESCRIPTION

[0027] The invention will be further described in detail below in conjunction with the accompanying drawings.

[0028] Traditional GCNMOS is based on FDSOI structure, forming NMOS devices on the BOX layer, and the gate is grounded through a resistor. Its cross-sectional structure is as follows Figure 1 As shown. Under normal operating voltage, the gate potential is 0, the entire channel is in a closed state, and the leakage current is low. When an ESD event occurs, the voltage is coupled to the gate through the BOX capacitor, channel capacitor, and gate resistor. Under the influence of the gate potential, the channel begins to conduct, thereby discharging current.

[0029] The present invention proposes a low-voltage ESD protection device using a SELBOX structure, the cross-sectional view of which is shown in FIG. Figure 2 As shown in the figure. This structure uses SELBOX instead of the traditional fully enclosed BOX, so that the channel contacts the Nwell. The upper layer uses GCNMOS as the trigger element. In the lower layer of SELBOX, an SCR (PNPN) with a low holding voltage is used. The substrate is doped with P type to form a reverse biased PN junction with Nwell, thereby reducing leakage current.

[0030] Under normal working conditions, the channel is in the off state because there is no coupling voltage on the gate. At the same time, the Nwell and Pwell below are in the reverse bias state, so the entire device is turned off.

[0031] When an ESD event occurs, on the one hand, the drain potential of GCNMOS rises rapidly, causing the collision of carriers in the reverse-biased junction between the N+ and channel P- regions to continue to increase, and eventually avalanche breakdown occurs. A large number of holes generated by avalanche breakdown move toward the cathode through the channel, and some of them flow to the cathode N+ on the far left through the P- / Nwell / Pwell path, thereby raising the Pwell potential and further promoting the conduction of the Pwell / N+ junction.

[0032] On the other hand, the changing drain voltage is coupled at the gate through the channel, gate capacitance and gate resistance R. When the gate voltage reaches the turn-on voltage of the MOS tube, the channel begins to conduct, and a large number of electrons move from the source N+ to the drain N+ through the channel. Due to a certain concentration difference between N+ and Nwell, a part of the electrons pass through the source N+ / P- / Nwelll parasitic path, causing the electrons to be injected downward. The injected electrons move to the anode P+ through Nwell, and this behavior promotes the conduction of the anode P+ / Nwell junction.

[0033] Under the auxiliary triggering of GCNMOS, the PN junctions on the anode and cathode sides are turned on faster, and then the P+ / Nwell / Pwell transistors and Nwell / Pwell / N+ transistors form a positive feedback loop, resulting in conductivity modulation effect and hysteresis in the device. As the ESD current increases, the device eventually forms a discharge path with GCNMOS as the auxiliary and SCR as the main.

[0034] The present invention uses TCAD simulation to analyze the design scheme. In order to simulate the physical behavior of the device under ESD stress, the physical models used include Mobility model, High Field Saturation model, Avalanche model, SRH model, Thin Layer model, Thermodynamic model, etc. The width of the device is 100 μm, and the other key structural parameters of the device are shown in Table 1.

[0035] Table 1 Key parameters of SBO-GCSCR

[0036]

[0037] The simulation experiment curves and ratios of the present invention include the following:

[0038] In order to meet the ESD protection of devices under advanced low-voltage processes, the worst ESD protection window required is 0.9V~5.1V. Considering that protection devices generally require a 10% margin, the ESD window of the present invention is set to 1V~4.5V. In order to simulate the electrostatic stress generated by the human body model, a pulse current source with a 10ns rising edge and a width of 100ns is selected as a simulation excitation and applied to the drain, while keeping the gate and source grounded. The basic parameter settings of SBO-GCSCR and GCNMOS are the same, and the final quasi-static IV curve is as follows Figure 3 shown.

[0039] It can be seen that the proposed new structure uses SCR as the main discharge path. When the SCR is fully turned on, the on-resistance is smaller than that of the narrow channel. Therefore, the maximum discharge current in the window is greatly increased from 0.125A to 1.84A compared with the traditional device. The trigger voltage of the traditional structure is about 3.65V, while the SBO-GCSCR can achieve voltage clamping at 2.06V due to the auxiliary trigger effect.

[0040] In order to verify the conduction principle of SBO-GCSCR, TCAD software was used to analyze the changes before and after the device was turned on. Figure 4 Schematic diagram of impact ionization distribution before the device is turned on. As the anode stress increases, the impact mobility of the N+ / P- reverse-biased junction increases, and when the electric field peak reaches the silicon avalanche critical value, avalanche breakdown occurs.

[0041] Figure 5 This is a simulation diagram of carrier distribution in the auxiliary turn-on process. Figure 5 (a) is the hole distribution diagram of holes injected into the main SCR after avalanche breakdown. Figure 5 (b) is the electron density distribution diagram when channel electrons are injected into Nwell through the opening.

[0042] Figure 5 In (a), holes are generated by avalanche breakdown and flow through the opening through Pwell to the cathode N+, thus opening the Pwell / N+ junction. However, the mobility and concentration of holes are low, and the auxiliary triggering is weaker than that of electrons. Figure 5 The coupled gate voltage in (b) increases the electron concentration in the channel, and a considerable number of electrons are injected into Nwell through the opening and eventually reach the anode. This behavior helps to open the P+ / Nwell junction of the anode.

[0043] Figure 6 This is the current density distribution diagram after the SBO-GCSCR device is fully turned on. At this time, it can be seen that the current is distributed in the channel and the bottom SCR path, and the main SCR plays a major role in large current discharge due to its large discharge area and low on-resistance.

[0044] The TLP characteristic curves of the device under different gate lengths are as follows: Figure 7 As shown in Figure 2. Since the SELBOX structure is used, the static leakage current of different gate lengths is also simulated, and the curve is shown in Figure 2. Figure 8 shown.

[0045] As the gate length decreases, the trigger voltage, holding voltage, and on-resistance of the device show a decreasing trend. This is because the reduction in gate length leads to a reduction in the length of the SCR base region. The same anode voltage applied to the reverse-biased Nwell / Pwell junction has a higher voltage, making the device easier to turn on. At the same time, the reduction in base length weakens base recombination, which increases the SCR gain, makes the conductivity modulation effect stronger, and reduces the holding voltage accordingly. The on-resistance (Ron) also decreases to a certain extent due to the reduction in SCR size.

[0046] Figure 8 It can be seen that the static leakage current changes greatly when the gate length is 50nm-100nm. First, the reduction of channel length reduces the channel on-resistance and increases the leakage current. Second, due to the existence of the buried oxide layer opening, the closer the channel length is to the opening length, the greater the static leakage current flowing through the opening. In order to control the leakage current to the order of -10, the gate length should be at least

[0047] The TLP IV characteristic curves of different opening lengths (Ls) are shown in Figure 2. Fig. 9 As shown in the figure. The trigger voltage of the device varies greatly when the opening length is 1-5nm. This is because the length of the opening controls the size of the SCR injection current. The larger the opening length, the faster the SCR conducts, and the device is triggered at a lower voltage. When the opening length is greater than 5nm, the injected current approaches saturation, and the effect of reducing the trigger voltage becomes worse.

[0048] By changing the gate coupling resistor (Rg), the IV characteristic curve of the device under different resistances is obtained. The trend is as follows: Fig.10 In order to control the coupling voltage to protect the gate, the maximum coupling voltage values ​​under different resistances are simulated, and the results are shown in Table 2.

[0049] Table 2 Maximum coupling voltage values ​​under different gate resistances

[0050]

[0051] It can be seen from the figure that as the resistance increases, the trigger voltage of the device decreases. When the resistance is between 1k and 10K, the gate voltage is too small and has little effect on the channel control, so the IV characteristic curves basically overlap. As the resistance continues to increase, the ability of the gate voltage to control the conduction of the channel becomes stronger. At this time, the ability to trigger the SCR through SELBOX becomes stronger, and the device is triggered at a lower voltage. As the gate voltage increases, the discharge current of the channel also increases accordingly, and the total current increases when the device reaches the trigger point. When the resistance reaches 1MΩ, the channel current is saturated, and it is difficult to continue to reduce the trigger voltage by increasing the resistance. At the same time, the increase in gate coupling voltage will also affect the gate reliability of the device.

Claims

1. A low-voltage ESD protection device using a SELBOX structure, characterized in that: The N+ on the far left and the P+ on the far right of the protection device are highly doped active areas, and the N+ / P- / N+ in the middle is an NMOS transistor, where N+ is highly doped and P- is low doped. STI is an oxide layer used to isolate NMOS and the active area. A coupling resistor is added to the NMOS. The two N+ and the resistor on the left are connected to the cathode through metal, and the N+ and P+ on the right are connected to the anode together. Below the NMOS is an etched oxide layer called SELBOX, and the etched area is doped with P-. Below are two well areas, P-well and N-well, respectively. P-well and N-well are medium doped, and the bottom uses a P-sub substrate, which is low doped (N-type refers to doping with phosphorus elements and P-type refers to doping with boron elements).

2. A method for implementing a low-voltage ESD protection device using a SELBOX structure, characterized in that: The method conduction process is as follows: The protection device can be placed at the chip IO port, and automatically performs ESD (electrostatic discharge) protection as a protection device. The protection device has two working modes. One is that when the Anode is at a normal working voltage of 0.9V, the protection device is in a closed state to reduce unnecessary power consumption. Under normal pressure, the gate has no coupling voltage, and the nmos channel is in a closed state. At the same time, Nwell and Pwell are in reverse bias. At this time, the anode voltage is not enough to open the discharge channel of the entire device. The other is when a large current is injected into the anode. The working state is divided into the following steps: Step 1: When an ESD event occurs, the voltage at the Anode rises rapidly. The voltage increase increases the local electric field of the N+ and P- reverse-biased junctions. The high electric field increases the carrier collision mobility in this area until avalanche breakdown occurs. Step 2: After avalanche breakdown occurs, the holes generated by the collision move directly to the cathode through the channel, and some holes flow to the cathode through P- / Pwell / N+. This behavior increases the P-well potential and promotes the conduction of the Pwell / N+ junction. Step 3: The continuously raised anode voltage further passes through the channel, gate capacitance, and resistance to couple a certain voltage value at the gate, which promotes the opening of NMOS. Electrons flow from the cathode through the channel to the anode. In this process, electrons also flow through the open P- through N-well / P+ to the anode anode. The process of electron flow promotes the conduction of the P+ / N-well junction. Step 4: With the assistance of holes and electrons generated by GCNOMS, the P+ / N-well and P-well / N+ junctions on the anode and cathode sides are quickly turned on, N-well and P-well themselves are in a reverse bias state, and the P+ / N-well / P-well transistors and N-well / pwell / N+ transistors form a positive feedback loop, resulting in a conductivity modulation effect, and the on-resistance decreases rapidly. The anode voltage decreases with the increase of current, and hysteresis occurs; Step 5: After the hysteresis reaches the minimum voltage (called the holding voltage), the on-resistance drops to the minimum. At this time, the P+ / N-well / P-well / N+ path serves as the main path, which is used to discharge the large current generated by the anode until the protection device reaches thermal failure and the device loses its protection function.

Images