Low-noise silicon carbide NPN phototransistor and preparation method thereof

Abstract

The low-noise silicon carbide NPN phototransistor comprises an n-type transition layer, an n + buried layer, an n-buffer layer, a p-type base region layer, an n-type current collection layer and a SiO2 oxide layer covering first isolation grooves which are arranged in the first direction, and the first isolation grooves are located on the two sides of the p-type base region layer in the second direction perpendicular to the first direction; the n + buried layers with high doping concentration are arranged at intervals in the n-type transition layer along the second direction; the n-buffer layer with low doping concentration is positioned on the upper surfaces of the n-type transition layer and the n + buried layer; the p-type base region layer is located on the upper surface of the n-buffer layer; the n-type current collection layer is located on the side, away from the n-buffer layer, in the p-type base region layer, the width of the n-type current collection layer is smaller than that of the p-type base region layer in the second direction, and the n-type current collection layer does not make contact with the SiO2 oxide layer located in the first isolation groove. According to the invention, the leakage current of the side wall can be greatly reduced, and the noise performance and the light-dark current ratio are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of photoelectric detection, and in particular relates to a low-noise silicon carbide NPN phototransistor and a preparation method thereof. Background Art

[0002] SiC materials have excellent properties such as wide bandgap, high critical breakdown electric field, high electron saturation velocity and high thermal conductivity, which makes SiC power devices very suitable for high temperature, high voltage and high power applications. For compound semiconductor materials, there is an inverse proportional relationship between the bandgap width and the cutoff wavelength for the photovoltaic effect. For the 3.27eV bandgap width of SiC, its cutoff wavelength is around 280nm. Therefore, another important application area of ​​wide bandgap semiconductors represented by SiC is ultraviolet photodetection. Compared with traditional silicon-based photodetectors, photodetectors made of SiC do not require additional filters, have very good selectivity for the ultraviolet band, and have very high detection. Compared with other wide bandgap semiconductor photoelectric materials, such as aluminum gallium nitride, the preparation technology of SiC is more mature, the process is more advanced, it can be homogeneously epitaxial, the epitaxial quality is very high, and it can be directly thermally oxidized to generate an oxide layer with simple process steps. In nature, the ultraviolet light band with a wavelength less than 280nm is called the solar-blind band. In the solar-blind band, the ultraviolet band from the sun is completely absorbed by the atmosphere, and the environmental interference is very low. Therefore, photoelectric detection in the solar-blind ultraviolet band is of great significance. At present, ultraviolet photodetectors made of SiC have been widely used in ultraviolet communications, environmental monitoring, biological detection and other fields.

[0003] Photodetection devices mainly include phototransistors, NPN phototransistors and APD avalanche diodes. The traditional vertical structure SiC phototransistor is epitaxially grown, which is the most commonly used single crystal thin film growth technology for SiC preparation. It has the advantages of fast growth rate and good process stability. During the preparation process, it is necessary to epitaxially grow the emitter emission region, base collector region and collector emission region on the N-type substrate in sequence, and then complete the preparation through the steps of trench etching, electrode sputtering, thermal annealing and thermal oxidation to generate an oxide layer. Whether it is a vertical structure or a horizontal structure, the existing technology adopts a three-layer epitaxial growth method. The emitter region, collector region and sidewall oxide layer are in direct contact, forming a sharp current gathering point, and the carrier recombination is serious, resulting in large surface leakage current of the device, large dark current, reduced light-to-dark current ratio, reduced noise performance, and affecting the detection performance of the ultraviolet photodetector. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-noise silicon carbide NPN phototransistor and a preparation method thereof.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a low-noise silicon carbide NPN phototransistor, comprising: an n-type transition layer, an n+ buried layer, an n- buffer layer, a p-type base layer and an n-type collector layer arranged along a first direction, and a SiO2 oxide layer covering a first isolation trench, wherein the first isolation trench is located on both sides of the p-type base layer along a second direction perpendicular to the first direction;

[0007] The n+ buried layer has a high doping concentration and is arranged in intervals along the second direction in the n-type transition layer;

[0008] The n-buffer layer has a low doping concentration and is located on the upper surfaces of the n-type transition layer and the n+ buried layer;

[0009] The p-type base layer is located on the upper surface of the n-buffer layer; wherein the first isolation trench extends downward from the upper surface of the p-type base layer to the upper surface of the n-buffer layer along the first direction;

[0010] The n-type collector layer is located on a side of the p-type base layer away from the n-buffer layer. Along the second direction, the width of the n-type collector layer is smaller than the width of the p-type base layer, and the n-type collector layer does not contact the SiO2 oxide layer located in the first isolation trench.

[0011] The present invention also provides a method for preparing a low-noise silicon carbide NPN phototransistor, comprising:

[0012] S1, preparing an n-type substrate, and forming an n-type emitter layer on the upper surface of the n-type substrate along a first direction;

[0013] S2, forming an n-type transition layer on the upper surface of the n-type emission layer;

[0014] S3, forming n+ buried layers with high doping concentration in the n-type transition layer and arranged at intervals along a second direction perpendicular to the first direction;

[0015] S4, forming an n-buffer layer with a low doping concentration on the upper surface of the n-type transition layer;

[0016] S5, forming a p-type base layer on the upper surface of the n-buffer layer;

[0017] S6, etching a first isolation trench on both sides of the p-type base layer along the second direction, wherein the first trench extends downward from the upper surface of the p-type base layer to the upper surface of the n-buffer layer along the first direction;

[0018] S7, forming an n-type collector layer on the upper surface of the p-type base layer, wherein along the second direction, the width of the n-type collector layer is smaller than the width of the p-type base layer;

[0019] S8, forming an n+ region in the n-type collector layer by ion implantation;

[0020] S9, forming n-isolation regions on both sides of the n-type collector layer along the second direction, and the n-isolation regions are distributed on both sides of the n-type collector layer along the second direction and are in contact with the p-type base layer;

[0021] S10, etching a second isolation trench in the middle of the n+ region, wherein along the second direction, the second isolation trench extends downward from the upper surface of the n-type collector layer to the inside of the n-type collector layer;

[0022] S11, forming an emitter metal layer on the lower surface of the n-type substrate;

[0023] S12, forming a collector metal layer on the upper surface of each n+ region;

[0024] S13, forming a SiO2 oxide layer outside the device obtained in S12 to obtain the phototransistor, wherein the n-type collector layer is not in contact with the SiO2 oxide layer located in the first isolation trench.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] Compared with the traditional NPN phototransistor, the NPN phototransistor provided by the present invention is provided with an n-buffer layer with a low doping concentration, so that the surface state in contact with the p-type base layer is reduced, thereby reducing the current aggregation, so that the current is distributed as evenly as possible. By providing an n+ buried layer with a high doping concentration and arranged at intervals in the n-type transition layer, the current can be evenly distributed and transported vertically, and the edge leakage current can be reduced. In addition, by providing an n-type collector layer with a region width less than the width of the p-type base layer in the p-type base layer, and making the n-type collector layer not contact the SiO2 oxide layer covering the isolation grooves on both sides of the p-type base layer, the n-type collector layer can be wrapped by the p-type base layer, so that the pn junction interface can be wrapped in the p-type base layer, so that it does not contact the SiO2 oxide layer of the side wall, and the lateral transport of the current in the horizontal direction can be avoided. Therefore, the present invention can promote the longitudinal transport of carriers, reduce current aggregation, greatly reduce the leakage current of the side wall, improve the noise performance, improve the light-dark current ratio, and thus improve the normalized detection degree of the detector.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a partial cross-sectional structural schematic diagram of a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present invention;

[0029] Figure 2 1 is a schematic diagram of a cross-sectional structure of a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present invention;

[0030] Figure 3 It is a schematic flow chart of a method for preparing a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present invention;

[0031] Figure 4a to Figure 4l It is a schematic diagram of the cross-sectional structure of a device obtained in each preparation step in the preparation process of the low-noise silicon carbide NPN phototransistor provided by an embodiment of the present invention;

[0032] Figure 5 It is a dark current comparison diagram of the low-noise silicon carbide NPN phototransistor provided by an embodiment of the present invention and an NPN phototransistor with a traditional structure. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0034] In a phototransistor, the pn junction is the key area for carrier recombination, and the collector junction formed by the base region and the collector region is the area where carrier recombination is concentrated. At the same time, after the SiC is thermally oxidized to generate the SiO2 oxide layer, there are a large number of oxide layer defects at the SiO2 / SiC interface, and there is a significant oxide layer leakage current at the side wall. These surface leakage currents constitute a very important part of the dark current, which will cause the noise of the device to increase, and the light-dark current ratio and detection degree to decrease. Paying attention to and optimizing surface leakage is of great significance for reducing the dark current of the photodetector. In the traditional three-layer epitaxial structure, the collector junction and the emitter junction are in direct contact with the side wall of the SiO2 oxide layer in the horizontal direction, resulting in a large carrier recombination in the area of ​​the collector junction close to the side wall oxide layer, causing current aggregation, resulting in an increase in the leakage current of the device, an increase in noise, and a decrease in the normalized detection degree of the device. To this end, the present invention combines the ion implantation method and designs the device structure under the scheme that is feasible in the existing process, which can significantly weaken the current aggregation and carrier recombination from the structural design, thereby reducing surface leakage, reducing dark current, and improving the device noise characteristics.

[0035] The present invention provides a low-noise silicon carbide NPN phototransistor, comprising: an n-type transition layer 3, an n+ buried layer 4, an n- buffer layer 5, a p-type base layer 6 and an n-type collector layer 7 arranged along a first direction, and a SiO2 oxide layer 12 covering a first isolation trench, wherein the first isolation trench is located on both sides of the p-type base layer 6 along a second direction perpendicular to the first direction.

[0036] The n+ buried layer 4 has a high doping concentration and is arranged in intervals along the second direction in the n-type transition layer 3;

[0037] The n-buffer layer 5 has a low doping concentration and is located on the upper surfaces of the n-type transition layer 3 and the n+ buried layer 4;

[0038] The p-type base layer 6 is located on the upper surface of the n-buffer layer 5; wherein the first trench extends downward from the upper surface of the p-type base layer 6 to the upper surface of the n-buffer layer 5 along a first direction;

[0039] The n-type collector layer 7 is located on the side of the p-type base layer 6 away from the n-buffer layer 5. Along the second direction, the width of the n-type collector layer 7 is smaller than the width of the p-type base layer 6, and the n-type collector layer 7 does not contact the SiO2 oxide layer 12 located in the first isolation trench.

[0040] In some embodiments, the region where the spaced n+ buried layers 4 are located is the central region of the n-type transition layer 3 , and, along the second direction, the width of the region where the spaced n+ buried layers 4 are located is at least 1 / 3 of the width of the n-type transition layer 3 .

[0041] In some embodiments, at least three n+ buried layers 4 are arranged in the n-type transition layer 3 along the second direction. Figure 1 A partial cross-sectional structural diagram of a low-noise silicon carbide NPN phototransistor provided by the present invention. Figure 1 As shown, the first direction is A, the second direction is B, and three n+ buried layers 4 are arranged at intervals along the second direction B in the n-type transition layer 3.

[0042] In some embodiments, the thickness of the n-type transition layer 3 is 5 μm to 10 μm.

[0043] In some embodiments, along the second direction, the width of each n+ buried layer 4 ranges from 3μm to 5μm, the spacing between every two adjacent n+ buried layers 4 ranges from 2μm to 4μm, and the junction depth (ie, thickness) of the n+ buried layer 4 ranges from 2μm to 4μm.

[0044] In some embodiments, the doping element of each n+ buried layer 4 is N, and the doping concentration of each n+ buried layer 4 is greater than or equal to 7e 18 cm -3 For example, the doping concentration of each n+ buried layer 4 is in the range of 7e18 cm -3 ~1e 19 cm -3 .

[0045] In some embodiments, the doping element of the n-buffer layer 5 is N, and the doping concentration is less than or equal to 1e 17 cm -3 For example, the doping concentration of the n-buffer layer 5 is in the range of 5e 16 cm -3 ~1e 17 cm -3 .

[0046] In some embodiments, the thickness of the n-buffer layer 5 is in the range of 2 μm to 3 μm.

[0047] Compared with the traditional NPN phototransistor, the present invention can reduce the surface state in contact with the p-type base layer by setting an n-buffer layer 5 with a very low doping concentration; by setting an n+ buried layer with a high doping concentration and an interval arrangement and located in the n-type transition layer, and making each n+ buried layer width range 3μm ~ 5μm, each n+ buried layer spacing 2μm ~ 4μm, and making the area where the n+ buried layer is located in the central 1 / 3 area of ​​the entire n-type transition layer, it can promote uniform current distribution and longitudinal transport, and reduce edge leakage current.

[0048] In some embodiments, as described above Figure 1 As shown, along the second direction B, the spacing L1 between the side walls of the n-type collector layer 7 and the p-type base layer 6 is at least 5 μm, so that the n-type collector layer and the SiO 2 oxide layer can be further isolated.

[0049] In some embodiments, the thickness of the p-type base layer 6 is 3 μm to 10 μm.

[0050] In some embodiments, the doping element of the p-type base layer 6 is Al, and the doping concentration ranges from 5e 15 cm -3 ~3e 16 cm -3 .

[0051] In some embodiments, along the second direction, the ratio of the width of each first isolation trench to the width of the p-type base layer 6 is in a range of 0.1 to 0.2.

[0052] In some embodiments, along the second direction, the ratio of the width of the n-type collector layer 7 to the width of the p-type base layer 6 is in the range of 0.7 to 0.8.

[0053] In some embodiments, the junction depth of the n-type collector layer 7 is in the range of 0.5 μm to 1 μm, the doping element is N, and the doping concentration is in the range of 5e17 cm -3 ~1e 18 cm -3 .

[0054] In some embodiments, the phototransistor provided by the present invention further includes: an n+ region 8, an n-isolation region 9 with a low doping concentration, and two collector metal layers 11. The n+ region 8 and the n-isolation region 9 are both located on the side of the n-type collector layer 7 away from the p-type base layer 6, and, along the second direction, the n-isolation region 9 is distributed on both sides of the n-type collector layer 7 and in contact with the p-type base layer 6, and each collector metal layer 11 is located on the upper surface of the n+ region 8. Here, by setting the n+ region, the longitudinal transport of carriers in the n-type collector layer can be promoted; by setting the n-isolation region, the side walls of the n-type collector layer and the p-type base layer can be further isolated.

[0055] For example, as mentioned above Figure 1 As shown, the phototransistor also includes two n+ regions 8, each collector metal layer 11 is located on the upper surface of an n+ region 8; there is a second isolation groove between the two n+ regions 8, and along the second direction B, the second isolation groove extends downward from the upper surface of the n-type collector layer 7 to the inside of the n-type collector layer 7. The present invention uses a double collector to replace the traditional single electrode, which can avoid the current from gathering on one side and further promote the uniform distribution of the current in the entire horizontal direction. At the same time, etching the grooves between the electrodes can avoid interference. Exemplarily, along the second direction, the width of the second isolation groove is greater than or equal to 2μm, so that interference can be effectively avoided.

[0056] In some embodiments, the metal forming the collector metal layer 11 is Ni.

[0057] In some embodiments, the phototransistor provided by the present invention further comprises: an n-type substrate 1, an n-type emitter layer 2 and an emitter metal layer 10; the n-type emitter layer 2 is located on the upper surface of the n-type substrate 1; the emitter metal layer 10 is located on the lower surface of the n-type substrate 1; and the n-type transition layer 3 is located on the upper surface of the n-type emitter layer 2. Exemplarily, Figure 2 A schematic diagram of the cross-sectional structure of a low-noise silicon carbide NPN phototransistor provided by the present invention.

[0058] In some embodiments, the thickness of the n-type emission layer 2 is 4 μm to 10 μm.

[0059] In some embodiments, the material of the n-type substrate is 4H-SiC material, the doping element is N, the thickness is 200 μm to 500 μm, and the doping concentration ranges from 4e 18 cm -3 ~1e 19 cm -3 .

[0060] In some embodiments, the metal forming the emitter metal layer 10 is Ni.

[0061] In some embodiments, along the second direction, the SiO2 oxide layer 12 also covers the exposed upper surfaces of the p-type base layer 6, the n-type collector layer 7 and the n-isolation region 9. Figure 2 As shown, the SiO2 oxide layer 12 also covers the exposed upper surfaces of the p-type base layer 6, the n-type collector layer 7 and the n-isolation region 9, but does not cover the two collector metal layers 11. The present invention further isolates the lateral transport of carriers and reduces surface leakage current by setting an n+ region in the area where the electrode (i.e., the collector metal layer) contacts in the n-type collector layer, and setting an n-isolation region at the side contacting the pn junction interface, and making the n-isolation region low-doped and located at the junction of the n-type collector layer and the p-type base layer, and contacting the SiO2 oxide layer at the same time.

[0062] The present invention also provides a method for preparing a low-noise silicon carbide NPN phototransistor, which is used to prepare the low-noise silicon carbide NPN phototransistor. Figure 3 As shown, the method includes:

[0063] S1 . Prepare an n-type substrate 1 , and form an n-type emitter layer 2 on the upper surface of the n-type substrate 1 along a first direction.

[0064] Specifically, the n-type substrate material can be selected from 4H-SiC material, the doping element is N, the thickness is 200μm to 500μm, and the doping concentration ranges from 4e18cm-3 to 1e19cm-3. A chemical vapor deposition device can be used to form an n-type emitter layer 2 on the upper surface of the n-type substrate. Exemplarily, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the dilution gas, the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm to 10sccm, the flow rate of N2 is 0.01sccm to 0.1sccm, and the RF power is 10W to 30W, and the annealing temperature is 900℃ to 1200℃. The thickness of the obtained n-type emitter layer 2 can be 4μm to 10μm, and the doping concentration ranges from 7e18cm-3 to 1e19cm-3. Exemplarily, the schematic diagram of the cross-sectional structure of the device prepared in step S1 is as shown below. Figure 4a shown.

[0065] S2 . Form an n-type transition layer 3 on the upper surface of the n-type emitter layer 2 .

[0066] Specifically, a chemical vapor deposition device can be used to prepare an n-type transition layer on the upper surface of the n-type emission layer 2. Exemplarily, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the dilution gas, the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm to 10sccm, the flow rate of N2 is 0.01sccm to 0.1sccm, and the RF power is 10W to 30W, and the annealing temperature is 900℃ to 1200℃. The thickness of the obtained n-type transition layer is 5μm to 10μm, and the doping concentration ranges from 1e 18 cm -3 ~2e 18 cm -3 For example, the cross-sectional structure diagram of the device prepared in step S2 is as follows: Figure 4b shown.

[0067] S3. Form n+ buried layers 4 having a high doping concentration and arranged at intervals along a second direction perpendicular to the first direction in the n-type transition layer 3 by ion implantation.

[0068] Specifically, a window is set as a buried layer area on the upper surface of the n-type transition layer 3 by a photolithography process when preparing a mask, and the window is exposed after exposure for ion implantation. The width of each n+ buried layer 4 is in the range of 3 μm to 5 μm, the spacing between two adjacent n+ buried layers 4 is 2 μm to 4 μm, the junction depth of each n+ buried layer 4 is in the range of 2 μm to 4 μm, the entire area where the n+ buried layer 4 is located is located in the central 1 / 3 area of ​​the entire n-type transition layer 3, the doping element is N, and the doping concentration range is 7e 18 cm -3 ~1e 19 cm -3 ;

[0069] Exemplarily, the cross-sectional structure diagram of the device prepared in step S3 is as follows: Figure 4c shown.

[0070] S4 . Form an n-buffer layer 5 with a low doping concentration on the upper surface of the n-type transition layer 3 .

[0071] Specifically, a chemical vapor deposition device can be used to prepare an n-buffer layer 5 on the upper surface of the n-type transition layer 3. Exemplarily, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the diluent gas, the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm-10sccm, the flow rate of N2 is 0.1sccm-1sccm, and the RF power is 10W-30W, the annealing temperature is 900℃-1200℃, and the thickness of the obtained n-buffer layer 5 is 2μm-3μm, the doping element is N, and the doping concentration range is 5e 16 cm -3~1e 17 cm -3 For example, the cross-sectional structure diagram of the device prepared in step S4 is as follows: Figure 4d shown.

[0072] S5 . Form a p-type base layer 6 on the upper surface of the n-buffer layer 5 .

[0073] Specifically, a p-type base layer 6 can be prepared on the upper surface of the n-buffer layer 5 using a chemical vapor deposition device. Exemplarily, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the diluent gas, the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm to 10sccm, the flow rate of N2 is 0.1sccm to 1sccm, and the RF power is 10W to 30W, and the annealing temperature is 900℃ to 1200℃. The thickness of the obtained p-type base layer is 3μm to 10μm, the doping element is Al, and the doping concentration range is 5e 15 cm -3 ~3e 16 cm -3 For example, the cross-sectional structure diagram of the device prepared in step S5 is as follows: Figure 4e shown.

[0074] S6 , etching first isolation trenches on both sides of the p-type base layer 6 along the second direction, wherein the first trenches extend downward from the upper surface of the p-type base layer 6 to the upper surface of the n-buffer layer 5 along the first direction.

[0075] Specifically, photolithography can be performed on the p-type base layer 6, and a mask can be used to protect the central region of the p-type base layer 6, leaving the edge exposed, and then an inductively coupled plasma ICP dry etching process is used to form a first isolation trench located on the side of the p-type base layer 6. Exemplarily, along the second direction, the ratio of the width of the protected central region to the overall width of the p-type base layer 6 is in the range of 0.8 to 0.9. Exemplarily, the cross-sectional structure schematic diagram of the device prepared in step S6 is as follows: Figure 4f shown.

[0076] S7 . Form an n-type collector layer 7 on the upper surface of the p-type base layer 6 by ion implantation, wherein the width of the n-type collector layer 7 is smaller than the width of the p-type base layer 6 along the second direction.

[0077] Specifically, a photolithography process is used on the upper surface of the p-type base layer 6, and a window is set as the n-type collector layer area when preparing the mask. After exposure, the window is exposed and ion implantation is performed, wherein along the second direction, on the p-type base layer 6, the width of the outer region of the n-type collector layer area is 0.2 to 0.3 of the overall width of the p-type base layer 6. When the well region is implanted, an ion implantation process is used to form the n-type collector layer 7. The junction depth of the n-type collector layer 7 ranges from 0.5 μm to 1 μm, the doping element is N, and the doping concentration ranges from 5e17 cm-3 to 1e18 cm-3. Exemplarily, the schematic diagram of the cross-sectional structure of the device prepared in step S7 is as follows: Figure 4g shown.

[0078] S8. Form an n+ region 8 in the n-type collector layer 7 by ion implantation.

[0079] Specifically, the n-type collector layer 7 is subjected to a photolithography process, and a window is set as an n+ region when preparing a mask. After exposure, the window is exposed, and ion implantation is performed to form an n+ region 8. The width of the n+ region 8 is in the range of 2 μm to 5 μm, the junction depth of the n+ region 8 is in the range of 0.2 μm to 0.3 μm, the doping element is N, and the doping concentration range is 5e 18 cm -3 ~1e 19 cm -3 For example, the cross-sectional structure diagram of the device prepared in step S8 is as follows: Figure 4h shown.

[0080] S9 . Along the second direction, n-isolation regions 9 are formed on both sides of the n-type collector layer 7 by ion implantation. Also, along the second direction, the n-isolation regions 9 are distributed on both sides of the n-type collector layer 7 and are in contact with the p-type base layer 6 .

[0081] Specifically, the n-type collector layer 7 is subjected to a photolithography process, and a window is set as an n-isolation region when preparing a mask. After exposure, the window is exposed, and ion implantation is performed to form an n-isolation region 9. The width of the n-isolation region 9 is in the range of 2 μm to 4 μm, the junction depth is in the range of 0.2 μm to 0.3 μm, the doping element is N, and the doping concentration range is 5e 16 cm -3 ~1e 17 cm -3 For example, the cross-sectional structure diagram of the device prepared in step S9 is as follows: Figure 4i shown.

[0082] S10 , etching a second isolation trench in the middle of the n+ region 8 , wherein the second isolation trench extends downward from the upper surface of the n-type collector layer 7 to the inside of the n-type collector layer 7 along the second direction.

[0083] Specifically, photolithography is performed on the n-type collector layer 7, and a mask is used to expose the area between the two n+ regions 8, wherein the width of the exposed area along the second direction ranges from 2 μm to 4 μm, and then, an inductively coupled plasma ICP dry etching process is used to form a second isolation trench in the exposed area, and exemplary, the etching depth ranges from 0.4 μm to 0.6 μm. Exemplarily, the cross-sectional structure schematic diagram of the device prepared in step S10 is as follows Figure 4j shown.

[0084] S11 , forming an emitter metal layer 10 on the lower surface of the n-type substrate 1 .

[0085] Specifically, the emitter metal is sputtered on the lower surface of the n-type substrate using magnetron sputtering technology. For example, the metal used is Ni, the sputtering rate is 10nm / min-15nm / min, the sputtering power is 100W-120W, and the sputtering thickness is 200nm-250nm. For example, the cross-sectional structure diagram of the device prepared in step S11 is as follows: Figure 4k shown.

[0086] S12 . Form a collector metal layer 11 on the upper surface of each n+ region 8 .

[0087] Specifically, photolithography is performed on each n+ region 8, so that the mask exposes the central area of ​​each n+ region 8, while protecting other areas. Exemplarily, along the second direction, the ratio of the width of the central area exposed by each n+ region 8 to the width of the n+ region 8 is in the range of 0.3 to 0.4. Then, magnetron sputtering of collector metal is performed on the exposed area using magnetron sputtering technology. Exemplarily, the metal used is Ni, the sputtering rate is 10nm / min-15nm / min, the sputtering power is 100W-120W, and the sputtering thickness is 200nm-250nm. Exemplarily, the cross-sectional structure schematic diagram of the device prepared in step S12 is as follows: Figure 4l shown.

[0088] S13, forming a SiO2 oxide layer outside the device obtained in S12 to obtain a phototransistor, wherein the n-type collector layer 7 is not in contact with the SiO2 oxide layer 12 located in the first isolation trench.

[0089] Specifically, for the entire device prepared in step S12, a SiO2 layer is oxidized on the surface of the silicon carbide material through a thermal oxidation process. Exemplarily, the thickness of the obtained SiO2 oxide layer 12 is 0.5 μm to 1 μm.

[0090] In the thermal oxidation process of the present invention, the thermal oxidation temperature is controlled at a maximum temperature of 1400°C-1450°C, which is lower than the melting point of nickel. In this way, the annealing temperature can be increased as much as possible while ensuring that the metallic nickel does not melt, thereby reducing the concentration of carbon para-site defects in the prepared oxide layer.

[0091] In the traditional process of thermal oxidation of SiC to generate SiO2 oxide layer, the oxygen flow rate and the argon flow rate are similar in an oxygen-rich environment. However, in an oxygen-rich environment, a large number of carbon para-position defects will be generated. These carbon para-position defects are of various types and have a high concentration. They are the main defects in the SiO2 / SiC interface defects. In the thermal oxidation process of the present invention, the flow rate of oxygen is less than 1 / 4 of that of argon. Exemplarily, the oxygen flow rate is controlled at 50sccm-100sccm, and the argon flow rate is 500sccm. In this way, it can be in an oxygen-poor environment, thereby reducing the concentration of carbon para-position defects in the prepared oxide layer. In other words, the high-temperature thermal oxidation and oxygen-poor environment processes used in the present invention can greatly reduce the generation of carbon para-position defects from a chemical point of view, thereby reducing the oxide layer leakage of the device, reducing carrier recombination, reducing noise current, and improving the normalized detection of the detector.

[0092] Exemplarily, the cross-sectional structure diagram of the device prepared in step S13 is as shown above. Figure 2 shown.

[0093] For example, Figure 5 The dark current comparison diagram of the low-noise silicon carbide NPN phototransistor provided by the present invention and the NPN phototransistor with a traditional structure is shown in FIG. Figure 5 As shown, it is obvious that the dark current of the low-noise silicon carbide NPN phototransistor provided by the present invention is much smaller than the dark current of the NPN phototransistor with a traditional structure.

[0094] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0095] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0096] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0097] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A low noise silicon carbide NPN phototransistor, characterized in that: include: An n-type transition layer (3), an n+ buried layer (4), an n- buffer layer (5), a p-type base layer (6) and an n-type collector layer (7) arranged along a first direction, and a SiO2 oxide layer (12) covering a first isolation trench, wherein the first isolation trench is located on both sides of the p-type base layer (6) along a second direction perpendicular to the first direction; The n+ buried layer (4) has a high doping concentration and is arranged at intervals along the second direction in the n-type transition layer (3); The n-buffer layer (5) has a low doping concentration and is located on the upper surfaces of the n-type transition layer (3) and the n+ buried layer (4); The p-type base layer (6) is located on the upper surface of the n-buffer layer (5); wherein the first isolation trench extends downward from the upper surface of the p-type base layer (6) to the upper surface of the n-buffer layer (5) along the first direction; The n-type collector layer (7) is located on a side of the p-type base layer (6) away from the n-buffer layer (5); along the second direction, the width of the n-type collector layer (7) is smaller than the width of the p-type base layer (6); and the n-type collector layer (7) is not in contact with the SiO2 oxide layer (12) located in the first isolation trench.

2. The low noise silicon carbide NPN phototransistor according to claim 1, characterized in that: The region where the spaced n+ buried layers (4) are located is the central region of the n-type transition layer (3), and, along the second direction, the width of the region where the spaced n+ buried layers (4) are located is at least 1 / 3 of the width of the n-type transition layer (3).

3. The low noise silicon carbide NPN phototransistor according to claim 1, characterized in that: Along the second direction, the width of each n+ buried layer (4) ranges from 3 μm to 5 μm, and the distance between each two adjacent n+ buried layers (4) ranges from 2 μm to 4 μm.

4. The low noise silicon carbide NPN phototransistor according to claim 1, characterized in that: Along the second direction, the distance between the side walls of the n-type collector layer (7) and the p-type base layer (6) is at least 5 μm.

5. The low noise silicon carbide NPN phototransistor according to claim 1, characterized in that: The phototransistor further comprises: an n+ region (8), an n-isolation region (9) with a low doping concentration, and two collector metal layers (11); The n+ region (8) and the n-isolation region (9) are both located on a side of the n-type collector layer (7) away from the p-type base layer (6), and along the second direction, the n-isolation region (9) is distributed on both sides of the n-type collector layer (7) and is in contact with the p-type base layer (6); Each collector metal layer (11) is located on the upper surface of the n+ region (8).

6. The low noise silicon carbide NPN phototransistor according to claim 5, characterized in that: The phototransistor further comprises two n+ regions (8), each collector metal layer (11) being located on the upper surface of one n+ region (8); a second isolation trench is provided between the two n+ regions (8), and along the second direction, the second isolation trench extends downward from the upper surface of the n-type collector layer (7) to the interior of the n-type collector layer (7).

7. The low noise silicon carbide NPN phototransistor according to claim 6, characterized in that: Along the second direction, a width of the second isolation trench is greater than or equal to 2 μm.

8. The low noise silicon carbide NPN phototransistor according to claim 6, characterized in that: Along the second direction, the SiO2 oxide layer (12) also covers the exposed upper surfaces of the p-type base layer (6), the n-type collector layer (7) and the n-isolation region (9).

9. The low noise silicon carbide NPN phototransistor according to claim 1, characterized in that: The phototransistor further comprises: an n-type substrate (1), an n-type emission layer (2) and an emitter metal layer (10); The n-type emission layer (2) is located on the upper surface of the n-type substrate (1); The emitter metal layer (10) is located on the lower surface of the n-type substrate (1); The n-type transition layer (3) is located on the upper surface of the n-type emission layer (2).

10. A method for preparing a low-noise silicon carbide NPN phototransistor, characterized in that: include: S1, preparing an n-type substrate (1), and forming an n-type emission layer (2) on an upper surface of the n-type substrate (1) along a first direction; S2, forming an n-type transition layer (3) on the upper surface of the n-type emission layer (2); S3, forming n+ buried layers (4) having a high doping concentration and arranged at intervals along a second direction perpendicular to the first direction in the n-type transition layer (3); S4, forming an n-buffer layer (5) having a low doping concentration on the upper surface of the n-type transition layer (3); S5, forming a p-type base layer (6) on the upper surface of the n-buffer layer (5); S6, etching first isolation trenches on both sides of the p-type base layer (6) along the second direction, wherein the first trenches extend downward from the upper surface of the p-type base layer (6) to the upper surface of the n-buffer layer (5) along the first direction; S7, forming an n-type collector layer (7) on the upper surface of the p-type base layer (6), wherein, along the second direction, the width of the n-type collector layer (7) is smaller than the width of the p-type base layer (6); S8, forming an n+ region (8) in the n-type collector layer (7); S9, forming an n-isolation region (9) on both sides of the n-type collector layer (7) along the second direction, and the n-isolation region (9) is distributed on both sides of the n-type collector layer (7) along the second direction and is in contact with the p-type base layer (6); S10, etching a second isolation trench in the middle of the n+ region (8), wherein along the second direction, the second isolation trench extends downward from the upper surface of the n-type collector layer (7) to the inside of the n-type collector layer (7); S11, forming an emitter metal layer (10) on the lower surface of the n-type substrate (1); S12, forming a collector metal layer (11) on the upper surface of each n+ region (8); S13, forming a SiO2 oxide layer on the outer side of the device obtained in S12 to obtain the phototransistor, wherein the n-type collector layer (7) is not in contact with the SiO2 oxide layer (12) located in the first isolation trench.

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