High luminous efficiency LED chip and its manufacturing method

Abstract

The present invention discloses a high light extraction efficiency LED chip and a preparation method thereof, relating to the field of semiconductor optoelectronic devices. The preparation method includes: providing an epitaxial wafer, which includes a substrate, a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence; forming a transparent conductive layer on the epitaxial wafer; etching to form a bare area exposing the first semiconductor layer; forming a first electrode and a second electrode, wherein the first electrode is formed on the first semiconductor layer in the bare area, and the second electrode is formed on the second semiconductor layer; using silicon and copper as targets to sputter and form a first composite film; annealing the first composite film in an oxygen-containing atmosphere at 550-700 °C to obtain a second composite film; forming a silicon oxide film on the second composite film; opening holes in the second composite film and the silicon oxide film in the areas where the first electrode and the second electrode are located to at least partially expose the first electrode and the second electrode. Implementing the present invention can improve the light extraction efficiency and reliability of the LED chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a high light extraction efficiency LED chip and a preparation method thereof. Background Art

[0002] An LED (Light Emitting Diode) is a semiconductor light emitting device that can convert electrical energy into light energy. With the development and progress of LED chip manufacturing technology, it has gradually become a new mainstream lighting source after incandescent lamps and fluorescent lamps. LEDs have the advantages of small size, fast response, long life, environmental protection and energy saving, and are widely used in the fields of lighting, displays, etc. An LED chip is composed of an epitaxial layer and a chip layer. The epitaxial layer generally includes a substrate, an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer; the chip layer from bottom to top is a current blocking layer, a transparent conductive layer, an electrode, and a passivation layer in sequence. The light of the LED chip is emitted from the epitaxial layer and exits into the air through the transparent conductive layer and the passivation layer. The passivation layer is generally made of SiO2 material and is deposited by a PECVD device. The existing passivation layer is a single film layer material, with a refractive index of about 1.48, the refractive index of air is 1, and the refractive index of the transparent conductive layer is generally between 1.8 and 2.0. The refractive index differences among the three are large, and total reflection is likely to occur, resulting in low light extraction efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a preparation method of a high light extraction efficiency LED chip, which can improve the light extraction efficiency of the LED chip.

[0004] Another technical problem to be solved by the present invention is to provide a high light extraction efficiency LED chip.

[0005] To solve the above problems, the present invention discloses a preparation method of a high light extraction efficiency LED chip, which includes:

[0006] Providing an epitaxial wafer, the epitaxial wafer includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0007] Forming a transparent conductive layer on the epitaxial wafer; wherein, the transparent conductive layer is formed on the second semiconductor layer;

[0008] Etching to form a bare area exposing the first semiconductor layer;

[0009] Forming a first electrode and a second electrode to obtain an intermediate; wherein, the first electrode is formed on the first semiconductor layer in the bare area, and the second electrode is formed on the transparent conductive layer;

[0010] Using silicon and copper as targets, sputtering to form a first composite film on the surface of the intermediate;

[0011] Anneal the first composite film in an oxygen-containing atmosphere at 550 - 700 °C to obtain a second composite film;

[0012] Form a silicon oxide film on the second composite film;

[0013] Open holes in the second composite film and the silicon oxide film in the regions where the first electrode and the second electrode are located to at least partially expose the first electrode and the second electrode.

[0014] As an improvement to the above technical solution, in the step of sputtering to form the first composite film on the surface of the intermediate with silicon and copper as targets, the sputtering power of the copper target is 10 - 20 W, the sputtering power of the silicon target is 30 - 60 W, and the sputtering time is 2 - 5 min; the sputtering gas is Ar, the gas pressure is 4 - 8 mtorr, and the sputtering temperature is 20 - 50 °C;

[0015] In the step of annealing the first composite film in an oxygen-containing atmosphere at 550 - 700 °C to obtain a second composite film, the annealing atmosphere is air, the annealing duration is 0.3 - 1 h, and the annealing is carried out in a PECVD chamber.

[0016] As an improvement to the above technical solution, in the step of sputtering to form the first composite film on the surface of the intermediate with silicon and copper as targets, first sputter the copper target for 10 - 20 s, then co-sputter the copper target and the silicon target for 2 - 4 min, and finally sputter the silicon target for 20 - 40 s;

[0017] The step of annealing the first composite film in an oxygen-containing atmosphere at 550 - 700 °C to obtain a second composite film includes:

[0018] Anneal the first composite film in an Ar or N₂ atmosphere at 800 - 900 °C for the first time;

[0019] Anneal the first composite film after the first annealing in an oxygen-containing atmosphere at 550 - 700 °C for the second time to obtain a second composite film.

[0020] As an improvement to the above technical solution, in the step of annealing the first composite film in an Ar or N₂ atmosphere at 800 - 900 °C for the first time, the annealing atmosphere is Ar, the annealing duration is 5 - 20 min, and the annealing is carried out in a PECVD chamber;

[0021] In the step of annealing the first composite film after the first annealing in an oxygen-containing atmosphere at 550 - 700 °C for the second time to obtain a second composite film, the annealing atmosphere is air, the annealing duration is 0.3 - 1 h, and the annealing is carried out in a PECVD chamber.

[0022] As an improvement of the above technical solution, in the step of forming a silicon oxide film on the second composite film, a first silicon oxide film and a second silicon oxide film are sequentially formed on the second composite film;

[0023] The porosity of the first silicon oxide film is less than that of the second silicon oxide film; the thickness of the first silicon oxide film is less than that of the second silicon oxide film.

[0024] As an improvement of the above technical solution, the porosity of the first silicon oxide film is 15-30%, and the porosity of the second silicon oxide film is 35-55%;

[0025] The thickness of the first silicon oxide film is 5-50 nm, and the thickness of the second silicon oxide film is 20-100 nm.

[0026] As an improvement of the above technical solution, both the first silicon oxide film and the second silicon oxide film are formed by PECVD; during the formation process, the radio frequency power is 80-100 W, the pressure of the PECVD chamber is 80-120 Pa, and the temperature is 200-250 °C;

[0027] The flow ratio of SiH4 to N2O during the formation of the first silicon oxide film is greater than that during the formation of the second silicon oxide film.

[0028] As an improvement of the above technical solution, during the formation of the first silicon oxide film, the flow rate of SiH4 is 400-600 sccm, and the flow rate of N2O is 1800-2000 sccm;

[0029] During the formation of the second silicon oxide film, the flow rate of SiH4 is 100-300 sccm, and the flow rate of N2O is 1800-2000 sccm.

[0030] As an improvement of the above technical solution, the thickness of the second composite film is 30-50 nm;

[0031] The transparent conductive layer is an ITO layer or an AZO layer, and its thickness is 40-80 nm.

[0032] Correspondingly, the present invention also discloses a high extraction efficiency LED chip, which is prepared by the preparation method of the high extraction efficiency LED chip described above.

[0033] Implementing the present invention has the following beneficial effects:

[0034] In the preparation method of the high extraction efficiency LED chip according to an embodiment of the present invention, a first composite film of Si-Cu material is first sputtered on an epitaxial wafer, and then annealed in an oxygen-containing atmosphere to be converted into SiO2-Cu xAn O composite film (the second composite film) is then formed with a silicon oxide film on the second composite film, and the two together form a passivation structure. This passivation structure can cooperate well with the transparent conductive layer to improve the light extraction efficiency; at the same time, the passivation structure also maintains good denseness, has excellent passivation performance, and improves the reliability of the LED chip. Brief Description of the Drawings

[0035] Figure 1 is a flowchart of a method for manufacturing a high light extraction efficiency LED chip according to an embodiment of the present invention;

[0036] Figure 2 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention;

[0037] Figure 3 is a schematic structural diagram of the epitaxial wafer after step S2 according to an embodiment of the present invention;

[0038] Figure 4 is a schematic structural diagram of the epitaxial wafer after step S3 according to an embodiment of the present invention;

[0039] Figure 5 is a schematic structural diagram of an intermediate after step S4 according to an embodiment of the present invention;

[0040] Figure 6 is a schematic structural diagram of an intermediate after step S6 according to an embodiment of the present invention;

[0041] Figure 7 is a schematic structural diagram of an intermediate after step S7 according to an embodiment of the present invention;

[0042] Figure 8 is a schematic structural diagram of a silicon oxide film according to an embodiment of the present invention;

[0043] Figure 9 is a schematic structural diagram of a high light extraction efficiency LED chip according to an embodiment of the present invention;

[0044] In the figures, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 2 is a transparent conductive layer, 3 is a bare area, 4 is a first electrode, 5 is a second electrode, 6 is a second composite film, 7 is a silicon oxide film, 71 is a first silicon oxide film, 72 is a second silicon oxide film, and 8 is an opening. Detailed Description of the Invention

[0045] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as a limitation to the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0047] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0048] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0049] See Figure 1 , the present invention discloses a method for preparing a high-light extraction efficiency LED chip, which comprises the following steps:

[0050] S1: Provide an epitaxial wafer;

[0051] See Figure 2, the epitaxial wafer 1 includes a substrate 11, and a first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 sequentially disposed on the substrate 11. Specifically, the LED chip of the present invention can be a red, green, yellow, or violet LED chip. Based on the control of the emission wavelength, different types of semiconductor layers and active layers can be selected. Exemplarily, in one embodiment, when the LED chip is a blue LED chip or a green LED chip, the first semiconductor layer 12 can be an N-type GaN layer, the active layer 13 can be an InGaN-GaN type multi-quantum well layer, and the second semiconductor layer 14 can be a P-type GaN layer, but not limited thereto. In another embodiment, when the LED chip is a violet LED chip, the first semiconductor layer 12 can be an N-type AlGaN layer, the active layer 13 can be an AlGaN-AlGaN type multi-quantum well layer, and the second semiconductor layer 14 can be a P-type AlGaN layer, but not limited thereto.

[0052] Preferably, in some embodiments, the epitaxial wafer may further include a buffer layer, an electron blocking layer, a P-type contact layer, etc., but not limited thereto.

[0053] S2: Form a transparent conductive layer on the epitaxial wafer;

[0054] Specifically, referring to Figure 3 , the transparent conductive layer 2 can be formed by processes such as PVD, electron beam evaporation, etc., but not limited thereto. Preferably, in some embodiments, the transparent conductive layer is formed by PVD, which can be combined with the subsequent formation process of the first composite film to improve the process efficiency. More preferably, sputtering is performed with an ITO target and / or an AZO target, the sputtering temperature is 20~50 °C, the sputtering power is 80~150 W, the sputtering gas is Ar, and the air pressure is 3~5 mtorr.

[0055] Specifically, the transparent conductive layer 2 is an ITO layer, an IZO layer, an AZO layer, an ATO layer, or an FTO layer, but not limited thereto. Preferably, it is an AZO layer or an ITO layer. This transparent conductive layer 2 can be combined with sputtered Cu to improve the light transmittance and conductivity, optimizing the current distribution while improving the light extraction efficiency.

[0056] Specifically, the thickness of the transparent conductive layer 2 is 40~100 nm, preferably 40~80 nm.

[0057] S3: Etch to form a bare area exposing the first semiconductor layer;

[0058] Specifically, referring to Figure 4 , the bare area 3 can be formed by a photolithography etching process, or a mask can be formed first and then etched to form the bare area, but not limited thereto.

[0059] Specifically, the etching process can be a wet etching process or a dry etching process (such as ICP or RIE). Preferably, a dry etching process is used for etching.

[0060] Specifically, in some embodiments, the transparent conductive layer, the second semiconductor layer, the active layer, and a preset amount of the first semiconductor layer can be removed by one etching process to form a bare area, or the transparent conductive layer can be removed by one etching process first, and then a secondary etching is performed to form a bare area.

[0061] S4: Form a first electrode and a second electrode to obtain an intermediate;

[0062] Specifically, referring to Figure 5 , the first electrode 4 and the second electrode 5 can be formed by processes such as PVD, electron beam evaporation, etc., but are not limited thereto. The first electrode 4 and the second electrode 5 can be formed synchronously or step by step.

[0063] Correspondingly, the first electrode 4 and the second electrode 5 have the same or different compositions, and both are composed of one or more of the common Al metal layer, Cr metal layer, Pt metal layer, Ag metal layer, and Au metal layer in the art.

[0064] S5: Sputter to form a first composite film on the surface of the intermediate with silicon and copper as targets;

[0065] Specifically, sputtering is carried out by a magnetron sputtering process. Among them, the sputtering power of the copper target is 10 - 20 W, the sputtering power of the silicon target is 30 - 60 W, and the sputtering time is 2 - 5 min; the sputtering gas is Ar, the gas pressure is 4 - 8 mtorr, and the sputtering temperature is 20 - 50 °C. Based on the above sputtering process, a Si - Cu composite film, that is, the first composite film, is formed on the surface of the intermediate. The first composite film covers the surfaces of the transparent conductive layer 2, the first electrode 4, and the second electrode 5, as well as the sidewalls of the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14. It should be noted that the surfaces of the transparent conductive layer 2, the first electrode 4, and the second electrode 5 include the upper surface and the sidewalls.

[0066] Specifically, the copper target and the silicon target can be sputtered together or step by step. Preferably, in some embodiments, the copper target is sputtered for 10 - 20 s first, then the copper target and the silicon target are co - sputtered for 2 - 4 min, and finally the silicon target is sputtered for 20 - 40 s. Based on this sputtering process, with subsequent specific annealing processes, Cu particles can be fused with part of the transparent conductive layer 2, thereby improving the light transmittance and conductivity of the transparent conductive layer 2 and optimizing its current spreading performance.

[0067] S6: Anneal the first composite film in an oxygen - containing atmosphere to obtain a second composite film;

[0068] Specifically, referring toFigure 6 Through annealing, the Si-Cu composite film can be transformed into a SiO2-Cu x O composite film (the second composite film 6). This second composite film 6 has a relatively high refractive index, which can improve the light extraction efficiency; secondly, it has a relatively high density, which can effectively prevent water vapor and the like from penetrating into the LED chip and improve its reliability; thirdly, it has good insulation properties and, in cooperation with the subsequently formed silicon oxide film 7, can play a good passivation role. Specifically, based on different annealing temperatures, oxygen concentrations, etc., a SiO2-CuO composite film or a SiO2-Cu2O composite film can be formed. Preferably, the first composite film is transformed into a SiO2-Cu2O film, which has a higher density.

[0069] Specifically, the oxygen-containing atmosphere can be an air atmosphere, an oxygen atmosphere, a nitrous oxide atmosphere, etc., but is not limited thereto. Preferably, it is an air atmosphere. The annealing temperature is 550-700 °C, preferably 550-600 °C. The annealing duration is 0.1-1 h, preferably 0.3-1 h.

[0070] Specifically, annealing can be carried out in a PECVD chamber to integrate with the formation process of the subsequent silicon oxide film 7 and improve production efficiency.

[0071] Preferably, in some embodiments, when the copper target is sputtered first, then the copper and silicon targets are co-sputtered, and finally the silicon target is sputtered, step S6 includes:

[0072] S61: Anneal the first composite film once in an Ar or N2 atmosphere;

[0073] S62: Anneal the first composite film after the first annealing in an oxygen-containing atmosphere for a second time to obtain the second composite film;

[0074] Based on the above annealing process, on the one hand, during the first annealing process, some Cu nanoparticles are embedded in the transparent conductive layer, optimizing its light transmittance and current spreading performance. On the other hand, the first composite film is transformed into SiO2-Cu x O composite film (the second composite film 6) through the second annealing, optimizing various properties.

[0075] Specifically, the temperature of the first annealing is 800-900 °C, preferably 800-850 °C. The duration of the first annealing is 5-30 min, preferably 5-20 min. The annealing atmosphere is Ar or N2, preferably Ar.

[0076] Specifically, during the second annealing process, the oxygen-containing atmosphere can be an air atmosphere, an oxygen atmosphere, a nitrous oxide atmosphere, etc., but is not limited thereto. Preferably, it is an air atmosphere. The temperature of the second annealing is 550-700 °C, preferably 550-600 °C. The duration of the second annealing is 0.1-1 h, preferably 0.3-1 h.

[0077] Specifically, the thickness of the second composite film 6 obtained through the above sputtering and annealing processes is 20 to 80 nm, preferably 30 to 50 nm.

[0078] S7: Form a silicon oxide film on the second composite film;

[0079] Specifically, referring to Figure 7 , a silicon oxide film 7 can be formed by processes such as MOCVD, PECVD, etc., but not limited thereto. Preferably, in some embodiments, the silicon oxide film 7 is formed by PECVD. Specifically, the process gases used include SiH4, Ar, N2, and / or N2O, the radio frequency power is 80 to 100 W, the deposition temperature is 200 to 250 °C, and the pressure in the PECVD chamber during deposition is 80 to 120 Pa, but not limited thereto.

[0080] Preferably, referring to Figure 8 , in some embodiments, a first silicon oxide film 71 and a second silicon oxide film 72 are sequentially formed on the second composite film 6, wherein the porosity of the first silicon oxide film 71 is less than that of the second silicon oxide film 72; the thickness of the first silicon oxide film 71 is less than that of the second silicon oxide film 72. Based on this setting, the light extraction efficiency can be further optimized. It should be noted that by increasing the porosity, the light transmittance of the silicon oxide film can be increased, but too large a porosity also poses a risk of tunneling and weakens the passivation performance. In the present invention, a dense second composite film 6 is first provided below the silicon oxide film 7, and then a silicon oxide film 7 with a higher porosity can be used, ensuring better passivation performance while optimizing the light extraction efficiency.

[0081] More specifically, the porosity of the first silicon oxide film 71 is 15 to 30%, and the porosity of the second silicon oxide film 72 is 35 to 55%; the thickness of the first silicon oxide film 71 is 5 to 50 nm, and the thickness of the second silicon oxide film 72 is 20 to 100 nm. The smaller thickness of the first silicon oxide film 71 can optimize the light transmittance and also improve the overall formation efficiency of the silicon oxide film 7.

[0082] Specifically, in order to form the first silicon oxide film 71 and the second silicon oxide film 72 with the above porosities, control the SiH4 / N2O (volume flow ratio) during the formation of the first silicon oxide film 71 to be greater than the SiH4 / N2O (volume flow ratio) during the formation of the second silicon oxide film 72.

[0083] More specifically, during the formation of the first silicon oxide film 71, the flow rate of SiH4 is 400 - 600 sccm, and the flow rate of N2O is 1800 - 2000 sccm; the radio frequency power is 80 - 100 W, the pressure in the PECVD chamber is 80 - 120 Pa, and the temperature is 200 - 250 °C. During the formation of the second silicon oxide film 72, the flow rate of SiH4 is 100 - 300 sccm, and the flow rate of N2O is 1800 - 2000 sccm; the radio frequency power is 80 - 100 W, the pressure in the PECVD chamber is 80 - 120 Pa, and the temperature is 200 - 250 °C.

[0084] S8: Open holes in the second composite film and the silicon oxide film in the regions where the first electrode and the second electrode are located, so as to at least partially expose the first electrode and the second electrode.

[0085] Specifically, referring to Figure 9 , the opening 8 can be formed by a photolithography etching process, or a mask can be formed first and then the opening 8 can be etched, but it is not limited thereto.

[0086] Specifically, the etching process can be a wet etching process or a dry etching process (such as ICP or RIE). Preferably, a dry etching process is used for etching.

[0087] In summary, in the preparation method of the high light extraction efficiency LED chip according to an embodiment of the present invention, a first composite film made of Si - Cu is sputtered on the epitaxial wafer, and then it is annealed in an oxygen - containing atmosphere and transformed into a SiO2 - Cu x O composite film (the second composite film 6), and then a silicon oxide film 7 is formed on the second composite film 6. The two together form a passivation structure. This passivation structure can cooperate well with the transparent conductive layer 2, improving the light extraction efficiency. At the same time, the passivation structure also maintains good compactness, has excellent passivation performance, and improves the reliability of the LED chip.

[0088] Correspondingly, the present invention also discloses a high light extraction efficiency LED chip, which is prepared by the above - mentioned preparation method.

[0089] The following further illustrates the present invention with specific examples:

[0090] Example 1

[0091] This example provides a preparation method of a high light extraction efficiency LED chip, which includes the following steps:

[0092] (1) Provide an epitaxial wafer;

[0093] Among them, the epitaxial wafer includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0094] (2) Form a transparent conductive layer on the second semiconductor layer by PVD;

[0095] Among them, the transparent conductive layer is an ITO layer with a thickness of 80 nm;

[0096] (3) Etch to form an exposed area exposing the first semiconductor layer;

[0097] (4) Evaporate to form a first electrode and a second electrode to obtain an intermediate;

[0098] Among them, the first electrode is formed on the first semiconductor layer in the exposed area, and the second electrode is formed on the transparent conductive layer;

[0099] (5) Using silicon and copper as targets, sputter to form a first composite film on the surface of the intermediate;

[0100] Among them, co-sputtering is carried out, the sputtering power of the copper target is 15 W, the sputtering power of the silicon target is 50 W, and the sputtering time is 5 min; the sputtering gas is Ar, the air pressure is 6 mtorr, and the sputtering temperature is 25 °C.

[0101] (6) Anneal the first composite film in an oxygen-containing atmosphere to obtain a second composite film;

[0102] Among them, the annealing atmosphere is air, the annealing temperature is 620 °C, the annealing duration is 0.5 h, and the annealing is carried out in a PECVD chamber. The thickness of the second composite film formed by annealing is 40 nm.

[0103] (7) Form a silicon oxide film on the second composite film;

[0104] Among them, the silicon oxide film is formed by PECVD. Among them, the flow rate of SiH4 is 200 sccm, and the flow rate of N2O is 1880 sccm; the radio frequency power is 85 W, the pressure in the PECVD chamber is 100 Pa, and the temperature is 240 °C. The thickness of the silicon oxide film is 100 nm.

[0105] (8) Open holes in the second composite film and the silicon oxide film in the areas where the first electrode and the second electrode are located to expose the first electrode and the second electrode.

[0106] Example 2

[0107] This example provides a method for manufacturing a high extraction efficiency LED chip, which includes the following steps:

[0108] (1) Provide an epitaxial wafer;

[0109] Among them, the epitaxial wafer includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0110] (2)Form a transparent conductive layer on the second semiconductor layer by PVD;

[0111] Among them, the transparent conductive layer is an ITO layer with a thickness of 80 nm;

[0112] (3)Etch to form an exposed area exposing the first semiconductor layer;

[0113] (4)Evaporate to form a first electrode and a second electrode to obtain an intermediate;

[0114] Among them, the first electrode is formed on the first semiconductor layer in the exposed area, and the second electrode is formed on the transparent conductive layer;

[0115] (5)Using silicon and copper as targets, sputter to form a first composite film on the surface of the intermediate;

[0116] Among them, co-sputtering is performed on both. The sputtering power of the copper target is 15 W, the sputtering power of the silicon target is 50 W, and the sputtering time is 5 min; the sputtering gas is Ar, the air pressure is 6 mtorr, and the sputtering temperature is 25 °C.

[0117] (6)Anneal the first composite film once in an Ar atmosphere;

[0118] Among them, the annealing duration is 5 min, the annealing temperature is 820 °C, and the annealing is carried out in a PECVD chamber.

[0119] (7)Anneal the first composite film after the first annealing in an oxygen-containing atmosphere for the second time to obtain a second composite film;

[0120] Among them, the annealing atmosphere is air, the annealing temperature is 620 °C, the annealing duration is 0.5 h, and the annealing is carried out in a PECVD chamber. The thickness of the second composite film formed by annealing is 40 nm.

[0121] (8)Form a silicon oxide film on the second composite film;

[0122] Among them, the silicon oxide film is formed by PECVD. Among them, the flow rate of SiH4 is 200 sccm, and the flow rate of N2O is 1880 sccm; the radio frequency power is 85 W, the pressure in the PECVD chamber is 100 Pa, and the temperature is 240 °C. The thickness of the silicon oxide film is 100 nm.

[0123] (9)Open holes in the second composite film and the silicon oxide film in the areas where the first electrode and the second electrode are located to expose the first electrode and the second electrode.

[0124] Example 3

[0125] This example provides a method for fabricating a high extraction efficiency LED chip, which includes the following steps:

[0126] (1)Provide an epitaxial wafer;

[0127] Among them, the epitaxial wafer includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0128] (2)Form a transparent conductive layer on the second semiconductor layer by PVD;

[0129] Among them, the transparent conductive layer is an ITO layer with a thickness of 80 nm;

[0130] (3)Etch to form a bare area exposing the first semiconductor layer;

[0131] (4)Evaporate to form a first electrode and a second electrode to obtain an intermediate;

[0132] Among them, the first electrode is formed on the first semiconductor layer in the bare area, and the second electrode is formed on the transparent conductive layer;

[0133] (5)Using silicon and copper as targets, sputter to form a first composite film on the surface of the intermediate;

[0134] Among them, first sputter the copper target for 20 s, then co-sputter the copper target and the silicon target for 4 min, and finally sputter the silicon target for 40 s. The sputtering power of the copper target is 15 W, the sputtering power of the silicon target is 50 W, the sputtering gas is Ar, the gas pressure is 6 mtorr, and the sputtering temperature is 25 °C.

[0135] (6)Anneal the first composite film once in an Ar atmosphere;

[0136] Among them, the annealing duration is 5 min, the annealing temperature is 820 °C, and the annealing is carried out in a PECVD chamber.

[0137] (7)Anneal the first composite film after the first annealing in an oxygen-containing atmosphere for the second time to obtain a second composite film;

[0138] Among them, the annealing atmosphere is air, the annealing temperature is 620 °C, the annealing duration is 0.5 h, and the annealing is carried out in a PECVD chamber. The thickness of the second composite film formed by annealing is 40 nm.

[0139] (8)Form a silicon oxide film on the second composite film;

[0140] Among them, the silicon oxide film is formed by PECVD. Among them, the flow rate of SiH4 is 200 sccm, and the flow rate of N2O is 1880 sccm; the radio frequency power is 85 W, the pressure in the PECVD chamber is 100 Pa, and the temperature is 240 °C. The thickness of the silicon oxide film is 100 nm.

[0141] (9)Open holes in the second composite film and the silicon oxide film in the areas where the first electrode and the second electrode are located to expose the first electrode and the second electrode.

[0142] Example 4

[0143] This embodiment provides a method for fabricating a high light extraction efficiency LED chip, which includes the following steps:

[0144] (1) Provide an epitaxial wafer;

[0145] Among them, the epitaxial wafer includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0146] (2) Form a transparent conductive layer on the second semiconductor layer by PVD;

[0147] Among them, the transparent conductive layer is an ITO layer with a thickness of 80 nm;

[0148] (3) Etch to form a bare area exposing the first semiconductor layer;

[0149] (4) Evaporate to form a first electrode and a second electrode to obtain an intermediate;

[0150] Among them, the first electrode is formed on the first semiconductor layer in the bare area, and the second electrode is formed on the transparent conductive layer;

[0151] (5) Use silicon and copper as targets to sputter-form a first composite film on the surface of the intermediate;

[0152] Among them, first sputter the copper target for 20 s, then co-sputter the copper target and the silicon target for 4 min, and finally sputter the silicon target for 40 s. The sputtering power of the copper target is 15 W, the sputtering power of the silicon target is 50 W, the sputtering gas is Ar, the gas pressure is 6 mtorr, and the sputtering temperature is 25 °C.

[0153] (6) Anneal the first composite film once in an Ar atmosphere;

[0154] Among them, the annealing duration is 5 min, the annealing temperature is 820 °C, and the annealing is carried out in a PECVD chamber.

[0155] (7) Anneal the first composite film after the first annealing in an oxygen-containing atmosphere for the second time to obtain a second composite film;

[0156] Among them, the annealing atmosphere is air, the annealing temperature is 620 °C, the annealing duration is 0.5 h, and the annealing is carried out in a PECVD chamber. The thickness of the second composite film formed by annealing is 40 nm.

[0157] (8) Sequentially form a first silicon oxide film and a second silicon oxide film on the second composite film;

[0158] Among them, the first silicon oxide film and the second silicon oxide film are formed by PECVD. The porosity of the first silicon oxide film is 22% and the thickness is 10 nm; the porosity of the second silicon oxide film is 44% and the thickness is 90 nm.

[0159] During the formation of the first silicon oxide film, the flow rate of SiH4 is 450 sccm, and the flow rate of N2O is 1880 sccm; the radio frequency power is 90 W, the pressure in the PECVD chamber is 90 Pa, and the temperature is 230 °C. During the formation of the second silicon oxide film, the flow rate of SiH4 is 200 sccm, and the flow rate of N2O is 1880 sccm; the radio frequency power is 90 W, the pressure in the PECVD chamber is 90 Pa, and the temperature is 230 °C.

[0160] (9)Open holes in the second composite film and the silicon oxide film in the regions where the first electrode and the second electrode are located to expose the first electrode and the second electrode.

[0161] Comparative Example 1

[0162] This comparative example provides a method for preparing an LED chip, and the difference from Example 1 is that:

[0163] The second composite film is not formed, that is, steps (5) to (6) are not included.

[0164] The rest is the same as in Example 1.

[0165] Comparative Example 2

[0166] This comparative example provides a method for preparing an LED chip, and the difference from Example 1 is that:

[0167] The silicon oxide film is not formed, that is, step (7) is not included.

[0168] The rest is the same as in Example 1.

[0169] Comparative Example 3

[0170] This comparative example provides a method for preparing an LED chip, and the difference from Example 1 is that:

[0171] The first composite film is not annealed, that is, step (6) is not included.

[0172] The rest is the same as in Example 1.

[0173] Prepare surface-mounted LED chips with a size of 10 mil * 24 mil according to the preparation methods of Examples 1 to 4 and Comparative Examples 1 to 3, and test them, specifically including:

[0174] (1) Test its brightness at 200 mA, and calculate the brightness improvement rate based on the data of the comparative example, where the brightness improvement rate = (brightness of the example / brightness of the comparative example - brightness of Comparative Example 1) / brightness of Comparative Example 1 × 100%;

[0175] (2) Light the LED chip at 85 °C, 85% RH, and a current of 5 mA for 1000 h, and use -10 V to test the leakage characteristics. A leakage failure is judged if it is ≥ 1 μA, and it is effective if it is less.

[0176] The specific test data are shown in the following table:

[0177]

[0178] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0179] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a high light extraction efficiency LED chip, characterized in that: include: Providing an epitaxial wafer, the epitaxial wafer comprising a substrate, a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence; forming a transparent conductive layer on the epitaxial wafer; wherein the transparent conductive layer is formed on the second semiconductor layer; Etching to form an exposed area exposing the first semiconductor layer; Forming a first electrode and a second electrode to obtain an intermediate; wherein the first electrode is formed on the first semiconductor layer in the exposed area, and the second electrode is formed on the transparent conductive layer; Using silicon and copper as targets, sputtering to form a first composite film on the surface of the intermediate; wherein the copper target is sputtered first and then the copper target and the silicon target are co-sputtered; annealing the first composite film in an oxygen-containing atmosphere at 550-700° C. to obtain a second composite film; forming a silicon oxide film on the second composite film; Openings are made in the second composite film and the silicon oxide film in the regions where the first electrode and the second electrode are located, so as to at least partially expose the first electrode and the second electrode.

2. The method for preparing a high light extraction efficiency LED chip according to claim 1, characterized in that: In the step of sputtering the first composite film on the surface of the intermediate using silicon and copper as targets, the sputtering power of the copper target is 10-20W, the sputtering power of the silicon target is 30-60W, the sputtering time is 2-5min; the sputtering gas is Ar, the gas pressure is 4-8mtorr, and the sputtering temperature is 20-50°C; In the step of annealing the first composite film in an oxygen-containing atmosphere at 550-700° C. to obtain the second composite film, the annealing atmosphere is air, the annealing time is 0.3-1 h, and the annealing is performed in a PECVD chamber.

3. The method for preparing a high light extraction efficiency LED chip according to claim 1, characterized in that: Using silicon and copper as targets, in the step of sputtering to form a first composite film on the surface of the intermediate, first sputter the copper target for 10 to 20 seconds, then sputter the copper target and the silicon target for 2 to 4 minutes, and finally sputter the silicon target for 20 to 40 seconds; The step of annealing the first composite film at 550-700° C. in an oxygen-containing atmosphere to obtain the second composite film comprises: Annealing the first composite film once in an Ar or N2 atmosphere at 800-900°C; The first composite film after the primary annealing is subjected to a secondary annealing in an oxygen-containing atmosphere at 550-700° C. to obtain a second composite film.

4. The method for preparing a high light extraction efficiency LED chip according to claim 3, characterized in that: In the step of annealing the first composite film in an Ar or N2 atmosphere at 800-900°C, the annealing atmosphere is Ar, the annealing time is 5-20 minutes, and the annealing is performed in a PECVD chamber; In the step of performing a secondary annealing on the first composite film after the primary annealing at 550-700° C. in an oxygen-containing atmosphere to obtain a second composite film, the annealing atmosphere is air, the annealing time is 0.3-1 h, and the annealing is performed in a PECVD chamber.

5. The method for preparing a high light extraction efficiency LED chip according to claim 1, characterized in that: In the step of forming a silicon oxide film on the second composite film, a first silicon oxide film and a second silicon oxide film are sequentially formed on the second composite film; The porosity of the first silicon oxide film is smaller than the porosity of the second silicon oxide film; The thickness of the first silicon oxide film is smaller than the thickness of the second silicon oxide film.

6. The method for preparing a high light extraction efficiency LED chip according to claim 5, characterized in that: The porosity of the first silicon oxide film is 15-30%, and the porosity of the second silicon oxide film is 35-55%; The thickness of the first silicon oxide film is 5-50 nm, and the thickness of the second silicon oxide film is 20-100 nm.

7. The method for preparing a high light extraction efficiency LED chip according to claim 5, characterized in that: The first silicon oxide film and the second silicon oxide film are both formed by PECVD; during the formation process, the radio frequency power is 80-100W, the pressure of the PECVD chamber is 80-120Pa, and the temperature is 200-250°C; The flow ratio of SiH 4 to N 2 O during the formation of the first silicon oxide film is greater than the flow ratio of SiH 4 to N 2 O during the formation of the second silicon oxide film.

8. The method for preparing a high light extraction efficiency LED chip according to claim 5, characterized in that: During the formation of the first silicon oxide film, the flow rate of SiH4 is 400-600 sccm, and the flow rate of N2O is 1800-2000 sccm; During the formation of the second silicon oxide film, the flow rate of SiH4 is 100-300 sccm, and the flow rate of N2O is 1800-2000 sccm.

9. The method for preparing a high light extraction efficiency LED chip according to claim 1, characterized in that: The thickness of the second composite film is 30-50 nm; The transparent conductive layer is an ITO layer or an AZO layer, and its thickness is 40-80 nm.

10. A high light extraction efficiency LED chip, characterized in that: The LED chip is prepared by the method for preparing a high light extraction efficiency LED chip as described in any one of claims 1 to 9.

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