Chip structure, manufacturing method thereof and display substrate

Abstract

The invention discloses a chip structure, a manufacturing method thereof and a display substrate, and belongs to the technical field of display. The chip structure comprises a first substrate, a light emitting unit, a color conversion unit and a box dam layer. The dam layer can be arranged around the light-emitting unit, and the maximum distance between the face, deviating from the color conversion unit, of the dam layer and the first substrate is larger than or equal to the maximum distance between the face, deviating from the first substrate, of the first semiconductor layer in the light-emitting unit and the first substrate. Therefore, after an optical waveguide phenomenon is generated in the first semiconductor layer, light which is transversely transmitted in the first semiconductor layer can be shielded by the box dam layer after being emitted from any position of the edge. Therefore, even if the light entering the first semiconductor generates an optical waveguide phenomenon, the light emitted from the edge of the first semiconductor can be shielded by arranging the box dam layer, so that the probability of light leakage of the chip structure can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a chip structure and a manufacturing method thereof, and a display substrate. Background Art

[0002] With the development of display technology, the display substrate integrated with LED chips will become the most advantageous new generation display media and has been widely used because of its advantages of pure chromaticity, wide dynamic range, high brightness, high definition, low operating voltage, low power consumption, long life, impact resistance, large viewing angle and stable and reliable operation. Summary of the invention

[0003] The embodiment of the present application provides a chip structure and a manufacturing method thereof, and a display substrate. The technical solution is as follows:

[0004] In one aspect, a chip structure is provided, comprising: a first substrate, a light-emitting unit and a color conversion unit, wherein the color conversion unit is located at a light-emitting side of the light-emitting unit, and the color conversion unit is closer to the first substrate than the light-emitting unit;

[0005] The light-emitting unit comprises: a plurality of sub-light-emitting functional layers, and a first semiconductor layer located at the light-emitting side of the plurality of sub-light-emitting functional layers, the first semiconductor layer comprises: a plurality of connecting parts corresponding to the plurality of sub-light-emitting functional layers one by one, and an auxiliary part connected to the plurality of connecting parts, the connecting parts are connected to the corresponding sub-light-emitting functional layers, at least part of the auxiliary part is located between adjacent connecting parts, and the auxiliary part and the connecting part are an integral structure;

[0006] The chip structure further includes: a dam layer arranged around the light-emitting unit, wherein the maximum distance between the first substrate and a side of the dam layer facing away from the color conversion unit is greater than or equal to the maximum distance between the first semiconductor layer and a side facing away from the first substrate.

[0007] Optionally, the multiple light-emitting functional layers in the light-emitting unit are all used to emit a first light; the dam layer is used to absorb the light in the first light emitted by the sub-light-emitting functional layer that is laterally transmitted in the first semiconductor layer, so that when the chip structure only emits red light under the action of the color conversion unit, the brightness of the first light accounts for less than or equal to 3% of the brightness of the red light, and when the chip structure only emits green light under the action of the color conversion unit, the brightness of the first light accounts for less than or equal to 3% of the brightness of the green light.

[0008] Optionally, an orthographic projection of the dam layer on the first substrate overlaps with an orthographic projection of the color conversion unit on the first substrate;

[0009] The orthographic projection of one side of the dam layer facing away from the first substrate on the first substrate is used to enclose an enclosing area, and the orthographic projection of the light-emitting unit on the first substrate is located in the enclosing area, or the orthographic projection of the light-emitting unit on the first substrate is located in the enclosing area after translation.

[0010] Optionally, the chip structure further includes: a connection layer, at least a portion of which is located between the light-emitting unit and the color conversion unit, and the connection layer includes: any one of an indium zinc oxide connection layer, a metal connection layer and an adhesive layer.

[0011] Optionally, when the connecting layer includes the adhesive layer, the connecting layer includes: a first filling portion and a second filling portion, the first filling portion is located between the light-emitting unit and the color conversion unit, and the second filling portion is located between the dam layer and the light-emitting unit.

[0012] Optionally, the connection layer further includes: an overflow portion, wherein the overflow portion is located on a side of the dam layer facing away from the first substrate.

[0013] Optionally, a thickness of a portion of the connection layer located between the light-emitting unit and the color conversion unit is between 0.3 micrometers and 3 micrometers.

[0014] Optionally, the light-emitting unit further comprises an electrode structure arranged opposite to the first semiconductor layer, and a maximum distance between a side of the electrode structure facing away from the first substrate and the first substrate is greater than or equal to a maximum distance between a side of the dam layer facing away from the color conversion unit and the first substrate.

[0015] Optionally, the material of the first substrate is glass, and the thickness of the first substrate is between 50 micrometers and 120 micrometers.

[0016] Optionally, the color conversion unit includes:

[0017] A light shielding layer located on one side of the first substrate, the light shielding layer having a plurality of light through holes;

[0018] a limiting dam layer located on a side of the light shielding layer away from the first substrate, the limiting dam layer having a plurality of opening areas corresponding one-to-one to the plurality of light through holes, and the plurality of opening areas corresponding one-to-one to the plurality of sub-light emitting functional layers, an orthographic projection of the opening area on the first substrate overlapping with an orthographic projection of a corresponding light through hole on the first substrate, and overlapping with an orthographic projection of a corresponding sub-light emitting functional layer on the substrate;

[0019] An optical functional layer located in the opening area, at least a portion of the optical functional layer is used to convert the color of light entering the optical functional layer;

[0020] a first encapsulation layer located on a side of the definition dam layer away from the first substrate;

[0021] The light-emitting unit is located on a side of the first encapsulation layer away from the first substrate, and at least a portion of the dam layer is located on a side of the first encapsulation layer away from the first substrate.

[0022] Optionally, the definition dam layer has: a first surface facing the first substrate, a second surface facing away from the first substrate, and a first outer contour surface located between the first surface and the second surface, wherein the first outer contour surface is a surface that is entirely arranged around the definition dam layer;

[0023] Wherein, the angle between the first surface and the first outer contour surface is an obtuse angle.

[0024] Optionally, the distance between the first surface and the second surface ranges from 5 micrometers to 15 micrometers; and the angle between the first surface and the first outer contour surface ranges from 90° to 130°.

[0025] Optionally, the material defining the dam layer includes: an organic material with light absorption or an organic material with light reflection.

[0026] Optionally, each of the sub-light-emitting functional layers includes a light-emitting layer;

[0027] In a direction parallel to the extension surface of the first substrate, the minimum distance between the outer contour of the light-emitting layer in any of the sub-light-emitting functional layers and the boundary of the opening surface of the adjacent opening area away from the first substrate is in a range of 22 microns to 90 microns.

[0028] Optionally, each of the sub-light-emitting functional layers includes a light-emitting layer;

[0029] In the case where the chip structure includes a connection layer, and the material of the connection layer includes an adhesive layer, in a direction parallel to the extension surface of the first substrate, the minimum distance range L between the outer contour of the light-emitting layer in any of the sub-light-emitting functional layers and the boundary of the opening surface of the adjacent opening area away from the first substrate side satisfies the following relationship:

[0030] L=k1×(h1×tanθ1+h2×tanθ2+d01);

[0031] Among them, h1 represents the thickness of the first semiconductor layer, h2 represents the thickness of the first filling part in the connecting layer, the value range of θ1 is between 30° and 45°, the value range of θ2 is between 80° and 85°, the value range of d01 is between 2 microns and 7 microns, and the value range of k1 is between 0.8 and 1.2.

[0032] Optionally, the first encapsulation layer includes: a first encapsulation portion disposed in contact with the second surface, and a second encapsulation portion disposed in contact with the outer contour surface;

[0033] The dam layer is entirely located on a side of the first encapsulation portion away from the first substrate, or a portion of the dam layer is located on a side of the first encapsulation portion away from the first substrate, and another portion is located on a side of the second encapsulation portion away from the defining dam layer.

[0034] Optionally, the first encapsulation layer is a film layer structure that is continuously distributed at various positions, and the orthographic projections of the limiting dam layer and the optical functional layer on the first substrate are both located within the orthographic projection of the first encapsulation layer on the first substrate;

[0035] The chip structure further includes: a second encapsulation layer located between the limiting dam layer and the light shielding layer;

[0036] The second encapsulation layer is arranged in contact with the first encapsulation layer to completely wrap the definition dam layer and the optical functional layer, and the area where the second encapsulation layer contacts the first encapsulation layer is distributed around the definition dam layer.

[0037] Optionally, in a case where the dam layer is entirely located on a side of the first encapsulation portion in the first encapsulation layer facing away from the first substrate, the dam layer has: a third surface bonded to the first encapsulation portion, and a fourth surface arranged opposite to the third surface;

[0038] Wherein, in a direction parallel to the extending surface of the first substrate, the width of the third surface is greater than or equal to 6.5 microns, and the width of the fourth surface is greater than or equal to 11.5 microns.

[0039] Optionally, in a direction parallel to the extending surface of the first substrate, a minimum distance between an outer contour of the limiting dam layer facing away from the first substrate and a boundary of the opening area facing away from the open surface of the first substrate is greater than or equal to 20 microns.

[0040] Optionally, in a direction parallel to the extension surface of the first substrate, a minimum distance D2 between an outer contour of the limiting dam layer facing away from the first substrate and a boundary of the opening area facing away from the open surface of the first substrate satisfies the following relationship:

[0041] D2=k2×(D1+d02+d03+d04);

[0042] Among them, D1 represents the width of the fourth surface in a direction parallel to the extension surface of the first substrate, the value ranges of d02 and d03 are both between 2 microns and 7 microns, the value range of d04 is between 1 micron and 3 microns, and the value range of k2 is between 0.8 and 1.2.

[0043] Optionally, in a direction parallel to the extending surface of the first substrate, a minimum width between opening surfaces of two adjacent opening regions facing away from the first substrate is in a range of 18 micrometers to 80 micrometers.

[0044] Optionally, in a direction parallel to the extension surface of the first substrate, a minimum width range D4 between opening surfaces of two adjacent opening regions facing away from the first substrate satisfies the following relationship:

[0045] D4 = k3 × [L - (J1 - J2) / 2];

[0046] Among them, L represents the minimum distance range between the outer contour of the light-emitting layer in any of the sub-light-emitting functional layers and the boundary of the opening surface of the adjacent opening area away from the first substrate side in the direction parallel to the extension surface of the first substrate; J1 represents the width range of the opening surface of the opening area away from the first substrate in the arrangement direction of two adjacent opening areas; J2 represents the width range of the light-emitting layer in the arrangement direction of two adjacent opening areas; and the value range of k3 is between 0.8 and 1.2.

[0047] Optionally, the dam layer further has: a second outer contour surface located between the third surface and the fourth surface, the second outer contour surface being a surface that entirely surrounds the limiting dam layer;

[0048] The included angle between the second outer contour surface and the third surface is an obtuse angle, and the included angle between the second outer contour surface and the third surface ranges from 120° to 140°.

[0049] Optionally, a distance between the third surface and the fourth surface in the dam layer ranges from 4.3 microns to 15 microns.

[0050] Optionally, the plurality of sub-light-emitting functional layers include: a first sub-light-emitting functional layer, a second sub-light-emitting functional layer and a third sub-light-emitting functional layer;

[0051] The plurality of opening regions include: a first opening region, a second opening region and a third opening region, the first opening region is arranged opposite to the first sub-light-emitting functional layer, the second opening region is arranged opposite to the second sub-light-emitting functional layer, and the third opening region is arranged opposite to the third sub-light-emitting functional layer;

[0052] The first opening area and the second opening area are arranged in a row in a first direction, the second opening area and the third opening area are arranged in a row in a second direction, and the first direction intersects with the second direction;

[0053] The area enclosed by the outer contour of the dam layer is a rectangle; the shapes of the first opening area, the second opening area and the third opening area are all rectangles.

[0054] Optionally, the orthographic projection of the sub-light-emitting functional layer on the first substrate is located within the orthographic projection of the corresponding opening area on the first substrate; the ratio of the area of ​​the opening surface of the opening area facing away from the first substrate to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer on the first substrate is in a range of 4 to 6.25.

[0055] Optionally, an orthographic projection of a surface of the limiting dam layer facing the first substrate on the first substrate is located within an orthographic projection of the light shielding layer on the first substrate.

[0056] Optionally, the color conversion unit also includes: a filter layer located between the first substrate and the optical functional layer; the filter layer includes a plurality of filter units corresponding one by one to the plurality of light passage holes, and the orthographic projection of the filter unit on the first substrate overlaps with the orthographic projection of the corresponding light passage hole on the first substrate.

[0057] Optionally, the material of the dam layer includes: any one of an organic material with light absorption, an organic material with light reflection and an organic material with light filtering.

[0058] Optionally, the multiple light-emitting functional layers in the light-emitting unit are all used to emit a first light; when the dam layer is made of an organic material with a light-filtering property, the dam layer is used to absorb the first light and transmit light of other colors.

[0059] Optionally, the first light is at least one of blue light and ultraviolet light; the dam layer is a green filter layer for transmitting green light, or the dam layer is a red filter layer for transmitting red light.

[0060] Optionally, in the case where the dam layer is the red filter layer, the chip structure further comprises: an auxiliary light-shielding layer located between the dam layer and the first encapsulation layer, the orthographic projection of the dam layer on the first substrate being located within the orthographic projection of the auxiliary light-shielding layer on the first substrate;

[0061] The auxiliary light-shielding layer has a plurality of auxiliary light-through holes corresponding one-to-one to the plurality of light-through holes, and the orthographic projections of the auxiliary light-through holes on the first substrate overlap with the orthographic projections of the corresponding light-through holes on the first substrate.

[0062] Optionally, the light emitting unit further includes: a first electrode connected to the first semiconductor layer;

[0063] The auxiliary part includes a first auxiliary part, a second auxiliary part and a third auxiliary part; the orthographic projection of the first auxiliary part on the first substrate overlaps with the orthographic projection of the first electrode on the first substrate; a part of the second auxiliary part is located between the adjacent connecting parts, and another part is located between the first auxiliary part and the connecting part; the third auxiliary part is arranged around the first auxiliary part, the second auxiliary part and the plurality of connecting parts, and the material of the auxiliary part is the same as that of the connecting part;

[0064] The sub-light emitting functional layer includes: a second electrode, a second semiconductor layer and the light emitting layer which are stacked vertically and toward the first substrate; wherein the light emitting layer is connected to a corresponding connecting portion in the first semiconductor layer.

[0065] Optionally, the first semiconductor layer includes: a first sublayer and a second sublayer stacked in a direction vertical to and toward the first substrate, the first sublayer is located between the second sublayer and the light-emitting layer, the material of the first sublayer is N-type doped gallium nitride, and the second sublayer is a gallium nitride buffer layer;

[0066] The material of the second semiconductor layer includes P-type doped gallium nitride, and the light-emitting layer is a multi-quantum well layer.

[0067] On the other hand, a display substrate is provided, comprising: a driving backplane, and a plurality of chip structures arranged in an array on one side of the driving backplane, wherein the chip structure is the above-mentioned chip structure.

[0068] In another aspect, a method for manufacturing a chip structure is provided, the method being used to prepare the above-mentioned chip structure, the method comprising:

[0069] Forming a first initial wafer including a plurality of the color conversion units, the first initial wafer comprising: a second substrate, a plurality of color conversion units distributed on one side of the second substrate, and a dam layer distributed on a side of each of the color conversion units away from the second substrate;

[0070] forming a second initial wafer including a plurality of the light emitting units, wherein the second initial wafer comprises: a temporary substrate, and a plurality of the light emitting units located on the temporary substrate;

[0071] forming an adhesive on the second initial wafer;

[0072] Aligning the second initial wafer with the first initial wafer so that the light-emitting unit is connected to the corresponding color conversion unit through the adhesive;

[0073] removing the temporary substrate to obtain a motherboard wafer, and performing an ashing process on the motherboard wafer to remove the colloid remaining on the dam layer away from the second substrate;

[0074] The second substrate is thinned, and the thinned second substrate is cut to cut the motherboard wafer into a plurality of chip structures.

[0075] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0076] A chip structure includes: a first substrate, a light-emitting unit, a color conversion unit, and a dam layer. Since the dam layer can be arranged around the light-emitting unit, and the maximum distance between the side of the dam layer facing away from the color conversion unit and the first substrate is greater than or equal to the maximum distance between the side of the first semiconductor layer in the light-emitting unit facing away from the first substrate and the first substrate. Therefore, after the light waveguide phenomenon occurs inside the first semiconductor layer, the light that is laterally transmitted in the first semiconductor layer can be blocked by the dam layer after it is emitted from any position of the edge. In this way, even if the light entering the first semiconductor generates the light waveguide phenomenon, the light emitted from the edge of the first semiconductor can be blocked by setting the dam layer, thereby effectively reducing the probability of light leakage in the chip structure, so that the display effect of the display substrate integrated with this chip structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0078] Figure 1is a top view of a chip structure provided in an embodiment of the present application;

[0079] Figure 2 yes Figure 1 The schematic diagram of the film layer structure of the chip structure at AA' is shown;

[0080] Figure 3 is a top view of a first semiconductor layer provided in an embodiment of the present application;

[0081] Figure 4 This is an effect diagram of an optical waveguide phenomenon generated inside the first semiconductor layer provided by an embodiment of the present application;

[0082] Figure 5 is a top view of a light-emitting unit located on a connecting layer provided in an embodiment of the present application;

[0083] Figure 6 yes Figure 5 The schematic diagram of the film structure of the light-emitting unit at BB' is shown;

[0084] Figure 7 is a top view of another first semiconductor layer provided in an embodiment of the present application;

[0085] Figure 8 is a top view of another light-emitting unit provided in an embodiment of the present application;

[0086] Fig. 9 yes Figure 8 The schematic diagram of the film structure of the light-emitting unit at CC' is shown;

[0087] Fig.10 is a schematic diagram of a membrane layer structure of another chip structure provided in an embodiment of the present application;

[0088] Fig.11 This is a schematic diagram of a film layer structure of another chip structure provided in an embodiment of the present application;

[0089] Fig.12 is a top view of another chip structure provided in an embodiment of the present application;

[0090] Fig.13 yes Fig.12 The schematic diagram of the film layer structure of the chip structure at D-D' is shown;

[0091] Fig.14 yes Fig.12 The schematic diagram of the film layer structure of the chip structure at position EE' is shown;

[0092] Fig.15 is a schematic diagram of a film layer structure of a chip structure provided by another embodiment of the present application;

[0093] Fig.16 is a schematic diagram of a membrane layer structure of another chip structure provided by another embodiment of the present application;

[0094] Fig.17 is a schematic diagram of a film layer structure of a chip structure provided by another embodiment of the present application;

[0095] Fig.18 is a schematic diagram of a film layer structure of another chip structure provided by yet another embodiment of the present application;

[0096] Fig.19 is a schematic diagram of a film layer structure of another chip structure provided by another embodiment of the present application;

[0097] Fig. 20 This is a schematic diagram of the structure of a first large board provided in an embodiment of the present application;

[0098] Fig.21 is a schematic structural diagram of a first initial wafer provided in an embodiment of the present application;

[0099] Fig. 22 is a schematic structural diagram of a second initial wafer provided in an embodiment of the present application;

[0100] Fig.23 is a schematic diagram of a film structure of forming a plurality of light-emitting units on a third substrate according to an embodiment of the present application;

[0101] Fig.24 is a schematic structural diagram of a second initial wafer provided in an embodiment of the present application;

[0102] Fig.25 This is a rendering of a second initial wafer and a first initial wafer bonded together according to an embodiment of the present application;

[0103] Fig.26 It is a structural schematic diagram of a motherboard wafer provided in an embodiment of the present application;

[0104] Fig. 27 It is a simplified schematic diagram of the internal light path of a chip structure provided in an embodiment of the present application when emitting light;

[0105] Fig.28 is a schematic diagram of a film layer structure of a chip structure provided in yet another embodiment of the present application;

[0106] Fig.29 is a schematic diagram of a membrane layer structure of another chip structure provided by yet another embodiment of the present application;

[0107] Fig.30 is a schematic diagram of a film layer structure of another chip structure provided by yet another embodiment of the present application;

[0108] Fig.31 This is a top view of a defined dam layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0109] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0110] Please refer to Figure 1 and Figure 2 , Figure 1 is a top view of a chip structure provided in an embodiment of the present application, Figure 2 yes Figure 1 The schematic diagram of the film layer structure of the chip structure at AA' is shown. The chip structure 000 may include: a first substrate 100, a light-emitting unit 300 and a color conversion unit 200. The color conversion unit 200 in the chip structure 000 may be located at the light-emitting side of the light-emitting unit 300. In a possible implementation, the color conversion unit 200 in the chip structure 000 is closer to the first substrate 100 than the light-emitting unit 300. That is, the color conversion unit 200 in the chip structure 000 may be located on one side of the first substrate 100, and the light-emitting unit 300 in the chip structure 000 may be located on the side of the color conversion unit 200 away from the first substrate 100. In this case, the light emitted by the light-emitting unit 300 may be emitted toward the color conversion unit 200, and then emitted after passing through the color conversion unit 200 and the first substrate 100.

[0111] The light emitting unit 300 in the chip structure 000 may include: a plurality of sub-light emitting functional layers 300a, and a first semiconductor layer 301 located on the light emitting side of the plurality of sub-light emitting functional layers 300a. To more clearly see the structure of the first semiconductor layer 301, please refer to Figure 3 , Figure 3 It is a top view of a first semiconductor layer provided in an embodiment of the present application. The first semiconductor layer 301 may include: a plurality of connection parts 3011 corresponding one-to-one to the plurality of sub-light-emitting functional layers 300a, and an auxiliary part 3012 connected to the plurality of connection parts 3011.

[0112] In which, each connecting portion 3011 in the first semiconductor layer 301 can be connected to the corresponding sub-light-emitting functional layer 300a, and the outer boundary of the orthographic projection of each connecting portion 3011 on the first substrate 100 can completely coincide with the outer boundary of the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100.

[0113] In the present application, the multiple connection parts 3011 and the auxiliary parts 3012 in the first semiconductor layer 301 are an integral structure, and the material of the connection parts 3011 in the first semiconductor layer 301 can be the same as the material of the auxiliary parts 3012. It can be understood that the multiple connection parts 3011 and the auxiliary parts 3012 in the first semiconductor layer 301 are arranged in a direction parallel to the extension surface of the first substrate 100, and the first semiconductor layer 301 is a planar structure arranged in an entire layer, and all parts of the first semiconductor layer 301 except the multiple connection parts 3011 are auxiliary parts 3012. The multiple connection parts 3011 can be connected through the auxiliary parts 3012 in the first semiconductor layer 301.

[0114] In the embodiment of the present application, the light emitted from the sub-light-emitting functional layer 300a in the light-emitting unit 300 first passes through the first semiconductor layer 301, and then is emitted toward the color conversion unit 200 and the first substrate 100. However, since the first semiconductor layer 301 is a planar structure arranged in an entire layer, part of the light emitted toward the inside of the first semiconductor layer 301 is very likely to generate an optical waveguide phenomenon inside the first semiconductor layer 301. For example, please refer to Figure 4 , Figure 4 This is a rendering of an optical waveguide phenomenon generated inside the first semiconductor layer provided by an embodiment of the present application. Part of the light entering the first semiconductor layer 301 can be totally reflected back and forth multiple times between two oppositely arranged planes in the first semiconductor layer 301, and transmitted laterally, and finally emitted from the edge of the first semiconductor layer 301. After the optical waveguide phenomenon is generated inside the first semiconductor layer 301, the light emitted from the edge of the first semiconductor layer 301 may not be absorbed by the light shielding layer in the color conversion unit 200, which may cause the chip structure 000 to easily leak light.

[0115] For this reason, Figure 2 As shown, the chip structure 000 in the present application may further include: a dam layer 400 disposed around the light-emitting unit 300. The maximum distance H1 between the side of the dam layer 400 facing away from the color conversion unit 200 and the first substrate 100 is greater than or equal to the maximum distance H2 between the side of the first semiconductor layer 301 facing away from the first substrate 100 and the first substrate 100.

[0116] Here, the dam layer 400 in the chip structure 000 is used to absorb the light emitted by the sub-light-emitting functional layer 300a and the light transmitted laterally in the first semiconductor layer 301. That is, after the light emitted by the sub-light-emitting functional layer 300a enters the first semiconductor layer 301 and generates an optical waveguide phenomenon in the first semiconductor layer 301, the light transmitted laterally in the first semiconductor layer 301 can be absorbed by the dam layer 400.

[0117] Furthermore, since the dam layer 400 is disposed around the light-emitting unit 300, and the maximum distance H1 between the side of the dam layer 400 facing away from the color conversion unit 200 and the first substrate 100 is greater than or equal to the maximum distance H2 between the side of the first semiconductor layer 301 facing away from the first substrate 100 and the first substrate 100, after the optical waveguide phenomenon is generated inside the first semiconductor layer 301, the light transmitted laterally in the first semiconductor layer 301 can be blocked by the dam layer 400 after being emitted from any position of the edge.

[0118] In this case, even if the light entering the first semiconductor 301 generates an optical waveguide phenomenon, the dam layer 400 can be provided to block the light emitted from the edge of the first semiconductor 301 , thereby effectively reducing the probability of light leakage in the chip structure 000 .

[0119] Exemplarily, the plurality of light-emitting functional layers 300a in the light-emitting unit 300 are all used to emit a first light, and the first light includes at least one of blue light and ultraviolet light. Under the action of the color conversion unit 200 in the chip structure 000, the chip structure 000 can emit at least one of red light, green light and blue light. Here, since the dam layer 400 in the chip structure 000 can absorb the light that is laterally transmitted in the first semiconductor layer 301 in the first light emitted by the sub-light-emitting functional layer 300a, it can be ensured that the brightness of the first light leaked from the edge of the chip structure 000 is low during the process of the chip structure 000 emitting only red light or green light under the action of the color conversion unit 200. Exemplarily, after controlling the chip structure 000 to emit only red light or green light, the light within the light emission range of -90° to 90° can be received by the light receiver, and then the proportion of the brightness of the first light to the brightness of the red light or the green light can be determined.

[0120] Here, when the chip structure 000 emits only red light under the action of the color conversion unit 200, the proportion of the brightness of the first light to the brightness of the red light is less than or equal to 3%; when the chip structure 000 emits only green light under the action of the color conversion unit 200, the proportion of the brightness of the first light to the brightness of the green light is less than or equal to 3%. Preferably, when the chip structure 000 emits only red light under the action of the color conversion unit 200, the proportion of the brightness of the first light to the brightness of the red light is less than or equal to 0.5%; when the chip structure 000 emits only green light under the action of the color conversion unit 200, the proportion of the brightness of the first light to the brightness of the green light is less than or equal to 2%. In this way, it can be ensured that the overall color deviation of this chip structure 000 is less than or equal to 0.02, so that the display effect of the display substrate integrated with this chip structure is better.

[0121] Optional, such as Figure 2As shown, the orthographic projection of the dam layer 400 in the chip structure 000 on the first substrate 100 can overlap with the orthographic projection of the color conversion unit 200 on the first substrate 100. The orthographic projection of the side of the dam layer 400 facing away from the first substrate 100 on the first substrate 100 is used to enclose an enclosed area. In the present application, the area of ​​this enclosed area can be greater than or equal to the area of ​​the orthographic projection of the light-emitting unit 300 on the first substrate 100, so as to ensure that the light-emitting unit 300 can be smoothly arranged in the area enclosed by the dam layer 400, so that the light emitted from the edge of the first semiconductor layer 301 in the light-emitting unit 300 can all be directed to the dam layer 400, thereby making the dam layer 400 have a better absorption effect on the light emitted from the edge of the first semiconductor layer 301.

[0122] In a possible implementation, the orthographic projection of the light emitting unit 300 on the first substrate 100 may be located within the enclosed area.

[0123] In another possible implementation, since the light-emitting unit 300 and the color conversion unit 200 can be bonded by adhesive, during the bonding process between the light-emitting unit 300 and the color conversion unit 200 by adhesive, the color conversion unit 200 may be displaced in the horizontal direction and / or vertical direction relative to the light-emitting unit 300. Therefore, the orthographic projection of the first semiconductor layer 301 in the light-emitting unit 300 on the first substrate 100 and the orthographic projection of the side of the dam layer 400 facing away from the first substrate 100 on the first substrate 100 may have an overlapping area. In this case, after the light-emitting unit 300 and the color conversion unit 200 are bonded by adhesive, the orthographic projection of the light-emitting unit 300 on the first substrate 100 may be located within this enclosed area after translation.

[0124] In the embodiment of the present application, the light-emitting unit 300 further includes an electrode structure disposed opposite to the first semiconductor layer 301. Here, the electrode structure is used to be welded with the driving backplane, so that the chip structure 000 can be fixed on the driving backplane, and the driving backplane can drive the light-emitting unit 300 in the chip structure 000 to emit light through the electrode structure. It should be noted that the electrode structure is the first electrode and the second electrode described in the subsequent embodiments, and for this reason, the electrode structure is not described in detail here.

[0125] In the present application, the maximum distance between the electrode structure in the light-emitting unit 300 facing away from the first substrate 100 and the first substrate 100 is greater than or equal to the maximum distance between the dam layer 400 facing away from the color conversion unit 200 and the first substrate 100. In this way, it can be ensured that the dam layer 400 will not affect the welding between the light-emitting unit 300 and the driving backplane.

[0126] In summary, the chip structure of the embodiment of the present application includes: a first substrate, a light-emitting unit, a color conversion unit and a dam layer. Since the dam layer can be arranged around the light-emitting unit, and the maximum distance between the side of the dam layer facing away from the color conversion unit and the first substrate is greater than or equal to the maximum distance between the side of the first semiconductor layer in the light-emitting unit facing away from the first substrate and the first substrate. Therefore, after the light waveguide phenomenon occurs inside the first semiconductor layer, the light that is laterally transmitted in the first semiconductor layer can be blocked by the dam layer after it is emitted from any position of the edge. In this way, even if the light entering the first semiconductor generates the light waveguide phenomenon, the light emitted from the edge of the first semiconductor can be blocked by setting the dam layer, thereby effectively reducing the probability of light leakage in the chip structure, so that the display effect of the display substrate integrated with such a chip structure is better.

[0127] In the embodiment of the present application, the material of the first substrate 100 is glass. For example, the first substrate 100 can transmit visible light.

[0128] In the embodiment of the present application, the extension surface of the first substrate 100 (ie, the upper surface or the lower surface of the first substrate 100 ) may be a plane.

[0129] In an embodiment of the present application, the shape of the extended surface of the first substrate 100 in the chip structure 000 may be a rectangle, and the length and width of the first substrate 100 are both less than or equal to 500 microns. It should be noted that the length and width of the rectangle may also be the same, that is, the shape of the extended surface of the first substrate 100 may also be a square. In this case, the overall size of the chip structure 000 is relatively small, and after a plurality of such chip structures 000 are fixed on the driving backplane, the resolution of the resulting display substrate can be guaranteed to be high. For example, the length and width of the rectangle may range from 200 microns to 400 microns. In this case, the preparation process of the chip structure 000 can be simplified while ensuring that the overall size of the chip structure 000 is relatively small.

[0130] In the embodiment of the present application, the thickness of the first substrate 100 in the chip structure 000 is in the range of 50 microns to 120 microns. For example, the thickness of the first substrate 100 can be (80±5) microns. In this way, the thickness of the first substrate 100 can be ensured to be thinner, which is more convenient for obtaining the chip structure 000 through the cutting process, and the overall thickness of the chip structure 000 can be ensured to be smaller, so that the center of gravity of the chip structure 000 is lower, and then the stability of the chip structure 000 after being fixed on the driving backplane can be ensured to be higher.

[0131] In the present application, the light emitting unit 300 and the conversion unit 200 in the chip structure 000 can be bonded via a connection layer 500. That is, a connection layer 500 for bonding the two together is distributed between the light emitting unit 300 and the conversion unit 200. In order to more clearly see the structure of the light emitting unit 300 in the chip structure 000, please refer to Figure 5 and Figure 6 , Figure 5 is a top view of a light-emitting unit located on a connecting layer provided in an embodiment of the present application, Figure 6 yes Figure 5 The light emitting unit 300 may further include: a first electrode 302 connected to the first semiconductor layer 301 .

[0132] Each sub-light-emitting functional layer 300a in the light-emitting unit 300 may include: a second electrode 303, a second semiconductor layer 304 and a light-emitting layer 305 stacked in a direction perpendicular to and toward the first substrate 100. That is, the light-emitting layer 305 in the sub-light-emitting functional layer 300a is closer to the first semiconductor layer 301 than the second electrode 303.

[0133] The light-emitting layer 305 in each sub-light-emitting functional layer 300a may be connected to the first semiconductor layer 301. Here, since the first semiconductor layer 301 in the light-emitting unit 300 is located at the light-emitting side of each sub-light-emitting functional layer 300a, and the first semiconductor layer 301 is closer to the first substrate 100 than each sub-light-emitting functional layer 300a. Therefore, the first semiconductor layer 301 may contact the side of the light-emitting layer 305 in each sub-light-emitting functional layer 300a that is away from the second semiconductor layer 304.

[0134] In this application, please refer to Figure 7 , Figure 7 It is a top view of another first semiconductor layer provided by an embodiment of the present application. The auxiliary portion 3012 in the first semiconductor layer 301 may include: a first auxiliary portion 3012a, a second auxiliary portion 3012b and a third auxiliary portion 3013c.

[0135] The orthographic projection of the first auxiliary portion 3012a on the first substrate 100 may overlap with the orthographic projection of the first electrode 302 on the first substrate 100. For example, the outer boundary of the orthographic projection of the first auxiliary portion 3012a on the first substrate 100 coincides with the outer boundary of the orthographic projection of the first electrode 302 on the first substrate 100.

[0136] A portion of the second auxiliary portion 3012 b may be located between adjacent connecting portions 3011 , and another portion may be located between the first auxiliary portion 3012 a and the connecting portion 3011 .

[0137] The third auxiliary portion 3012 c may be disposed around the first auxiliary portion 3012 a , the second auxiliary portion 3012 b , and the plurality of connection portions 3011 .

[0138] To this end, the first auxiliary portion 3012a, the second auxiliary portion 3012b, the third auxiliary portion 3013c and the plurality of connecting portions 3011 in the first semiconductor layer 301 may form a planar structure arranged in an entire layer.

[0139] Optionally, in the light-emitting unit 300, the material of the second semiconductor layer 304 in each sub-light-emitting functional layer 300a may include: P-type doped gallium nitride; the light-emitting layer 305 in each sub-light-emitting functional layer 300a may be a multi-quantum well layer. Figure 6 As shown, the first semiconductor layer 301 may include: a first sublayer 301a and a second sublayer 301b stacked in a direction perpendicular to and toward the first substrate 100. That is, the second sublayer 301b is closer to the connection layer 500 than the first sublayer 301a. It can be understood that the first semiconductor layer 301 can be divided into: an auxiliary portion 3012 and a plurality of connection portions 3011 in a direction parallel to the extension surface of the first substrate 100, and the first semiconductor layer 301 can be divided into: a first sublayer 301a and a second sublayer 301b in a direction perpendicular to the extension surface of the first substrate 100.

[0140] The first sublayer 301a in the first semiconductor layer 301 may be located between the second sublayer 301b and the light-emitting layer 305 in each sub-light-emitting functional layer 300a, that is, the first sublayer 301a is closer to the light-emitting layer 305 in each sub-light-emitting functional layer 300a than the second sublayer 301b. Here, the material of the first sublayer 301a in the first semiconductor layer 301 may be N-type doped gallium nitride, and the second sublayer 301b in the first semiconductor layer 301 may be a gallium nitride buffer layer.

[0141] In this case, in the light-emitting unit 300, after the first electrode 302 is loaded with a cathode signal, if the second electrode 303 in a sub-light-emitting functional layer 300a is loaded with an anode signal, the light-emitting layer 304 in the sub-light-emitting functional layer 300a can emit a first light.

[0142] In the embodiment of the present application, each sub-light-emitting functional layer 300a in the light-emitting unit 300 may further include: a current spreading layer 306 located between the second electrode 303 and the second semiconductor layer 304. Here, one side of the current spreading layer 306 in each sub-light-emitting functional layer 300a may be in contact with the second semiconductor layer 304, and the other side may be electrically connected to the second electrode 303. Optionally, the material of the current spreading layer 306 is ITO (indium tin oxide), and the current spreading layer 306 is provided in the sub-light-emitting functional layer 300a, which is conducive to the transmission of holes and improves the electrical performance of the chip structure 000.

[0143] In this application, please refer to Figure 8 and Fig. 9 , Figure 8 is a top view of another light-emitting unit provided in an embodiment of the present application, Fig. 9 yes Figure 8 The light-emitting unit 300 is shown as a schematic diagram of the film structure at CC'. The light-emitting unit 300 may also include: a common electrode layer 307 disposed in contact with the first semiconductor layer 301, and the side of the common electrode layer 307 facing away from the first substrate 100 may be electrically connected to the first electrode 302. Here, the first electrode 302 may be disposed in the same layer and made of the same material as the second electrode 303 in each sub-light-emitting functional layer 300a, that is, the first electrode 302 and each second electrode 303 are formed by the same patterning process.

[0144] In the embodiment of the present application, the light-emitting unit 300 may further include: an insulating protection layer 308 located on the side of the common electrode layer 307 and each sub-light-emitting functional layer 300a away from the first semiconductor layer 301. Here, the insulating protection layer 308 may have: a first connection hole V1 arranged corresponding to the first electrode 302, and a plurality of second connection holes V2 arranged one-to-one corresponding to the plurality of second electrodes 303.

[0145] The first connection hole V1 may correspond to the common electrode layer 307, and the first electrode 302 may be electrically connected to the common electrode layer 307 through the first connection hole V1. The plurality of second connection holes V2 may also correspond to the plurality of sub-light-emitting functional layers 300a one by one, and each second electrode 303 may be electrically connected to the current spreading layer 306 in the corresponding sub-light-emitting functional layer 300a through the corresponding second connection hole V2. It should be noted that for ease of viewing Figure 6 The insulating protective layer 308 is shown in the light emitting unit shown. Fig. 9 The insulating protection layer 308 is not shown in the illustrated light emitting unit.

[0146] For example, the common electrode layer 307 can play a role in current spreading.

[0147] For example, the common electrode layer 307 and the first electrode 302 are both made of metal.

[0148] Optionally, the thickness of the common electrode layer 307 can be much greater than the thickness of the current spreading layer 306. For example, the side of the common electrode layer 307 facing away from the first semiconductor layer 301 can be flush with the side of the current spreading layer 306 facing away from the first semiconductor layer 301. That is, the thickness of the common electrode layer 307 can be equal to the sum of the thicknesses of the current spreading layer 306, the second semiconductor layer 304 and the light-emitting layer 305 in the sub-light-emitting functional layer 300a. In this way, the second electrode 303 and the first electrode 302 in the light-emitting unit 300 are also flush with each other on the side facing away from the connection layer 500. Since the second electrode 303 and the first electrode 302 in the chip structure 000 need to be welded on the driving backplane when the chip structure 000 is subsequently connected to the driving backplane. Therefore, when the second electrode 303 and the first electrode 302 of the chip structure 000 are flush with each other on the side facing away from the connection layer 500, it can be ensured that the chip structure 000 can be stably fixed on the driving backplane.

[0149] In the embodiment of the present application, the common electrode layer 307 may include: a common electrode body 3071, a first support portion 3072 fixedly connected to the common electrode body 3071, and two second support portions 3073 fixedly connected to the first support portion 3072. The common electrode body 3071 may be electrically connected to the first electrode 302, the first support portion 3072 may be distributed at the periphery of the common electrode body 3071, and each second support portion 3073 may be distributed on the side of the first support portion 3072 away from the common electrode body 3071. And among the two second support portions 3073, one second support portion 3073 may be between two adjacent sub-light-emitting functional layers 300a distributed in the row direction, and the other second support portion 3073 may be between two adjacent sub-light-emitting functional layers 300a distributed in the column direction. In this way, the strength of the entire light-emitting unit 300 can be ensured to be high, and the volume of the common electrode layer 307 can be ensured to be large, thereby reducing the resistance used to transmit the common cathode signal in the light-emitting unit 300.

[0150] It should be noted that there are various relative positional relationships between the dam layer 400 and the light-emitting unit 300 in the chip structure 000. The following relationships are used as examples for schematic illustration:

[0151] A surface of the dam layer 400 facing away from the first substrate 100 may be flush with a surface of the first semiconductor layer 300 a in the light emitting unit 300 facing away from the first substrate 100 .

[0152] Alternatively, the side of the dam layer 400 facing away from the first substrate 100 may be located between the upper surface and the lower surface of the light-emitting layer 305 in the light-emitting unit 300. The upper surface of the light-emitting layer 305 refers to the side facing the first substrate 100, and the lower surface of the light-emitting layer 305 refers to the side facing away from the first substrate 100.

[0153] Alternatively, a surface of the dam layer 400 facing away from the first substrate 100 may be flush with a surface of the light-emitting layer 305 in the light-emitting unit 300 facing away from the first substrate 100 .

[0154] Alternatively, the side of the dam layer 400 facing away from the first substrate 100 may be located between the upper surface and the lower surface of the second semiconductor layer 304 in the light emitting unit 300. The upper surface of the second semiconductor layer 304 refers to the side facing the first substrate 100, and the lower surface of the second semiconductor layer 304 refers to the side facing away from the first substrate 100.

[0155] Alternatively, a surface of the dam layer 400 facing away from the first substrate 100 may be flush with a surface of the second semiconductor layer 304 in the light emitting unit 300 facing away from the first substrate 100 .

[0156] Alternatively, the side of the dam layer 400 facing away from the first substrate 100 may be located between the upper surface and the lower surface of the current spreading layer 306 in the light emitting unit 300. The upper surface of the current spreading layer 306 refers to the side facing the first substrate 100, and the lower surface of the current spreading layer 306 refers to the side facing away from the first substrate 100.

[0157] Alternatively, a surface of the dam layer 400 facing away from the first substrate 100 may be flush with a surface of the current spreading layer 306 in the light emitting unit 300 facing away from the first substrate 100 .

[0158] Alternatively, the side of the dam layer 400 facing away from the first substrate 100 may be located between the side of the current spreading layer 306 facing away from the first substrate 100 and the side of the electrode structure (ie, the first electrode and the second electrode) facing away from the first substrate 100 .

[0159] Optional, such as Fig.10 As shown, Fig.10 000 is a schematic diagram of a film layer structure of another chip structure provided in an embodiment of the present application. The color conversion unit 200 in the chip structure 000 may include: a light shielding layer 201 , a defining dam layer 202 , an optical function layer 203 and a first encapsulation layer 204 .

[0160] The light shielding layer 201 in the color conversion unit 200 may be located on one side of the first substrate 100. The light shielding layer 201 may have a plurality of light through holes K1. Here, the plurality of light through holes K1 may correspond one-to-one to the plurality of sub-light-emitting functional layers 300a in the light-emitting unit 300, and the orthographic projection of each light through hole K1 on the first substrate 100 may overlap with the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100. For example, the orthographic projection of each sub-light-emitting functional layer 300a in the light-emitting unit 300 on the first substrate 100 may be located within the orthographic projection of the corresponding light through hole K1 on the first substrate 100.

[0161] The defining dam layer 202 in the color conversion unit 200 may be located on the side of the light shielding layer 201 away from the first substrate 100. The defining dam layer 202 may have a plurality of opening areas K2 corresponding to the plurality of light holes K1, and these opening areas K2 may also correspond to the plurality of sub-light-emitting functional layers 300a in the light-emitting unit 300. Here, the orthographic projection of each opening area K2 in the defining dam layer 202 on the first substrate 100 may overlap with the orthographic projection of the corresponding light hole K1 on the first substrate 100, and may overlap with the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100. For example, the light-emitting side of each sub-light-emitting functional layer 300a in the light-emitting unit 300 may face the corresponding opening area K2, and the orthographic projection of each sub-light-emitting functional layer 300a on the first substrate 100 may be located within the orthographic projection of the corresponding opening area K2 on the first substrate 100. The orthographic projection of each opening area K2 in the dam layer 202 on the first substrate 100 may be located within the orthographic projection of the corresponding light-through hole K1 on the first substrate 100 .

[0162] The optical function layer 203 in the color conversion unit 200 may be located inside the opening area K2 defining the dam layer 202, and at least part of the optical function layer 203 is used to convert the color of the light entering the optical function layer 203. Here, the light emitted by the light emitting unit 300 in the chip structure 000 may be directed toward the optical function layer 203, and then the optical function layer 203 converts the color of the light, and then the light is emitted after passing through the through hole K1 of the light shielding layer 201.

[0163] It should be noted that, since the light-emitting side of each sub-light-emitting functional layer 300a in the light-emitting unit 300 faces the corresponding opening area K2, and the orthographic projection of each sub-light-emitting functional layer 300a on the first substrate 100 is located within the orthographic projection of the corresponding opening area K2 on the first substrate 100. Therefore, the orthographic projection of the sub-light-emitting functional layer 300a in the light-emitting unit 300 on the first substrate 100 can also be located within the orthographic projection of the optical functional layer 203 in the corresponding opening area K2 on the first substrate 100, so that the light emitted by the sub-light-emitting functional layer 300a can be directed to the optical functional layer 203 inside the corresponding opening area K2 in the defined dam layer 202. It should also be noted that each sub-light-emitting functional layer 300a in the light-emitting unit 300 can emit light of the same color, and the types of optical functional layers 203 filled in different opening areas K2 are different, so that the light emitted by the sub-light-emitting functional layer 300a can be converted into light of other different colors by different types of optical functional layers 203 after passing through different opening areas K2.

[0164] The first encapsulation layer 204 in the color conversion unit 200 may be located on the side of the definition dam layer 202 away from the first substrate 100. The definition dam layer 202 and the optical function layer 203 may be encapsulated by the first encapsulation layer 204 to prevent water and oxygen in the external environment from penetrating the definition dam layer 202 and corroding the optical function layer 203, thereby ensuring that the optical function layer 203 can stably convert the color of light, so that the reliability of the optical function layer 203 is high.

[0165] Here, the light emitting unit 300 in the chip structure 000 may be located on a side of the first encapsulation layer 204 away from the first substrate 100 , and at least a portion of the dam layer 300 in the chip structure 000 may also be located on a side of the first encapsulation layer 204 away from the first substrate 100 .

[0166] In the examples of this application, refer to Fig.10 and Fig.11, the defining dam layer 202 in the color conversion unit 200 may have: a first surface S1 facing the first substrate 100, a second surface S2 facing away from the first substrate 100, and a first outer contour surface S3 located between the first surface S1 and the second surface S2. The first outer contour surface S1 may be a surface that is disposed around the defining dam layer 202 as a whole, that is, the first outer contour surface S1 may be an outer side surface of the defining dam layer 202. In the present application, the material of the defining dam layer 202 in the color conversion unit 200 is generally an organic material. If the thickness of the defining dam layer 202 is too thick, after the defining dam layer 202 is formed by the process of exposure and development, in the direction parallel to the extension surface of the first substrate 100, the width of the first surface S1 in the defining dam layer 202 is less than the width of the second surface S2. To this end, the angle α1 between the first surface S1 in the dam layer 202 and the first outer contour surface S3 is defined as an obtuse angle, and the angle β1 between the second surface S2 in the dam layer 202 and the first outer contour surface S3 is defined as an acute angle. With such a design, on the one hand, the color conversion unit 200 can have a larger bonding area without changing the distance between the opening area and the chip boundary, thereby improving the bonding stability of the color conversion unit 200 and the light-emitting unit 300 while ensuring a small chip size; on the other hand, it can play a shading role at the edge of the chip structure 000, reducing the influence of the side light leakage caused by the light-emitting unit 11 on the light-emitting effect.

[0167] Exemplary, reference Fig.10 and Fig.11 , the distance range between the first surface S1 and the second surface S2 in the dam layer 202 (the thickness range of the dam layer 202) is limited to between 5 microns and 15 microns. For example, the thickness of the dam layer 202 is limited to (10±0.5) microns. In this way, the thickness of the dam layer 202 can be relatively high while ensuring that the thickness of the dam layer 202 is relatively uniform, thereby ensuring that the optical function layer 203 disposed in the opening area 202 has a better effect on the conversion of light color.

[0168] The angle α1 between the first surface S1 and the first contour surface S3 in the dam layer 202 is defined to be in a range of 90° to 130°. For example, the angle between the first surface S1 and the first contour surface S3 in the dam layer 202 is defined to be 103°±2°.

[0169] In the embodiment of the present application, the orthographic projection of the side of the definition dam layer 202 in the color conversion unit 200 facing the first substrate 100 on the first substrate 100 may be located within the orthographic projection of the light shielding layer 201 on the first substrate 100. The first encapsulation layer 204 in the color conversion unit 200 needs to at least cover the side of the definition dam layer 202 and the optical functional layer 203 away from the first substrate, and the outer side of the definition dam layer 202. For example, the first encapsulation layer 204 in the color conversion unit 200 may include: a first encapsulation portion 2041 and a second encapsulation portion 2042. The first encapsulation portion 2041 in the first encapsulation layer 204 may be arranged in contact with the second surface S2 in the definition dam layer 202, and the first encapsulation portion 2041 may cover the second surface S2 in the definition dam layer 202, and the first encapsulation portion 2041 may also cover the side of the optical functional layer 203 away from the first substrate. The second encapsulation portion 2042 in the first encapsulation layer 204 may be disposed in contact with the first outer contour surface S3 defined in the dam layer 202 , and the second encapsulation portion 2042 may at least cover the first outer contour surface S3 defined in the dam layer 202 .

[0170] In a possible implementation, the first encapsulation layer 204 in the color conversion unit 200 may also cover the outer side of the light shielding layer 201. For example, the second encapsulation portion 2042 in the first encapsulation layer 204 also needs to extend to the outer side of the light shielding layer 201, so that the second encapsulation portion 2042 may also be arranged in contact with the outer side of the light shielding layer 201. In this way, the light shielding layer 201 may also be encapsulated by the first encapsulation layer 204, so that water and oxygen in the external environment will not corrode the optical functional layer 203 through the light shielding layer 201 and the limiting dam layer 202.

[0171] In another possible implementation, Fig.11 As shown, Fig.11It is a schematic diagram of the film layer structure of another chip structure provided in an embodiment of the present application. The color conversion unit 200 in the chip structure 000 may also include: a second encapsulation layer 205 located between the light shielding layer 201 and the defining dam layer 202. Among them, the optical functional layer 203 and the defining dam layer 202 in the color conversion unit 200 may be located on the side of the second encapsulation layer 205 away from the first substrate 100, and the second encapsulation layer 205 needs to at least cover the outer side of the light shielding layer 201 and the side of the light shielding layer 201 away from the first substrate 100. In this case, the light shielding layer 201 can be encapsulated by the second encapsulation layer 205, so that water and oxygen in the external environment will not corrode the optical functional layer 203 through the light shielding layer 201 and the defining dam layer 202. Moreover, in this case, the first encapsulation layer 204 only needs to cover the second surface S2 and the first outer contour surface S3 in the dam layer 202, that is, the second encapsulation part 2042 in the first encapsulation layer 204 does not need to extend to the outer surface of the light-shielding layer 201, thereby reducing the step difference of the first encapsulation layer 204 and reducing the risk of breakage of the first encapsulation layer 204.

[0172] Here, the first encapsulation layer 204 may be a film layer structure that is continuously distributed at all positions, and of course, the second encapsulation layer 205 may also be a film layer structure that is continuously distributed at all positions. In addition, the orthographic projections of the dam layer 202 and the optical functional layer 203 on the first substrate 100 are both located within the orthographic projection of the first encapsulation layer 204 on the first substrate 100, and are also located within the orthographic projection of the second encapsulation layer 205 on the first substrate 100. At the same time, the second encapsulation layer 205 is arranged in contact with the first encapsulation layer 204, so that the dam layer 202 and the optical functional layer 203 can be completely wrapped by the cooperation of the first encapsulation layer 204 and the first encapsulation layer 204. Here, the area where the second encapsulation layer 205 contacts the first encapsulation layer 204 is distributed around the dam layer 202, so that the packaging effect of the optical functional layer 203 can be ensured to be better through the cooperation of the first encapsulation layer 204 and the second encapsulation layer 205, and the reliability of the optical functional layer 203 is further improved.

[0173] For example, Fig.11 As shown, the first encapsulation layer 204 may further include: a third encapsulation portion 2043, the third encapsulation portion 2043 may be connected to the side of the second encapsulation portion 2042 away from the first encapsulation portion 2041, and the third encapsulation portion 2043 may be located on the side of the second encapsulation layer 205 away from the first substrate 100, and may directly contact the side of the second encapsulation layer 205 away from the first substrate 100. In this way, it can be ensured that there is a portion in the first encapsulation layer 204 that contacts the second encapsulation layer 205.

[0174] In the embodiment of the present application, the side of the third packaging part 2043 facing away from the second packaging part 2042 is the outer side surface of the first packaging layer 204. The outer side surface of the first packaging layer 204 can be flush with the outer side surface of the second packaging layer 205, so that the contact area between the first packaging layer 204 and the second packaging layer 205 is wider, thereby ensuring that the first packaging layer 204 and the second packaging layer 205 have a better packaging effect on the defined dam layer 202.

[0175] In this application, if Fig.12 , Fig.13 and Fig.14 As shown, Fig.12 is a top view of another chip structure provided in an embodiment of the present application, Fig.13 yes Fig.12 The schematic diagram of the film structure of the chip structure at D-D' is shown. Fig.14 yes Fig.12 The schematic diagram of the film structure of the chip structure at E-E' is shown. The multiple sub-light-emitting functional layers in the light-emitting unit 300 may include: a first sub-light-emitting functional layer 300a1, a second sub-light-emitting functional layer 300a2 and a third sub-light-emitting functional layer 300a3. Here, the first sub-light-emitting functional layer 300a1, the second sub-light-emitting functional layer 300a2 and the third sub-light-emitting functional layer 300a3 are all used to emit the first light in the working state.

[0176] Accordingly, the plurality of opening regions defined in the dam layer 202 may include: a first opening region K21, a second opening region K22, and a third opening region K23. The first opening region K21 may be disposed opposite to the first sub-light emitting functional layer 300a1, the second opening region K22 may be disposed opposite to the second sub-light emitting functional layer 300a2, and the third opening region K23 may be disposed opposite to the third sub-light emitting functional layer 300a3.

[0177] Here, the first opening area K21 and the second opening area K22 are arranged in a row in the first direction X, and the second opening area K22 and the third opening area K23 are arranged in a row in the second direction Y. The first direction X intersects with the second direction Y. For example, the first direction X may be perpendicular to the second direction Y. In the present application, the area enclosed by the outer contour of the dam layer 202 is defined as a rectangle; the shapes of the first opening area K21, the second opening area K22, and the third opening area K23 are all rectangular.

[0178] The optical function layer 203 in the color conversion unit 200 may include: a first color conversion portion 203a, a second color conversion portion 203b and a third color conversion portion 203c. The first color conversion portion 203a may be located in the first opening area K21, the second color conversion portion 203b may be located in the second opening area K22, and the third color conversion portion 203c may be located in the third opening area K23.

[0179] In this case, the first light emitted by the first sub-light-emitting functional layer 300a1 can be directed toward the first color conversion portion 203a, and the first color conversion portion 203a converts the first light emitted by the first sub-light-emitting functional layer 300a1 into light of another color. The first light emitted by the second sub-light-emitting functional layer 300a1 can be directed toward the second color conversion portion 203b, and the second color conversion portion 203b converts the first light emitted by the second sub-light-emitting functional layer 300a2 into light of another color. The first light emitted by the third sub-light-emitting functional layer 300a3 can be directed toward the third color conversion portion 203c, and the first light can be transmitted through the third color conversion portion 203c or can be converted by the third color conversion portion 203c.

[0180] For example, the chip structure 000 may have a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B. The first light emitted by the first sub-light emitting functional layer 300a1, the second sub-light emitting functional layer 300a2 and the third sub-light emitting functional layer 300a3 in the light emitting unit 300 includes at least one of blue light and ultraviolet light.

[0181] Here, the first color conversion unit 203a is used to convert the first light into red light. For example, the first color conversion unit 203a includes red quantum dots for converting the first light into red light; preferably, the first color conversion unit 203a also includes scattering particles for scattering the light. Here, after the first light emitted by the first sub-light-emitting functional layer 300a1 is emitted to the first color conversion unit 203a distributed in the first opening area K21, the first light can be converted into red light by the red quantum dots, and the first light and red light can be scattered by the scattering particles to ensure that more first light can be converted into red light by the red quantum dots, and the emission angle of the converted red light can be larger, so as to ensure that the display substrate integrated with such a chip structure 000 has a larger viewing angle. To this end, the red sub-pixel R in the chip structure 000 can include: a first sub-light-emitting functional layer 300a2 and a first color conversion unit 203a.

[0182] The second color conversion part 203b is used to convert the first light into green light. For example, the second color conversion part 203b includes green quantum dots for converting the first light into green light; preferably, the second color conversion part 203b also includes scattering particles for scattering the light. Here, after the first light emitted by the second sub-light-emitting functional layer 300a2 is emitted to the second color conversion part 203b distributed in the second opening area K22, the first light can be converted into green light by the green quantum dots, and the first light and green light can be scattered by the scattering particles to ensure that more first light can be converted into green light by the green quantum dots, and the emission angle of the converted green light can be larger, so as to ensure that the display substrate integrated with such chip structure 000 has a larger viewing angle. For this reason, the red sub-pixel R in the chip structure 000 can include: the first sub-light-emitting functional layer 300a1 and the first color conversion part 203a. For this reason, the green sub-pixel G in the chip structure 000 can include: the second sub-light-emitting functional layer 300a2 and the second color conversion part 203b.

[0183] The third color conversion part 203c is used to convert the first light into blue light or maintain the blue light emission. For example, when the first light only contains blue light, the third color conversion part 203c can be a transparent part or the third color conversion part 203c can include blue quantum dots; wherein the transparent part is used for direct transmission of the first light, and the blue quantum dots can be used to convert the first light into blue light with a wavelength different from that of the first light. Preferably, the third color conversion part 203c also includes scattering particles for scattering the light. Here, after the first light emitted by the third sub-light-emitting functional layer 300a3 is emitted to the third color conversion part 203c distributed in the third opening area K23, the first light can be scattered by the scattering particles to ensure that the blue light has a larger emission angle, thereby ensuring that the display substrate integrated with this chip structure 000 has a larger viewing angle. For another example, when the first light includes ultraviolet light, the third color conversion unit 203c includes blue quantum dots that convert the first light into blue light, or the third color conversion unit 203c includes scattering particles for scattering light and blue quantum dots for converting ultraviolet light into blue light. Here, after the first light emitted by the second sub-light-emitting functional layer 300a2 is emitted to the third color conversion unit 203c distributed in the third opening area K23, the ultraviolet light in the first light can be converted into blue light by the blue quantum dots, and the first light and blue light can be scattered by the scattering particles to ensure that more ultraviolet light is converted into blue light by the blue quantum dots, and the output angle of the converted blue light is larger, so as to ensure that the viewing angle of the display substrate integrated with the chip structure 000 is larger. To this end, the blue sub-pixel B in the chip structure 000 may include: a third sub-light-emitting functional layer 300a3 and a third color conversion unit 203c.

[0184] Optionally, the material defining the dam layer 202 in the color conversion unit 200 may include: an organic material with light absorption or an organic material with light reflection. Here, the color of the organic material with light absorption is usually black, which can absorb the light emitted from the side of the optical functional layer 203; the organic material with light reflection is usually gray, which can reflect the light emitted from the side of the optical functional layer 203.

[0185] To this end, when the material of the defined dam layer 202 includes an organic material with light reflection, the light emitted from the side of the optical function layer 203 can be reflected back to the optical function layer 203 by the defined dam layer 202, so that the quantum dots in the optical function layer 203 can convert the blue light or ultraviolet light in the reflected light into light of corresponding colors, thus further improving the excitation efficiency of the quantum dots. In addition, the light reflected back by the defined dam layer 202 can be emitted from the side of the optical function layer 203 toward the first substrate 100, so that the light can be emitted after passing through the corresponding light hole K1, thus effectively improving the light extraction efficiency of the chip structure 000.

[0186] For example, when the material of the defined dam layer 202 includes an organic material with light reflectivity, the reflectivity of the defined dam layer 202 may range from 40% to 80%. For example, the reflectivity of the defined dam layer 202 may be 63%±5%. It should be noted that when the reflectivity of the defined dam layer 202 is above 30%, it can be considered that the defined dam layer 202 has a certain light reflectivity. When the reflectivity of the defined dam layer 202 is 40% to 80%, it can be ensured that the defined dam layer 202 can reflect more light back to the optical functional layer 203.

[0187] In the embodiment of the present application, the color conversion unit 200 in the chip structure 000 may further include: a filter layer 206 located between the first substrate 100 and the optical functional layer 200. Here, the filter layer 206 may include: a plurality of filter units corresponding to the plurality of light through holes K1 one by one, and the orthographic projection of each filter unit on the first substrate 100 may overlap with the orthographic projection of the corresponding light through hole K1 on the first substrate 100.

[0188] For example, the plurality of filter units in the filter layer 206 may include: a first filter unit 206a, a second filter unit 206b, and a third filter unit 206c. Here, the first filter unit 206a may be arranged corresponding to the first color conversion unit 203a, the second filter unit 206b may be arranged corresponding to the second color conversion unit 203b, and the third filter unit 206c may be arranged corresponding to the third color conversion unit 203c. To this end, the red sub-pixel R in the chip structure 000 may further include: a first filter unit 206a; the green sub-pixel G in the chip structure 000 may further include: a second filter unit 206b; and the blue sub-pixel B in the chip structure 000 may further include: a third filter unit 206c.

[0189] For example, the first light emitted by the first sub-light-emitting functional layer 300a1, the second sub-light-emitting functional layer 300a2, and the third sub-light-emitting functional layer 300a3 in the light-emitting unit 300 are all blue light, and the first filter unit 206a can be a red color block, which can transmit red light and absorb light of other colors. In this way, the light emitted from the first color conversion unit 203a can be emitted after passing through the first filter unit 206a, and the first filter unit 206a can filter out light of other colors except red light, so as to ensure that the red sub-pixel R in the chip structure 000 can filter out the blue light component. It should be noted that, in other possible implementations, the first filter unit 206a may also be: a film layer for transmitting red light and reflecting blue light. In this way, after the light emitted from the first color conversion unit 203a is emitted to the first filter unit 206a, the red light in these light rays can pass through the first filter unit 206a before being emitted, and the blue light in these light rays can be reflected back to the first color conversion unit 203a by the first filter unit 206a, so that the red quantum dots in the first color conversion unit 203a can excite the blue light into red light. In this way, the excitation efficiency of the red quantum dots can be further improved.

[0190] For example, the first light emitted by the first sub-light-emitting functional layer 300a1, the second sub-light-emitting functional layer 300a2, and the third sub-light-emitting functional layer 300a3 in the light-emitting unit 300 are all blue light, and the second filter unit 206b can be a green color block, which can transmit green light and absorb light of other colors. In this way, the light emitted from the second color conversion unit 203b can be emitted after passing through the second filter unit 206b, and the second filter unit 206b can filter out light of other colors except green light, so as to ensure that the green sub-pixel G in the chip structure 000 can filter out the blue light component. It should be noted that, in other possible implementations, the second filter unit 206b may also be: a film layer for transmitting green light and reflecting blue light. In this way, after the light emitted from the second color conversion unit 203b is emitted to the second filter unit 206b, the green light in these light rays can pass through the second filter unit 206b before being emitted, and the blue light in these light rays can be reflected back to the second color conversion unit 203b by the second filter unit 206b, so that the green quantum dots in the second color conversion unit 203b can excite the blue light into green light. In this way, the excitation efficiency of the green quantum dots can be further improved.

[0191] It should be noted that the film structures of the first filter unit 206a and the second filter unit 206b can be the same and can be prepared by the same process; for example, the first filter unit 206a and the second filter unit 206b are both films that transmit red light and green light and reflect blue light.

[0192] For example, the first light emitted by the first sub-light-emitting functional layer 300a1, the second sub-light-emitting functional layer 300a2, and the third sub-light-emitting functional layer 300a3 in the light-emitting unit 300 are all blue light, and the third filter unit 206c can be a blue color block, which can transmit blue light and absorb light of other colors. In this way, the light emitted from the third color conversion unit 203c can be emitted after passing through the third filter unit 206c, and the third filter unit 206c can filter out light of other colors except blue light, so as to ensure that the blue sub-pixel B in the chip structure 000 can emit relatively pure blue light.

[0193] For example, the first light emitted by the first sub-light-emitting functional layer 300a1, the second sub-light-emitting functional layer 300a2 and the third sub-light-emitting functional layer 300a3 in the light-emitting unit 300 are all blue light, and the third filter unit 206c may be a transparent block that can transmit blue light.

[0194] It should be noted that, since the orthographic projection of each filter unit in the filter layer 206 on the first substrate 100 overlaps with the orthographic projection of the corresponding light hole K1 in the light shielding layer 201 on the first substrate 100, a portion of the light shielding layer 201 is distributed between two adjacent filter units in the filter layer 206 in the direction parallel to the extension surface of the first substrate 100. In this way, the light emitted from the side of a filter unit in the filter layer 206 can be absorbed by the light shielding layer 201, so as to ensure that the light intensity emitted by each sub-pixel to the adjacent sub-pixel is low, which can effectively reduce the probability of color crosstalk in the chip structure 000.

[0195] Optionally, the materials of the first encapsulation layer 204 and the second encapsulation layer 205 in the color conversion unit 200 can both be inorganic insulating materials. For example, the inorganic insulating material may include: one or more of silicon oxide, silicon nitride, and silicon oxynitride. The thickness range of the second encapsulation layer 205 and the first encapsulation layer 204 can both be between 0.5 microns and 5 microns. In this way, through the cooperation of the second encapsulation layer 205 and the first encapsulation layer 204, the dam layer 202 and the optical functional layer 203 can be isolated from the external environment, so that water and oxygen in the external environment will not corrode the optical functional layer 203.

[0196] In the embodiment of the present application, the second encapsulation layer 205 in the color conversion unit 200 is located between the light shielding layer 201 and the limiting dam layer 202, and there are many situations in which the positional relationship between the second encapsulation layer 205 and the filter layer 206 in the color conversion unit 200 is described schematically using the following two situations as examples:

[0197] The first possible situation is Fig.15 As shown, Fig.15 2 is a schematic diagram of a film structure of a chip structure provided by another embodiment of the present application, the filter layer 206 in the color conversion unit 200 can be located on the side of the second encapsulation layer 205 away from the first substrate 100, and a portion of the second encapsulation layer 205 can be located in the light hole K1 in the light shielding layer 201. Here, the side of the filter layer 206 away from the first substrate 100 can be in direct contact with the side of the optical functional layer 203 facing the first substrate 100.

[0198] Optionally, the orthographic projection of each filter unit in the filter layer 206 on the first substrate 100 may cover the orthographic projection of the corresponding opening area K2 in the limiting dam layer 202 on the first substrate 100. In this way, the light emitted from the optical functional layer 203 distributed in the opening area K2 of the limiting dam layer 202 may all be emitted to the corresponding filter unit in the filter layer 206, thereby ensuring that the filter unit has a better effect of filtering the light, so that the color of the light subsequently emitted from the corresponding light hole K1 in the light shielding layer 201 is purer.

[0199] The second possible situation is Fig.16 As shown, Fig.16 2 is a schematic diagram of the film layer structure of another chip structure provided by another embodiment of the present application. The filter layer 206 in the color conversion unit 200 can be located on the side of the second encapsulation layer 205 facing the first substrate 100, and at least part of each filter unit in the filter layer 206 can be located in the corresponding light hole K1 in the light shielding layer 201. Here, the side of the second encapsulation layer 205 in the color conversion unit 200 facing the first substrate 100 can be in direct contact with the side of the light shielding layer 201 facing away from the first substrate 100, and directly contact with the side of the filter layer 206 facing away from the first substrate 100; the side of the second encapsulation layer 205 in the color conversion unit 200 facing away from the first substrate 100 can be in direct contact with the side of the limiting dam layer 202 facing the first substrate 100, and directly contact with the side of the optical functional layer 203 facing the first substrate 100.

[0200] Optionally, the orthographic projection of each filter unit in the filter layer 206 on the first substrate 100 may cover the orthographic projection of the corresponding light through hole K1 in the light shielding layer 201 on the first substrate 100. Here, in the filter layer 206, a part of each filter unit may be distributed in the corresponding light through hole K1 in the light shielding layer 201, and the other part may be distributed outside the corresponding light through hole K1. In this way, the light emitted from the optical functional layer 203 distributed in the opening area K2 of the limiting dam layer 202 can be completely filtered by the corresponding filter unit in the filter layer 206 after emitting to the corresponding light through hole K1 in the light shielding layer 201, thereby ensuring that the filter unit has a better effect of filtering the light, so that the color of the light emitted from the corresponding light through hole K1 in the light shielding layer 201 is purer.

[0201] In the embodiment of the present application, the chip structure 000 may further include: a connection layer 500. Here, the light emitting unit 300 in the chip structure 000 may be located on a side of the connection layer 500 away from the first substrate 100, and the light emitting unit 300 may be fixed to a side of the color conversion unit 200 away from the first substrate 100 through the connection layer 500. For example, the first semiconductor layer 301 in the light emitting unit 300 may be fixed to a side of the first encapsulation layer 204 in the color conversion unit 200 away from the first substrate 100 through the connection layer 500.

[0202] It should be noted that the color conversion unit 200 and the light emitting unit 300 in the chip structure 000 in the present application are manufactured separately and independently, and then the two are fixed together through the connection layer 500 to obtain the chip structure 000.

[0203] In some examples, first, a plurality of color conversion units 200 may be formed on a second substrate that is connected as a whole and has a larger area, and a dam layer 400 may be formed on the side of each color conversion unit 200 that is away from the second substrate. After that, a plurality of light-emitting units 300 may be formed on a third substrate (usually a sapphire substrate or a silicon-based substrate), and a temporary substrate may be formed on the side of the plurality of third light-emitting units that are away from the third substrate. Then, the third substrate is removed, and a connecting layer 500 is used to fix the side of the light-emitting unit 300 that is away from the temporary substrate to the side of the corresponding color conversion unit 200 that is away from the second substrate. Finally, the temporary substrate is peeled off, and the second substrate is thinned, and then the thinned second substrate is cut by a cutting process to obtain a plurality of chip structures 000.

[0204] Optionally, the connection layer 500 in the chip structure 000 may include: any one of an indium zinc oxide connection layer, a metal connection layer, and an adhesive layer. For different types of connection layers 500, the principles of the connection layer 500 fixing the color conversion unit 200 and the light-emitting unit 300 together are also different. To this end, the embodiments of the present application will be schematically described using the following three possible situations as examples:

[0205] The first possible situation is Fig.17 As shown, Fig.17 : This is a schematic diagram of the film layer structure of a chip structure provided by another embodiment of the present application. When the connecting layer 500 includes an adhesive layer, the connecting layer 500 is a single-layer structure, and the color conversion unit 200 and the light-emitting unit 300 can be bonded together through the adhesive layer. Exemplarily, the material of the adhesive layer is an organic adhesive material of the epoxy resin type. And this adhesive layer is transparent, so even if the adhesive layer covers each sub-light-emitting functional layer 300a in the light-emitting unit 300, it can also ensure that each sub-light-emitting functional layer 300a can pass through the adhesive layer and emit to the color conversion unit 200.

[0206] In this case, since the adhesive layer is viscous before curing, after the adhesive is provided on the light-emitting unit 300 and the light-emitting unit 300 provided with the adhesive is attached to the corresponding color conversion unit 200, it is usually necessary to apply a certain pressing force to the light-emitting unit 300. In the process of applying the pressing force to the light-emitting unit 300, part of the adhesive will overflow between the light-emitting unit 300 and the dam layer 400 under the action of the pressing force. Therefore, after the adhesive layer is cured, the adhesive is also distributed between the light-emitting unit 300 and the dam layer 400. To this end, the connecting layer 500 may include: a first filling portion 501 and a second filling portion 502. The first filling portion 501 may be located between the light-emitting unit 300 and the color conversion unit 200, and the light-emitting unit 300 may be firmly bonded to the side of the color conversion unit 200 away from the first substrate 100 through the first filling portion 501. The second filling portion 502 may be located between the dam layer 400 and the light-emitting unit 300.

[0207] In this case, in a direction perpendicular to the extension surface of the first substrate 100, the thickness of the dam layer 400 is greater than or equal to the sum of the thickness of the first filling portion 501 in the connecting layer 500 and the thickness of the first semiconductor layer 301 in the light-emitting unit 300, so as to ensure that the dam layer 400 can block light transmitted laterally in the first semiconductor layer 301.

[0208] In the embodiment of the present application, the connection layer 500 may further include: an overflow portion 503, and the overflow portion 503 may be distributed on the side of the dam layer 400 away from the first substrate 100. It should also be noted that in other possible implementations, the connection layer 500 may not include the overflow portion 503 disposed on the side of the dam layer 400 away from the first substrate 100. Whether there is an overflow portion 503 on the side of the dam layer 400 away from the first substrate 100 is related to the preparation process of the chip structure 000, which will be described here first, and will be further described in subsequent embodiments.

[0209] The second possible situation is Fig.18 As shown, Fig.18 1 is a schematic diagram of a film layer structure of another chip structure provided by another embodiment of the present application. When the connection layer 500 includes an indium zinc oxide connection layer, the connection layer 500 may include: a first indium zinc oxide layer 504 and a second indium zinc oxide layer 505 stacked. Here, the first indium zinc oxide layer 504 and the second indium zinc oxide layer 505 may be connected by molecular bond bonding.

[0210] The first indium zinc oxide layer 504 can be fixed on the side of the color conversion unit 200 away from the first substrate 100, and the second indium zinc oxide layer 505 can be fixed on the light-emitting side of the light-emitting unit 300. In this way, the color conversion unit 200 and the light-emitting unit 300 can be fixed by the molecular bond between the first indium zinc oxide layer 504 and the second indium zinc oxide layer 505.

[0211] It should be noted that the first indium zinc oxide layer 504 and the second indium zinc oxide layer 505 are both transparent conductive layers. Therefore, even if the first indium zinc oxide layer 504 and the second indium zinc oxide layer 505 cover each sub-light-emitting functional layer 300a in the light-emitting unit 300, it can be ensured that each sub-light-emitting functional layer 300a can pass through the second indium zinc oxide layer 505 and the first indium zinc oxide layer 504 and then emit to the corresponding opening area K2.

[0212] The third possible situation is Fig.19 As shown, Fig.19 This is a schematic diagram of the film layer structure of another chip structure provided by another embodiment of the present application. When the connection layer 500 includes a metal connection layer, the connection layer 500 may include: a first sub-metal layer 506, a second sub-metal layer 507 and a third sub-metal layer 508 that are stacked. The second sub-metal layer 507 may be located between the first sub-metal layer 506 and the third sub-metal layer 508, and may serve as a eutectic alloy layer connecting the first sub-metal layer 506 and the third sub-metal layer 508.

[0213] The first sub-metal layer 506 may be fixed on the side of the color conversion unit 200 away from the first substrate 100, and the third sub-metal layer 508 may be fixed on the light-emitting side of the light-emitting unit 300. In this way, the first sub-metal layer 506 and the third sub-metal layer 508 may be connected as a whole through the eutectic alloy layer (also the second sub-metal layer 507) to achieve fixation between the color conversion unit 200 and the light-emitting unit 300.

[0214] It should be noted that the first sub-metal layer 506, the second sub-metal layer 507 and the third sub-metal layer 508 are all reflective conductive layers. Therefore, it is necessary to set a plurality of avoidance holes K4 corresponding to the plurality of sub-light-emitting functional layers 300a in the light-emitting unit 300 in the connecting layer 500 to ensure that the light emitted by each sub-light-emitting functional layer 300a can pass through the corresponding avoidance hole K4 and then be emitted to the corresponding opening area K2.

[0215] Optionally, the light-emitting unit 300 in the chip structure 000 may include a plurality of light-emitting chips, and each light-emitting chip may have a sub-light-emitting functional layer 300a. Here, the light-emitting chip is an LED chip. It should be noted that the LED chip may be an LED chip of ordinary size, or a mini light-emitting diode (English: mini Light-Emitting Diode, referred to as: mini-LED) chip, or a micro LED (English: Micro Light-Emitting Diode, referred to as: Micro-LED) chip. The embodiments of the present application are not limited to this.

[0216] In the embodiment of the present application, the thickness of the portion of the connecting layer 500 located between the light-emitting unit 300 and the color conversion unit 400 ranges from 0.3 microns to 3 microns. Here, in the case where the connecting layer 500 includes an adhesive layer, since the first filling portion 501 in the connecting layer 500 is located between the light-emitting unit 300 and the color conversion unit 400, the thickness of the first filling portion 501 in the connecting layer 500 can range from 0.3 microns to 3 microns. For example, the thickness of the first filling portion 501 in the connecting layer 500 can range from 0.7 microns to 2 microns. For example, the thickness of the first filling portion 501 in the connecting layer 500 can range from 1 micron to 1.5 microns. For example, the thickness of the first filling portion 501 in the connecting layer 500 is (0.9±0.2) microns.

[0217] The following embodiment will take the connection layer 500 including the adhesive layer as an example to schematically illustrate the preparation process of the chip structure 000. Here, the preparation process of the chip structure 000 may include the following structural steps:

[0218] Step S101 , forming a first initial wafer including a plurality of color conversion units 200 .

[0219] In the embodiment of the present application, during the preparation process of the color conversion unit 200, as shown in FIG. Fig. 20 As shown, Fig. 20 is a schematic diagram of the structure of a first large board provided in an embodiment of the present application. A first large board M including a plurality of color conversion units 200 arranged in an array can be formed synchronously first. Then, a dam layer 400 is formed on each color conversion unit 200 in the first large board M. For example, the dam layer 400 can be formed on each color conversion unit 200 by a photolithography process. Then, the first large board M can be cut to obtain a plurality of first initial wafers F.

[0220] For example, Fig. 20 and Fig.21 As shown, Fig.21: is a schematic diagram of the structure of a first initial wafer provided in an embodiment of the present application. Each first initial wafer F may include: a second substrate 004, color conversion units 200 distributed on the second substrate 004, and a dam layer 400 distributed on the side of each color conversion unit 200 away from the second substrate 004. Here, the second substrate 004 is usually a glass substrate, and the thickness of the second substrate 004 is relatively thick, usually more than 500 microns, to ensure that the support strength of the second substrate 004 is high, so as to form multiple color conversion units 200 on the second substrate 004.

[0221] Optionally, the shape of the first initial wafer F may be circular, and the first large plate M may be cut anisotropically, so that a plurality of first initial wafers F may be cut out of the first large plate M. Exemplarily, the size of the first initial wafer F is 4 inches or 6 inches.

[0222] Step S102 , forming a second initial wafer including a plurality of light-emitting units 300 .

[0223] In the embodiment of the present application, the light-emitting unit 300 is formed on a third substrate. Here, the shape of the third substrate is usually circular, and a plurality of light-emitting units 300 can be first formed on the third substrate (usually a sapphire substrate or a silicon-based substrate), and then a temporary substrate with the same shape as the third substrate is formed on the side of the plurality of light-emitting units away from the third substrate, and then the third substrate can be peeled off from the plurality of light-emitting units 300. Here, after the third substrate is peeled off from the plurality of light-emitting units 300, the obtained structure can be referred to as a second initial wafer. That is, please refer to Fig. 22 , Fig. 22 003 and a plurality of light emitting units 300 located on the temporary substrate 003. Exemplarily, the size of the second initial wafer N may also be 4 inches or 6 inches.

[0224] In the present application, the temporary substrate and the light-emitting unit can be bonded by a temporary bonding adhesive. For example, please refer to Fig.23 , Fig.23 This is a schematic diagram of a film structure of forming multiple light-emitting units on a third substrate according to an embodiment of the present application. After forming multiple light-emitting units 300 on the third substrate 001, a temporary bonding adhesive 002 can be formed on the side of the multiple light-emitting units 300 away from the third substrate 001, and then the temporary substrate 003 can be bonded to the side of the multiple light-emitting units 300 away from the third substrate 001 through the temporary bonding adhesive 002. After that, please refer to Fig.24 , Fig.24001 from the side of the plurality of light-emitting units 300 away from the temporary substrate 003, and then the second initial wafer N can be obtained. It should be noted that: Fig.24 The schematic diagram shown can be Fig. 22 The film layer structure of the second initial wafer at H-H' is shown.

[0225] Step S103: forming an adhesive on the second initial wafer N.

[0226] In the embodiment of the present application, an adhesive may be formed on a side of the plurality of light emitting units 300 in the second initial wafer N that is away from the temporary substrate.

[0227] It should be noted that if Fig.23 and Fig.24 As shown, since the multiple light-emitting units 300 in the second initial wafer N need to be connected to the temporary substrate 003 through the temporary bonding glue 002, and the temporary bonding glue 002 is able to flow before it is solidified. Therefore, in the process of forming the temporary bonding glue 002, the temporary bonding glue 002 will flow between two adjacent light-emitting units 300. In this way, it can be ensured that the side of the second initial wafer N opposite to the temporary substrate is relatively flat, while the step difference of the side of the first initial wafer F opposite to the second substrate is usually higher. For this reason, when the adhesive is formed on the second initial wafer N, it can be ensured that the overall thickness of the adhesive is small, which is more conducive to the subsequent bonding of the second initial wafer N and the first initial wafer F.

[0228] Step S104: aligning the second initial wafer N and the first initial wafer F.

[0229] In the embodiment of the present application, the side of each light-emitting unit 300 in the second initial wafer N facing away from the temporary substrate can be attached to the side of the corresponding color conversion unit 200 in the first initial wafer F facing away from the second substrate through an adhesive layer. After the adhesive is cured, each light-emitting unit 300 of the second initial wafer N can be bonded to the corresponding color conversion unit 200 in the first initial wafer F.

[0230] It should be noted that after bonding each light emitting unit 300 of the second initial wafer N to the corresponding color conversion unit 200 in the first initial wafer F, Fig.25 As shown, Fig.25 This is a rendering of a second initial wafer and a first initial wafer bonded together, provided in an embodiment of the present application. At least part of the light-emitting unit 300 may be distributed in an area enclosed by a dam layer 400 disposed on the side of the corresponding color conversion unit 200 away from the second substrate 004 .

[0231] Step S105: removing the temporary substrate to obtain a motherboard wafer.

[0232] In the embodiment of the present application, after the temporary substrate in the second initial wafer N is removed, the second substrate, the multiple color conversion units 200 located on the second substrate, the dam layer 400 located on the side of each color conversion unit 200 away from the second substrate, and the light-emitting units 300 located in the area surrounded by the dam layer 400 can be obtained. Here, the second substrate, the multiple color conversion units 200 and the multiple light-emitting units 300 located on the second substrate can be referred to as a motherboard wafer.

[0233] It should be noted that after the second initial wafer N and the first initial wafer F are bonded, the adhesive 005 and the temporary bonding adhesive 002 may be distributed on the side of the dam layer 400 facing away from the second substrate 004, and the adhesive 005 and the temporary bonding adhesive 002 are also distributed between adjacent color conversion units 200, and the adhesive 005 is closer to the second substrate 004 than the temporary bonding adhesive 002. In the process of peeling off the temporary substrate 003, at least part of the temporary bonding adhesive 002 and the adhesive 005 on the side of the dam layer 400 facing away from the second substrate 004, and at least part of the temporary bonding adhesive 002 and the adhesive 005 distributed between adjacent color conversion units 200, can be peeled off together with the temporary substrate 003.

[0234] Of course, after the temporary substrate 003 is peeled off, part of the temporary bonding glue 002 and the adhesive glue 005 may still remain on the side of the dam layer 400 away from the second substrate 004, and part of the temporary bonding glue 002 and the adhesive glue 005 may still remain between adjacent color conversion units 200. Therefore, after the temporary substrate 003 is removed, the motherboard wafer needs to be ashed to remove the colloid remaining on the side of the dam layer 400 away from the second substrate 004, and the colloid remaining between adjacent color conversion units 200. During the ashing process, since the colloid between the light-emitting unit 300 and the color conversion unit 200 (that is, the connecting layer 500) can be protected by the light-emitting unit 300, the colloid between the light-emitting unit 300 and the color conversion unit 200 will not be removed, and the two can be stably connected by this colloid.

[0235] Step S106, reducing the thickness of the second substrate in the mother wafer.

[0236] In the embodiment of the present application, the thickness of the second substrate in the motherboard wafer can be thinned to facilitate subsequent cutting of the second substrate. For example, the thickness of the second substrate in the motherboard wafer can be thinned to within 50 microns to 100 microns.

[0237] Step 107 , cutting the thinned second substrate to cut the motherboard wafer into a plurality of chip structures 000 .

[0238] In the embodiment of the present application, the single chip structure 000 is obtained by cutting the thinned second substrate in the motherboard wafer. Fig.26 , Fig.26 : is a schematic diagram of the structure of a motherboard wafer provided in an embodiment of the present application. The motherboard wafer may include multiple chip structures 000. After the thinned second substrate in the motherboard wafer is cut according to the cutting line L0, multiple chip structures 000 can be obtained. Each chip structure 000 includes the first substrate 100, the light-emitting unit 300, the color conversion unit 200 and the dam layer 400 in the above embodiment. Here, after the thinned second substrate is cut, multiple chip structures 000 can be obtained, and the first substrate 100 in each chip structure 000 is a part of the thinned second substrate in the motherboard wafer. For this reason, the thickness of the first substrate 100 in each chip structure 000 is also 50 microns to 120 microns.

[0239] In the present application, before cutting the mother wafer, the light absorption layer 201, the limiting dam layer 202, the first encapsulation layer 204 and the second encapsulation layer 205 in each chip structure 000 are independently distributed. In this way, it is only necessary to cut the thinned second substrate in the mother wafer to obtain multiple chip structures 000.

[0240] Exemplarily, the thinned second substrate in the motherboard wafer can be cut by laser hidden cutting. Here, during the cutting process, the laser cutting beam can be focused to the middle position of the thinned second substrate in the thickness direction of the thinned second substrate, so that the middle position of the thinned second substrate can be melted or vaporized, and then, a tool can be used to apply force to the upper surface and / or lower surface of the thinned second substrate, so that the part of the first substrate 100 in the single chip structure 000 in the thinned second substrate can be separated. It should be noted that in this process, because the laser cutting beam reaches the middle position of the second substrate, no extra debris (for example, cutting sparks) will be generated during the cutting process and sputtered onto the light-emitting unit 200 or the color conversion unit 300, so that the chip structure 000 obtained by subsequent cutting has a higher reliability.

[0241] In the embodiments of the present application, Fig. 27 As shown, Fig. 27It is a simple schematic diagram of the internal light path of a chip structure provided in an embodiment of the present application when emitting light. In order to further reduce the probability of color crosstalk in the chip structure 000, it is necessary to limit the minimum distance range L between the outer contour of the light-emitting layer 305 in any sub-light-emitting functional layer 300a and the boundary of the opening surface of the adjacent opening area K2 away from the first substrate 100 in the extension direction parallel to the first substrate 100. For example, the minimum distance range L can be: 22 microns to 90 microns. For example, the minimum distance range L can be: (80±3) microns. Preferably, the minimum distance range L can be between 22 microns and 45 microns. In this way, the volume of the chip structure 000 can be minimized while minimizing or avoiding the mutual crosstalk of the light-emitting functional layer 300a.

[0242] For example, taking the first sub-light-emitting functional layer 300a1 in the above embodiment as an example, in the first direction X, the minimum distance between the outer contour of the light-emitting layer 305 in the first sub-light-emitting functional layer 300a1 and the boundary of the opening surface of the second opening area K22 away from the first substrate 100 is between 22 micrometers and 90 micrometers. For another example, taking the third sub-light-emitting functional layer 300a3 in the above embodiment as an example, in the second direction Y, the minimum distance between the outer contour of the light-emitting layer 305 in the third sub-light-emitting functional layer 300a3 and the boundary of the opening surface of the second opening area K22 away from the first substrate 100 is between 22 micrometers and 90 micrometers.

[0243] In the present application, in the extension direction parallel to the first substrate 100, the minimum distance range L between the outer contour of the light-emitting layer 305 in any sub-light-emitting functional layer 300a and the boundary of the opening surface of the adjacent opening area K2 away from the first substrate 100 satisfies the following relationship:

[0244] L=k1×(h1×tanθ1+h2×tanθ2+d01);

[0245] Wherein, h1 represents the thickness of the first semiconductor layer 301, h2 represents the thickness of the first filling portion 501 in the connecting layer 500, θ1 has a value range of 30° to 45°, θ2 has a value range of 80° to 85°, d01 has a value range of 2 microns to 7 microns, and k1 has a value range of 0.8 to 1.2. Here, the thickness of the first semiconductor layer 301 can be: 4 microns to 10 microns.

[0246] Here, d01 in the above formula can be used to characterize: the alignment accuracy between the film layers in the process of forming the film layers in the color conversion unit 200, and the alignment accuracy when the color conversion unit 200 is bonded to the light-emitting unit 300. K1 in the above formula is used to characterize a coefficient so that there is a certain fluctuation space when setting the minimum distance range L. Here, the preferred range of k1 is between 0.98 and 1.02. For example, k1 can also be equal to 1.

[0247] It should be noted that the above-mentioned known θ1 can represent the critical angle at which the light emitted by the sub-light-emitting functional layer 300a and entering the first semiconductor layer 301 undergoes total reflection when it is emitted toward the first filling portion 501. Since the light emitted by the light-emitting layer 305 in the sub-light-emitting functional layer 300a is divergent, and the refractive index of the first semiconductor layer 301 is smaller than the refractive index of the first filling portion 501 in the connecting layer 500. Therefore, for the light emitted from the edge of the light-emitting layer 305, when passing through the first semiconductor layer 301 and emitting toward the first filling portion 501, the light emitted from the first semiconductor layer 301 with an angle greater than the critical angle of total reflection θ1 will undergo total reflection, and this part of the light will definitely not be emitted toward the color conversion unit 200, thereby ensuring that this part of the light will definitely not be emitted toward the adjacent opening area. For this reason, h1×tanθ1 in the above formula can be expressed as Fig. 27 The distance z1 in.

[0248] As for the light emitted from the edge of the light-emitting layer 305, when passing through the first semiconductor layer 301 and emitting to the first filling part 501, the light emitted into the first filling part 501 can be transmitted in the first filling part 501. Here, it is necessary to block the light with a smaller incident angle among the light transmitted in the first filling part 501 by limiting the dam layer 202, so that these light rays will not be emitted to the adjacent opening area; and the light with a larger incident angle among the light transmitted in the first filling part 501 is usually of low light intensity, and even if these light rays are emitted to the adjacent opening area, the probability of cross-color phenomenon can be guaranteed to be low. For example, θ2 can be a preset light output angle set according to the light emission characteristics of the LED, and the light is mainly concentrated in the interval less than or equal to the preset light output angle θ2. Among the light transmitted in the first filling part 501, the light with an incident angle less than or equal to the preset light output angle θ2 among the light rays emitted into the first filling part 501 needs to be blocked by the limiting dam layer 202, while the light with an incident angle greater than the preset light output angle θ2 does not need to be blocked by the limiting dam layer 202. To this end, h2×tanθ2 in the above formula can be expressed as Fig. 27 The distance z2 in.

[0249] In the embodiments of the present application, the above embodiments (for example, please refer to Fig.10 and Fig.11) are schematically described by taking the case where the dam layer is entirely located on the side of the first encapsulation portion 2041 in the first encapsulation layer 204 in the color conversion unit 200 away from the first substrate 100 as an example. In other implementations, please refer to Fig.28 , Fig.28 000 is a schematic diagram of a film structure of a chip structure provided by another embodiment of the present application. A portion of the dam layer 400 in the chip structure 000 may be located on a side of the first packaging portion 2041 in the first packaging layer 204 away from the first substrate 100, and another portion may be located on a side of the second packaging portion 2042 in the first packaging layer 204 away from the limiting dam layer 203. In this case, the dam layer 400 can not only block the light transmitted laterally in the first semiconductor layer 301 in the light-emitting unit 300, but also block the light transmitted laterally in the first packaging layer 204 after the optical waveguide phenomenon is generated in the first packaging layer 204. In this way, the probability of light leakage in the chip structure 000 can be further reduced.

[0250] It should be noted that, since the dam layer 400 is entirely located on the side of the first packaging portion 2041 in the first packaging layer 204 away from the first substrate 100, the stability of the dam layer 400 is relatively high. Therefore, the following embodiments will take the case where the dam layer 400 is entirely located on the side of the first packaging portion 2041 away from the first substrate 100 as an example to describe the various film layers in the chip structure 000 accordingly.

[0251] In the embodiment of the present application, the material of the dam layer 400 in the chip structure 000 may include: any one of an organic material with light absorption and an organic material with light filtering. Here, the organic material with light absorption is a black organic material, which can absorb the light transmitted laterally in the first semiconductor layer 301 in the light-emitting unit 300.

[0252] Exemplarily, since the first light emitted by the light-emitting unit 300 is blue light and / or ultraviolet light, when the material of the dam layer 400 includes an organic material with a light-filtering property, the organic material with a light-filtering property can be a red or green organic material, and its transmittance to blue light is less than 0.02%, so it can absorb the first light transmitted laterally in the first semiconductor layer 301.

[0253] Exemplarily, when the material of the dam layer 400 includes an organic material with light reflection, the reflectivity of the dam layer 400 may range from 40% to 80%. For example, the reflectivity of the dam layer 400 may be 63%±5%. It should be noted that when the reflectivity of the dam layer 400 is above 30%, it can be considered that the dam layer 400 has a certain light reflection. When the reflectivity of the dam layer 400 is between 40% and 80%, after the first light beam transmitted laterally in the first semiconductor layer 301 is emitted from the edge of the first semiconductor layer 301, more of the first light beam can be reflected back through the dam layer 400, thereby improving the phenomenon of edge light leakage in the chip structure 000.

[0254] In the present application, when the material of the dam layer 400 includes an organic material having a light filtering property, the dam layer 400 can absorb the first light and transmit light of other colors. For example, the dam layer 400 can be a green filter layer for transmitting green light, that is, the material of the dam layer 400 can be a green organic material. For another example, the dam layer 400 can be a red filter layer for transmitting red light, that is, the material of the dam layer 400 can be a red organic material.

[0255] Optional, please refer to Fig.29 , Fig.29 3 is a schematic diagram of the film layer structure of another chip structure provided by another embodiment of the present application. In the case where the dam layer 300 is a red filter layer, since the absorptivity of the red filter layer to blue light is lower than that of the green filter layer to blue light, in order to reduce the probability of light leakage in the chip structure 000, the chip structure 000 also needs to include: an auxiliary light shielding layer 600 located between the dam layer 400 and the first encapsulation layer 204. Here, the orthographic projection of the dam layer 400 on the first substrate 100 can be located within the orthographic projection of the auxiliary light shielding layer 600 on the first substrate 100. In this way, even after the light transmitted laterally in the first semiconductor layer 301 is directed to the dam layer 400, and a small part of the light is emitted from the dam layer 400, the light emitted from the dam layer 400 can be shielded by the auxiliary light shielding layer 600, thereby reducing the probability of light leakage in the chip structure 000.

[0256] In the embodiment of the present application, the auxiliary light-shielding layer 600 may have a plurality of auxiliary light-through holes K5. The plurality of auxiliary light-through holes K5 may correspond one-to-one to the plurality of light-through holes K1 in the light-shielding layer 201, and the orthographic projection of each auxiliary light-through hole K5 on the first substrate 100 may overlap with the orthographic projection of the corresponding light-through hole K1 on the first substrate 100. For example, the orthographic projection of each auxiliary light-through hole K5 on the first substrate 100 may be located within the orthographic projection of the corresponding light-through hole K1 on the first substrate 100. Here, the plurality of auxiliary light-through holes K5 may also correspond one-to-one to the plurality of sub-light-emitting functional layers 300a in the light-emitting unit 300, and the orthographic projection of each light-emitting functional layer 300a on the first substrate 100 may be located within the orthographic projection of the corresponding auxiliary light-through hole K5 on the first substrate 100.

[0257] It should be noted that, since the absorption effect of the first light by the light-absorbing organic material is better than that of the light-filtering organic material, the following embodiments will take the material of the dam layer 400 as the light-absorbing organic material as an example to illustrate the size and shape of the dam layer 400.

[0258] Please refer to Fig.30 , Fig.30 It is a schematic diagram of the film layer structure of another chip structure provided by another embodiment of the present application. The dam layer 400 in the chip structure 000 may have: a third surface S4 bonded to the first packaging part 2041 in the first packaging layer 204, and a fourth surface S5 arranged opposite to the third surface S4. It can be understood that the third surface S4 in the dam layer 400 is a side of the dam layer 400 facing the first substrate 100, and the fourth surface S5 in the dam layer 400 is a side of the dam layer 400 facing away from the first substrate 100.

[0259] In the present application, the material of the dam layer 400 is an organic material. If the thickness of the dam layer 400 is too thick, after the dam layer 400 is formed through exposure and development processes, in a direction parallel to the extension surface of the first substrate 100, the width of the third surface S4 in the dam layer 400 is smaller than the width of the fourth surface S5.

[0260] Optionally, the width D3 of the third surface S4 in the dam layer 400 may be greater than or equal to 6.5 microns, so that the firmness of the adhesion between the dam layer 400 and the first encapsulation layer 204 can be ensured to be high. For example, the width D3 of the third surface S4 in the dam layer 400 may be (8±0.5) microns. In the present application, when the dam layer 400 is made of an organic material with light absorption, and the OD value of the organic material is 0.2, in the direction parallel to the first substrate 100, the width D1 of the fourth surface S5 in the dam layer 400 needs to be greater than or equal to 11.5 microns, so that the dam layer 400 has a better effect of shielding the light transmitted laterally in the first semiconductor layer 301. For example, the width D1 of the fourth surface S5 in the dam layer 400 is (18±0.5) microns.

[0261] In the embodiments of the present application, Fig.30 As shown, the dam layer 400 in the chip structure 000 may also have: a second outer contour surface S6 located between the third surface S4 and the fourth surface S5. The second outer contour surface S6 may be a surface that is disposed around the dam layer 400 as a whole, that is, the second outer contour surface S6 may be an outer side surface of the dam layer 400. Here, in a direction parallel to the extension surface of the first substrate 100, when the width of the third surface S4 in the dam layer 400 is smaller than the width of the fourth surface S5, the angle α2 between the third surface S4 in the dam layer 400 and the second outer contour surface S6 is an obtuse angle, and the angle β2 between the fourth surface S5 in the dam layer 400 and the second outer contour surface S6 is an acute angle.

[0262] Exemplarily, the distance range between the third surface S4 and the fifth surface S5 in the dam layer 400 (the thickness range of the dam layer 400) is between 4.3 microns and 15 microns to ensure a good shading effect while not affecting the chip structure 000 being soldered to the substrate (e.g., a driving backplane) that supports it when used as a display element; exemplary, the thickness range of the dam layer 400 can be (6±0.2) microns.

[0263] Exemplarily, the angle ɑ2 between the third surface S4 and the second outer contour surface S6 in the dam layer 400 ranges from 120° to 140°. Exemplarily, the angle ɑ2 between the third surface S4 and the second outer contour surface S6 in the dam layer 400 is 134°±2°.

[0264] When the angle ɑ2 between the third surface S4 and the second outer contour surface S6 in the dam layer 400 is fixed, the width D1 of the fourth surface S5 in the dam layer 400 in the direction parallel to the extension surface of the first substrate 100, the width D3 of the third surface S4 in the dam layer 400, and the thickness of the dam layer 400, two of which can determine the design of another parameter. For example, here, in the direction parallel to the extension surface of the first substrate 100, the width D1 of the fourth surface S5 in the dam layer 400 can be greater than or equal to 17 microns, so that the chip structure 000 can achieve a better side shading effect. For example, the width D1 of the fourth surface S5 in the dam layer 400 can be (18±0.5) microns.

[0265] In the examples of this application, please refer to Fig.31 , Fig.31 It is a top view of a dam layer defined by an embodiment of the present application. In a direction parallel to the extension surface of the first substrate 100, the minimum distance D2 between the outer contour of the dam layer 202 that is away from the first substrate 100 and the boundary of the opening surface of the opening area K2 away from the first substrate 100 is greater than or equal to 20 microns. In this way, the side light leakage of the light-emitting unit 300 can be effectively reduced or avoided, and the light purity of the light-emitting chip 000 can be improved. Preferably, D2 is set between 20 microns and 50 microns. In this way, it is beneficial to reduce the distance between the opening area of ​​the chip structure 000 and the outer contour of the chip structure 000, thereby reducing the overall size of the chip structure 000. Optionally, D2 is set between 20 microns and 40 microns. Optionally, D2 is set between 25 microns and 50 microns.

[0266] For example, in a direction parallel to the extension surface of the first substrate 100, the minimum distance range D5 between the outer contour of the light shielding layer 201 and the light through hole K1 is greater than or equal to 20 micrometers. For example, the orthographic projection of the side of the dam layer 202 in the color conversion unit 200 facing the first substrate 100 on the first substrate 100 may be located within the orthographic projection of the light shielding layer 201 on the first substrate 100. For example, in order to consider the manufacturing accuracy or to make the outer contour of the light shielding layer 201 closer to the outer contour of the first substrate 100 to increase the peripheral anti-light leakage effect, in a direction parallel to the extension surface of the first substrate 100, the minimum distance range D5 between the outer contour of the light shielding layer 201 and the light through hole K1 is greater than or equal to 21 micrometers. For example, D5 may be greater than or equal to 22 micrometers. Optionally, D5 is set between 26 micrometers and 51 micrometers.

[0267] For example, taking the first opening area K21 in the above embodiment as an example, in the first direction X or the second direction Y, the minimum distance D2 between the outer contour of the dam layer 202 facing away from the first substrate 100 and the boundary of the opening surface of the first opening area K21 facing away from the first substrate 100 is greater than or equal to 20 microns. For example, D2 is set between 25 microns and 50 microns.

[0268] In the present application, in a direction parallel to the extension surface of the first substrate 100, the minimum distance range D2 between the outer contour of the dam layer 202 facing away from the first substrate 100 and the boundary of the opening surface of the opening area K2 facing away from the first substrate 100 is related to the width D1 of the fourth surface S5 in the dam layer 400. The minimum distance range D2 may be greater than the width D1 of the fourth surface S5.

[0269] For example, Fig.30 As shown, in the direction parallel to the extension surface of the first substrate 100, the minimum distance range D2 between the outer contour of the dam layer 202 facing away from the first substrate 100 and the boundary of the opening area K2 facing away from the opening surface of the first substrate 100 satisfies the following relationship:

[0270] D2=k2×(D1+d02+d03+d04);

[0271] Among them, D1 represents the width of the fourth surface S5 in the dam layer 400 in the direction parallel to the extension surface of the first substrate 100, the value range of d02 and d03 is between 2 microns and 7 microns, the value range of d04 is between 1 micron and 3 microns, and the value range of k2 is between 0.8 and 1.2.

[0272] Here, d04 in the above formula can be used to characterize: the alignment accuracy between the film layers in the process of forming the film layers in the color conversion unit 300. K2 in the above formula is used to characterize a coefficient so that there is a certain fluctuation space when setting the minimum distance range D2. Here, the preferred range of k2 is between 0.98 and 1.02. For example, k2 can also be equal to 1.

[0273] In the present application, it is defined that the orthographic projections of the opening areas K2 in the dam layer 202 on the first substrate 100 can all be located within the orthographic projections of the first semiconductor layer 301 in the light-emitting unit 300 on the first substrate 100. To this end, the orthographic projections of the optical functional layer 203 in the color conversion unit 200 on the first substrate 100 can all be located within the orthographic projections of the first semiconductor layer 301 in the light-emitting unit 300 on the first substrate 100. In this way, it can be ensured that the light emitted by each sub-light-emitting functional layer 300a in the light-emitting unit 300 can be smoothly projected to the corresponding optical functional layer 203, so as to ensure that the optical functional layer has a good light conversion effect.

[0274] In this case, it is necessary to ensure that the orthographic projection of the outer contour of the first semiconductor layer 301 on the first substrate 100 all falls within the orthographic projection of the dam layer 302 on the first substrate 100. That is, d02 in the above formula can represent: in the direction parallel to the extension surface of the first substrate 100, the minimum distance range between the outer contour of the first semiconductor layer 301 and the boundary of the opening area K2 away from the opening surface of the first substrate 100. At the same time, it is also necessary to ensure that there is a certain distance between the outer contour of the first semiconductor layer 301 and the inner contour of the dam layer 400. That is, d03 in the above formula can represent: in the direction parallel to the extension surface of the first substrate 100, the distance range between the outer contour of the first semiconductor layer 301 and the inner contour of the dam layer 400. For this reason, d02+d03 in the above formula can represent: in the direction parallel to the extension surface of the first substrate 100, the minimum distance range between the inner contour of the dam layer 400 and the boundary of the opening area K2 away from the opening surface of the first substrate 100.

[0275] Here, the value ranges of d02 and d03 in the above formula are related to: the alignment accuracy between the film layers in the process of forming the film layers in the color conversion unit 200, and the alignment accuracy when the color conversion unit 200 is bonded to the light-emitting unit 300. For this reason, the value ranges of d02 and d03 can be the same, and this value range can represent: the alignment accuracy between the film layers in the process of forming the film layers in the color conversion unit 200, and the alignment accuracy when the color conversion unit 200 is bonded to the light-emitting unit 300.

[0276] It should be noted that after determining the minimum distance range D2 between the outer contour of the dam layer 202 facing away from the first substrate 100 in the direction parallel to the extension surface of the first substrate 100 and the boundary of the opening area K2 facing away from the opening surface of the first substrate 100, the minimum distance range D5 between the outer contour of the light shielding layer 201 and the light through hole K1 in the direction parallel to the extension surface of the first substrate 100 can be determined according to the minimum distance range D2. Here, in the direction parallel to the extension surface of the first substrate 100, the minimum distance range D5 between the outer contour of the light shielding layer 201 and the light through hole K1 satisfies the following relationship: D5 = k4 × (D2 + d04). Wherein, the value range of d04 is between 1 micron and 3 microns. Here, k4 in the above formula is used to characterize a coefficient so that there is a certain fluctuation space when setting D5, for example, the value range of k4 is between 1 and 1.2. For example, the preferred range of k4 is between 1 and 1.02. For example, k4 can be equal to 1.

[0277] In the embodiments of the present application, Fig.31As shown, in the direction parallel to the extension surface of the first substrate 100, the minimum width range D4 between the opening surfaces of two adjacent opening areas K2 in the dam layer 202 away from the first substrate 100 is greater than or equal to 18 microns, so that the probability of color crosstalk in the chip structure can be ensured to be low. For example, D4 ​​is in the range of 18 to 80 microns. For example, the value of D4 is 65±3um. In order to facilitate the miniaturization of the chip 000, preferably, D4 can be in the range of 18 to 60 microns. For example, D4 ​​can be in the range of 18 to 30 microns. For example, D4 ​​can be in the range of 22 to 45 microns.

[0278] For example, taking the two adjacent opening areas of the first opening area K21 and the second opening area K22 in the above embodiment as an example, in the first direction X, the minimum width between the opening surface of the first opening area K21 away from the first substrate 100 and the opening surface of the second opening area K22 away from the first substrate 100 is between 18 microns and 80 microns. For another example, taking the two adjacent opening areas of the second opening area K22 and the third opening area K23 in the above embodiment as an example, in the second direction Y, the minimum width between the opening surface of the second opening area K22 away from the first substrate 100 and the opening surface of the third opening area K23 away from the first substrate 100 is between 18 microns and 80 microns.

[0279] In the present application, in a direction parallel to the extension surface of the first substrate 100, a minimum width range D4 between opening surfaces of two adjacent opening areas K2 in the dam layer 202 facing away from the first substrate 100 is defined, which is related to the size of the opening area K2 and the size of the light-emitting layer 305 in the sub-light-emitting functional layer 300a, and the minimum width range D4 is also related to the lowest width range L in the above-mentioned embodiment.

[0280] For example, Fig.30 As shown, in a direction parallel to the extension surface of the first substrate 100, the minimum width range D4 between the opening surfaces of two adjacent opening regions K2 in the dam layer 202 facing away from the first substrate 100 satisfies the following relationship:

[0281] D4 = k3 × [L - (J1 - J2) / 2];

[0282] Among them, J1 represents the width range of the opening surface of the opening area K2 away from the first substrate 100 in the arrangement direction of two adjacent opening areas K2 (for example, the first direction X or the second direction Y); J2 represents the width range of the light-emitting layer 305 in the sub-light-emitting functional layer 300a in the arrangement direction of two adjacent opening areas K2; the value range of k3 is between 0.8 and 1.2.

[0283] Here, k3 in the above formula is used to represent a coefficient, so that there is a certain fluctuation space when setting the minimum distance range D2. For example, the preferred range of k3 is between 0.98 and 1.02. For example, k3 can also be equal to 1.

[0284] It should be noted that after determining the minimum width range D4 between the opening surfaces of two adjacent opening areas K2 in the dam layer 202 away from the first substrate 100 in the direction parallel to the extension surface of the first substrate 100, the minimum width range D6 between the opening surfaces of two adjacent light holes K1 in the light shielding layer 201 away from the first substrate 100 in the direction parallel to the extension surface of the first substrate 100 can be determined based on the minimum distance range D4. Here, in the direction parallel to the extension surface of the first substrate 100, the minimum width range D6 between the opening surfaces of two adjacent light holes K1 in the light shielding layer 201 away from the first substrate 100 satisfies the following relationship: D6 = k5 × (D4 + d04). Wherein, the value range of d04 is between 1 micron and 3 microns. Here, k5 in the above formula is used to characterize a coefficient so that there is a certain fluctuation space when setting D6, for example, the value range of k5 is between 1 and 1.2. For example, k5 can be equal to 1.

[0285] In the embodiment of the present application, the orthographic projection of the sub-light-emitting functional layer 300a in the light-emitting unit 300 on the first substrate 100 may be located within the orthographic projection of the corresponding opening area K2 in the defined dam layer 202 on the first substrate 100. The ratio of the area of ​​the opening surface of the opening area K2 away from the first substrate 100 to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100 is in the range of 3 to 6.25. Preferably, the ratio of the area of ​​the opening surface of the opening area K2 away from the first substrate 100 to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100 is in the range of 4 to 6.25.

[0286] Here, when the ratio of the area of ​​the opening surface of the opening region K2 away from the first substrate 100 to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100 is greater than or equal to 3, it can be ensured that the light emitted by the sub-light-emitting functional layer 300a has a high light extraction efficiency when it is emitted through the corresponding opening region K2. For example, when the ratio of the area of ​​the opening surface of the opening region K2 away from the first substrate 100 to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100 is greater than or equal to 4, its light extraction efficiency can be above 90%. When the ratio of the area of ​​the opening surface of the opening region K2 away from the first substrate 100 to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100 is 6.25, the light extraction efficiency of the light emitted by the sub-light-emitting functional layer 300a when it is emitted through the corresponding opening region K2 tends to be stable. If the area of ​​the opening surface of the opening region K2 away from the first substrate 100 is further increased, the light extraction efficiency will not be significantly improved, and the size of the chip structure 000 will also be larger. For this reason, the ratio of the area of ​​the opening surface of the opening region K2 away from the first substrate 100 to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer 300a on the first substrate 100 needs to be less than or equal to 6.25.

[0287] Exemplarily, the shape of the orthographic projection of the sub-light-emitting functional layer 300a on the first substrate 100 and the shape of the opening surface of the opening area K2 away from the first substrate 100 can both be square. For example, when the side length of the orthographic projection of the sub-light-emitting functional layer 300a on the first substrate 100 is 20 microns, if the side length of the opening surface of the opening area K2 away from the first substrate 100 is 40 microns, the light extraction efficiency of the light emitted by the sub-light-emitting functional layer 300a when it is emitted through the corresponding opening area K2 is 94.4%; if the side length of the opening surface of the opening area K2 away from the first substrate 100 is 50 microns, the light extraction efficiency of the light emitted by the sub-light-emitting functional layer 300a when it is emitted through the corresponding opening area K2 is 97.1%; if the side length of the opening surface of the opening area K2 away from the first substrate 100 is greater than 50 microns, for example, it is 60 microns or 70 microns, then the light extraction efficiency of the light emitted by the sub-light-emitting functional layer 300a when it is emitted through the corresponding opening area K2 is still 97.1%.

[0288] For another example, when the side length of the orthographic projection of the sub-light-emitting functional layer 300a on the first substrate 100 is 30 microns, if the side length of the opening surface of the opening area K2 away from the first substrate 100 is 60 microns, the light output efficiency of the light emitted by the sub-light-emitting functional layer 300a when it passes through the corresponding opening area K2 is 92.7%; if the side length of the opening surface of the opening area K2 away from the first substrate 100 is 80 microns, the light output efficiency of the light emitted by the sub-light-emitting functional layer 300a when it passes through the corresponding opening area K2 is 95.7%; if the side length of the opening surface of the opening area K2 away from the first substrate 100 is greater than 80 microns, for example, it is 90 microns or 100 microns, then the light output efficiency of the light emitted by the sub-light-emitting functional layer 300a when it passes through the corresponding opening area K2 can be increased to 95.9%.

[0289] It should be noted that the light output efficiency of the sub-light-emitting functional layer 300a when it passes through the corresponding opening area K2 refers to: the light intensity of the light emitted by the sub-light-emitting functional layer 300a when it passes through the corresponding opening area K2, as a percentage of the light intensity of the light emitted by the sub-light-emitting functional layer 300a.

[0290] In summary, the chip structure of the embodiment of the present application includes: a first substrate, a light-emitting unit, a color conversion unit and a dam layer. Since the dam layer can be arranged around the light-emitting unit, and the maximum distance between the side of the dam layer facing away from the color conversion unit and the first substrate is greater than or equal to the maximum distance between the side of the first semiconductor layer in the light-emitting unit facing away from the first substrate and the first substrate. Therefore, after the light waveguide phenomenon occurs inside the first semiconductor layer, the light that is laterally transmitted in the first semiconductor layer can be blocked by the dam layer after it is emitted from any position of the edge. In this way, even if the light entering the first semiconductor generates the light waveguide phenomenon, the light emitted from the edge of the first semiconductor can be blocked by setting the dam layer, thereby effectively reducing the probability of light leakage in the chip structure, so that the display effect of the display substrate integrated with such a chip structure is better.

[0291] The embodiment of the present application also provides a display substrate, which can be a display screen in a mobile phone, a laptop or a flat-panel computer, or an outdoor advertising screen. Among them, the display substrate may include: a driving backplane, and a plurality of chip structures located on one side of the driving backplane. Here, each chip structure in the display substrate can be a chip structure in the above embodiment. And each anode pad and cathode pad in the chip structure can be fixed on the driving backplane by welding to be electrically connected to the driving backplane. It should be noted that the driving backplane can provide corresponding driving signals to each chip structure, so that the light-emitting unit in the chip structure emits light, and then the display substrate can present a corresponding display screen.

[0292] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0293] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0294] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip structure, characterized in that: include: A first substrate, a light-emitting unit and a color conversion unit, wherein the color conversion unit is located at a light-emitting side of the light-emitting unit and is closer to the first substrate than the light-emitting unit; The light-emitting unit comprises: a plurality of sub-light-emitting functional layers, and a first semiconductor layer located at the light-emitting side of the plurality of sub-light-emitting functional layers, the first semiconductor layer comprises: a plurality of connecting parts corresponding to the plurality of sub-light-emitting functional layers one by one, and an auxiliary part connected to the plurality of connecting parts, the connecting parts are connected to the corresponding sub-light-emitting functional layers, at least part of the auxiliary part is located between adjacent connecting parts, and the auxiliary part and the connecting part are an integral structure; The chip structure further includes: a dam layer arranged around the light-emitting unit, wherein the maximum distance between the first substrate and a side of the dam layer facing away from the color conversion unit is greater than or equal to the maximum distance between the first semiconductor layer and a side facing away from the first substrate.

2. The chip structure according to claim 1, characterized in that: The multiple light-emitting functional layers in the light-emitting unit are all used to emit a first light; the dam layer is used to absorb the light emitted by the sub-light-emitting functional layer and transmitted laterally in the first semiconductor layer, so that when the chip structure only emits red light under the action of the color conversion unit, the brightness of the first light accounts for less than or equal to 3% of the brightness of the red light, and when the chip structure only emits green light under the action of the color conversion unit, the brightness of the first light accounts for less than or equal to 3% of the brightness of the green light.

3. The chip structure according to claim 1, characterized in that: The orthographic projection of the dam layer on the first substrate overlaps with the orthographic projection of the color conversion unit on the first substrate; The orthographic projection of one side of the dam layer facing away from the first substrate on the first substrate is used to enclose an enclosing area, and the orthographic projection of the light-emitting unit on the first substrate is located in the enclosing area, or the orthographic projection of the light-emitting unit on the first substrate is located in the enclosing area after translation.

4. The chip structure according to claim 1, characterized in that: The chip structure further includes: a connection layer, at least a portion of which is located between the light-emitting unit and the color conversion unit, and the connection layer includes: any one of an indium zinc oxide connection layer, a metal connection layer and an adhesive layer.

5. The chip structure according to claim 4, characterized in that: In the case where the connection layer includes the adhesive layer, the connection layer includes: a first filling portion and a second filling portion, the first filling portion is located between the light emitting unit and the color conversion unit, and the second filling portion is located between the dam layer and the light emitting unit.

6. The chip structure according to claim 5, characterized in that: The connection layer further includes an overflow portion, and the overflow portion is located at a side of the dam layer facing away from the first substrate.

7. The chip structure according to any one of claims 4 to 6, characterized in that: The thickness of a portion of the connection layer located between the light emitting unit and the color conversion unit is between 0.3 micrometers and 3 micrometers.

8. The chip structure according to claim 1, characterized in that: The light emitting unit further comprises an electrode structure arranged opposite to the first semiconductor layer, and a maximum distance between the electrode structure facing away from the first substrate and the first substrate is greater than or equal to a maximum distance between the dam layer facing away from the color conversion unit and the first substrate.

9. The chip structure according to claim 1, characterized in that: The material of the first substrate is glass, and the thickness of the first substrate is between 50 micrometers and 120 micrometers.

10. The chip structure according to any one of claims 1-6, 8-9, characterized in that: The color conversion unit comprises: A light shielding layer located on one side of the first substrate, the light shielding layer having a plurality of light through holes; a limiting dam layer located on a side of the light shielding layer away from the first substrate, the limiting dam layer having a plurality of opening areas corresponding one-to-one to the plurality of light through holes, and the plurality of opening areas corresponding one-to-one to the plurality of sub-light emitting functional layers, an orthographic projection of the opening area on the first substrate overlapping with an orthographic projection of a corresponding light through hole on the first substrate, and overlapping with an orthographic projection of a corresponding sub-light emitting functional layer on the substrate; An optical functional layer located in the opening area, at least a portion of the optical functional layer is used to convert the color of light entering the optical functional layer; a first encapsulation layer located on a side of the definition dam layer away from the first substrate; The light-emitting unit is located on a side of the first encapsulation layer away from the first substrate, and at least a portion of the dam layer is located on a side of the first encapsulation layer away from the first substrate.

11. The chip structure according to claim 10, characterized in that: The defining dam layer comprises: a first surface facing the first substrate, a second surface facing away from the first substrate, and a first outer contour surface between the first surface and the second surface, wherein the first outer contour surface is a surface that is entirely disposed around the defining dam layer; Wherein, the angle between the first surface and the first outer contour surface is an obtuse angle.

12. The chip according to claim 11, characterized in that: The distance between the first surface and the second surface ranges from 5 micrometers to 15 micrometers; the angle between the first surface and the first outer contour surface ranges from 90° to 130°.

13. The chip structure according to claim 11, characterized in that: The material of the dam layer includes: an organic material with light absorption or an organic material with light reflection.

14. The chip structure according to claim 10, characterized in that: Each of the sub-light-emitting functional layers comprises a light-emitting layer; In a direction parallel to the extension surface of the first substrate, the minimum distance between the outer contour of the light-emitting layer in any of the sub-light-emitting functional layers and the boundary of the opening surface of the adjacent opening area away from the first substrate is in a range of 22 microns to 90 microns.

15. The chip structure according to claim 10, characterized in that: Each of the sub-light-emitting functional layers comprises a light-emitting layer; In the case where the chip structure includes a connection layer, and the material of the connection layer includes an adhesive layer, in a direction parallel to the extension surface of the first substrate, the minimum distance range L between the outer contour of the light-emitting layer in any of the sub-light-emitting functional layers and the boundary of the opening surface of the adjacent opening area away from the first substrate side satisfies the following relationship: L=k1×(h1×tanθ1+h2×tanθ2+d01); Among them, h1 represents the thickness of the first semiconductor layer, h2 represents the thickness of the first filling part in the connecting layer, the value range of θ1 is between 30° and 45°, the value range of θ2 is between 80° and 85°, the value range of d01 is between 2 microns and 7 microns, and the value range of k1 is between 0.8 and 1.

2.

16. The chip structure according to claim 11, characterized in that: The first packaging layer includes: a first packaging portion disposed in contact with the second surface, and a second packaging portion disposed in contact with the outer contour surface; The dam layer is entirely located on a side of the first encapsulation portion away from the first substrate, or a portion of the dam layer is located on a side of the first encapsulation portion away from the first substrate, and another portion is located on a side of the second encapsulation portion away from the defining dam layer.

17. The chip structure according to claim 10, characterized in that: The first encapsulation layer is a film layer structure that is continuously distributed at various positions, and the orthographic projections of the limiting dam layer and the optical functional layer on the first substrate are both located within the orthographic projection of the first encapsulation layer on the first substrate; The chip structure further includes: a second encapsulation layer located between the limiting dam layer and the light shielding layer; The second encapsulation layer is arranged in contact with the first encapsulation layer to completely wrap the definition dam layer and the optical functional layer, and the area where the second encapsulation layer contacts the first encapsulation layer is distributed around the definition dam layer.

18. The chip structure according to claim 16, characterized in that: In the case where the dam layer is entirely located on a side of the first encapsulation portion in the first encapsulation layer facing away from the first substrate, the dam layer has: a third surface bonded to the first encapsulation portion, and a fourth surface arranged opposite to the third surface; Wherein, in a direction parallel to the extending surface of the first substrate, the width of the third surface is greater than or equal to 6.5 microns, and the width of the fourth surface is greater than or equal to 11.5 microns.

19. The chip structure according to claim 10, characterized in that: In a direction parallel to the extension surface of the first substrate, a minimum distance between an outer contour of the dam layer that is defined as facing away from the first substrate and a boundary of the opening area that is facing away from the open surface of the first substrate is greater than or equal to 20 microns.

20. The chip structure according to claim 10, characterized in that: In a direction parallel to the extension surface of the first substrate, a minimum distance D2 between an outer contour of the limiting dam layer facing away from the first substrate and a boundary of the opening area facing away from the open surface of the first substrate satisfies the following relationship: D2=k2×(D1+d02+d03+d04); Among them, D1 represents the width of the fourth surface in a direction parallel to the extension surface of the first substrate, the value ranges of d02 and d03 are both between 2 microns and 7 microns, the value range of d04 is between 1 micron and 3 microns, and the value range of k2 is between 0.8 and 1.

2.

21. The chip structure according to claim 10, characterized in that: In a direction parallel to the extending surface of the first substrate, a minimum width between opening surfaces of two adjacent opening regions facing away from the first substrate is in a range of 18 micrometers to 80 micrometers.

22. The chip structure according to claim 10, characterized in that: In a direction parallel to the extension surface of the first substrate, the minimum width range D4 between the opening surfaces of two adjacent opening regions facing away from the first substrate satisfies the following relationship: D4 = k3 × [L - (J1 - J2) / 2]; Among them, L represents the minimum distance range between the outer contour of the light-emitting layer in any of the sub-light-emitting functional layers and the boundary of the opening surface of the adjacent opening area away from the first substrate side in the direction parallel to the extension surface of the first substrate; J1 represents the width range of the opening surface of the opening area away from the first substrate in the arrangement direction of two adjacent opening areas; J2 represents the width range of the light-emitting layer in the arrangement direction of two adjacent opening areas; and the value range of k3 is between 0.8 and 1.

2.

23. The chip structure according to claim 18, characterized in that: The dam layer further comprises: a second outer contour surface located between the third surface and the fourth surface, the second outer contour surface being a surface that entirely surrounds the limiting dam layer; The included angle between the second outer contour surface and the third surface is an obtuse angle, and the included angle between the second outer contour surface and the third surface ranges from 120° to 140°.

24. The chip structure according to claim 18, characterized in that: A distance between the third surface and the fourth surface in the dam layer ranges from 4.3 micrometers to 15 micrometers.

25. The chip structure according to any one of claims 11 to 24, characterized in that: The plurality of sub-light emitting functional layers include: a first sub-light emitting functional layer, a second sub-light emitting functional layer and a third sub-light emitting functional layer; The plurality of opening regions include: a first opening region, a second opening region and a third opening region, the first opening region is arranged opposite to the first sub-light-emitting functional layer, the second opening region is arranged opposite to the second sub-light-emitting functional layer, and the third opening region is arranged opposite to the third sub-light-emitting functional layer; The first opening area and the second opening area are arranged in a row in a first direction, the second opening area and the third opening area are arranged in a row in a second direction, and the first direction intersects with the second direction; The area enclosed by the outer contour of the dam layer is a rectangle; the shapes of the first opening area, the second opening area and the third opening area are all rectangles.

26. The chip structure according to claim 10, characterized in that: The orthographic projection of the sub-light-emitting functional layer on the first substrate is located within the orthographic projection of the corresponding opening area on the first substrate; the ratio of the area of ​​the opening surface of the opening area away from the first substrate to the area of ​​the orthographic projection of the corresponding sub-light-emitting functional layer on the first substrate is in a range of 4 to 6.

25.

27. The chip structure according to claim 10, characterized in that: The orthographic projection of a surface of the limiting dam layer facing the first substrate on the first substrate is located within the orthographic projection of the light shielding layer on the first substrate.

28. The chip structure according to claim 10, characterized in that: The color conversion unit also includes: a filter layer located between the first substrate and the optical functional layer; the filter layer includes a plurality of filter units corresponding one by one to the plurality of light holes, and the orthographic projection of the filter unit on the first substrate overlaps with the orthographic projection of the corresponding light hole on the first substrate.

29. The chip structure according to claim 10, characterized in that: The material of the dam layer includes any one of an organic material with light absorption, an organic material with light reflection and an organic material with light filtering.

30. The chip structure according to claim 29, characterized in that: The multiple light-emitting functional layers in the light-emitting unit are all used to emit the first light; when the dam layer is made of an organic material with light filtering properties, the dam layer is used to absorb the first light and transmit light of other colors.

31. The chip structure according to claim 30, characterized in that: The first light is at least one of blue light and ultraviolet light; the dam layer is a green filter layer for transmitting green light, or the dam layer is a red filter layer for transmitting red light.

32. The chip structure according to claim 31, characterized in that: In the case where the dam layer is the red filter layer, the chip structure further comprises: an auxiliary light shielding layer located between the dam layer and the first encapsulation layer, the orthographic projection of the dam layer on the first substrate being located within the orthographic projection of the auxiliary light shielding layer on the first substrate; The auxiliary light-shielding layer has a plurality of auxiliary light-through holes corresponding one-to-one to the plurality of light-through holes, and the orthographic projections of the auxiliary light-through holes on the first substrate overlap with the orthographic projections of the corresponding light-through holes on the first substrate.

33. The chip structure according to any one of claims 1-6, 8-9, 11-24, 26-32, characterized in that: The light emitting unit further includes: a first electrode connected to the first semiconductor layer; The auxiliary part includes a first auxiliary part, a second auxiliary part and a third auxiliary part; the orthographic projection of the first auxiliary part on the first substrate overlaps with the orthographic projection of the first electrode on the first substrate; a part of the second auxiliary part is located between the adjacent connecting parts, and another part is located between the first auxiliary part and the connecting part; the third auxiliary part is arranged around the first auxiliary part, the second auxiliary part and the plurality of connecting parts, and the material of the auxiliary part is the same as that of the connecting part; The sub-light-emitting functional layer includes: a second electrode, a second semiconductor layer and the light-emitting layer stacked in a direction vertical to and toward the first substrate; wherein the light-emitting layer is connected to a corresponding connecting portion in the first semiconductor layer.

34. The chip structure according to claim 33, characterized in that: The first semiconductor layer includes: a first sublayer and a second sublayer stacked in a direction vertical to and toward the first substrate, the first sublayer is located between the second sublayer and the light-emitting layer, the material of the first sublayer is N-type doped gallium nitride, and the second sublayer is a gallium nitride buffer layer; The material of the second semiconductor layer includes P-type doped gallium nitride, and the light-emitting layer is a multi-quantum well layer.

35. A display substrate, characterized in that: include: A driving backplane, and a plurality of chip structures arranged in an array on one side of the driving backplane, wherein the chip structure is the chip structure described in any one of claims 1 to 34.

36. A method for manufacturing a chip structure, characterized in that: The method is used to prepare the chip structure according to any one of claims 1 to 34, and the method comprises: Forming a first initial wafer including a plurality of the color conversion units, the first initial wafer comprising: a second substrate, a plurality of color conversion units distributed on one side of the second substrate, and a dam layer distributed on a side of each of the color conversion units away from the second substrate; forming a second initial wafer including a plurality of the light emitting units, wherein the second initial wafer comprises: a temporary substrate, and a plurality of the light emitting units located on the temporary substrate; forming an adhesive on the second initial wafer; Aligning the second initial wafer with the first initial wafer so that the light-emitting unit is connected to the corresponding color conversion unit through the adhesive; removing the temporary substrate to obtain a motherboard wafer, and performing an ashing process on the motherboard wafer to remove the colloid remaining on the dam layer away from the second substrate; The second substrate is thinned, and the thinned second substrate is cut to cut the motherboard wafer into a plurality of chip structures.

Images