Single crystal silicon substrate with nitride semiconductor layer, and method for producing single crystal silicon substrate with nitride semiconductor layer

Abstract

The present invention is a single crystal silicon substrate with a nitride semiconductor layer, the single crystal silicon substrate having a single crystal silicon substrate, a 3C-SiC single crystal film epitaxially grown on the single crystal silicon substrate, and a nitride semiconductor layer epitaxially grown on the 3C-SiC single crystal film, the single crystal silicon substrate being characterized in that: the nitride semiconductor layer is formed on the 3C-SiC single crystal film; dislocations are formed on the entire single crystal silicon substrate, the length (dislocation length) when the dislocation plane is projected on the single crystal silicon substrate is 1 mm or more, and the density of the dislocation is 10 / cm2 or more. As a result, it is possible to provide: a single crystal silicon substrate with a nitride semiconductor layer, which is a single crystal silicon substrate with a nitride semiconductor layer having a large diameter such as 200 mm or 300 mm, which uses a Si substrate having a general thickness, has reduced warpage, and is capable of producing a single crystal silicon substrate with a nitride semiconductor layer; particularly, no crack is generated.

Description

Technical Field

[0001] The present invention relates to a single crystal silicon substrate with a nitride semiconductor layer and a method for manufacturing the single crystal silicon substrate with a nitride semiconductor layer. More specifically, it relates to a single crystal silicon substrate with a nitride semiconductor layer having a large diameter of 200 mm, 300 mm or even larger and a method for manufacturing the single crystal silicon substrate with a nitride semiconductor layer. Background Art

[0002] Nitride semiconductor materials, such as GaN, are materials that can be used in a very wide range. They can perform very fast high-speed operations through the two-dimensional electron gas layer generated by self-polarization. Therefore, in addition to being used in high-speed switches, high-frequency devices, and power devices, they can even be used in light-emitting devices such as LEDs.

[0003] Against this background, nitride semiconductors (e.g., GaN) have been studied since a very early stage. In addition to self-supporting substrates, there are also heteroepitaxial substrates formed by epitaxially growing nitride semiconductor layers on substrates such as sapphire. Among them, the "single crystal silicon substrate with a nitride semiconductor layer" formed by forming a nitride semiconductor layer on a single crystal silicon substrate uses highly versatile single crystal silicon (Si) as a substrate, is cheap, and has a high affinity with silicon (Si) device processes, and is highly anticipated. In order to take advantage of such characteristics, research on growing nitride semiconductor layers on single crystal silicon (Si) substrates with a large diameter of 300mm is extremely attractive and has been actively studied.

[0004] When a nitride semiconductor layer such as GaN is grown on a single crystal silicon (Si) substrate, a nitride semiconductor layer such as AlN is usually used as a buffer layer. In addition, at this time, the following problem occurs: Al and Ga melt back from the nitride semiconductor layer to the single crystal silicon (Si) substrate and become defects. As a method for preventing this phenomenon, a method for growing SiC on a single crystal silicon (Si) substrate is disclosed, and in particular, a method for growing 3C-SiC on a single crystal silicon (Si) substrate is disclosed considering the ease of growth on a single crystal silicon (Si) substrate (see patent documents 1 to 4).

[0005] In addition, when manufacturing a large-diameter single-crystal silicon substrate with a nitride semiconductor layer, the problem is the deformation and cracking of the single-crystal silicon substrate (wafer) caused by the difference in the linear expansion coefficients of Si and GaN. For the growth of GaN, a high growth temperature of more than 1000°C is required, but during the cooling process from the growth temperature to room temperature, it will be greatly affected by the linear expansion coefficient and cause deformation and cracking. If it is only a deformation such as warping, there is a solution. However, if a large-diameter single-crystal silicon substrate (wafer) of 300mm is cracked, there is no solution, so the problem is very serious.

[0006] Furthermore, even if the nitride semiconductor layer does not break immediately after it is grown and formed, it may still break due to the pressure during the transportation of the single crystal silicon substrate (wafer) or the pressure during the device manufacturing process of repeatedly clamping the single crystal silicon substrate (wafer) onto the stage, etc., which may cause the problem of not being able to manufacture devices with good yield. In addition, the breakage of the wafer may cause contamination and breakage of process equipment, so it is not just a problem of the wafer.

[0007] In order to solve the problem of warping and cracking, it is known to make the Si substrate 1mm to 1.5mm thick. By increasing the thickness, warping and cracking can be alleviated, but since the wafer becomes thicker, there will be problems such as the inability to put it into device processing, and the problem of cutting loss (kerf loss) caused by grinding and polishing the Si substrate to make it thinner, so it cannot be fundamentally solved.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent No. 5693946

[0011] Patent Document 2: Japanese Patent No. 6450282

[0012] Patent Document 3: Japanese Patent No. 6781095

[0013] Patent Document 4: Japanese Patent No. 6266490

[0014] Non-patent literature

[0015] Non-patent literature 1: TI Technical White Paper, “Achieving GaN Products with Lifetime Reliability” (2021). Summary of the invention

[0016] 1. Technical issues to be resolved

[0017] The present invention is completed to solve the above-mentioned problems, and its purpose is to provide a single crystal silicon substrate with a nitride semiconductor layer and a method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer. The single crystal silicon substrate with a nitride semiconductor layer is a single crystal silicon substrate with a nitride semiconductor layer with a large diameter such as 200 mm or 300 mm, which uses a Si substrate of general thickness, reduces warping, and especially does not produce cracks.

[0018] (II) Technical solution

[0019] The present invention is completed in order to achieve the above-mentioned purpose, and provides a single crystal silicon substrate with a nitride semiconductor layer, which has a single crystal silicon substrate, a 3C-SiC single crystal film epitaxially grown on the single crystal silicon substrate, and a nitride semiconductor layer epitaxially grown on the 3C-SiC single crystal film, wherein the single crystal silicon substrate with a nitride semiconductor layer is characterized in that dislocations are formed on the entire single crystal silicon substrate, the length of the dislocation plane when projected onto the single crystal silicon substrate (dislocation length) is greater than 1 mm, and the density of the dislocations is 10 / cm 2 above.

[0020] Based on such a single crystal silicon substrate with a nitride semiconductor layer, a single crystal silicon substrate with a nitride semiconductor layer having a large diameter of 200 mm or 300 mm is formed, which uses a Si substrate of general thickness, reduces warping, and especially does not produce cracks.

[0021] In this case, the thickness of the 3C-SiC single crystal film can be set to be greater than or equal to 50 nm and less than or equal to 200 nm.

[0022] As a result, a single crystal silicon substrate with a nitride semiconductor layer having a large diameter of 200 mm or 300 mm can be more reliably formed, using a Si substrate of normal thickness, reducing warping and especially preventing cracks, and being able to fully prevent the remelting of Al and Ga.

[0023] At this time, the nitride semiconductor layer can be made of Al x In y Ga 1-x-y N (0≤x+y≤1) is the principal component.

[0024] As a result, a useful single crystal silicon substrate having a nitride semiconductor layer with a large diameter of 200 mm or 300 mm can be formed, which uses a Si substrate of normal thickness, reduces warping, and particularly does not cause cracks.

[0025] The present invention is completed in order to achieve the above-mentioned purpose, and provides a method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer, characterized in that it has a step of epitaxially growing a 3C-SiC single crystal film on the single crystal silicon substrate and a step of epitaxially growing a nitride semiconductor layer on the 3C-SiC single crystal film. In the manufacturing method, the thickness of the 3C-SiC single crystal film is made less than 200nm by the step of epitaxially growing the 3C-SiC single crystal film on the single crystal silicon substrate, and dislocations are formed on the entire single crystal silicon substrate by implementing the step of epitaxially growing the nitride semiconductor layer on the 3C-SiC single crystal film, and the length of the dislocation plane when projected onto the single crystal silicon substrate (dislocation length) is made more than 1mm, and the density of the dislocations is made 10 / cm 2 above.

[0026] According to such a method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer, a single crystal silicon substrate with a nitride semiconductor layer having a large diameter such as 200 mm or 300 mm can be manufactured, which uses a Si substrate of general thickness, reduces warping, and especially does not produce cracks.

[0027] (III) Beneficial effects

[0028] As described above, according to the single crystal silicon substrate with a nitride semiconductor layer of the present invention, a single crystal silicon substrate with a nitride semiconductor layer having a large diameter of 200 mm or 300 mm is formed, which uses a Si substrate of general thickness, reduces warping, and especially does not produce cracks.

[0029] According to the manufacturing method of a single crystal silicon substrate with a nitride semiconductor layer of the present invention, a single crystal silicon substrate with a nitride semiconductor layer of a large diameter such as 200mm or 300mm can be manufactured. It uses a Si substrate of general thickness, reduces warping, and especially does not produce cracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 FIG. 1 is a cross-sectional view showing an example of a single crystal silicon substrate with a nitride semiconductor layer.

[0031] Figure 2 The present invention is a schematic flow chart showing an example of a method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer.

[0032] Figure 3 This is an example of the cross-sectional structure when 3C-SiC is grown.

[0033] Figure 4 This is the XRT measurement result of the substrate in Example 1.

[0034] Figure 5 It is the XRT measurement result of the substrate of Comparative Example 1.

[0035] Figure 6 It is the XRT measurement result of the substrate of Comparative Example 2. DETAILED DESCRIPTION

[0036] Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.

[0037] As described above, a single crystal silicon substrate with a nitride semiconductor layer and a method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer are sought. The single crystal silicon substrate with a nitride semiconductor layer is a single crystal silicon substrate with a nitride semiconductor layer of a large diameter such as 200 mm or 300 mm, which uses a Si substrate of general thickness, reduces warping, and especially does not produce cracks.

[0038] The inventors of the present application have conducted in-depth research on the above-mentioned technical problems and found that a single crystal silicon substrate with a nitride semiconductor layer having a large diameter of 200 mm or 300 mm can be provided by using a single crystal silicon substrate with a nitride semiconductor layer. The single crystal silicon substrate uses a Si substrate of general thickness, reduces warping, and in particular does not produce cracks. The present invention is thus completed. The single crystal silicon substrate with a nitride semiconductor layer comprises a single crystal silicon substrate, a 3C-SiC single crystal film epitaxially grown on the single crystal silicon substrate, and a nitride semiconductor layer epitaxially grown on the 3C-SiC single crystal film. The single crystal silicon substrate with a nitride semiconductor layer is characterized in that dislocations are formed on the entire single crystal silicon substrate, the length of the dislocation plane when projected onto the single crystal silicon substrate (dislocation length) is greater than 1 mm, and the density of the dislocations is 10 / cm 2 above.

[0039] The structure of growing SiC on a Si substrate has been disclosed in Patent Documents 1 to 4. In particular, in Patent Document 4, paragraphs

[0030] and

[0031] disclose that the thickness of SiC is greater than 2 nm and less than 3.5 μm, but there is no record of dislocation density. In addition, the original technical concept of using a thicker Si substrate is to use the Si substrate to receive stress and not deform it, but the method of the present invention is a method of relieving the deformation of the wafer by uniformly introducing dislocations into the Si substrate, so it is an unprecedented and new concept and method.

[0040] GaN devices form and utilize a two-dimensional electron gas layer to produce a large saturation drift velocity and electron mobility, so they are horizontal devices with a planar structure of heterojunction field effect transistors (HFET) that can allow a large current density to flow. Therefore, as described in non-patent document 1, even if there are a large number of dislocations on the Si substrate, there will be no problem as long as there are no dislocations in the GaN layer.

[0041] Hereinafter, a single crystal silicon substrate with a nitride semiconductor layer and a method for manufacturing the single crystal silicon substrate with a nitride semiconductor layer according to an embodiment of the present invention will be described.

[0042] (Single crystal silicon substrate with nitride semiconductor layer)

[0043] Figure 1 FIG. 1 is a cross-sectional view showing an example of a single crystal silicon substrate with a nitride semiconductor layer.

[0044] like Figure 1 As shown, the single crystal silicon substrate 1 with a nitride semiconductor layer includes a single crystal silicon substrate 10 , a SiC single crystal film 11 , and a nitride semiconductor layer 31 .

[0045] (Single crystal silicon substrate)

[0046] The diameter and thickness of the single crystal silicon substrate 10 are not particularly limited.

[0047] For example, the diameter can be set to 50 mm to 300 mm or more. A large diameter such as 200 mm or 300 mm is particularly preferred. The thickness is set to be 750 μm or more and 800 μm or less, based on 775 μm, which is a general thickness. By using a single crystal silicon substrate 10 of 750 μm or more and 800 μm or less, no special processing is required, and for a device process using a single crystal silicon substrate 1 with a nitride semiconductor layer, there is no need to worry about various adverse conditions caused by the input of thicker wafers, which is a concern when inputting wafers of different thicknesses.

[0048] The plane orientation of the single crystal silicon substrate 10 is not particularly limited.

[0049] For example, the plane orientation can be any one of (100), (111), and (110). In particular, it is preferred that the plane orientation of the single crystal silicon substrate 10 be (111). The reason for this is that the (111) substrate has fewer directions (slip planes) in which dislocations are prone to slip than the (100) substrate, and has strength against wafer deformation.

[0050] (3C-SiC single crystal film)

[0051] The thickness of the 3C-SiC single crystal film 11 is preferably set to be 50 nm or more and 200 nm or less. x Ga 1-x When the N (0<x≤1) layer is grown, the melting back of Al and Ga can be fully prevented. In addition, as long as it is less than 200nm, the subsequent GaN or Al x Ga 1-x When the N (0 < x ≤ 1) layer is grown, dislocations can be introduced over the entire surface of the wafer. In addition, there is no tendency for cracks to occur due to the extension of dislocations generated by the growth of 3C-SiC. The thickness is preferably about 100 nm.

[0052] (Nitride semiconductor layer 31)

[0053] The nitride semiconductor layer 31 includes an intermediate layer 12 and a device layer 21 .

[0054] The device layer 21 has GaN or Al x Ga 1-x N (0<x≤1) layer 13 and electron supply layer 14 .

[0055] The structure of the nitride semiconductor layer 31 is merely an example and the present invention is not limited to this structure.

[0056] As the nitride semiconductor constituting the nitride semiconductor layer 31 , for example, GaN, AlN, InN, AlGaN, InGaN, AlInN, AlScN or the like can be used.

[0057] The nitride semiconductor layer 31 is preferably made of Al x In y Ga 1-x-y N (0≤x+y≤1) is the main component. For example, the following components can be the main components: GaN when x=0, y=0; AlN when x=1, y=0; InN when x=0, y=1; AlN when x=0.5, y=0.5 0.5 In 0.5 N.

[0058] The thickness of the nitride semiconductor layer 31 is 0.1 to 10 μm, and can be designed in accordance with the device.

[0059] (Middle layer 12)

[0060] The intermediate layer 12 functions as a buffer layer and is inserted to improve the crystallinity of the device layer 21 and control stress.

[0061] The intermediate layer 12 is made of a nitride semiconductor, so that the intermediate layer 12 can be made using the same equipment as the device layer 21 .

[0062] (Device layer 21)

[0063] In order to improve device characteristics, the device layer 21 is preferably a crystal with few crystal defects and few impurities such as carbon and oxygen.

[0064] High electron mobility transistor (HEMT) structure is based on GaN or Al x Ga 1-x The N (0<x≤1) layer 13 and the electron supply layer 14 constitute the device layer 21. The electron supply layer 14 is formed on GaN or Al x Ga 1-x The N (0<x≤1) layer 13 is composed of AlGaN.

[0065] (GaN or Al x Ga 1-x N (0<x≤1) layer 13)

[0066] GaN or Al x Ga 1-x The N (0<x≤1) layer 13 is a nitride semiconductor, so GaN or Al can be produced using the same equipment as the electron supply layer 14 and the intermediate layer 12. x Ga 1-x N (0<x≤1) layers 13 .

[0067] (Electron Supply Layer 14)

[0068] The electron supply layer 14 is also a nitride semiconductor, so it can be used in conjunction with GaN or Al x Ga 1-x The electron supply layer 14 is fabricated using the same equipment as the N (0<x≤1) layer 13 and the intermediate layer 12 .

[0069] The single crystal silicon substrate 1 with a nitride semiconductor layer having the above structure has dislocations formed throughout the single crystal silicon substrate 10, and the length (dislocation length) when the dislocation plane is projected onto the single crystal silicon substrate 10 is 1 mm or more, and the dislocation density is 10 / cm 2 above.

[0070] 10 / cm 2 By forming dislocations at a high density such that dislocations having a length of 1 mm or more are formed on the entire surface of the Si substrate at the above density, it is possible to reduce the warpage of the wafer caused by the difference in linear expansion coefficient between GaN and Si.

[0071] GaN devices form and utilize a two-dimensional electron gas layer to produce a large saturation drift velocity and electron mobility, so they are horizontal devices with a planar structure of heterojunction field effect transistors (HFET) that can allow a large current density to flow. Therefore, as described in non-patent document 1, even if there are a large number of dislocations on the Si substrate, there will be no problem as long as there are no dislocations in the GaN layer.

[0072] Thus, it is possible to provide a single crystal silicon substrate with a nitride semiconductor layer having a large diameter of 200 mm or 300 mm, which uses a Si substrate of normal thickness, reduces warping, and particularly does not cause cracks.

[0073] In addition, the upper limit of the dislocation length is not particularly limited, and is, for example, 40 mm or less. In addition, the upper limit of the dislocation density is not particularly limited, and is, for example, 50 / cm 2 the following.

[0074] (Method for Manufacturing Single Crystal Silicon Substrate with Nitride Semiconductor Layer)

[0075] Figure 2 The present invention is a schematic flow chart showing an example of a method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer.

[0076] like Figure 2As shown, the method for manufacturing a single crystal silicon substrate 1 with a nitride semiconductor layer according to an embodiment of the present invention includes a step of epitaxially growing a 3C-SiC single crystal film 11 on a single crystal silicon substrate 10 (hereinafter referred to as the first step) and a step of epitaxially growing a nitride semiconductor layer 31 on the 3C-SiC single crystal film 11 (hereinafter referred to as the second step).

[0077] (First process)

[0078] (Preparation of single crystal silicon substrate)

[0079] First, a single crystal silicon substrate 10 is prepared.

[0080] For example, a silicon substrate having a thickness of 775 μm and a plane orientation of <111> is prepared.

[0081] (Oxide film removal)

[0082] A single crystal silicon substrate 10 is placed in a reduced pressure (RP)-CVD apparatus, and a natural oxide film on the surface is removed by hydrogen baking (H2 annealing).

[0083] If the oxide film remains, it becomes impossible to form SiC nuclei on the single crystal silicon substrate 10 .

[0084] For the H2 annealing at this time, it is preferred to set the temperature to a condition of 1000°C or more and 1200°C or less. If the temperature is lower than 1000°C, the processing time needs to be long in order to prevent the residual natural oxide film. In addition, if the temperature is higher than 1200°C, there is a concern that slippage starting from the wafer support of the RP-CVD device may occur, which is not preferred. The pressure and time of the H2 annealing at this time are not particularly specified as long as the natural oxide film can be removed.

[0085] (SiC nucleus formation and 3C-SiC single crystal film formation)

[0086] Figure 3 This is an example of the cross-sectional structure when a 3C-SiC single crystal film is grown.

[0087] While introducing a carbonizing gas such as propane gas as a raw material gas, the temperature is slowly raised from a temperature in the range of 300° C. to 950° C. to a temperature in the range of 1000° C. to less than 1200° C. Thus, SiC nuclei are formed on the surface of the single crystal silicon substrate 10 and a 3C-SiC single crystal film 11 is formed thereafter.

[0088] The heating rate during growth is set in the range of 0.5 to 5°C / min, preferably about 1°C / min.

[0089] Next, as a step of forming a 3C-SiC single crystal film, the single crystal silicon substrate is heated to a temperature of 800° C. or higher and lower than 1200° C., and monomethylsilane or trimethylsilane is introduced as a raw material gas of SiC. Thus, a 3C-SiC single crystal film 11 is formed.

[0090] At this time, after the temperature is raised to a predetermined temperature, the growth may be stopped at this point, or the growth may be continued until a predetermined film thickness is reached. Alternatively, the growth may be stopped at this point after the predetermined film thickness is reached during the temperature rise process. By growing while changing the temperature, the growth mode can be continuously changed while growing, thereby slowly increasing the speed.

[0091] The thickness of the 3C-SiC single crystal film 11 is set to be 50 nm or more and 200 nm or less. By setting the thickness to be 50 nm or more, it is possible to sufficiently prevent the subsequent GaN or Al x Ga 1-x The Al and Ga melt back during the growth of the N (0<x≤1) layer. In addition, by setting the thickness to 200nm or less, the subsequent GaN or Al x Ga 1-x When the N (0 < x ≤ 1) layer is grown, dislocations are introduced into the entire surface of the wafer. In addition, there is no tendency for cracks to occur due to the extension of dislocations generated by the growth of 3C-SiC. It is preferably set to about 100 nm.

[0092] (Second process)

[0093] The second step is a step of forming the nitride semiconductor layer 31 on the 3C-SiC single crystal film 11 by vapor phase growth.

[0094] In the first step, the thickness of the 3C-SiC single crystal film 11 is set to be less than 200 nm, and by implementing the second step, dislocations are formed on the entire single crystal silicon substrate 10, and the length (dislocation length) when the dislocation plane is projected on the single crystal silicon substrate 10 is made to be more than 1 mm, and the dislocation density is made to be 10 / cm 2 above.

[0095] A method for growing the nitride semiconductor layer 31 suitable for practicing the present invention is described below.

[0096] [1] Process of introducing into the reactor

[0097] The single crystal silicon substrate 10 on which the 3C-SiC single crystal film 11 is grown is cleaned with chemicals and then introduced into a reaction furnace of a MOVPE device.

[0098] Next, the furnace is filled with a high-purity inert gas such as nitrogen, and the interior of the furnace is replaced with the high-purity inert gas.

[0099] [2] Process of cleaning the substrate surface in the furnace

[0100] The single crystal silicon substrate 10 on which the 3C-SiC single crystal film 11 is grown is heated in a furnace, and the surface of the substrate is cleaned.

[0101] Cleaning was carried out after the pressure in the furnace was reduced to 50 mbar.

[0102] The furnace pressure can be set between 200 mbar and 30 mbar.

[0103] Cleaning was performed for 10 minutes while hydrogen or nitrogen was supplied into the furnace.

[0104] The cleaning temperature can be set between 1000° C. and 1200° C., based on the temperature of the substrate surface. In particular, a clean surface can be obtained by cleaning at 1050° C.

[0105] [3] Step of growing the intermediate layer 12

[0106] In this process, the gases serving as the raw materials and the source of Al, Ga, and N are introduced under a predetermined furnace pressure and substrate temperature, thereby forming a substrate composed of AlN or Al x Ga 1-x The intermediate layer 12 composed of N (0≤x<1) is epitaxially grown on the substrate.

[0107] In this step, growth can be performed under the conditions of, for example, a furnace pressure of 50 mbar and a substrate temperature of 1120°C.

[0108] As an Al source, trimethylaluminum (TMAl) is used, as a Ga source, trimethylgallium (TMGa) is used, and as an N source, ammonia (NH3) is used. In addition, in order to obtain a mixed crystal of a desired Al composition, the flow rates of the raw materials TMAl and TMGa are set in such a way that the Al / Ga ratio captured in the thin film becomes a set ratio, taking into account the material efficiency of the raw material gas.

[0109] In this process, AlN is grown under the conditions that the flow rate of TMAl is 0.24 L / min (240 sccm) in a standard state and the flow rate of NH3 is 2 L / min (2000 sccm). Hydrogen can be used as a carrier gas for TMAl, TMGa, and NH3, for example. The above conditions are just an example and are not particularly limited.

[0110] The device layer 21 composed of a thin film of a nitride semiconductor is formed on the intermediate layer 12 by vapor phase growth such as MOVPE or sputtering. The device layer 21 is formed at 900 to 1350° C. by MOVPE, for example.

[0111] [4] Make GaN or Alx Ga 1-x Step of growing the N (0<x≤1) layer 13

[0112] In this process, a gas serving as a raw material and a source of Ga or N is introduced under a predetermined furnace pressure and substrate temperature, thereby forming GaN or Al x Ga 1-x The N (0<x≤1) layer 13 is epitaxially grown on the intermediate layer 12 .

[0113] In this step, growth can be performed under the conditions of, for example, a furnace pressure of 200 mbar and a substrate temperature of 1120°C.

[0114] As a Ga source, trimethylgallium (TMGa) is used, and as a N source, ammonia (NH3) is used. In addition, in order to obtain a mixed crystal of a desired Al composition, the flow rates of TMAl and TMGa of the raw materials are set in such a way that the Al / Ga ratio captured in the thin film becomes a set ratio, taking into account the material efficiency of the raw material gas. For example, hydrogen can be used as a carrier gas for TMAl, TMGa, and NH3. The above conditions are an example and are not particularly limited.

[0115] [5] Step of growing the electron supply layer 14

[0116] In this process, the electron supply layer 14 is formed by introducing a gas which is a source of Al, Ga, or N as a raw material under a predetermined furnace pressure and substrate temperature, thereby forming a GaN or Al x Ga 1-x Epitaxial growth is performed on the N (0<x≤1) layer 13.

[0117] In this step, growth can be performed under the conditions of, for example, a furnace pressure of 150 mbar and a substrate temperature of 1120°C.

[0118] As an Al source, trimethylaluminum (TMAl) is used, as a Ga source, trimethylgallium (TMGa) is used, and as an N source, ammonia (NH3) is used. In addition, in order to obtain a mixed crystal of a desired Al composition, the flow rates of TMAl and TMGa of the raw materials are set in such a way that the Al / Ga ratio captured in the thin film becomes a set ratio, taking into account the material efficiency of the raw material gas. For example, hydrogen can be used as a carrier gas for TMAl, TMGa, and NH3. The above conditions are an example and are not particularly limited.

[0119] Through the above steps, dislocations can be generated throughout the single crystal silicon substrate 10 without cracking. In addition, the length of the dislocation plane when projected onto the single crystal silicon substrate 10 (dislocation length) can be made greater than 1 mm, and the density of the dislocations can be made 10 / cm 2 above.

[0120] After the step of forming a 3C-SiC single crystal film to a thickness of 200 nm or less, AlN and GaN are grown, it is possible to grow the 3C-SiC single crystal film at a thickness of 10 / cm 2 Dislocations having a length of 1 mm or more are formed at the above density. By forming dislocations at such a high density, the warpage of the wafer caused by the difference in linear expansion coefficient between GaN and Si can be reduced.

[0121] Example

[0122] Hereinafter, the present invention will be specifically described with reference to Examples, but the present invention is not limited to these Examples.

[0123] (Example 1)

[0124] First, a (111) boron-doped normal-resistance single-crystal silicon substrate (resistivity: 10Ω·cm, thickness: 775 μm) with a diameter of 300 mm was prepared.

[0125] Next, the wafer was placed on a susceptor in a reactor of the RP-CVD device and subjected to H2 annealing at 1080°C for 1 minute.

[0126] Next, the temperature in the furnace was cooled to 300°C, and then the temperature was raised to 1130°C at a heating rate of 1°C / second while trimethylsilane gas was introduced to perform the SiC nucleus formation process and the subsequent 3C-SiC single crystal film formation. The growth pressure at this time was set to 100 Torr. After reaching 1130°C, it was maintained for 10 minutes to form a 3C-SiC single crystal film (film thickness: 100nm).

[0127] Next, the substrate on which the 3C-SiC single crystal film has been grown is introduced into a reactor of an MOCVD device and replaced with nitrogen to remove oxygen and moisture in the atmosphere.

[0128] Next, the pressure in the furnace was reduced to 50 mbar, the temperature was raised to 1050° C., and then the furnace was kept in a hydrogen atmosphere for 10 minutes to clean the surface layer.

[0129] Next, in order to form an intermediate layer as a buffer layer, the pressure in the furnace was maintained at 50 mbar and the substrate temperature was maintained at 1020°C. Trimethylaluminum as an Al source, trimethylgallium as a Ga source, and ammonia as a nitrogen source were introduced into the furnace to form an AlN film of 180 nm and an AlGaN film of 580 nm.

[0130] Next, in order to grow a gallium nitride layer, the pressure in the furnace was maintained at 200 mbar and the substrate temperature was maintained at 1120° C., trimethylgallium and ammonia were introduced into the furnace, and a GaN film was formed to a thickness of 900 nm.

[0131] Next, AlGaN was grown as a charge supply layer. Specifically, AlGaN was grown under the conditions of a furnace pressure of 200 mbar and a substrate temperature of 1120°C. 0.25 Ga 0.75 N grows 25nm.

[0132] Through the above operations, a single crystal silicon substrate (775 μm) / 3C-Si single crystal film (100 nm) / AlN (180 nm) / AlGaN (580 nm) / GaN (900 nm) / Al 0.25 Ga 0.75 The substrate of Example 1 is composed of N (25nm).

[0133] Figure 4 This is the XRT measurement result of the substrate in Example 1.

[0134] Depend on Figure 4 It can be seen that the dislocation is formed in the entire single crystal silicon substrate, the length of the dislocation plane when projected onto the single crystal silicon substrate (dislocation length) is more than 1 mm, and the density of the dislocation is 10 / cm 2 above.

[0135] (Comparative Example 1)

[0136] A substrate of Comparative Example 1 was produced in the same manner as in Example 1 except that the thickness of the single crystal silicon substrate was set to 1.5 mm and GaN was grown instead of 3C-SiC.

[0137] That is, a single crystal silicon substrate (1.5 mm) / AlN (180 nm) / AlGaN (580 nm) / GaN (900 nm) / Al 0.25 Ga 0.75 The substrate of Comparative Example 1 is composed of N (25 nm).

[0138] Figure 5 It is the XRT measurement result of the substrate of Comparative Example 1.

[0139] Depend on Figure 5 It was found that the wafer was cracked and specific dislocations occurred in the portion of the single crystal silicon substrate in contact with the device base portion.

[0140] (Comparative Example 2)

[0141] A substrate for Comparative Example 2 was produced in the same manner as in Example 1 except that the thickness of the single crystal silicon substrate was set to 1.5 mm, 3C-SiC was grown to 300 nm, and then GaN was grown.

[0142] That is, a single crystal silicon substrate (1.5 mm) / 3C-SiC single crystal film (300 nm) / AlN (180 nm) / AlGaN (580 nm) / GaN (900 nm) / Al 0.25 Ga 0.75 The substrate of Comparative Example 2 is composed of N (25nm).

[0143] Figure 6 It is the XRT measurement result of the substrate of Comparative Example 2.

[0144] Depend on Figure 6 It was found that the wafer was cracked and specific dislocations occurred in the portion of the single crystal silicon substrate in contact with the device base portion.

[0145] (Comparative Example 3)

[0146] A substrate of Comparative Example 3 was produced in the same manner as in Example 1 except that GaN was grown instead of 3C-SiC.

[0147] That is, a single crystal silicon substrate (775 μm) / AlN (180 nm) / AlGaN (580 nm) / GaN (900 nm) / Al 0.25 Ga 0.75 The substrate of Comparative Example 3 is composed of N (25nm).

[0148] Wafers have cracked during the GaN process.

[0149] As described above, according to the embodiments of the present invention, a large-diameter single-crystal silicon substrate with a nitride semiconductor layer can be manufactured using a Si substrate of a normal thickness with reduced warpage and, in particular, without cracks.

[0150] In addition, the present invention is not limited to the above-mentioned embodiments. The above-mentioned embodiments are only examples, and technical solutions having substantially the same structure and exerting the same technical effects as the technical concept described in the claims of the present invention are all included in the protection scope of the present invention.

Claims

1. A single crystal silicon substrate with a nitride semiconductor layer, comprising a single crystal silicon substrate, a 3C-SiC single crystal film epitaxially grown on the single crystal silicon substrate, and a nitride semiconductor layer epitaxially grown on the 3C-SiC single crystal film, wherein the single crystal silicon substrate with a nitride semiconductor layer is characterized in that: Dislocations are formed on the entire single crystal silicon substrate, the length of the dislocation plane when projected onto the single crystal silicon substrate (dislocation length) is greater than 1 mm, and the density of the dislocations is 10 / cm 2 above.

2. The single crystal silicon substrate with a nitride semiconductor layer according to claim 1, wherein: The thickness of the 3C-SiC single crystal film is greater than or equal to 50 nm and less than or equal to 200 nm.

3. The single crystal silicon substrate with a nitride semiconductor layer according to claim 1 or 2, characterized in that The nitride semiconductor layer is Al x In y Ga 1-x-y N is the principal component, where 0≤x+y≤1.

4. A method for manufacturing a single crystal silicon substrate with a nitride semiconductor layer, characterized in that: The invention has a process of epitaxially growing a 3C-SiC single crystal film on a single crystal silicon substrate and a process of epitaxially growing a nitride semiconductor layer on the 3C-SiC single crystal film. By the process of epitaxially growing the 3C-SiC single crystal film on the single crystal silicon substrate, the thickness of the 3C-SiC single crystal film is made to be less than 200nm. By implementing the process of epitaxially growing the nitride semiconductor layer on the 3C-SiC single crystal film, dislocations are formed in the entire single crystal silicon substrate, and the length (dislocation length) of the dislocation plane when projected onto the single crystal silicon substrate is made to be more than 1mm, and the density of the dislocations is made to be 10 / cm 2 above.

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