Relaxation oscillator with offset resistor

Abstract

According to an aspect, there is provided a relaxation oscillator (100) comprising a first current source (101, 11) and a second current source (102, 12) and a comparator (103) having an output, a first input (103-) connected to the first current source and a second input (103 +) connected to the second current source. One of the first input and the second input is an inverted input, and the other of the first input and the second input is a non-inverted input. The relaxation oscillator also includes a resistance circuit (110) connected between the first input of the comparator and ground. The resistive circuit comprises at least a first resistor (R) and a capacitor charging circuit (111) connected between the second input of the comparator and ground. The capacitor charging circuit includes a capacitor (105, C), a second resistor (107, R0) connected in series with the capacitor, and a switch (106) connected in parallel with the capacitor. The switch is configured to be controlled based on an output of the comparator.

Description

Technical Field

[0001] Various example embodiments relate to relaxation oscillators. Background Art

[0002] A relaxation oscillator is a nonlinear electronic oscillator circuit for generating a non-sinusoidal (e.g., square wave) periodic output signal. The operation of a relaxation oscillator is based on the periodic charging and discharging of a capacitor. For most relaxation oscillator applications, it is desirable to have a zero or at least low temperature coefficient, which means that the output of the relaxation oscillator does not depend on temperature or is only slightly dependent on temperature. Although the capacitors of a relaxation oscillator typically have a negligible (i.e., close to zero) temperature coefficient, the temperature coefficient of the sheet resistor of the relaxation oscillator typically has a considerable positive value. To overcome this problem, a mixture of resistors with positive and negative temperature coefficients can be used in a relaxation oscillator to obtain a clock with a flat temperature coefficient. However, a typical complementary metal oxide semiconductor (CMOS) manufacturing process does not provide resistors with negative temperature coefficients. Even if such resistors are provided in a CMOS manufacturing process, including such resistors is expensive and makes the manufacturing process quite complicated due to the need to apply additional masks during the manufacturing process. Summary of the invention

[0003] According to a first aspect, there is provided a relaxation oscillator, comprising:

[0004] a first current source and a second current source;

[0005] a comparator having an output, a first input connected to a first current source, and a second input connected to a second current source, wherein one of the first input and the second input is an inverting input and the other of the first input and the second input is a non-inverting input;

[0006] a resistor circuit connected between the first input of the comparator and ground, wherein the resistor circuit comprises at least a first resistor; and

[0007] A capacitor charging circuit is connected between the second input of the comparator and ground, wherein the capacitor charging circuit includes a capacitor, a second resistor connected in series with the capacitor, and a switch connected in parallel with the capacitor, the switch being configured to be controlled based on an output of the comparator.

[0008] According to a second aspect, there is provided a differential relaxation oscillator, comprising:

[0009] a first current source, a second current source, and a third current source;

[0010] a first comparator having an output, a first input connected to the first current source, and a second input connected to the third current source, wherein one of the first input and the second input of the first comparator is an inverting input and the other of the first input and the second input of the first comparator is a non-inverting input;

[0011] a second comparator having an output, a first input connected to the first current source, and a second input connected to the second current source, wherein one of the first input and the second input of the second comparator is an inverting input and the other of the first input and the second input of the second comparator is a non-inverting input, and the first input of the second comparator is of the same type as the first input of the first comparator;

[0012] a resistance circuit connected between the first input of the first comparator and ground, wherein the resistance circuit comprises at least a first resistor;

[0013] a first capacitor charging circuit connected between the second input of the first comparator and ground, wherein the first capacitor charging circuit comprises a first capacitor, a second resistor connected in series with the first capacitor, and a first switch connected in parallel with the first capacitor;

[0014] a second capacitor charging circuit connected between the second input of the second comparator and ground, wherein the second capacitor charging circuit comprises a second capacitor, a third resistor connected in series with the second capacitor, and a second switch connected in parallel with the second capacitor;

[0015] a third switch connected between the second current source and the first capacitor charging circuit;

[0016] a fourth switch connected between the third current source and the second capacitor charging circuit; and

[0017] A reset circuit is configured to control the first switch, the second switch, the third switch and the fourth switch based on the output of the first comparator and the output of the second comparator to achieve alternating charging of the first capacitor and the second capacitor and periodic resetting of the charges of the first capacitor and the second capacitor.

[0018] The first aspect and the second aspect provide the following technical effects: a relaxation oscillator or a differential relaxation oscillator for generating a non-sinusoidal periodic output signal is implemented.

[0019] The first and second aspects provide the following advantages. Due to the inclusion of at least one offset resistor (i.e., the second resistor for a single-ended relaxation oscillator or the second and third resistors for a differential relaxation oscillator), the temperature dependency of the realized relaxation oscillator or differential relaxation oscillator is minimized in a simple but effective manner with a minimum number of required electronic components. Notably, no special resistor type (i.e., a resistor type that enables a negative temperature coefficient) needs to be employed to flatten the temperature gradient of the relaxation oscillator or differential relaxation oscillator.

[0020] Embodiments are defined in the dependent claims. The scope of protection sought for the various embodiments is set out in the independent claims.

[0021] The embodiments and features described in this specification that do not fall within the scope of the independent claims, if any, should be interpreted as examples useful for understanding various embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which:

[0023] Figure 1 shows a relaxation oscillator according to an embodiment;

[0024] Figure 2A and Figure 2B Implementation of a falling edge delay circuit according to an embodiment and exemplary input signals and output signals of the falling edge delay circuit are respectively shown;

[0025] Figure 3A and Figure 3B illustrates an exemplary operation of a relaxation oscillator according to an embodiment;

[0026] Figure 4 shows a differential relaxation oscillator according to an embodiment;

[0027] Figure 5 shows a process performed by a reset circuit of a differential relaxation oscillator according to an embodiment; and

[0028] Figure 6 An exemplary operation of a differential relaxation oscillator according to an embodiment is shown. DETAILED DESCRIPTION

[0029] The following embodiments are presented only as examples. Although the specification may refer to embodiments and / or examples, "one" or "some" embodiments and / or examples in several places in the text, this does not necessarily mean that each reference is to the same embodiment or example, or that a particular feature applies only to a single embodiment and / or example. Individual features of different embodiments and / or examples may also be combined to provide other embodiments and / or examples.

[0030] Figure 1 A relaxation oscillator 100 (or specifically an RC relaxation oscillator) for providing a flat frequency response according to an embodiment is shown. The relaxation oscillator 100 may specifically be an integrated relaxation oscillator (i.e., a relaxation oscillator implemented on at least one integrated circuit). For example, the relaxation oscillator 100 may be a CMOS-based integrated relaxation oscillator.

[0031] The relaxation oscillator 100 includes a first current source 101 and a second current source 102. The first current source 101 may be configured to output a first current I1, and the second current source may be configured to output a second current I2. In some embodiments, the first current and the second current may be (substantially) equal (ie, I1=I2).

[0032] The relaxation oscillator 100 further includes a comparator 103 having an inverting input connected to the first current source 101, a non-inverting input connected to the second current source 102, and an output 109 (corresponding to an output voltage V out ). The output 109 of the comparator 103 may also correspond to the output of the relaxation oscillator 100 .

[0033] The output 109 of the comparator 103 may correspond to a (binary) digital output. Specifically, the output of the comparator 103 may (at least ideally) have the following logical (binary) form:

[0034]

[0035] In practice, a logical "1" may be associated with a first voltage (a high voltage), and a logical "0" may be associated with a second voltage (a low voltage) that is typically less than the first voltage.

[0036] The comparator 103 may be of any conventional type or model. The comparator 103 may be implemented, for example, using a (high gain) differential amplifier (e.g., an operational amplifier or a dedicated comparator chip). The gain of the differential amplifier is preferably high enough so that even a very small difference between the input voltages will saturate the output, and thus the output voltage will correspond to a low logic voltage or a high logic voltage, as described above in connection with (1).

[0037] The relaxation oscillator 100 further includes a resistor (or resistor) circuit 110 connected between the inverting input of the comparator 103 and ground (or equivalently between the output of the first current source 101 and ground). The resistor circuit 110 includes at least (or consists of) a first resistor 104 (or a first resistor element), such as Figure 1 . The first resistor 104 has a first resistance R and a first (positive) temperature coefficient α. The voltage at the node between the first current source 101 and the resistance circuit 110 (or equivalently between the inverting input of the comparator 103 and the resistance circuit 110) is denoted as V R .

[0038] The relaxation oscillator 100 further includes a capacitor charging circuit 111 connected between the non-inverting input of the comparator 103 and ground (or equivalently between the output of the second current source 102 and ground). The capacitor charging circuit 111 includes (or, as Figure 1 As shown, it is composed of the following: a capacitor 105, a second resistor 107 (equivalently referred to as an offset resistor) connected in series with the capacitor 105, and a switch 106 connected in parallel with the capacitor 105. The capacitor 105 has a capacitance C, the second resistor 107 has a second resistance R0 and a second (positive) temperature coefficient α0, and the voltage at the node between the second current source 102 and the capacitor 105 (or equivalently between the non-inverting input of the comparator 103 and the capacitor 105) is represented as V C Capacitor 105 may also be associated with a third temperature coefficient, although typically the third temperature coefficient has a value close to zero (and thus has a negligible effect on the temperature coefficient of relaxation oscillator 100 as a whole).

[0039] Switch 106 may be an active HIGH switch (ie, opened when the input voltage is high). When switch 106 is open, capacitor 105 is being charged. Closing switch 106 enables capacitor 105 to be bypassed, which causes capacitor 105 to discharge. It should be noted that although voltage V R During the operation of the relaxation oscillator 100, the voltage V C It continues to rise due to the charging of the capacitor when the switch is open. Figure 3A and Figure 3B This charge / discharge operation is discussed in further detail.

[0040] In embodiments, the second resistor 107R0 may be specifically used to compensate for the positive or negative temperature coefficient of the first (sheet) resistor R. It should be noted that without the second resistor R0, the temperature coefficient of the relaxation oscillator 100 as a whole would be highly dependent on the temperature coefficient of the first resistor 104 (R). In other words, the second resistor R0 (i.e., the offset resistor) is included in the capacitor charging circuit 111 to offset the temperature coefficient of the first resistor R from the (adjacent) resistor circuit 110, thereby making the temperature gradient of the relaxation oscillator 100 as a whole flat.

[0041] The first resistor 104 and / or the second resistor 107 may be, for example, a resistor of any of the following types (or a combination of one or more types): diffusion, well, squeezed well polysilicon, and metal. In general, the first resistor 104 and / or the second resistor 107 may correspond to any element that provides resistance.

[0042] In an embodiment, the first resistor (R) 104 is a polysilicon resistor and / or the second resistor (R0) 107 is a diffused resistor.

[0043] In some implementations, the resistance R of the first resistor 104 can be greater than the resistance R0 of the second resistor 107 , or even greater than the resistance R0 of the second resistor 107 multiplied by 2, 3, 4, 5, 6, 7, or 8.

[0044] The capacitor 105 may correspond to any element that provides capacitance.

[0045] Exemplary values ​​of the capacitance C of the capacitor 105 and the resistances R & R0 of the first and second resistors 104 and 107 may be, for example, C=2.2 pF, R=6 MΩ, and R0=0.7 MΩ.

[0046] The relaxation oscillator 100 also includes a clock divider 108. The clock divider 108 is connected to the output of the comparator 103 and provides an output clock (voltage) signal V out 109. The clock divider 108 is configured to ensure that the output clock duty cycle is substantially 50%. In other words, the clock divider 108 is configured to output an output clock signal V having a high value at approximately 50% of the time and a low value at approximately 50% of the time. out 109.

[0047] In some implementations, clock divider 108 may be configured to Figure 1 The relaxation oscillator 100 is omitted. For example, it may be provided as a separate element relative to the relaxation oscillator 100.

[0048] If the response delay of the comparator 103 is very small, the switch 106 may be closed for too short a time to ensure the complete discharge of the capacitor C 105. To avoid this, the relaxation oscillator 100 includes a falling edge delay circuit 113. The falling edge delay circuit 113 is connected between the output of the comparator 103 and the switch 106 to be able to switch the switch 106 in a delayed manner based on the output of the comparator 103. That is, the falling edge delay circuit 113 is configured to ensure that the capacitor 105 is completely discharged after the closure of the switch 106. In other words, the falling edge delay circuit 113 ensures that the input of the switch 106 remains high (i.e., "1") a little longer than the output of the comparator 103 and V C Fully discharged to V R0 The falling edge delay circuit 113 is discussed in more detail below.

[0049] The switching operation of the relaxation oscillator 100 may work as follows.

[0050] When the output of comparator 103 indicates the voltage V C Failure to exceed the inverting input voltage V R In response to the output of comparator 103 corresponding to a logic 1 (indicating that the voltage V at the non-inverting input is C exceeds the voltage at the inverting input V R ), switch 106 is closed, causing the capacitor 105 to discharge. This results in a voltage V C Reset to V R0 When the output of comparator 103 again indicates the voltage V C Failure to exceed the inverting input voltage V R When the switch 106 returns to the open position, this causes the capacitor 105 to be charged again. Due to the falling edge delay circuit 113, the opening of the switch 106 is delayed in this case, as shown in FIG. Figure 2A and Figure 2B Described in detail.

[0051] In some embodiments, the Figure 1 The falling edge delay circuit 113 of the comparator 103 can be connected directly to the switch 106. This can be done in particular if the propagation delay caused by the comparator 103 itself is greater than the duration associated with the discharge process or cycle of the capacitor 105, or if the inability to fully discharge the capacitor 105 can be tolerated.

[0052] In some alternative embodiments, the order of the inverting input and the non-inverting input of the comparator 103 may be reversed. Thus, the comparator 103 may have a first input connected to the first current source 101, a second input connected to the second current source 102, wherein one of the first input and the second input is an inverting input and the other is a non-inverting input. The resistor circuit 110 may be connected between the first input of the comparator and ground, and the capacitor charging circuit 111 may be connected between the second input of the comparator 103 and ground. If the order of the inverting input and the non-inverting input of the comparator 103 is reversed (with Figure 1 ), the output of comparator 103 may be inverted, or alternatively switch 106 may be configured as an active low switch (ie, closed when the input voltage is low).

[0053] Figure 2A An implementation of the falling edge delay circuit 210 according to an embodiment is shown. Figure 2A The falling edge delay circuit 210 may correspond to Figure 1 Falling edge delay circuit 113.

[0054] Reference Figure 2A , the falling edge delay circuit 210 has an input 211 and an output 214. The falling edge delay circuit includes a delay element 212 connected to the input 211 and an OR gate 213 having a first input connected to the delay element 212 and a second input connected to the input 211 of the falling edge delay circuit 210 and an output connected to the output 214 of the falling edge delay circuit 210.

[0055] The falling edge delay circuit 210 operates as follows. When the input 211 is equal to 0 (and has been equal to 0 for some time), the delayed signal has the same value of 0, and therefore the output 214 of the falling edge delay circuit 210 is also equal to 0. When the value of the input 211 of the falling edge delay circuit 210 switches from 0 to 1, the output of the OR gate 213 (and therefore the output 214 of the falling edge delay circuit 210) also switches from 0 to 1, while the output 214 of the delay element 212 remains at 0 for a predefined amount of time until it also eventually switches from 0 to 1. When the value of the input 211 of the falling edge delay circuit 210 switches to 0, the output 214 of the falling edge delay circuit 210 remains at 1 for a predefined length of time defined by the delay element 212 that is equivalent to the falling edge delay between the input 211 and the output 214.

[0056] Figure 2B Shows Figure 2A 1 and 2. Exemplary input signals and output signals of the falling edge delay circuit 210 of FIG. Specifically, the input signal 211 is shown on the upper half of the figure, and the output signal 214 is shown on the lower half of the figure. Figure 2B The delay operation described in the previous paragraph is clearly shown, ie the falling edge of the output signal 214 is delayed by a predefined time length relative to the falling edge of the input signal 211 to ensure a (more) complete discharge of the capacitor of the relaxation oscillator.

[0057] In combination Figure 1 (as well as Figure 2A and / or Figure 2B ) In some embodiments of the relaxation oscillator described in FIG. 1 , the first resistor R and the second resistor R0 and the first temperature coefficient α and the second temperature coefficient α0 can be selected to achieve a substantially flat temperature response of the relaxation oscillator 100 as a whole. In order to keep the temperature gradient of the relaxation oscillator 100 at zero, the following voltage (V R ) changes with temperature and the voltage across R0 (V R0 ) with temperature must hold:

[0058]

[0059] By multiplying each side of (2) by dT and based on Figure 1 Applying Ohm's law, the equation can be written as

[0060] d(I·R)=d(I·R0). (3)

[0061] It should be noted that it is assumed here that the first current source and the second current source provide equal currents (I1=I2=I). By applying the differential to the resistance term (assuming the current I to be constant) and using the basic definition of the temperature coefficient (dR / R=α·dT), equation (3) can be written as

[0062] I(R(1+α·dT))=I(R0(1+α0·dT)). (4)

[0063] Finally, equation (4) can be rearranged to give the ratio of the first resistor R and the second resistor R0 as:

[0064]

[0065] Therefore, the first resistor R and the second resistor R0 and the associated first temperature coefficient α and second temperature coefficient α0 can be selected to at least approximately satisfy equation (5). In practice, the design process of the circuit elements of the relaxation oscillator can be performed, for example, as follows. First, the values ​​of R, C, I1 and I2 can be selected to achieve the desired nominal power consumption and the desired nominal frequency of the relaxation oscillator. Then, the value of R and its temperature coefficient α can be selected based on (5). In order to ensure that the capacitor voltage V CIn order to have as large a margin as possible for charging and discharging, the resistor R0 with the highest available temperature coefficient α0 can be selected from the available devices of the CMOS process. As shown in (5), the higher the value of the temperature coefficient α0, the lower the required absolute value of the sheet resistance R0, and thus the maximum margin of the capacitor C is achieved.

[0066] Figure 3A and Figure 3B Shows Figure 1 Exemplary operation of the relaxation oscillator. That is, Figure 3A The voltage V is plotted C (top sub-figure) and V R (bottom subplot) versus time, and Figure 3B The voltage V is plotted R (top sub-figure) and V R0 (Bottom sub-graph) Curves relative to temperature. Figure 1 As shown in and discussed above, the voltage V C is the voltage at the node between the second current source and the capacitor (or equivalently between the non-inverting input of the comparator and the capacitor), the voltage V R is the voltage at the node between the first current source and the first resistor (or equivalently between the inverting input of the comparator and the first resistor), and the voltage V R0 is the voltage across the (offset) resistor R0. Figure 3A and Figure 3B The horizontal axes of the subplots are aligned with each other.

[0067] Reference Figure 3A , initially assuming that the switch has just opened. Therefore, V C is initially at zero, but the relaxation oscillator capacitor is charging, and therefore V C On the other hand, V R remains constant during operation of the relaxation oscillator (independent of the position of the switch). Figure 3A The vertical dashed line in indicates the time when the switch is closed. This causes the capacitor to discharge, and therefore V C drops to zero (while V R When the voltage V C The value exceeds V R When , the output of comparator 103 changes from a low "0" state to a high "1" state. This results in Figure 1 106 in the circuit, and the capacitor C 105 is discharged. Immediately after the closing of the switch, the switch is opened again, and the capacitor is thus charged again (e.g., by a rising V CThe length of time that switch 106 remains closed depends on the propagation delay of comparator 103, the discharge rate of capacitor C 105, and the additional delay caused by falling edge delay circuit 113. C The voltage level is determined by V C =C R =RI is given. In other words, when V C >V R When the comparator output has the indication V C >V R To ensure that capacitor C 105 is fully discharged when the switch is closed, falling edge delay circuit 113 keeps switch 106 closed longer than if input 112 were directly connected to switch 106. Note that capacitor C 105 is discharged to V R0 potential, which is the product of the second current source and R0, that is, V R0 =I2R0.

[0068] Reference Figure 3B , based on V R and V R0 The two subgraphs of V R and V R0 depends on temperature in the same way. Specifically, Figure 3B The slopes of the two curves in the two subgraphs of are equal (i.e., temperature derivatives). In other words, the term dV R / dT is equal to dV R0 / dT, such as Figure 3B This corresponds to the condition (2) discussed above.

[0069] Although a single-ended (ie, non-differential) relaxation oscillator according to an embodiment is specifically described in detail above, in other embodiments, a differential relaxation oscillator having two offset resistors may be provided. Figure 4 A differential relaxation oscillator 400 (or specifically a differential RC relaxation oscillator) for providing a flat frequency response according to an embodiment is shown. The differential relaxation oscillator 400 may specifically be an integrated relaxation oscillator (i.e., a relaxation oscillator implemented on at least one integrated circuit). For example, the differential relaxation oscillator 400 may be a CMOS-based integrated relaxation oscillator.

[0070] The operation of the differential relaxation oscillator 400 is similar in many respects to the operation of the single-ended relaxation oscillator 100. In general, both relaxation oscillators are based on the use of an offset resistor arranged in series with a capacitor. Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B Any of the definitions provided for a single-ended relaxation oscillator in any of the definitions provided in may be applied mutatis mutandis to the differential relaxation oscillator 400 (i.e., taking into account Figure 4 after the differential nature of circuit 400).

[0071] In general, it should be noted that the architecture of the differential relaxation oscillator 400 is very similar to Figure 1 The architecture of the single-ended relaxation oscillator 100 is similar to that of the single-ended relaxation oscillator 100. The obvious difference between the two architectures is that the differential relaxation oscillator 400 includes two differential branches defined by elements 402', 403', 405' to 407', 411', 420' and elements 402, 403, 405 to 407, 411, 420, respectively. Each of the branches is completely similar to the one defined by the third switch 420' and the fourth switch 420. Figure 1 It is worth noting that the components 401, 403, 410 can completely correspond to Figure 1 Elements 101, 103, 110.

[0072] It should be noted that, if Figure 1 The falling edge delay circuit 113 and the clock delay circuit 108 used in the single-ended relaxation oscillator 100 are Figure 4 The operation of the differential relaxation oscillator 400 is not necessary. This is due to the fundamental nature of the differential relaxation oscillator. That is, when Figure 4 Reset circuit 408 operates in a similar manner to falling edge circuit 113 and clock delay circuit 108 as capacitors C and C′ (elements 405 and 405 ′) of differential relaxation oscillator 400 are alternately (as opposed to simultaneously) charged and discharged.

[0073] The differential relaxation oscillator 400 includes a first current source 401, a second current source 402', and a third current source 402. The first current source 401 may be configured to output a first current I1, the second current source may be configured to output a second current I2, and the third current source may be configured to output a third current I3. In some embodiments, the first current, the second current, and the third current may be (substantially) equal (i.e., I1=I2=I3).

[0074] The relaxation oscillator 400 also includes a first comparator 403' having an output, an inverting input connected to the first current source 401, and a non-inverting input connected to the second current source 402'. In addition, the relaxation oscillator 400 includes a second comparator 403 having an output, an inverting input connected to the first current source 401, and a non-inverting input connected to the third current source 402. The outputs of the first comparator 403' and the second comparator 403 may also correspond to the output of the relaxation oscillator 400. The first comparator 403' and the second comparator 403 may be as described above for Figure 1 The comparator 103 is defined as discussed above.

[0075] Similar to Figure 1 The relaxation oscillator 100 of the present invention comprises a resistor (or resistor) circuit 410 connected between the inverting input of the first comparator 403' (or equivalently the second comparator 403) and the ground. The resistor circuit 410 comprises at least (or, as Figure 4 , only the first resistor 404 is included. The first resistor 404 has a first resistance R and a first temperature coefficient α. The first resistor 404 can be as shown in FIG. Figure 1 The first resistor 104 is defined as described above. Figure 1 , the voltage at the node between the first current source 401 and the resistor circuit 410 (or equivalently between the inverting input of the first comparator 403' or the second comparator 403 and the resistor circuit 410) is represented as V R .

[0076] The relaxation oscillator 400 further includes a first capacitor charging circuit 411' connected between the non-inverting input of the first comparator 403' and ground (or equivalently between the output of the second current source 402' and ground). The first capacitor charging circuit 411' includes (or, as Figure 4 As shown in FIG. 1 , the first capacitor 405′ is composed of the following: a first capacitor 405′, a second resistor 407′ (equivalently referred to as a first offset resistor) connected in series with the first capacitor 405′, and a first switch 406′ connected in parallel with the first capacitor 405′. The first capacitor 405′ has a first capacitance C′, the second resistor 407′ has a second resistance R0′ and a second temperature coefficient α0′, and the voltage at the node between the second current source 402′ and the first capacitor 405′ (or equivalently between the non-inverting input of the first comparator 403′ and the first capacitor 405′) is represented as V C1 .

[0077] In addition, the relaxation oscillator 400 also includes a second capacitor charging circuit 411 defined in a similar manner to the first capacitor charging circuit 411'. That is, the second capacitor charging circuit 411 is connected between the non-inverting input of the second comparator 403 and ground (or equivalently between the output of the third current source 402 and ground). The second capacitor charging circuit 411 includes (or, as Figure 4 As shown in FIG. 1 , the circuit 402 is composed of a second capacitor 405, a third resistor 407 (equivalently referred to as a second offset resistor) connected in series with the second capacitor 405, and a second switch 406 connected in parallel with the second capacitor 405. The second capacitor 405 has a second capacitance C, the third resistor 407 has a third resistance R0 and a third temperature coefficient α0, and the voltage at the node between the third current source 402 and the second capacitor 405 (or equivalently between the non-inverting input of the second comparator 403 and the second capacitor 405) is represented as V C2 .

[0078] The first capacitor 405 ′ and the second capacitor 405 may also be associated with fourth and fifth temperature coefficients, although typically the fourth and fifth temperature coefficients have values ​​close to zero (and thus have a negligible effect on the temperature coefficient of the relaxation oscillator 400 as a whole).

[0079] and Figure 1 Compared to the relaxation oscillator 100 , the differential relaxation oscillator 400 further includes a third switch 420 ′ and a fourth switch 420 arranged between the second current source 402 ′ and the first capacitor charging circuit 411 ′ and between the third current source 402 and the second capacitor charging circuit 411 , respectively.

[0080] Finally, the differential relaxation oscillator 400 includes a reset circuit 408 (e.g., a latch), which is configured to control the first switch 406', the second switch 406, the third switch 420', and the fourth switch 420 based on the outputs of the first comparator 403' and the second comparator 403 to achieve alternating charging of the first capacitor 405' and the second capacitor 405 and periodic resetting of the charges of the first capacitor 405' and the second capacitor 405 (while the other of the first capacitor 405' and the second capacitor 405 is being charged), as will be described in conjunction with Figure 5 A and Figure 5B. The reset circuit 408 can be configured to control the first switch 406', the second switch 406, the third switch 420', and the fourth switch 420 so that at any given time, the state (i.e., open / closed state) of the third switch 420' matches the state of the second switch 406, and the state of the fourth switch 420 matches the state of the first switch 406'. Therefore, at any given time, only two of the first switch 406', the second switch 406, the third switch 420', and the fourth switch 420 are closed (or open).

[0081] exist Figure 4 In the embodiment of the present invention, the reset circuit 408 specifically corresponds to an SR (set-reset) latch (or flip-flop). The SR latch 408 has a reset (R) input connected to the output of the first comparator 403 and a set (S) input connected to the output of the second comparator 403'. In addition, the SR latch has a reset (R) input connected to (and controlling) the first switch 406' and the fourth switch 420. The SR latch 408 is connected to (and controls) the Q output (equivalently referred to as the second output or Q2 output) and the Q output (equivalently referred to as the first output or Q1 output) connected to (and controlling) the second switch 406' and the third switch 420'. Both the input and output are logic (binary) inputs, and both outputs are logic (binary) outputs. The first switch 406', the second switch 406, the third switch 420', and the fourth switch 420 can be configured to open when a logic 0 is received and close when a logic 1 is received. The SR latch 408 can have the following truth table:

[0082]

[0083]

[0084] Here, a logic '1' of Q1 may be associated with a first voltage (high voltage), and a logic '0' of Q2 may be associated with a second voltage (low voltage) that is typically less than the first voltage. Similarly, a logic '1' of Q2 may be associated with a third voltage (high voltage), and a logic '0' of Q2 may be associated with a fourth voltage (low voltage) that is typically less than the third voltage. The first voltage and the third voltage may be equal, or may not be equal. The second voltage and the fourth voltage may be equal, or may not be equal.

[0085] It should be noted that under normal operating conditions of the differential relaxation oscillator 400 (ie, unless there is a fault in the operation of the differential relaxation oscillator 400 ), the situation R=S=0 & R=1=1 is not possible.

[0086] In some embodiments, the second resistor R0′ may be equal to the third resistor R0. Additionally or alternatively, the first capacitor C′ may be equal to the second capacitor C.

[0087] In some embodiments, the first temperature coefficient α, the second temperature coefficient α0′, and the third temperature coefficient α0 are either all positive or all negative.

[0088] exist Figure 4 (and Figure 5 In some embodiments of the differential relaxation oscillator of FIG. 100 , the first resistor R, the second resistor R0′, and the third resistor R0 and the first temperature coefficient α, the second temperature coefficient α0′, and the third temperature coefficient α0 may be selected to achieve a substantially flat temperature response of the differential relaxation oscillator 100 as a whole. Figure 1 The formulas (2) to (5) written with R and R0 are modified as necessary and are applicable to Figure 4 R and R0 as well as Figure 4 Both R and R0'.

[0089] Similar to Figure 1 As described above with respect to the single-ended relaxation oscillator 100 of FIG. 1 , the order of the inverting input and the non-inverting input of the first comparator 403 and the second comparator 403 ′ may be reversed. Therefore, the first comparator 403 may have a first input connected to the first current source 401 and a second input connected to the third current source 402, wherein one of the first input and the second input of the first comparator 403 is an inverting input, and the other of the first input and the second input of the first comparator 403 is a non-inverting input. In addition, the second comparator 403 ′ may have a first input connected to the first current source 401 and a second input connected to the second current source 402 ′, wherein one of the first input and the second input of the second comparator 403 ′ is an inverting input, and the other of the first input and the second input of the second comparator 403 ′ is a non-inverting input. The first input of the second comparator 403 ′ may be assumed to be of the same type as the first input of the first comparator 403 (i.e., an inverting or non-inverting type). If the order of the inverting input and the non-inverting input of the first comparator 403 and the second comparator 403 ′ is reversed (with Figure 4 ), the outputs of the first comparator 403 and the second comparator 403′ may be inverted, or alternatively, the first switch 406 and the second switch 406′ may be configured as active low switches (ie, closed when the input voltage is low).

[0090] Figure 5 FIG. 1 shows a process performed by a reset circuit of a differential relaxation oscillator according to an embodiment. The reset circuit that performs the process shown may correspond to Figure 4The reset circuit 408 of the differential relaxation oscillator 400. The process may be performed by the reset circuit in software (i.e., using computer software maintained in at least one memory of the reset circuit and defining steps to be performed by at least one processor of the reset circuit) or in hardware (i.e., using hardware circuitry such as latches) or using a combination of hardware and software.

[0091] In the following discussion, it is assumed that the first switch and the fourth switch (elements 406' and 420) are initially open, and the second switch and the third switch (elements 406 and 420') are initially closed. This is referred to as the first switch state hereinafter. The first switch state can correspond to the logic output Q1=1&Q0=0. The opposite switch state, that is, the situation where the first switch and the fourth switch (elements 406' and 420) are closed and the second switch and the third switch (elements 406 and 420') are open is referred to as the second switch state hereinafter. The second switch state can correspond to the logic output Q1=0&Q2=1. The first switch state and the second switch state are mutually exclusive (i.e., only one of them can be active at any given time).

[0092] In block 501, the reset circuit monitors the output of the first comparator (element 403') and the output of the second comparator (element 403), or specifically the output voltage of the first comparator and the output voltage of the second comparator. In block 502, the reset circuit checks whether the output of the first comparator indicates the voltage V of the non-inverting input of the first comparator. C1 exceeds the voltage at the inverting input V R For example, this may correspond to checking that the output of the first comparator is equal to a logic 1 (indicating that V C >V R ) or equal to logic 0 (indicating V C ≤V R ). It should be noted that at voltage V R While the voltage V C1 The voltage rises continuously due to the charging of the first capacitor when the first switch (element 406') is open and the third switch (element 420') is closed (ie, when the first switch state is activated).

[0093] In response to the comparator output indicating the voltage V at the non-inverting input of the first comparator in block 502 C1 Failure to exceed the inverting input voltage V R (eg, corresponding to a logic output of 0), in block 506, the reset circuit maintains the first switch, the second switch, the third switch, and the fourth switch in the first switch state.

[0094] In response to the output of the first comparator corresponding to a logic 1 (indicating the voltage V at the non-inverting input in block 502), C exceeds the voltage at the inverting input V R ), in block 503, the reset circuit causes activation of the second switch state to discharge the first capacitor. This results in a voltage V C1 Down to zero.

[0095] In blocks 504, 505, and 507, the reset circuit also performs corresponding processing based on the output of the second comparator (element 403). That is, in block 504, the reset circuit checks whether the output of the second comparator indicates that the voltage V of the non-inverting input of the second comparator is C2 exceeds the voltage at the inverting input V R For example, this may correspond to checking that the output of the second comparator is equal to a logic 1 (indicating that V C >V R ) or equal to logic 0 (indicating V C ≤V R ). It should be noted that the voltage V C2 It continuously rises due to the charging of the second capacitor when the second switch (element 406) is open and the fourth switch (element 420) is closed (ie, when the second switch state is activated).

[0096] In response to the output of the second comparator indicating the voltage V at the non-inverting input of the second comparator in block 506 C2 Failure to exceed the inverting input voltage V R (eg, corresponding to a logic output of 0), in block 507 , the reset circuit maintains the first switch, the second switch, the third switch, and the fourth switch in the second switch state.

[0097] In response to the output of the second comparator corresponding to a logic 1 (indicating the voltage V at the non-inverting input in block 504), C exceeds the voltage at the inverting input V R ), in block 505, the reset circuit causes activation of the first switch state to discharge the second capacitor. This results in a voltage V C2 Down to zero.

[0098] After executing block 505 or 507, the process returns to block 501. In other words, the process is repeated.

[0099] Therefore, if Figure 5It can be observed that the reset circuit is configured to activate the first switch state and the second switch state in turn, so that the first capacitor and the second capacitor can be periodically charged and discharged. It should be noted that at any given time, only one of the first capacitor and the second capacitor is being charged. While one of the first capacitor and the second capacitor is being charged, the other of the first capacitor and the second capacitor (and the associated differential branch) is in a discharge state.

[0100] Figure 6 Shows Figure 4 Example operation of a differential relaxation oscillator. That is, Figure 6 The voltage V is plotted C1 、V C2 、V R , Q1 and Q2 versus time. Figure 4 As shown in and discussed above, the voltage V C1 is the voltage at the node between the second current source 402' and the first capacitor 405' (or equivalently between the non-inverting input of the first comparator 403' and the first capacitor 405'), the voltage V C2 is the voltage at the node between the third current source 402 and the second capacitor 405 (or equivalently between the non-inverting input of the second comparator 403 and the second capacitor 405), the voltage V R is the voltage at the node between the first current source 401 and the first resistor 404 (or equivalently between the inverting input of the first comparator / second comparator and the first resistor 404). Figure 6 The subplots share the same horizontal axis.

[0101] Reference Figure 6 , the first switch 406' and the fourth switch 420 are initially closed, while the second switch 406 and the third switch 420' are open (ie, the second switch state is active). Therefore, V C1 Initially at zero, and V C2 is non-zero and rising (i.e., the second capacitor is charging). This corresponds to the case where Q1 has a low value (corresponding to a logical 0) and Q2 has a high value (corresponding to a logical 1). On the other hand, V R remains constant during operation of the differential relaxation oscillator (regardless of the positions of the first switch, the second switch, the third switch, and the fourth switch), similar to Figure 3A .

[0102] When V C2 Exceed V R (=RI), the first switch state is activated (and thus the second switch state is deactivated), which in turn results in charging of the first capacitor (as indicated by the rising V C1as demonstrated by V C2 This corresponds to the case where Q1 has a high value (corresponding to a logical 1) and Q2 has a low value (corresponding to a logical 0).

[0103] Similarly, when V C1 Exceed V R (=RI), the second switch state is activated again (and thus the first switch state is deactivated), which in turn leads to a recharging of the second capacitor (as caused by the rising V C2 as demonstrated by V C1 becomes zero). This corresponds to the case where Q1 has a low value (corresponding to a logical 0) and Q2 has a high value (corresponding to a logical 1). The above operation is then repeated.

[0104] Although the above Figure 1 The Single-Ended Relaxation Oscillator 100 is discussed in Figure 3B ,but Figure 3B It can also be seen as depicting Figure 4 behavior of the differential relaxation oscillator 400. In addition, Figure 4 The voltage V R0 'Can show Figure 3B For V R0 The same temperature-dependent behavior is depicted.

[0105] The embodiments provide at least the following advantages.

[0106] Simplicity and low cost: Including the offset resistor R0 in the relaxation oscillator enables the aforementioned problems associated with the positive temperature coefficient of the sheet resistance of the relaxation oscillator to be overcome in a simple and cost-effective manner. For example, it is not necessary to employ a special resistor type (i.e., a resistor type that enables a negative temperature coefficient) to flatten the temperature gradient of the relaxation oscillator. Typical CMOS processes do not provide resistors with negative temperature coefficients. In some CMOS processes, such resistors may be available, although they require the application of additional masks during production in the CMOS process, which makes the manufacturing process more complex and expensive. In addition, the following operations enable better duty cycles and more reliable clocks to be obtained: for a single-ended relaxation oscillator, the first current source and the second current source are made the same (i.e., setting I1=I2=I), or for a differential relaxation oscillator, the first current source, the second current source and the third current source are made equal (i.e., setting I1=I2=I3=I). Temperature compensation by including the offset resistor R0 is simpler than other compensation techniques and requires fewer electronic components to implement.

[0107] Reliability: All resistors in the first resistor R and the second resistor R0 for a single-ended relaxation oscillator or the first resistor R, the second resistor R0' and the third resistor R0 for a differential relaxation oscillator can be placed close to each other to obtain good matching. Similar or identical resistor types can be selected to obtain process correlation.

[0108] The embodiments described herein are applicable not only to the systems defined above, but also to other systems. The specifications of systems and their components are developing rapidly. Such developments may require additional changes to the described embodiments. Therefore, all words and expressions should be interpreted broadly, and these words and expressions are intended to illustrate the embodiments rather than to limit the embodiments. It will be apparent to those skilled in the art that, as technology advances, the inventive concept can be implemented in various ways. The embodiments are not limited to the examples described above, but may vary within the scope of the claims.

Claims

1. A relaxation oscillator, comprising: a first current source and a second current source; a comparator having an output, a first input connected to the first current source, and a second input connected to the second current source, wherein one of the first input and the second input is an inverting input and the other of the first input and the second input is a non-inverting input; a resistance circuit connected between the first input of the comparator and ground, wherein the resistance circuit comprises at least a first resistor; and a capacitor charging circuit connected between the second input of the comparator and the ground, wherein the capacitor charging circuit includes a capacitor, a second resistor connected in series with the capacitor, and a switch connected in parallel with the capacitor, the switch being configured to be controlled based on the output of the comparator.

2. The relaxation oscillator according to claim 1, further comprising: A falling edge delay circuit is connected between the output of the comparator and the switch, and is used to delay the switching of the switch so that the charge of the capacitor can be more completely reset when the switch is turned off.

3. The relaxation oscillator according to claim 1 or 2, further comprising: A clock divider circuit is connected to the output of the comparator.

4. A relaxation oscillator according to any preceding claim, wherein: The first current source and the second current source are configured to output substantially equal currents.

5. A relaxation oscillator according to any preceding claim, wherein: The first resistor and the second resistor have first and second resistances, respectively, and first and second temperature coefficients, respectively, and the first resistance, the second resistance, the first temperature coefficient, and the second temperature coefficient are selected to achieve a substantially flat temperature response of the relaxation oscillator as a whole.

6. The relaxation oscillator according to claim 5, wherein: The first temperature coefficient and the second temperature coefficient are both positive or negative and / or the first resistance is greater than the second resistance, and the second temperature coefficient is greater than the first temperature coefficient.

7. The relaxation oscillator according to any one of claims 5 to 6, wherein: The first resistance, the second resistance, the first temperature coefficient, and the second temperature coefficient have values ​​that substantially satisfy the following equation: Here, R, R0, α, and α0 are the first resistance, the second resistance, the first temperature coefficient, and the second temperature coefficient, respectively, and dT is the differential of temperature.

8. A relaxation oscillator according to any preceding claim, wherein: The falling edge delay circuit comprises: enter, Output, a delay element having an output and an input connected to the input of the falling edge delay circuit, and An OR gate having a first input connected to the output of the delay element, a second input connected to the input of the falling edge delay circuit, and an output connected to the output of the falling edge delay circuit.

9. A differential relaxation oscillator, comprising: a first current source, a second current source, and a third current source; a first comparator having an output, a first input connected to the first current source, and a second input connected to the third current source, wherein one of the first input and the second input of the first comparator is an inverting input and the other of the first input and the second input of the first comparator is a non-inverting input; a second comparator having an output, a first input connected to the first current source, and a second input connected to the second current source, wherein one of the first input and the second input of the second comparator is an inverting input and the other of the first input and the second input of the second comparator is a non-inverting input, and the first input of the second comparator is of the same type as the first input of the first comparator; a resistance circuit connected between the first input of the first comparator and ground, wherein the resistance circuit comprises at least a first resistor; a first capacitor charging circuit connected between the second input of the first comparator and the ground, wherein the first capacitor charging circuit comprises a first capacitor, a second resistor connected in series with the first capacitor, and a first switch connected in parallel with the first capacitor; a second capacitor charging circuit connected between the second input of the second comparator and the ground, wherein the second capacitor charging circuit comprises a second capacitor, a third resistor connected in series with the second capacitor, and a second switch connected in parallel with the second capacitor; a third switch connected between the second current source and the first capacitor charging circuit; a fourth switch connected between the third current source and the second capacitor charging circuit; and A reset circuit is configured to control the first switch, the second switch, the third switch and the fourth switch based on the output of the first comparator and the output of the second comparator to achieve alternating charging of the first capacitor and the second capacitor and periodic resetting of the charges of the first capacitor and the second capacitor.

10. The differential relaxation oscillator according to claim 9, wherein: The reset circuit is configured to control the first switch, the second switch, the third switch, and the fourth switch such that at any given time, a state of the third switch matches a state of the second switch and a state of the fourth switch matches a state of the first switch.

11. The differential relaxation oscillator according to claim 9 or 10, wherein: The resistance circuit includes the first resistor, the first capacitor charging circuit includes the first capacitor, the second resistor and the first switch, and / or the second capacitor charging circuit includes the second capacitor, the third resistor and the second switch.

12. The differential relaxation oscillator according to any one of claims 9 to 11, wherein: The first current source, the second current source, and the third current source are configured to output substantially equal currents.

13. The differential relaxation oscillator according to any one of claims 9 to 12, wherein: The first resistor, the second resistor and the third resistor have a first resistance, a second resistance and a third resistance, respectively, and have a first temperature coefficient, a second temperature coefficient and a third temperature coefficient, respectively. The first resistor, the second resistor, the third resistor, the first temperature coefficient, the second temperature coefficient and the third temperature coefficient are selected to achieve a substantially flat temperature response of the differential relaxation oscillator as a whole.

14. The differential relaxation oscillator according to claim 13, wherein: The first temperature coefficient, the second temperature coefficient and the third temperature coefficient are all positive or negative, and / or the first resistance is greater than the second resistance and greater than the third resistance, and the second temperature coefficient and the third temperature coefficient are greater than the first temperature coefficient.

15. The differential relaxation oscillator according to any one of claims 9 to 14, wherein: The reset circuit is configured to: receiving an output of the first comparator and an output of the second comparator; In response to the output of the first comparator corresponding to a first logic value, closing the first switch and the third switch, wherein the first logic value is equal to logic 1 or logic 0; In response to the output of the first comparator corresponding to a second logic value, the first switch and the third switch are turned off or kept turned off, wherein the second logic value is a logic value opposite to the first logic value; In response to the output of the second comparator corresponding to the first logic value, closing the second switch and the fourth switch or keeping the first switch and the third switch closed; and In response to the output of the second comparator corresponding to the second logic value, the second switch and the fourth switch are turned off or kept off.

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