Detection circuit, semiconductor integrated circuit, semiconductor device, and control method

Abstract

According to one embodiment, there is provided a detection circuit having a comparison circuit and a signal generation circuit. The comparison circuit has a first input node, a second input node, and an output node. The first input node is connected with one end of the power device. The second input node is connected to a threshold voltage. The signal generation circuit has a first input node and an output node. The first input node is connected with an output node of the comparison circuit. The output node is connected with a control node of the protection circuit of the power device.

Description

Technical Field

[0001] The present embodiment relates to a detection circuit, a semiconductor integrated circuit, a semiconductor device, and a control method. Background Art

[0002] A semiconductor device connected to a control terminal of a power device drives the power device. The power device is connected to a load through which a relatively large current flows, and is used to switch the load. In the semiconductor device, it is desirable to appropriately protect the power device from an overcurrent.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2018 / 0097515 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] One embodiment provides a detection circuit, a semiconductor integrated circuit, a semiconductor device, and a control method suitable for appropriately protecting a power device from an overcurrent.

[0008] Technical solutions for solving technical problems

[0009] According to one embodiment, a detection circuit having a comparison circuit and a signal generation circuit is provided. The comparison circuit has a first input node, a second input node, and an output node. The first input node is connected to one end of a power device. The second input node is connected to a threshold voltage. The signal generation circuit has a first input node and an output node. The first input node is connected to the output node of the comparison circuit. The output node is connected to a control node of a protection circuit of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit diagram showing the configuration of a semiconductor device according to an embodiment.

[0011] Figure 2 It is a diagram showing the concept of DESAT in the embodiment.

[0012] Figure 3 It is a waveform diagram showing the operation of the semiconductor device according to the embodiment.

[0013] Figure 4 is a circuit diagram showing a configuration of a semiconductor device according to a first modified example of the embodiment.

[0014] Figure 5 : is a circuit diagram showing the configuration of a time history generating circuit in a first modified example of the embodiment.

[0015] Figure 6 1 is a waveform diagram showing the operation of the time history generating circuit according to the first modified example of the embodiment.

[0016] Figure 7 is a circuit diagram showing a configuration of a semiconductor device according to a second modification example of the embodiment.

[0017] Figure 8 This is a circuit diagram showing the configuration of a semiconductor device according to a third modified example of the embodiment.

[0018] Fig. 9 is a circuit diagram showing a configuration of a semiconductor device according to a fourth modified example of the embodiment.

[0019] Fig.10 is a circuit diagram showing a configuration of a semiconductor device according to a fifth modification example of the embodiment. DETAILED DESCRIPTION

[0020] (Implementation Method)

[0021] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the embodiment.

[0022] (Implementation Method)

[0023] The semiconductor device of the embodiment is connected to the control terminal of the power device to drive the power device, but research is being conducted to appropriately protect the power device from the influence of overcurrent.

[0024] The semiconductor device 1 may also be Figure 1 The control terminal G of the power device PT shown is connected to drive the power device PT. Figure 1 : is a circuit diagram showing the structure of the semiconductor device 1.

[0025] The power device PT is connected to a load LD that operates with a relatively large current, and is used to switch the load LD. The load LD may include a resistance component LDa and an induction component LDb. For example, the load LD may be a part of a DC motor and its drive circuit (e.g., an H-bridge circuit), and the power device PT may be another part of the drive circuit. Alternatively, the load LD may also be a part of an AC motor and its drive circuit (e.g., an inverter circuit), and the power device PT may also be another part of the drive circuit.

[0026] The power device PT can be any device that can handle relatively large currents. The power device PT can be an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a bipolar transistor. The substrate used for the element structure of the power device PT can be a SiC substrate or a Si substrate.

[0027] When a short circuit or other fault occurs in the load LD, an overcurrent may flow through the power device PT. In order to protect the power device PT from the overcurrent, it is more effective to detect the start of the overcurrent flowing through the power device PT and disconnect the power device PT according to the situation. The start of the overcurrent flowing through the power device PT can be detected by detecting DESAT (hereinafter referred to as DESAT detection).

[0028] DESAT can be used as Figure 2 Defined as shown in . Figure 2 This is a diagram for explaining DESAT.

[0029] For example, when the power device PT is an N-type IGBT, Figure 2 As shown in (a), one end of the power device PT becomes the collector C, the other end becomes the emitter E, and the control terminal becomes the gate G.

[0030] Power device PT such as Figure 2 As shown in (b), if the voltage V between the gate G and the emitter E is CE If the voltage V between the collector C and the emitter E exceeds the specified value and turns on, in the region RG1, CE The current I from the collector C to the emitter E increases. C In the region RG2 on the higher voltage side, the current I C Relative voltage V CE increases slowly with the increase of .

[0031] like Figure 2 As shown by the hollow arrow in (b), the current I C The sharp area RG1 to the current I C The gentle transition of region RG2 is called DESAT. Region RG1 is sometimes called saturation region. Region RG2 is sometimes called active region.

[0032] In addition, when the power device PT is a P-type IGBT, the polarity of the voltage between the turned-on gate G and the emitter E is opposite and the collector current flows from the emitter E to the collector C, which is the same as the case where the power device PT is an N-type IGBT.

[0033] Alternatively, in the case where the power device PT is an N-type power MOSFET, as Figure 2 As shown in (c), one end of the power device PT becomes the drain D, the other end becomes the source S, and the control terminal becomes the gate G.

[0034] Power device PT such as Figure 2 As shown in (d), if the voltage V between the gate G and the source S is GS If the voltage V between the drain D and the source S exceeds the specified value and turns on, in the region RG11, DS The drain current I D In the region RG12 on the higher voltage side, the current I D Relative voltage V DS increases slowly with the increase of .

[0035] like Figure 2 As shown by the hollow arrow in (d), the current I D In the steep area RG11 flows the current I D The gentle transition of region RG12 is called DESAT. Region RG11 is sometimes called the linear region. Region RG12 is sometimes called the saturation region.

[0036] In addition, when the power device PT is a P-type power MOSFET, it is the same as the case where the power device PT is an N-type power MOSFET, except that the polarity of the voltage between the turned-on gate G and the source S is opposite and the drain current flows in the direction from the source S toward the drain D.

[0037] Although not shown, when the power device PT is a bipolar transistor, one end of the power device PT becomes a collector, the other end becomes an emitter, and the control terminal becomes a base. The transition from a region where the current at both ends is steep to a region where the current at both ends is gentle is called DESAT.

[0038] The following description will focus on the case where the power device PT is an N-type power MOSFET. One end, the other end, and the control terminal of the power device PT are respectively represented as D, S, and G. The following description can also be applied to the case where the power device PT is of other types.

[0039] Figure 1The semiconductor device 1 shown has input nodes 1a to 1c and an output node 1d. The input node 1a is connected to the outside (for example, a higher-level controller) and receives an input signal INPUT from the outside. The input node 1b is connected to one end D of the power transistor PT and one end of the load LD. The input node 1c is connected to one end D of the power transistor PT and one end of the load LD. The output node 1d is connected to the control terminal G of the power transistor PT.

[0040] One end D of the power device PT is connected to the input nodes 1b and 1c of the semiconductor device 1 and one end of the load LD, the other end S is connected to the ground potential GND, and the control terminal G is connected to the output node 1d of the semiconductor device 1 .

[0041] The semiconductor device 1 includes a semiconductor integrated circuit 2, a rectifying element D DESAT , capacitor element C DESAT , resistance element R DESAT , Rectifier element D DET , resistance element R DET .

[0042] The semiconductor integrated circuit 2 may be formed of a single chip or may be divided into a plurality of chips. The semiconductor integrated circuit 2 is provided with a terminal INPUT, a terminal VDDET, a terminal DESAT, and a terminal GATE_DRIVE.

[0043] Rectifier element D DESAT Connected between the terminal DESAT and one end D of the power device PT. Rectifier element D DESAT The direction from the terminal DESAT toward the end D is defined as the forward direction. DESAT It could also be a diode.

[0044] Capacitor element C DESAT One end of the DESAT terminal and the rectifier element D DESAT The node between them is connected, and the other end is connected to the ground potential. DESAT The capacitance value of can be predetermined according to the operating characteristics required by the protection circuit 4. DESAT The capacitance value can be determined based on the capacitance element C required by the DESAT detection of the power device PT. DESAT The charging characteristics (e.g., RC time constant or charging time of current source 43) are predetermined.

[0045] Resistor element R DESAT Connect the DESAT terminal to the rectifier element D DESAT The resistor element R DESAT The resistance value of can be predetermined according to the characteristics required of the protection circuit 4. DESATThe resistance value of can be predetermined according to the operating characteristics required by the protection circuit 4. DESAT The resistance value can be used to detect the required capacitance element C according to the DESAT of the power device PT. DESAT The charging characteristics (e.g., RC time constant) are predetermined.

[0046] Rectifier element D DET Connected between the terminal VDDET and one end D of the power device PT. Rectifier element D DET The direction from the terminal VDDET toward the end D is defined as the forward direction. DET It could also be a diode.

[0047] Resistor element R DET Connect the terminal VDDET and the rectifier element D DET The resistor element R DET The resistance value of can be predetermined according to the operation characteristics required by the detection circuit 3. DET The resistance value of the resistor element R is required to detect the voltage drop at one end D of the power device PT. DET The resistance characteristics (e.g., transient current limiting) of the device are predetermined.

[0048] The semiconductor integrated circuit 2 includes a detection circuit 3 , a protection circuit 4 , and a drive circuit 5 .

[0049] The detection circuit 3 is connected between the terminal INPUT, the protection circuit 4 and the terminal VDDET. The detection circuit 3 can detect a voltage drop at one end D of the power device PT via the terminal VDDET. When the detection circuit 3 detects a voltage drop at one end D, it generates a signal to activate the protection circuit 4 and supplies it to the protection circuit 4.

[0050] The detection circuit 3 includes a comparison circuit 31 , a voltage source 32 , a current source 33 , a capacitor 34 , a switch 35 , and a control unit (signal generation circuit) 36 .

[0051] The comparison circuit 31 has an input node 31a, an input node 31b, and an output node 31c. The input node 31a is connected to the output node 31c via a terminal VDDET, a resistor element R DET And the rectifying element D DET The input node 31 b is connected to one end D of the power device PT. The input node 31 b is connected to the voltage source 32 . The output node 31 c is connected to the control unit 36 ​​.

[0052] One end of the voltage source 32 is connected to the input node 31b of the comparison circuit 31, and the other end is connected to the ground potential. The voltage source 32 may also be a constant voltage source, generating a reference voltage corresponding to the threshold voltage Vth1. The threshold voltage Vth1 is related to the voltage V at one end D of the power device PT. D The waveform of the falling correspondence (refer to Figure 3 ).

[0053] For example, the comparison circuit 31 compares the voltage V VDDET It is compared with the threshold voltage Vth1.

[0054] In the case where the input node 31a is a non-inverting input node and the input node 31b is an inverting input node, if the voltage V VDDET If the voltage V VDDET When it is lower than the threshold voltage Vth1, the comparison circuit 31 outputs a comparison result of the L level.

[0055] In the case where the input node 31a is the inverting input node and the input node 31b is the non-inverting input node, if the voltage V VDDET If the voltage V VDDET If the voltage is lower than the threshold voltage Vth1, the comparison circuit 31 outputs a comparison result of the H level.

[0056] One end of the current source 33 is connected to the power supply potential, and the other end is connected to a node between the input node 31a of the comparison circuit 31 and the terminal VDDET. The current source 33 may also be a constant current source, and can supply a constant current to the capacitor 34. The constant current supplied by the current source 33 can be predetermined according to the operation characteristics required by the detection circuit 3. The constant current supplied by the current source 33 can be predetermined according to the charging characteristics of the capacitor 34 required for detecting the drop in the voltage at one end D of the power device PT.

[0057] One end of the capacitor 34 is connected to a node between the input node 31a of the comparison circuit 31 and the terminal VDDET, and the other end is connected to the ground potential. The capacitance value of the capacitor 34 can be predetermined based on the operation characteristics required by the detection circuit 3. The capacitance value of the capacitor 34 can be predetermined based on the charging characteristics of the capacitor 34 required for detecting a drop in the voltage at one end D of the power device PT.

[0058] The switch 35 is connected between one end of the capacitor 34 and the ground potential. The switch 35 has one end connected to a node between the input node 31a of the comparison circuit 31 and the terminal VDDET, the other end connected to the ground potential, and a control terminal connected to the control unit 36.

[0059] When the switch 35 receives the control signal MASK1 of the non-valid level (e.g., L level) from the control unit 36, the switch 35 disconnects one end of the capacitor element 34 from the ground potential by turning off, so that the capacitor element 34 becomes chargeable. When the switch 35 receives the control signal MASK1 of the valid level (e.g., H level) from the control unit 36, the switch 35 connects one end of the capacitor element 34 to the ground potential by turning on, extracts charge from one end of the capacitor element 34, sets the input node 31a of the comparison circuit 31 to the ground potential, and invalidates the function of the detection circuit.

[0060] An input node 36 a of the control unit 36 ​​is connected to the terminal INPUT, an input node 36 b is connected to the comparison circuit 31 , an output node 36 d is connected to the switch 35 , and an output node 36 e is connected to the protection circuit 4 .

[0061] The control unit 36 ​​generates a control signal MASK based on the input signal INPUT and supplies the control signal MASK to the switch 35 .

[0062] In response to the fact that the comparison result of the comparison circuit 31 is inverted, the control unit 36 ​​generates a control signal EN_DESAT for activating the protection circuit 4 and supplies the control signal to the protection circuit 4 .

[0063] When the input node 31a of the comparison circuit 31 is a non-inverting input node and the input node 31b is an inverting input node, the control unit 36 ​​supplies the control signal EN_DESAT of a non-active level to the protection circuit 4 during the period TP1 when the comparison circuit 31 outputs the comparison result of the H level. The control unit 36 ​​supplies the control signal EN_DESAT of an active level to the protection circuit 4 during the period TP2 when the comparison circuit 31 outputs the comparison result of the L level.

[0064] When the input node 31a of the comparison circuit 31 is an inverting input node and the input node 31b is a non-inverting input node, the control unit 36 ​​supplies the control signal EN_DESAT of a non-active level to the protection circuit 4 during the period TP11 during which the comparison circuit 31 outputs the comparison result of the L level. The control unit 36 ​​supplies the control signal EN_DESAT of an active level to the protection circuit 4 during the period TP12 during which the comparison circuit 31 outputs the comparison result of the H level.

[0065] The protection circuit 4 is connected between the terminal INPUT, the detection circuit 3, the drive circuit 5, and the terminal DESAT. The protection circuit 4 can detect the DESAT of the power device PT via the terminal DESAT. When the protection circuit 4 detects the DESAT of the power device PT, it supplies the drive circuit 5 with a signal OFF_CTR instructing the power device PT to shut down.

[0066] The protection circuit 4 includes a comparison circuit 41 , a voltage source 42 , a current source 43 , a switch 45 , a filter 47 , and a control unit (signal generation circuit) 46 .

[0067] The comparison circuit 41 has an input node 41a, an input node 41b, and an output node 41c. The input node 41a is connected to the output node 41c via the terminal DESAT, the resistor element R DESAT And the rectifying element D DESAT The input node 41 b is connected to one end D of the power device PT. The input node 41 b is connected to the voltage source 42 . The output node 41 c is connected to the control unit 46 via the filter 47 .

[0068] The filter 47 is connected between the comparison circuit 41 and the control unit 46. The filter 47 rejects a short pulse signal in the case of erroneous determination with respect to the comparison result of the comparison circuit 41 and supplies the signal to the control unit 46.

[0069] One end of the voltage source 42 is connected to the input node 41b of the comparison circuit 41, and the other end is connected to the ground potential. The voltage source 42 may also be a constant voltage source, generating a reference voltage corresponding to the threshold voltage Vth2. The threshold voltage Vth2 is related to the voltage V at one end D of the power device PT. D The rising waveform corresponds to (refer to Figure 3 ).

[0070] For example, the comparison circuit 41 converts the voltage V at the terminal DESAT to DESAT It is compared with the threshold voltage Vth2.

[0071] In the case where the input node 41a is a non-inverting input node and the input node 41b is an inverting input node, if the voltage V DESAT If the voltage V DESAT If the voltage is lower than the threshold voltage Vth2, the comparison circuit 41 outputs a comparison result of the L level.

[0072] In the case where the input node 41a is an inverting input node and the input node 41b is a non-inverting input node, if the voltage V DESAT When the voltage V is higher than the threshold voltage Vth2, the comparison result of L level is output. DESAT If the voltage is lower than the threshold voltage Vth2, the comparison circuit 41 outputs a comparison result of the H level.

[0073] One end of the current source 43 is connected to the power supply potential, and the other end is connected to a node between the input node 41a of the comparison circuit 41 and the terminal DESAT. The current source 43 may also be a constant current source that can supply a current to the capacitor element C via the terminal DESAT. DESATThe constant current supplied by the current source 43 can be predetermined according to the operation characteristics required by the protection circuit 4. The constant current supplied by the current source 43 can be determined in advance according to the capacitance element C required for the DESAT detection of the power device PT. DESAT The charging characteristics are predetermined.

[0074] Switch 45 is connected between the capacitor element C DESAT One end of the switch 45 is connected to a node between the input node 41a of the comparison circuit 41 and the terminal DESAT, the other end is connected to the ground potential, and the control terminal is connected to the control unit 46.

[0075] When the switch 45 receives the control signal MASK2 of the non-active level (e.g., L level) from the control unit 46, the switch 45 is turned off to disconnect one end of the capacitor element 34 from the ground potential, so that the capacitor element 34 can be charged. When the switch 45 receives the control signal MASK2 of the active level (e.g., H level) from the control unit 46, the switch 45 is turned on to connect one end of the capacitor element 34 to the ground potential, so that the capacitor element 34 can be charged. K The charge is extracted from one end and discharged to ground potential.

[0076] The input node 46 a of the control unit 46 is connected to the terminal INPUT, the input node 46 b is connected to the comparison circuit 41 via the filter 47 , the control node 46 c is connected to the detection circuit 3 , the output node 46 d is connected to the switch 45 , and the output node 46 e is connected to the drive circuit 5 .

[0077] In response to the fact that the comparison result of the comparison circuit 41 is inverted, the control unit 46 generates a control signal OFF_CTR instructing to shut down the power device PT and supplies the control signal to the drive circuit 5 .

[0078] When the input node 41a of the comparison circuit 41 is a non-inverting input node and the input node 41b is an inverting input node, the control unit 46 supplies the control signal OFF_CTR of the active level to the drive circuit 5 during the period TP21 when the comparison circuit 41 outputs the comparison result of the H level. The control unit 46 supplies the control signal OFF_CTR of the inactive level to the drive circuit 5 during the period TP22 when the comparison circuit 41 outputs the comparison result of the L level.

[0079] When the input node 41a of the comparison circuit 41 is an inverting input node and the input node 41b is a non-inverting input node, the control unit 46 supplies the control signal OFF_CTR of an active level to the drive circuit 5 during the period TP11 when the comparison circuit 41 outputs the comparison result of the L level. The control unit 46 supplies the control signal OFF_CTR of an inactive level to the drive circuit 5 during the period TP12 when the comparison circuit 41 outputs the comparison result of the H level.

[0080] The drive circuit 5 has an input node 5a, an output node 5b, and a control node 5c. The input node 5a is connected to the terminal INPUT. The output node 5b is connected to the control terminal G of the power transistor PT. The control node 5c is connected to the protection circuit 4.

[0081] While receiving the control signal Shutdown of the non-active level, the drive circuit 5 generates a drive signal DRV for switching according to the input signal IN and supplies the drive signal DRV to the control terminal G of the power transistor PT. Thus, the power transistor PT can be switched.

[0082] When receiving the control signal Shutdown of the active level, the drive circuit 5 generates a drive signal DRV for maintaining the off state regardless of the input signal IN and supplies it to the control terminal G of the power transistor PT. Therefore, the power transistor PT is maintained in the off state. Therefore, the power transistor PT can be protected from the influence of the overcurrent generated in the load LD.

[0083] exist Figure 1 In the semiconductor device 1 shown, Figure 3 As shown, DESAT detection is performed during the period from timing t4 to timing t8. Figure 3 It is a waveform diagram showing the operation of the semiconductor device 1 .

[0084] During the period from timing t4 to t8, the protection circuit 4 is enabled, and the DESAT detection of the protection circuit 4 is enabled. The period (t4 to t8) of the DESAT detection is within the period from timing t4 to t10 when the power device PT is in the on state.

[0085] In the DESAT detection, the protection circuit 4 senses the voltage V at one end D of the power device PT according to the fact that an excess current flows into the power device PT in the on state. D exceeds the rise of the threshold voltage Vth2. Figure 3 In the example, during the period from t4 to t8, the voltage V D is maintained below the threshold voltage Vth2, and the voltage V is not sensed. D The case where the threshold voltage Vth2 rises.

[0086] Although not shown in the figure, when the voltage V is sensed D When the voltage exceeds the threshold voltage Vth2, the protection circuit 4 changes the control signal OFF_CTR to an active level and supplies it to the drive circuit 5. In response, the drive circuit 5 turns the drive signal V GATE DRIVEThe voltage is changed to a non-active level (for example, L level), and the power device PT is turned off. Thus, the power device PT is controlled to be turned off.

[0087] At the start timing of “DESAT Valid”, which enables DESAT detection, the input signal INPUT becomes active (eg, H level), and accordingly, the drive signal V GATE_DRIVE The timing t1 when the driving signal V GATE_DRIVE The period from timing t1 to timing t8 during which the active level is maintained is described as “control signal on”.

[0088] At this time, if Figure 3 As shown, there is a difference between the drive signal V GATE_DRIVE The voltage V at the control terminal G becomes an effective level. G The delay time Td1 corresponding to the dead time until the rise starts and the delay time Td2 corresponding to the dead time from the voltage V G The delay time Td2 corresponds to the switching time from when the rising edge starts to when the power device PT is turned on.

[0089] Here, it is considered that the dead time and the switching time are measured in advance, and the blanking time T is determined in advance by experiments as the delay time from the trigger timing t1 to the start timing of "DESAT is valid" (= dead time + switching time). BLANK And it is fixedly set in the protection circuit 4.

[0090] For example, in the protection circuit 4, the timer 461 of the control unit 46 may be preset to have the same value as the blanking time T BLANK In this case, just before the timing t1, the protection circuit 4 sets the count value of the timer 461 to the initial value and sets the control signal MASK2 to the effective level. When the protection circuit 4 senses the rising of the waveform of the input signal INPUT, the timer 461 starts counting. When the count value reaches the prescribed value, the control signal MASK2 is set to the inactive level and the switch 45 is turned off, so that the DESAT detection is effective.

[0091] However, at least the switching time out of the dead time and the switching time tends to vary due to the influence of manufacturing variations of the power device PT, ambient temperature, and the like.

[0092] The blanking time T is fixedly set BLANK If it is longer than the actual "dead time + switching time", the blanking time T will be longer than the actual "dead time + switching time". BLANKDuring the period from 0 to 100 , DESAT detection cannot be performed. During this period, if an excessive current flows into the power device PT in the on state, the power device PT may be damaged. In other words, it may be difficult to perform DESAT detection appropriately.

[0093] The blanking time T is set at a fixed BLANK When the blanking time T is shorter than the actual "dead time + switching time", the power device PT is in the off state but the blanking time T has passed. BLANK During this period, although no excess current flows into the power device PT, if the voltage V at one end D is D If the threshold voltage Vth is exceeded, there is a possibility that the occurrence of DESAT may be erroneously detected. In other words, it may be difficult to properly perform DESAT detection.

[0094] Therefore, in the semiconductor device 1, the voltage V at the terminal D of the power device PT is detected by the detection circuit 3. D The decrease in DESAT value is detected by the protection circuit 4 according to the detection timing, thereby realizing the appropriateness of the start timing of DESAT validation.

[0095] For example, just before timing t1, the detection circuit 3 sets the control signal MASK1 to an effective level and maintains the switch 35 in an on state. As a result, the detection circuit 3 invalidates the falling detection of the waveform. The detection circuit 3 sets the control signal EN_DESAT to an inactive level. The protection circuit 4 sets the control signal MASK2 to an effective level and maintains the switch 45 in an on state. As a result, the DESAT detection of the protection circuit 4 is invalidated.

[0096] At timing t1, when sensing the rising edge of the waveform of the input signal INPUT, the driving circuit 5 turns the driving signal V GATE_DRIVE Set to an effective level.

[0097] When the detection circuit 3 detects the rising of the waveform of the input signal INPUT, it sets the control signal MASK1 to an inactive level to turn off the switch 35. D , the falling detection of the waveform is made effective. That is, the detection circuit 3 becomes capable of detecting the voltage V D The falling state of the waveform.

[0098] At this time, the power device PT is disconnected, and the voltage V D In response, the rectifying element D DETThe current of the current source 33 is turned off, and the current of the capacitor 34 is charged. The voltage of the terminal VDDET becomes higher than the threshold voltage Vth1, and the comparison result V 31 Before the effective level control signal EN_DESAT arrives from the detection circuit 3, the protection circuit 4 sets the control signal MASK2 to the effective level and maintains the switch 45 in the on state, so that the voltage of the terminal DESAT is lower than the threshold voltage Vth2, and the comparison result V 41 Becomes L level.

[0099] At timing t2, the voltage V at the control terminal G G begins to rise, and accordingly, the power device PT begins to turn on. At timing t3, the voltage V D Start to descend.

[0100] At timing t4, when the voltage V D When the comparison result V 31 In other words, the detection circuit 3 detects the voltage V at one end D. D Correspondingly, the detection circuit 3 sets the control signal EN_DESAT to an active level and supplies it to the protection circuit 4.

[0101] According to the active level control signal EN_DESAT, the protection circuit 4 sets the control signal MASK2 to an inactive level and turns off the switch 45. In this way, the protection circuit 4 enables the DESAT detection. That is, the protection circuit 4 becomes capable of detecting the DESAT of the power device PT. Figure 3 In the figure, the blanking period from timing t1 to t4 is expressed as "blanking".

[0102] At the timing t5 immediately thereafter, the transition of the power device PT to the on state is completed.

[0103] At timing t7, the voltage V at the control terminal G is G Reach and maintain a specified level (e.g., H level).

[0104] At timing t8, when the falling edge of the waveform of the input signal INPUT is sensed, the driving circuit 5 turns the driving signal V GATE_DRIVE Set to an inactive level. Figure 3 In the example, the driving signal V GATE_DRIVE The period from timing t1 to timing t8 during which the active level is maintained is expressed as “control signal on”.

[0105] In addition, when the falling waveform of the input signal INPUT is sensed, the detection circuit 3 sets the control signal MASK1 to the effective level and turns on the switch 35. As a result, the falling waveform detection of the detection circuit 3 is invalidated again. The detection circuit 3 sets the control signal EN_DESAT to the inactive level and supplies it to the protection circuit 4. The protection circuit 4 sets the control signal MASK2 to the effective level and turns on the switch 45. As a result, the DESAT detection of the protection circuit 4 is invalidated again. Figure 3 In FIG. 1 , the period from timing t4 to timing t8 when DESAT detection is enabled is expressed as “DESAT enabled”.

[0106] At timing t9, the voltage V at the control terminal G is G At the next timing t10, the power device PT starts to turn off, and the voltage V D Start to rise. Figure 3 In FIG. 1 , a period from timing t5 to timing t10 ​​during which the power device PT is maintained in the on state is expressed as “power device on state”.

[0107] At timing t11, the voltage V D Reach and maintain a specified level (e.g., H level).

[0108] At the subsequent timing t12, the voltage V at the control terminal G is G The voltage drops to a reference level (eg, L level), and the transition of the power device PT to the off state is completed.

[0109] like Figure 3 As shown, according to the voltage V at one end D of the power device PT D The transition timing of the power device PT to the on state is determined based on the detection result of the falling waveform, and is set as the DESAT detection validation timing. As a result, the blanking time can be ended at the timing close to the completion of the transition of the power device PT to the on state without being affected by the manufacturing deviation of the power device PT or the temperature dependence, and the DESAT detection validation can be started.

[0110] As described above, in the embodiment, in the semiconductor device 1, the voltage V at the terminal D of the power device PT is detected by the detection circuit 3. D The DESAT detection of the protection circuit 4 is enabled according to the detection timing. Thus, the start timing of DESAT activation can be optimized. In addition, the system does not need to design a margin for the activation timing of DESAT detection, which can reduce the load of system design and make the system design QTAT-efficient.

[0111] In addition, Figure 1In the detection circuit 3 shown, the capacitor element 34 may be omitted. In this case, the current source 33 charges the current to the parasitic capacitance of the line connecting the comparison circuit 31 and the terminal VDDET.

[0112] exist Figure 1 In the semiconductor device 1 shown in FIG. 1 , the capacitor element C may be omitted. DESAT In this case, the current source 43 of the protection circuit 4 charges the current to the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT.

[0113] Figure 1 The control unit 46 of the protection circuit 4 shown in the figure does not use the timer 461, and sets the control signal MASK2 to the active level according to the control signal EN_DESAT received from the detection circuit 3. Therefore, in the control unit 46, the timer 461 may be omitted.

[0114] (First Modification of Embodiment)

[0115] In addition, the voltage V across one end D of the power device PT D When the DESAT detection is validated by detecting the drop of, the voltage V at one end D is also considered when the power device PT is turned on, according to the timing of the failure or malfunction of the load (for example, the inverter device) LD. D Therefore, the voltage V at one end D can also be kept D The history of descent detection time is used to validate DESAT detection based on past time history.

[0116] In the semiconductor device 1i, as Figure 4 As shown, the detection circuit 3i of the semiconductor integrated circuit 2i can also replace the control unit 36 ​​(see Figure 1 ) and has a control unit 36i. Figure 4 1 is a diagram showing a configuration of a semiconductor device 1i according to a first modification of the embodiment. The control unit 36i includes a time history generating unit 361i.

[0117] In the control unit 36i, the time history generating unit 361i measures the time from the rise of the waveform of the input signal INPUT to the comparison result V 31 The time history generating unit 361i calculates the time from the rising of the waveform of the input signal INPUT to the measured time Δt (refer to Figure 3 ) corresponding to the predetermined time, a control signal EN_DESAT for activating the protection circuit 4 is generated and supplied to the protection circuit 4. The predetermined time may be obtained by offset The time obtained by adding the history time Δt. Offset time toffset Any time greater than 0 can be used.

[0118] The time history generating unit 361i may also be as follows Figure 5 As shown. Figure 5 : is a circuit diagram showing the configuration of a time history generating unit 361i in a first modification example of the embodiment.

[0119] The time history generating unit 361i includes a counter 361i1, a latch circuit 361i2, an adder 361i3, a setting circuit 361i4, and a timer 361i5.

[0120] The node S￣ of the counter 361i1 is connected to the terminal INPUT and the node S￣ of the counter 361i1, the node E is connected to the comparison circuit 31, and the node O is connected to the node D of the latch circuit 36ii2. The voltage V at one end D of the counter 361i1 is D The voltage V at one end D is counted. D The falling time is the time from when the input signal INPUT changes from L level to H level to when the voltage V at one end changes from L level to H level. D That is, the counter 361i1 starts counting according to the rising of the input signal INPUT received at the node S￣, and counts according to the comparison result V of the comparison circuit 31 received at the node E. 31 The counter 361i1 outputs the count value to the latch circuit 361i2. The count value represents the time Δt measured by the counter 361i1.

[0121] The node CK￣ of the latch circuit 361i2 is connected to the terminal INPUT, and the node Q is connected to the adder 361i3. The falling time of the voltage VD at one end counted by the counter 361i1 is held by the latch circuit 361i2 at the transition timing of the input signal INPUT from the H level to the L level. That is, the latch circuit 361i2 latches the count value of the counter 361i1 according to the falling of the input signal INPUT received at the node CK￣, and outputs the latched value from the node Q to the adder 361i3.

[0122] The output node of the setting circuit 361i4 is connected to the adder 361i3. The setting circuit 361i4 sets the offset time t in advance. offset The setting circuit 361i4 will represent the offset time t offset The value of is output to adder 361i3.

[0123] The first input node of the adder 361i3 is connected to the latch circuit 361i2, the second input node is connected to the setting circuit 361i4, and the output node is connected to the node E of the timer-361i5. The adder 361i3 adds the latched value (i.e., the value representing the measured time Δt) to the value representing the offset time t offset The value of the addition is added and the value of the addition result is output to the timer 361i5. The value of the addition result represents the specified time Δt+t offset .

[0124] The node O of the timer-361i5 is connected to the protection circuit 4. The timer-361i5 receives the value of the addition result at the node G. In the reset state, the timer-361i5 outputs the control signal EN_DESAT of the non-effective level from the node O to the protection circuit 4. The timer-361i5 starts counting according to the rising of the input signal INPUT received at the node S, and ends the counting operation when the count value reaches the value of the addition result received at the node G, so that the control signal EN_DESAT is changed to the effective level and supplied to the protection circuit 4.

[0125] For example, the time history generating unit 361i may also be as follows Figure 6 Perform the action as shown. Figure 6 It is a waveform diagram showing the operation of the time history generating unit 361i in the first modification example of the embodiment.

[0126] At timing t21, the counter 361i1 of the time history generating unit 361i starts counting the time Δt according to the rising of the input signal INPUT. The timer 361i5 starts counting the time (Δt0+t offset ) count operation. Δt0 is the time when Δt was measured last time. The comparison circuit 31 starts to output the comparison result V at the H level. 31 .

[0127] At timing t22, the counter 361i1 is set based on the comparison result V of the comparison circuit 31. 31 When the voltage is inverted from the H level to the L level, the counting operation of the time Δt is terminated, and the count value of the measured time Δt=Δt1 is output to the latch circuit 361i2.

[0128] After a predetermined time (Δt0+t offset ) at timing t23, the count value of the timer 361i5 reaches the predetermined time (Δt0+t offset ) corresponding value.

[0129] At the timing t24 immediately thereafter, the timer 361i5 sets the control signal EN_DESAT to the active level and supplies it to the protection circuit 4. As a result, in the protection circuit 4, DESAT is activated.

[0130] At timing t25, the latch circuit 361i2 latches the count value of the counter 361i1 according to the falling of the input signal INPUT, and starts to output the latched value to the adder 361i3. In response to this, the adder 361i3 starts to output the value obtained by adding the offset to the latched value. The value of the addition result of the adder 361i3 is output to the timer 361i5 and is set as the value to be counted by the timer 361i5.

[0131] In response to the falling edge of the input signal INPUT, the timer 361i5 sets the control signal EN_DESAT to a non-active level and supplies the control signal to the protection circuit 4. As a result, in the protection circuit 4, DESAT is disabled.

[0132] At timing t26, the counter 361i1 of the time history generating unit 361i starts counting the time Δt according to the rising of the input signal INPUT. The timer 361i5 starts counting the predetermined time (Δt1+t offset ) count operation. Δt1 is the time when Δt was measured last time. The comparison circuit 31 starts to output the comparison result V at the H level. 31 .

[0133] At timing t27, the counter 361i1 is set based on the comparison result V of the comparison circuit 31. 31 When the voltage is inverted from the H level to the L level, the counting operation of the time Δt is terminated, and the count value of the measured time Δt=Δt2 is output to the latch circuit 361i2.

[0134] After a predetermined time (Δt1+t offset ) at timing t28, the count value of the timer 361i5 reaches the predetermined time (Δt1+t offset ) corresponding value.

[0135] At the timing t29 immediately following this, the timer 361i5 sets the control signal EN_DESAT to the active level and supplies it to the protection circuit 4. As a result, in the protection circuit 4, DESAT is activated.

[0136] At timing t30, in response to the fall of the input signal INPUT, the latch circuit 361i2 latches the count value of the counter 361i1 and starts outputting the latched value to the adder 361i3. In response to this, the adder 361i3 starts outputting a value obtained by adding the offset to the latched value. The value of the addition result of the adder 361i3 is output to the timer 361i5 and is set as the value to be counted by the timer 361i5.

[0137] In response to the falling edge of the input signal INPUT, the timer 361i5 sets the control signal EN_DESAT to a non-active level and supplies the control signal to the protection circuit 4. As a result, in the protection circuit 4, DESAT is disabled.

[0138] Thus, in the semiconductor device 1i, the detection circuit 3i retains the voltage V at one end D. D The detection circuit 4 uses the history of the falling detection time to validate the DESAT detection based on the past time history. For example, the detection circuit 4 uses the predetermined time obtained by adding the offset toffset that takes into account the change to the time Δt just measured to validate the DESAT detection. In this way, the start timing of the DESAT validation can also be optimized.

[0139] (Second Modification of Embodiment)

[0140] Alternatively, the start timing of "DESAT effective" for enabling DESAT detection may be a combination of the operation of the embodiment and the operation of the first variant. For example, the start timing of "DESAT effective" may correspond to the falling timing of the voltage VD at one end D of the power transistor PT and the time (Δt+t offset )’s timing, whichever is earlier.

[0141] At this time, in the semiconductor device 1j, the detection circuit 3j of the semiconductor integrated circuit 2j may also be Figure 7 As shown, instead of the control unit 36i (refer to Figure 4 ) and has a control unit 36j. Figure 7 FIG. 1 is a diagram showing a configuration of a semiconductor device 1 j according to a second modification example of the embodiment.

[0142] The control unit 36j generates a control signal based on the comparison result V of the comparison circuit 31. 31 Inverted, or after a predetermined time (Δt+t offset ), and generates a control signal EN_DESAT to enable the protection circuit 4. For example, the control unit 36j may also generate a control signal EN_DESAT to enable the protection circuit 4 according to the comparison result V of the comparison circuit 31. 31The inversion timing is the same as the time (Δt+t offset ) at an earlier timing, a control signal EN_DESAT is generated to enable the protection circuit 4.

[0143] The control unit 36 ​​j may further include an operator 362 j . The operator 362 j has a first input node connected to the output node 31 c of the comparison circuit 31 , a second input node connected to an output node of the time history generator 361 i , and an output node connected to the protection circuit 4 .

[0144] The logical sum operator 362j calculates the comparison result V of the comparison circuit 31. 31 The logical inversion of the control signal EN_DESAT output by the time history generating unit 361i (refer to Figure 5 ) is calculated and the control signal EN_DESAT is generated as the result of the operation. The control signal EN_DESAT is generated at the timing of the voltage VD at the end D of the power transistor PT and the predetermined time (Δt+t offset ) is changed from the inactive level to the active level at the earlier timing. Therefore, the start timing of "DESAT is active" can be the falling timing of the voltage VD at one end D of the power transistor PT and the specified time (Δt+t offset ) in the earlier timing.

[0145] Thus, in the semiconductor device 1j, the detection circuit 3j detects the comparison result V of the comparison circuit 31. 31 Inverted, or after a predetermined time (Δt+t offset ) to generate a control signal EN_DESAT for activating the protection circuit 4. This also makes it possible to optimize the start timing of activating DESAT.

[0146] (Third Modification of Embodiment)

[0147] The semiconductor device 1k may also be Figure 8 The structure is simplified as shown. Figure 8 FIG. 1 is a diagram showing a structure of a semiconductor device 1 k according to a third modified example of the embodiment.

[0148] The semiconductor integrated circuit 2k of the semiconductor device 1k includes a detection circuit 3 and a protection circuit 4 (see Figure 1 ) are combined to form a protection circuit 4k including the detection circuit 3k. The detection circuit 3k omits the current source 33, the capacitor 34, the switch 35, and the control unit 36. The protection circuit 4k has a control unit 46k instead of the control unit 46 (see Figure 1 ).

[0149] The control unit 46k has the additional function of the control unit 36. The control unit 46k activates the protection circuit 4k based on the fact that the comparison result of the comparison circuit 31 is inverted, thereby activating the DESAT detection of the protection circuit 4k.

[0150] In addition, the semiconductor device 1k omits the capacitor element C DESAT (Refer to Figure 1 ), instead, the protection circuit 4k adds a capacitor element C DESAT1 . Capacitor element C DESAT1 The capacitance value can be determined by detecting the voltage drop at one end D of the power device PT. DESAT1 The charging characteristics are predetermined.

[0151] Thus, the semiconductor integrated circuit 2k of the semiconductor device 1k includes the protection circuit 4k including the detection circuit 3k, and the structure is simplified, thereby reducing the circuit scale of the semiconductor integrated circuit 2k, thereby saving space for the semiconductor device 1k and reducing the cost of the semiconductor device 1k.

[0152] exist Figure 8 In the structure shown, the capacitor element C can also be omitted. DESAT1 In this case, the current source 43 of the protection circuit 4k charges the current to the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT.

[0153] (Fourth Modification of Embodiment)

[0154] like Fig. 9 As shown, the semiconductor device 1n can also be simplified in structure. Fig. 9 It is a diagram showing a structure of a semiconductor device 1n according to a fourth modified example of the embodiment.

[0155] The semiconductor integrated circuit 2n of the semiconductor device 1n includes a detection circuit 3i and a protection circuit 4 (see Figure 4 ) are combined to form a protection circuit 4n including the detection circuit 3n. The detection circuit 3n omits the current source 33, the capacitor 34, the switch 35, and the control unit 36i. The protection circuit 4n has a control unit 46n instead of the control unit 46i (see Figure 4 ).

[0156] The control unit 46n adds the function of the control unit 36i. The control unit 46n controls the input signal INPUT based on the time (Δt+t offset ), the protection circuit 4n is enabled, and the DESAT detection of the protection circuit 4n is enabled. For example, the control unit 46n is based on the predetermined time (Δt+toffset ) This makes the DESAT detection effective. As a result, the protection circuit 4n becomes capable of performing the DESAT detection of the power transistor PT.

[0157] In addition, the semiconductor device 1n omits the capacitor element C DESAT (Refer to Figure 1 ), instead, the protection circuit 4k adds a capacitor element C DESAT1 . Capacitor element C DESAT1 The capacitance value can be determined by detecting the voltage drop at one end D of the power device PT. DESAT1 The charging characteristics are predetermined.

[0158] Thus, in the semiconductor integrated circuit 2n of the semiconductor device 1n, the protection circuit 4n including the detection circuit 3n is formed and the structure is simplified, thereby reducing the circuit scale of the semiconductor integrated circuit 2n, thereby saving space and reducing the cost of the semiconductor device 1n.

[0159] exist Fig. 9 In the structure shown, the capacitor element C can also be omitted. DESAT1 In this case, the current source 43 of the protection circuit 4n charges the current to the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT.

[0160] (Fifth Modification of Embodiment)

[0161] The semiconductor device 1p may also be Fig.10 The structure is simplified as shown. Fig.10 It is a diagram showing a structure of a semiconductor device 1p according to a fifth modification of the embodiment.

[0162] The semiconductor integrated circuit 2p of the semiconductor device 1p includes a detection circuit 3j and a protection circuit 4 (see Figure 7 ) are combined to form a protection circuit 4p including the detection circuit 3p. The detection circuit 3p omits the current source 33, the capacitor 34, the switch 35, and the control unit 36j. The protection circuit 4p has a control unit 46p instead of the control unit 46j (see Figure 7 ).

[0163] The control unit 46p adds the function of the control unit 36j. The control unit 46p inverts the comparison result of the comparison circuit 31 or changes the input signal INPUT to a predetermined time (Δt+t offset ), the protection circuit 4p is enabled, and the DESAT detection of the protection circuit 4p is enabled. For example, the control unit 46p may detect the DESAT detection of the protection circuit 4p based on the time (Δt+t offset) In this case, for example, the control unit 46p sets the start timing of "DESAT is effective" to the falling timing of the voltage VD at one end D of the power transistor PT and the predetermined time (Δt+t offset ) makes the DESAT detection effective at an earlier timing. As a result, the protection circuit 4p becomes capable of performing the DESAT detection of the power transistor PT.

[0164] In addition, the semiconductor device 1k omits the capacitor element C DESAT (Refer to Figure 1 ), instead, the protection circuit 4k adds a capacitor element C DESAT1 . Capacitor element C DESAT1 The capacitance value can be determined by detecting the voltage drop at one end D of the power device PT. DESAT1 The charging characteristics are predetermined.

[0165] Thus, in the semiconductor integrated circuit 2p of the semiconductor device 1p, the protection circuit 4p including the detection circuit 3p is formed and the structure is simplified, thereby reducing the circuit scale of the semiconductor integrated circuit 2p, thereby saving space for the semiconductor device 1p and reducing the cost of the semiconductor device 1p.

[0166] exist Fig.10 In the structure shown, the capacitor element C can also be omitted. DESAT1 In this case, the current source 43 of the protection circuit 4p charges the current to the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT.

[0167] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A detection circuit, characterized in that: have: A comparison circuit having a first input node connected to one end of the power device, a second input node connected to a threshold voltage corresponding to a drop in the waveform, and an output node; as well as The signal generating circuit has a first input node connected to the output node of the comparison circuit and an output node connected to the control node of the protection circuit of the power device.

2. The detection circuit according to claim 1, characterized in that: The signal generating circuit generates a control signal for activating the protection circuit in response to the fact that the comparison result of the comparing circuit is inverted.

3. The detection circuit according to claim 2, characterized in that: The signal generating circuit supplies the control signal of a non-valid level to the protection circuit during a first period when the comparison circuit outputs a first comparison result, and supplies the control signal of a valid level to the protection circuit during a second period when the comparison circuit outputs a second comparison result that is opposite to the first comparison result.

4. The detection circuit according to claim 1, characterized in that: The signal generating circuit further includes a second input node connected to the input terminal.

5. The detection circuit according to claim 4, characterized in that: The signal generating circuit measures the time from the rise of the waveform of the input signal supplied to the input terminal to the time when the comparison result of the comparison circuit is inverted, and generates a signal to activate the protection circuit based on the fact that a specified time corresponding to the measured time has passed since the rise of the waveform of the input signal.

6. The detection circuit according to claim 5, characterized in that: The signal generating circuit generates a signal for activating the protection circuit in response to the comparison result of the comparing circuit being inverted or the predetermined time elapsed from the rising edge of the waveform of the input signal.

7. A semiconductor integrated circuit, characterized in that: have: The detection circuit according to any one of claims 1 to 6; A protection circuit having an input node connected to one end of the power device, a control node connected to the output node of the detection circuit, and an output node; as well as The drive circuit has an input node connected to the input terminal, a control node connected to the output node of the protection circuit, and an output node connected to the control terminal of the power device.

8. A semiconductor integrated circuit, characterized in that: have: a drive circuit having an input node, a control node, and an output node connected to a control terminal of the power device; A first comparison circuit having a first input node connected to one end of the power device, a second input node connected to a first threshold voltage corresponding to the fall of the waveform, and an output node; A second comparison circuit having a first input node connected to one end of the power device, a second input node connected to a second threshold voltage corresponding to the rise of the waveform, and an output node; as well as The signal generating circuit has a first input node connected to the output node of the first comparing circuit, a first output node, and a second output node connected to the control node of the driving circuit.

9. The semiconductor integrated circuit according to claim 8, wherein: The semiconductor integrated circuit further includes a switch having a first node connected to the first input node of the second comparison circuit, a second node connected to a reference potential, and a control node. The signal generating circuit generates a signal for activating the protection circuit in response to the fact that the comparison result of the first comparing circuit is inverted.

10. The semiconductor integrated circuit according to claim 8, wherein: The semiconductor integrated circuit further includes a switch having a first node connected to the first input node of the second comparison circuit, a second node connected to a reference potential, and a control node. The signal generating circuit measures the time from the rise of the waveform of the input signal of the driving circuit to the fall of the waveform of the voltage at one end of the power device, and generates a signal to activate the protection circuit based on the fact that a specified time corresponding to the measured time has passed since the rise of the waveform of the input signal.

11. The semiconductor integrated circuit according to claim 10, wherein: The signal generating circuit generates a signal for activating the protection circuit in response to the comparison result of the first comparing circuit being inverted or the predetermined time having passed since the waveform of the input signal rises.

12. A semiconductor device, characterized in that: have: The semiconductor integrated circuit according to claim 7; A first rectifying element connected between the detection circuit and one end of the power device; and The second rectifying element is connected between the protection circuit and one end of the power device.

13. A semiconductor device, characterized in that: have: The semiconductor integrated circuit according to any one of claims 8 to 11; and A rectifying element is connected between the first input node of the second comparison circuit and one end of the power device.

14. A control method, characterized in that: The steps include: comparing a voltage at one end of the power device to a threshold voltage; and In response to the fact that the comparison result is inverted, the protection circuit of the power device is activated.

15. The control method according to claim 14, characterized in that: The method further includes the following steps: measuring the time from the rise of the waveform of the input signal to the fall of the waveform of the voltage at one end of the power device corresponding to the opposite phase of the comparison result; The effectiveness of the protection circuit includes: The protection circuit is activated based on at least one of an inversion of the comparison result and a lapse of a predetermined time corresponding to the measured time from a rising edge of the waveform of the input signal.

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