Chip test system and test method

Abstract

The invention belongs to the technical field of chip testing, and provides a chip testing system and method, and the system comprises an upper computer, ATE testing equipment, and SLT testing equipment. The ATE testing equipment is matched with the translation manipulator so as to complete automatic testing of the to-be-tested chip; the SLT test equipment comprises an SAP assembly, an SLT test board, a liftable supporting mechanism and an SLT test machine table. The SLT test board is a PCB which is subjected to limited layout according to the structural characteristics of the translation manipulator, and the limited layout at least comprises the limited layout of the SAP assembly relative to the SLT test board; according to the SLT test equipment, the translation type manipulator of the automatic test equipment ATE can be directly used in the chip SLT test, and the STL professional manipulator equipment does not need to be purchased by consuming extra cost, so that the cost is saved for related personnel, and the cost increase caused by equipment purchase is avoided.

Description

Technical Field

[0001] The present application belongs to the field of chip testing technology, and in particular, relates to a chip testing system and testing method. Background Art

[0002] Chip testing includes automatic test equipment test (ATE) and system level test (SLT). As chips become more and more complex, system level test SLT has become an important part of chip testing.

[0003] In the field of chip testing, the translational manipulator suitable for ATE automatic test equipment testing can usually only be used for ATE automatic test equipment testing due to structural and communication limitations. Therefore, the conventional method for the SLT system-level test of the chip requires the purchase of an additional set of STL professional manipulator equipment specifically used for chip system-level testing to complete the SLT test of the chip, which increases the cost of related personnel. Summary of the invention

[0004] The embodiments of the present application provide a chip testing system and testing method, which can directly use the translational manipulator of the automatic test equipment ATE device in the chip SLT test, without spending extra costs to purchase STL professional manipulator equipment, thereby saving costs for related personnel and avoiding cost increases caused by equipment procurement.

[0005] In a first aspect, an embodiment of the present application provides a chip testing system, the chip testing system comprising a host computer, an ATE testing device and an SLT testing device; the ATE testing device cooperates with a translation manipulator to complete automatic testing of a chip to be tested; the SLT testing device comprises a SAP component, an SLT testing board, a liftable support mechanism, and an SLT testing machine;

[0006] The SLT test board is a PCB board with restricted layout according to the structural characteristics of the translation manipulator, and the restricted layout at least includes the restricted layout of the SAP component relative to the SLT test board;

[0007] The SLT test equipment is used to perform system-level testing on the chip to be tested, wherein, during the system-level testing of the SLT test equipment, the upper surface of the SAP component is connected to the translation manipulator, and the lower surface of the SAP component is connected to the SLT test board:

[0008] The host computer is used to communicate with the translational manipulator through a preset communication interface, and is used to control the movement of the translational manipulator;

[0009] The translational manipulator is used to control the SAP component to move toward the SLT test machine, place the chip to be tested at a predetermined test point on the SLT test board, and feed back a preparation signal to the host computer;

[0010] The host computer is further used to send a test instruction to the SLT test equipment when receiving the preparation signal, so that the SLT test equipment performs a system-level test on the chip to be tested at each predetermined test point on the SLT test board;

[0011] The host computer is also used to receive and display the system-on-chip test results fed back by the SLT test equipment.

[0012] In one example, during the system-level test, the center position of the upper surface of the SLT test board is attached to and fixed with the center position of the lower surface of the SAP component to form a chip test area on the upper surface of the SLT test board; the translation manipulator grabs the SAP component and the SLT test board and moves toward the bottom of the SLT test machine, so that the SLT test board is close to the bottom of the SLT test machine to form an overlapping area of ​​the bottom surface projection of the SLT test machine, and the SLT test board and the bottom of the SLT test machine are separated by a preset height limit distance; wherein the center position of the upper surface of the SLT test board is within the range of the overlapping area of ​​the bottom surface projection of the SLT test machine;

[0013] The restricted layout of the SAP component relative to the SLT test board includes the top surface layout restrictions of the SAP component, including:

[0014] m predetermined test points are arranged along the upper surface of the SAP component, and the m predetermined test points are divided into n rows and arranged in parallel, each row having m / n predetermined test points; the spacing between the predetermined test points in the first direction is a first spacing, and the spacing between the predetermined test points in the second direction is a second spacing, wherein the second direction is perpendicular to the first direction;

[0015] Among them, the SLT test board is provided with a first surface device layout area on the first side of the chip test area in the second direction, and a second surface device layout area is provided on the second side of the chip test area in the second direction, and the remaining area of ​​the overlapping area of ​​the bottom projection of the SLT test machine except the first surface device layout area and the second surface device layout area is an area where device placement is prohibited.

[0016] In one example, the chip test area is provided with an air pipe interface; and the heights of the components arranged in the first surface component arrangement area and the second surface component arrangement area do not exceed the preset height limit distance.

[0017] In one example, a temperature sensor is disposed in the area between the first row and the last row of the m predetermined test points, and the temperature sensor is used to obtain the current test temperature.

[0018] In one example, transverse fastening screws are arranged around the overlapping area of ​​the bottom projection of the SLT test machine, and the height of the components placed on the periphery of the overlapping area of ​​the bottom projection does not exceed the preset height limit distance.

[0019] In one example, the restriction layout further includes a screw hole position restriction layout of the SAP component relative to the translation manipulator, and the screw hole position restriction layout includes:

[0020] Four through screw holes with a first diameter are arranged on the fixture of each predetermined test point of the SAP component, and the through screw holes with a first diameter are used to fix the fixture and the SAP component.

[0021] In one example, the screw hole position restriction layout includes:

[0022] Within the chip testing area, through screw holes with a second diameter are respectively arranged in an area away from the predetermined test points in the first row and an area away from the predetermined test points in the last row, and the through screw holes with a second diameter are used to fix the SAP component and the SLT test board.

[0023] In one example, the first arrangement area and the second arrangement area are provided with through screw holes with a diameter of a third size, and the through screw holes with a diameter of the third size are used to fix the SAP assembly to the translation robot.

[0024] In one example, the restricted layout of the SAP component relative to the SLT test board also includes the lower surface layout restriction of the SAP component, including a test point metal area located at the center of the lower surface of the SAP component, the test point metal area is integrated with the m predetermined test points, and the current test temperature of the test point metal area needs to be controlled within a preset test temperature range.

[0025] The beneficial effect of the first aspect of the present application is that the translational manipulator of the automatic test equipment ATE equipment can be directly used in the chip SLT test, without spending extra costs to purchase STL professional manipulator equipment, thus saving costs for relevant personnel and avoiding cost increases caused by equipment procurement.

[0026] In a second aspect, the present application further proposes a chip testing method, which is applied to the SLT testing device of the chip testing system as described in the first aspect above, wherein the SAP component of the SLT testing device is pre-layout-designed according to a preset manner for the upper surface of the SAP component, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component, so that the upper surface of the SAP component, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component match the translation manipulator of the ATE testing device of the chip testing system; the chip testing method comprises the following steps:

[0027] The host computer controls the translational manipulator to move, so that the SAP component moves toward the SLT test machine, places the chip to be tested at a predetermined test point on the SLT test board, and feeds back a preparation signal to the host computer;

[0028] When receiving the preparation signal, the host computer sends a test instruction to the SLT test equipment, so that the SLT test equipment performs a system-level test on the chip to be tested at each predetermined test point on the SLT test board;

[0029] The host computer receives and displays the system-on-chip test results fed back by the SLT test equipment.

[0030] The beneficial effect of the second aspect of the present application is that: the SAP component of the SLT test equipment is designed and laid out according to the preset method of the first aspect, so that the upper surface of the SAP component, the lower surface of the SAP component, and the position of the screw holes on the upper surface of the SAP component match the translation manipulator of the ATE test equipment of the chip test system; then a set of chip test programs is designed, and the chip test program is executed by the host computer, so that the external control of the translation manipulator of the ATE automatic test equipment can be realized, and the translation manipulator of the ATE automatic test equipment is controlled to act on the SLT test equipment, and the STL system-level test of the chip to be tested is completed with the help of the translation manipulator. There is no need to spend extra cost to purchase STL professional manipulator equipment, which saves costs for relevant personnel and avoids the cost increase caused by equipment procurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a structural block diagram of a chip testing system provided by an embodiment of the present invention;

[0033] Figure 2 1 is a schematic diagram of the layout of the upper surface of the SAP assembly relative to the translation manipulator provided by an embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of the upper surface structure of a SAP component provided by an embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of the lower surface structure of a SAP component provided by an embodiment of the present invention;

[0036] Figure 5 It is a schematic diagram of the bottom structure of a manipulator provided by an embodiment of the present invention;

[0037] Figure 6 is a schematic diagram of a screw hole position restriction layout provided by an embodiment of the present invention;

[0038] Figure 7 is a structural schematic diagram of a liftable support mechanism provided by an embodiment of the present invention;

[0039] Figure 8 is a schematic diagram of an example flow of a chip testing method provided by the present invention;

[0040] Fig. 9 is another exemplary flow chart of a chip testing method provided by an embodiment of the present invention;

[0041] Fig.10 It is a structural diagram of a host computer provided by an embodiment of the present invention.

[0042] Reference numerals:

[0043] Translational manipulator-01, SAP component-02, SLT test board-03, liftable support mechanism-04, SLT test machine-05. DETAILED DESCRIPTION

[0044] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0045] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0046] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0047] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0049] It is understandable that the chip testing process includes ATE automatic test equipment testing and STL system-level testing. As chips become more and more complex, system-level testing SLT has become an important part of chip testing.

[0050] In the prior art, the translation manipulator suitable for ATE automatic test equipment testing can usually only be used for ATE automatic test equipment testing due to the limitations of structure and communication mode. The specific limitations include two aspects:

[0051] On the one hand, the complex structure of the translational manipulator of the ATE automatic test equipment leads to many restrictions on the layout of the PCB test board of the system-level test SLT, making it difficult to implement system design;

[0052] On the other hand, the communication method of the translational manipulator of the ATE automatic test equipment is deeply bound to the machine of the ATE automatic test equipment, making it difficult to achieve external control;

[0053] Therefore, conventional testing methods cannot use the translational manipulator of ATE automatic testing equipment to complete the STL system-level testing of chips. It is necessary to purchase an additional set of STL professional manipulator equipment specifically for chip system-level testing to complete the SLT testing of chips, which increases the cost of related personnel.

[0054] The present application invents a chip testing system and a chip testing method, which can use the translational manipulator of ATE automatic testing equipment to complete the SLT system-level test of the chip, so that enterprises can use the original manipulator equipment of ATE automatic testing equipment to implement SLT testing, avoiding the cost increase caused by equipment procurement.

[0055] In the first aspect, in order to solve the above technical problems, the embodiment of the present application proposes a chip testing system. The chip testing system includes a host computer, an ATE testing device and an SLT testing device; the ATE testing device cooperates with a translation manipulator 01 to complete the automatic test of the chip to be tested; the SLT testing device includes a SAP component 02, an SLT testing board 03, a liftable support mechanism 04, and an SLT testing machine 05;

[0056] The SLT test board 03 is a PCB board with restricted layout according to the structural features of the translation manipulator 01;

[0057] The SLT testing device is used to perform system-level testing on the chip to be tested, wherein during the system-level testing of the SLT testing device, the upper surface of the SAP component 02 is connected to the translation robot 01, and the lower surface of the SAP component 02 is connected to the SLT testing board 03.

[0058] The host computer is used to communicate with the translational manipulator through a preset communication interface (the present embodiment takes the GPIB interface as the preset communication interface as an example for explanation, of course, in other embodiments, TTL, RS232 and other communication interfaces can also be used as the preset communication interface, depending on the specific situation) to control the movement of the translational manipulator;

[0059] The translational manipulator 01 is used to control the SAP component 02 to move toward the SLT test machine 05, place the chip to be tested at a predetermined test point on the SLT test board 03, and feed back a preparation signal to the host computer;

[0060] The host computer is further used to send a test instruction to the SLT test equipment when receiving the preparation signal, so that the SLT test equipment performs a system-level test on the chip to be tested at each predetermined test point on the SLT test board 03;

[0061] The host computer is also used to receive and display the system-on-chip test results fed back by the SLT test equipment.

[0062] Specifically, the above-mentioned restricted layout of this embodiment includes the upper surface layout restriction of the SAP component 02, the lower surface layout restriction of the SAP component 02, and the screw hole position restriction layout of the SAP component 02 relative to the translation manipulator 01.

[0063] Specifically, during the system-level test, the center position of the upper surface of the SLT test board 03 is aligned and fixed with the center position of the lower surface of the SAP component 02 to form a chip test area (such as Figure 2 The "chip test area" shown in the figure corresponds to Figure 3 The translation manipulator 01 grabs the SAP component 02 and the SLT test board 03 and moves them toward the bottom of the SLT test platform 05, so that the SLT test board 03 is close to the bottom of the SLT test platform 05 to form an overlapping area of ​​the bottom surface projection of the SLT test platform (corresponding to Figure 3 The SLT test board 03 and the bottom of the SLT test machine 05 are separated by a preset height limit distance (the preset height limit distance is 10 mm in this embodiment); wherein the center position of the upper surface of the SLT test board 03 is located within the range of the overlapped area (385 mm*345 mm) of the bottom projection of the SLT test machine;

[0064] The restricted layout of the SAP component 02 relative to the SLT test board 03 includes the upper surface layout restrictions of the SAP component 02, including:

[0065] m predetermined test sites are arranged along the upper surface of the SAP component 02, and the m predetermined test sites are divided into n rows and arranged in parallel, each row having m / n predetermined test sites; the spacing between each predetermined test site in the first direction is a first spacing, and the spacing between each predetermined test site in the second direction is a second spacing, wherein the second direction is perpendicular to the first direction; specifically, in this embodiment, the first direction is the X-axis direction, and the second direction is the Y-axis direction, and m=8, n=2, the first spacing=40mm, and the second spacing=60mm are set as an example, that is, in the chip test area, two rows and 4 predetermined test sites in each row are set in the X-axis direction, and the predetermined test sites in the X-axis direction are set at a spacing of 40mm between each other, and the predetermined test sites in the Y-axis direction are set at a spacing of 60mm between each other,

[0066] In addition, if Figure 2As shown, the SLT test board is located at the first side of the chip test area in the second direction ( Figure 2 The upper side of the chip test area is provided with a first surface device arrangement area, and the second side ( Figure 2 The second surface device layout area is provided on the lower side of the SLT test machine. Figure 3 Only the upper and lower 252mm*26mm long strip areas shown in the figure can be used to place devices within the range of the 385mm*345mm corresponding size area), with a height limit of 10mm, and devices are prohibited from being placed in the rest of the area where the SLT test machine bottom projection overlaps.

[0067] The chip test area is provided with an air pipe interface; and the height of the devices arranged in the first surface device arrangement area and the second surface device arrangement area does not exceed the preset height limit distance of 10 mm. Figure 3 As shown, a plurality of air pipe interfaces with a diameter of 6 mm are arranged at the junction of the chip test area and the second arrangement area of ​​the surface device.

[0068] In addition, the SLT test machine bottom projection overlap area (corresponding to Figure 3 The 385mm*345mm corresponding size area) is surrounded by transverse fastening screws (such as Figure 3 As shown, the fastening screw has a diameter of 5 mm and a height of 4 mm), components can be placed outside the overlapping area of ​​the bottom projection, and the height of the components placed outside does not exceed the preset height limit distance of 10 mm.

[0069] In addition, in some embodiments, a temperature sensor is disposed in the area between the first row and the last row (in this embodiment, there are two rows, the last row is the second row) of the m predetermined test points, and the temperature sensor is used to obtain the current test temperature. It should be noted that when placing the temperature sensor, it is necessary to determine whether the temperature sensor will interfere with the SAP component 02, and to avoid interference.

[0070] Further, such as Figure 3 As shown, the restricted layout of the SAP component 02 relative to the SLT test board 03 includes the lower surface layout restrictions of the SAP component 02, including:

[0071] The restricted layout of the SAP component 02 relative to the SLT test board 03 also includes the lower surface layout restriction of the SAP component 02, such as Figure 5As shown, it includes a test point metal area located at the center of the lower surface of the SAP component 02, the test point metal area is integrated with the m predetermined test points, and the current test temperature of the test point metal area needs to be controlled within a preset test temperature range (in this embodiment, the "preset test temperature range" is set to -55 degrees to 125 degrees).

[0072] It is understandable that in this embodiment, the area of ​​the metal area at the test point in the middle area of ​​the lower surface of the SAP component 02 is 250mm*200mm, and the temperature of the metal area at the test point is greatly affected by the front heat source: the back temperature is 10 degrees when the low temperature is -55 degrees, and the back temperature is 50 degrees when the high temperature is 125 degrees (test conditions: board thickness 4.2mm, compressed air). Temperature-sensitive devices need to be carefully evaluated. The plug-in pins in the SAP contact area on the BOTTOM surface cannot be extended.

[0073] Further, refer to Figure 2 and Figure 3 The restriction layout also includes a screw hole position restriction layout of the SAP component 02 relative to the translation manipulator 01, and the screw hole position restriction layout includes:

[0074] The fixture of each predetermined test point of the SAP component 02 is provided with four through screw holes with a first diameter (the first diameter in this embodiment is 2 mm), and the through screw holes with a first diameter of 2 mm are used to fix the fixture and the SAP component 02. Figure 3 As shown, the clamp of each predetermined test point SITE has 2mm*4 screw holes, 32 in total.

[0075] Furthermore, the screw hole position restriction layout further includes:

[0076] Within the chip test area, in an area away from the predetermined test points in the first row and the area away from the predetermined test points in the last row (such as Figure 2 or Figure 3 As shown, in this embodiment, the area away from the predetermined test points of the first row 11 / the last row is Figure 2 The "140mm*140mm position" in the figure is respectively provided with a through screw hole with a second size diameter (the second size in this embodiment is set to 4mm), and the through screw hole of the second size 4mm is used to fix the SAP component and the SLT test board.

[0077] Furthermore, the first arrangement area and the second arrangement area are provided with through screw holes with a diameter of the third size of 6 mm, and the through screw holes with a diameter of the third size of 6 mm are used to fix the SAP component to the translation robot 01.

[0078] Furthermore, in the specific implementation, this embodiment will take into account the force analysis of the screws between the SAP component 02 and the SLT test board 03:

[0079] A. This embodiment uses a conductive adhesive socket. The single-point force of the socket used in this embodiment is 40g. The chip has 117 balls in total, so the force on a single chip is 117*40g=4.68Kg.

[0080] B. In this embodiment, there are 8 chips to be tested, and the total force is 8*4.68Kg=37.5Kg

[0081] C. The weight of the PCB and support frame of SLT test board 03 is estimated to be 10Kg, and the total pressure is 37.5Kg+10KG=47.5Kg

[0082] Because the downward pressure of the translation robot 01 is uncontrollable, the force that the screws between the SLT test board 03 and the SAP component 02 can withstand should be greater than 47.5KG. 32 socket screws of the first size diameter (2mm) + 4 screws of the second size diameter (4mm) can withstand such a force without any problem.

[0083] In the specific implementation, this embodiment also considers the force analysis of the screws between the SAP component 02 and the translation manipulator 01:

[0084] The 8 third-size diameter (6mm) screws between SAP component 02 and translation manipulator 01 bear 300KG+10KG (board weight) = 310KG. 300KG is the pressure for fixing the equipment. The SLT test machine 05 of the SLT test equipment will provide support force (the board is deformed) to prevent the 8 third-size diameter (6mm) screws from being damaged, and can be used as a bottom support frame.

[0085] In the specific implementation, this embodiment also considers the structural design of the liftable support mechanism 04:

[0086] Specifically, in this embodiment, the overall structure of the liftable support mechanism 04 is an aluminum alloy frame, with a built-in electric lift and a hand wheel. The upper layer of the liftable support mechanism 04 is a high-precision platform, which can be used to place the test board, has the functions of PCB board positioning and heat insulation sealing, and has a dry air duct at the bottom, which ensures the dryness and levelness of the test board while ensuring sealing; the lower layer of the liftable support mechanism 04 is placed with a motor control unit.

[0087] Equipment structure Figure 7 As shown in the figure, an elastic heat-insulating sealing pad is provided on the upper part of the "high-precision platform", a PCB board (i.e., SLT test board 03) positioning and mounting groove is provided in the middle part, and a dry air channel (evenly distributed) is provided under the PCB board.

[0088] The beneficial effect of the first aspect of the embodiment of the present application is that the translational manipulator of the automatic test equipment ATE device can be directly used in the chip SLT test, without spending extra costs to purchase STL professional manipulator equipment, thus saving costs for relevant personnel and avoiding cost increases caused by equipment procurement.

[0089] In the second aspect, the embodiment of the present application further proposes a chip testing method, the chip testing method is applied to the SLT testing device of the chip testing system described in the embodiment of the first aspect above, with reference to Figure 8 , the chip testing method comprises the following steps:

[0090] Step S10: Designing the layout of the upper surface of the SAP component of the SLT test equipment, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component in a preset manner, so that the upper surface of the SAP component, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component match the translation manipulator of the ATE test equipment of the chip test system;

[0091] It is understandable that the step S10 may be that the staff pre-layouts the SAP component of the SLT testing equipment in a preset manner according to the first aspect of the embodiment, so that the upper surface of the SAP component, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component match the translation manipulator of the ATE testing equipment of the chip testing system.

[0092] Step S20: the host computer controls the translational manipulator to move so that the SAP component moves toward the SLT test machine, places the chip to be tested at a predetermined test point on the SLT test board, and feeds back a preparation signal to the host computer;

[0093] Step S30: upon receiving the preparation signal, the host computer sends a test instruction to the SLT test equipment, so that the SLT test equipment performs a system-level test on the chips to be tested at each predetermined test point on the SLT test board;

[0094] like Fig. 9As shown, in the specific test process, the host computer sends a "test point status query instruction" to the translational manipulator 01, and the translational manipulator 01 feeds back the test point Site status. If the test point status is a null value, the host computer sends the "test point status query instruction" to the translational manipulator 01 again; when the test point status is not a null value, a chip ID query instruction is sent to the translational manipulator 01 to query the chip ID of the chip to be tested currently loaded on each predetermined test point on the SLT test board 03; when the translational manipulator 01 queries the chip ID of the currently loaded chip to be tested, it feeds back the test data packet of the chip ID to the host computer, and sends a test instruction to the SLT test equipment, so that the SLT test machine performs a system-level test on the currently loaded chip to be tested.

[0095] Step S40: The host computer receives and displays the system-on-chip test results fed back by the SLT test equipment.

[0096] It is understandable that the steps S20 to S40 can be a set of chip testing programs executed by the host computer. The chip testing method of this embodiment designs the layout of the SAP component of the SLT test equipment in accordance with the preset method of the first aspect, so that the upper surface of the SAP component, the lower surface of the SAP component, and the position of the screw holes on the upper surface of the SAP component match the translation manipulator of the ATE test equipment of the chip testing system; then a set of chip testing programs is designed, and the host computer executes this set of chip testing programs to realize external control of the translation manipulator of the ATE automatic test equipment, control the translation manipulator of the ATE automatic test equipment to act on the SLT test equipment, and use the translation manipulator to complete the STL system-level test of the chip to be tested. There is no need to spend extra cost to purchase STL professional manipulator equipment, which saves costs for relevant personnel and avoids the cost increase caused by equipment procurement.

[0097] Fig.10 FIG. 1 is a schematic diagram of the structure of an embodiment of a host computer to which the chip testing method provided in this application is applicable. Fig.10 As shown, the host computer of this embodiment includes: at least one processor 60 ( Fig.10 Only one processor is shown in the figure), a memory 61, and a chip test program 62 stored in the memory 61 and executable on the at least one processor 60, wherein the processor 60 implements the steps in any of the above-mentioned test method embodiments when executing the chip test program 62.

[0098] The host computer may include a mobile phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant (PDA), a smart watch, a smart speaker, and other terminal devices that support wireless communication.

[0099] The host computer may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will appreciate that Fig.10 It is only an example of a host computer and does not constitute a limitation on the host computer. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0100] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0101] In some embodiments, the memory 61 may be an internal storage unit of the host computer, such as a hard disk or memory of the host computer. In other embodiments, the memory 60 may also be an external storage device of the host computer, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped with the host computer. Further, the memory 60 may also include both the internal storage unit of the user terminal and an external storage device. The memory 61 is used to store an operating system, an application, a boot loader (BootLoader), data and other programs, such as the program code of the computer program. The memory 61 may also be used to temporarily store data that has been output or is to be output. When the processor 60 executes the chip test program, the steps of the test method of the embodiment described above are implemented.

[0102] The embodiment of the present application also provides a chip testing program, which, when executed by a processor, can implement the steps in the above-mentioned various method embodiments.

[0103] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a chip test program, and when the chip test program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0104] Based on such understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program (chip test program), and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of each of the above-mentioned method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit it. The specific dimensions of the overlapping area of ​​the bottom projection of the SLT test machine, the specific dimensions of the preset height limit distance, the specific dimensions of the first dimension, the specific dimensions of the second dimension, the specific dimensions of the third dimension, the specific range threshold examples of the preset test temperature range, etc. in the above embodiments are only preferred embodiments of the present invention. Although the above is described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A chip testing system, characterized in that: The chip testing system includes a host computer, an ATE testing device and an SLT testing device; the ATE testing device cooperates with a translation manipulator to complete automatic testing of the chip to be tested; the SLT testing device includes a SAP component, an SLT testing board, a lifting support mechanism, and an SLT testing machine; The SLT test board is a PCB board with restricted layout according to the structural characteristics of the translation manipulator, and the restricted layout at least includes the restricted layout of the SAP component relative to the SLT test board; The SLT test equipment is used to perform system-level testing on the chip to be tested, wherein, during the system-level testing of the SLT test equipment, the upper surface of the SAP component is connected to the translation manipulator, and the lower surface of the SAP component is connected to the SLT test board: The host computer is used to communicate with the translational manipulator through a preset communication interface, and is used to control the movement of the translational manipulator; The translational manipulator is used to control the SAP component to move toward the SLT test machine, place the chip to be tested at a predetermined test point on the SLT test board, and feed back a preparation signal to the host computer; The host computer is further used to send a test instruction to the SLT test equipment when receiving the preparation signal, so that the SLT test equipment performs a system-level test on the chip to be tested at each predetermined test point on the SLT test board; The host computer is also used to receive and display the system-on-chip test results fed back by the SLT test equipment.

2. The chip testing system according to claim 1, characterized in that: During the system-level test, the center position of the upper surface of the SLT test board is attached and fixed to the center position of the lower surface of the SAP component to form a chip test area on the upper surface of the SLT test board; the translation manipulator grabs the SAP component and the SLT test board and moves toward the bottom of the SLT test machine, so that the SLT test board is close to the bottom of the SLT test machine to form an overlapping area of ​​the bottom surface projection of the SLT test machine, and the SLT test board and the bottom of the SLT test machine are separated by a preset height limit distance; wherein the center position of the upper surface of the SLT test board is located within the range of the overlapping area of ​​the bottom surface projection of the SLT test machine; The restricted layout of the SAP component relative to the SLT test board includes the top surface layout restrictions of the SAP component, including: m predetermined test points are arranged along the upper surface of the SAP component, and the m predetermined test points are divided into n rows and arranged in parallel, each row having m / n predetermined test points; the spacing between the predetermined test points in the first direction is a first spacing, and the spacing between the predetermined test points in the second direction is a second spacing, wherein the second direction is perpendicular to the first direction; Among them, the SLT test board is provided with a first surface device layout area on the first side of the chip test area in the second direction, and a second surface device layout area is provided on the second side of the chip test area in the second direction, and the remaining area of ​​the overlapping area of ​​the bottom projection of the SLT test machine except the first surface device layout area and the second surface device layout area is an area where device placement is prohibited.

3. The chip testing system according to claim 2, characterized in that: The chip testing area is provided with an air pipe interface; and the heights of the devices arranged in the first surface device arrangement area and the second surface device arrangement area do not exceed the preset height limit distance.

4. The chip testing system according to claim 2, characterized in that: A temperature sensor is disposed in the area between the first row and the last row of the m predetermined test points, and the temperature sensor is used to obtain the current test temperature.

5. The chip testing system according to claim 2, characterized in that: Transverse fastening screws are arranged around the overlapping area of ​​the bottom projection of the SLT test machine, and the height of the components placed on the periphery of the overlapping area of ​​the bottom projection does not exceed the preset height limit distance.

6. The chip testing system according to claim 2, characterized in that: The restriction layout further includes a screw hole position restriction layout of the SAP component relative to the translation manipulator, and the screw hole position restriction layout includes: Four through screw holes with a first diameter are arranged on the fixture of each predetermined test point of the SAP component, and the through screw holes with a first diameter are used to fix the fixture and the SAP component.

7. The chip testing system according to claim 6, characterized in that: The screw hole position restriction layout includes: Within the chip testing area, through screw holes with a second diameter are respectively arranged in an area away from the predetermined test points in the first row and an area away from the predetermined test points in the last row, and the through screw holes with a second diameter are used to fix the SAP component and the SLT test board.

8. The chip testing system according to claim 6, characterized in that: The first arrangement area and the second arrangement area are provided with through screw holes with a diameter of a third size, and the through screw holes with a diameter of the third size are used to fix the SAP component to the translation manipulator.

9. The chip testing system according to claim 2, characterized in that: The restricted layout of the SAP component relative to the SLT test board also includes the lower surface layout restriction of the SAP component, including a metal area of ​​a test point located at the center of the lower surface of the SAP component, the metal area of ​​the test point is integrated with the m predetermined test points, and the current test temperature of the metal area of ​​the test point needs to be controlled within a preset test temperature range.

10. A chip testing method, characterized in that: The chip testing method is applied to the SLT testing device of the chip testing system as described in any one of claims 1 to 9 above; wherein, the SAP component of the SLT testing device is pre-layout-designed in a preset manner for the upper surface of the SAP component, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component, so that the upper surface of the SAP component, the lower surface of the SAP component, and the positions of the screw holes on the upper surface of the SAP component match the translation manipulator of the ATE testing device of the chip testing system; the chip testing method comprises the following steps: The host computer controls the translational manipulator to move, so that the SAP component moves toward the SLT test machine, places the chip to be tested at a predetermined test point on the SLT test board, and feeds back a preparation signal to the host computer; When receiving the preparation signal, the host computer sends a test instruction to the SLT test equipment, so that the SLT test equipment performs a system-level test on the chip to be tested at each predetermined test point on the SLT test board; The host computer receives and displays the system-on-chip test results fed back by the SLT test equipment.

Images