Method for generating patterning device patterns at segment boundaries

Abstract

Described herein is a method for generating a mask pattern to be used in a patterning process. The method comprises: (P301) obtaining (i) a first feature segment comprising a first polygonal portion of an initial mask pattern and (ii) a second feature segment (P302) comprising a second polygonal portion of the initial mask pattern; adjusting (P303) the second polygonal portion at a segment boundary between the first feature segment and the second component segment such that a difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced; and (P305) combining the first polygonal portion with the adjusted second polygonal portion at the segment boundary to form the mask pattern (330).

Description

[0001] This application is a divisional application of the patent application with application number 2019800869268, whose application entry date in China is June 28, 2021 and whose invention name is “Method for generating a pattern in a pattern forming device at a segment boundary” (international application date is November 18, 2019, and international application number is PCT / EP2019 / 081574), whose applicant is “ASML Netherlands B.V.” and whose application entry date in China is June 28, 2021.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Application No. 62 / 785,981, filed on December 28, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The description herein generally relates to a patterning process and apparatus and methods for determining a pattern of a patterning device corresponding to a design layout. Background Art

[0005] Lithographic projection apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In such cases, a patterning device (e.g., a mask) may contain or provide a pattern corresponding to a single layer of the IC (a "design layout"), and this pattern may be transferred to a target portion (e.g., comprising one or more dies) on a substrate (e.g., a silicon wafer) that has been coated with a layer of radiation-sensitive material ("resist"), such as by irradiating the target portion through the pattern on the patterning device. Typically, a single substrate comprises a plurality of adjacent target portions to which the pattern is sequentially transferred, one target portion at a time, by the lithographic projection apparatus. In this type of lithographic projection apparatus, the pattern on the entire patterning device is transferred to one target portion at a time; such apparatus is often referred to as a stepper. In an alternative apparatus, often referred to as a stepper-scan apparatus, the projection beam is scanned over the patterning device in a given reference direction (the "scanning" direction) while the substrate is synchronously moved parallel or antiparallel to this reference direction. Different portions of the pattern on the patterning device are gradually transferred to one target portion. Typically, since the lithographic projection apparatus will have a reduction ratio M (e.g. 4), the speed F at which the substrate is moved will be 1 / M times the speed at which the projection beam scans the patterning device. More information on lithographic devices as described herein can be gleaned, for example, from US 6,046,792, which is incorporated herein by reference.

[0006] Before the pattern is transferred from the pattern forming device to the substrate, the substrate may undergo various processes, such as priming, resist coating and soft baking. After exposure, the substrate may undergo other processes ("post-exposure processes"), such as post-exposure baking (PEB), development, hard baking and measurement / inspection of the transferred pattern. This array of processes is used as the basis for forming a single layer of a device (e.g., IC). The substrate may then undergo various processes, such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all of which are intended to complete a single layer of the device. If several layers are required in the device, the entire process or its variant is repeated for each layer. Ultimately, the device will be present in each target portion on the substrate. These devices are then separated from each other by techniques such as dicing or sawing, whereby individual devices can be mounted on a carrier, connected to pins, and the like.

[0007] Therefore, manufacturing devices such as semiconductor devices typically involves using multiple manufacturing processes to process a substrate (e.g., a semiconductor wafer) to form various features and multiple layers of the device. Such layers and features are typically manufactured and processed using, for example, deposition, lithography, etching, chemical mechanical polishing, and ion implantation. Multiple devices can be made on multiple dies on a substrate, and the devices are then separated into separate devices. This device manufacturing process can be considered a patterning process. The patterning process involves using a pattern forming device in a lithographic device to transfer a pattern on the pattern forming device to a patterning step of the substrate, such as optical and / or nanoimprint lithography, and the patterning process typically but optionally involves one or more related pattern processing steps, such as resist development by a developing device, baking the substrate using a baking tool, etching using a pattern using an etching device, etc.

[0008] As mentioned, photolithography is a central step in the manufacture of devices such as ICs, where patterns formed on a substrate define the functional elements of the device, such as microprocessors, memory chips, etc. Similar photolithography techniques are also used to form flat panel displays, microelectromechanical systems (MEMS), and other devices.

[0009] As semiconductor manufacturing processes continue to advance, the size of functional elements has been continuously reduced for decades, while the number of functional elements, such as transistors, per device has been steadily increasing, following a trend generally referred to as "Moore's Law." In the current state of the art, the layers of a device are manufactured using a lithography projection apparatus that projects a design layout onto a substrate using illumination from a deep ultraviolet illumination source, thereby forming individual functional elements having dimensions well below 100 nm, i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source).

[0010] This process for printing features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus is often referred to as low-k1 lithography, according to the resolution formula CD=k1×λ / NA, where λ is the wavelength of the radiation employed (currently 248 nm or 193 nm in most cases), NA is the numerical aperture of the projection optics in the lithographic projection apparatus, CD is the "critical dimension" (generally the size of the smallest feature printed), and k1 is an empirical resolution factor. In general, the smaller k1 is, the more difficult it becomes to reproduce a pattern on a substrate that resembles the shape and dimensions planned by the designer in order to achieve specific electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps are applied to the lithographic projection apparatus, the design layout, or the patterning device. These steps include, for example, but are not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase-shifting patterning devices, optical proximity correction (OPC, sometimes also referred to as "optical and process correction") in the design layout, or other methods generally defined as "resolution enhancement techniques" (RET). The term "projection optics" as used herein should be broadly interpreted to cover various types of optical systems, including (for example) refractive optics, reflective optics, apertures, and reflective-refractive optics. The term "projection optics" may also include components that operate according to any of these design types to guide, shape, or control a projection radiation beam, either collectively or individually. The term "projection optics" may include any optical component in a lithographic projection apparatus, regardless of where the optical component is positioned on the optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, adjusting, and / or projecting radiation from a source before it passes through a patterning device, and / or optical components for shaping, adjusting, and / or projecting radiation after it passes through a patterning device. Projection optics generally do not include a source and a patterning device. Summary of the invention

[0011] In an embodiment, a method is provided for determining a mask pattern to be used in a patterning process. The method involves: obtaining (i) a first feature segment, the first feature segment including a first polygonal portion of an initial mask pattern, and (ii) a second feature segment, the second feature segment including a second polygonal portion of the initial mask pattern; adjusting the second polygonal portion at a segment boundary between the first feature segment and the second feature segment so that the difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced; and combining the first polygonal portion and the adjusted second polygonal portion at the segment boundary to form the mask pattern.

[0012] In an embodiment, the initial mask pattern is a design layout comprising a plurality of features to be imaged on a substrate undergoing the patterning process.

[0013] In an embodiment, the first polygonal portion and the second polygonal portion are aspects corresponding to features of the initial mask pattern.

[0014] In an embodiment, the aspect is an assist feature corresponding to the target feature, the assist feature being obtained via optical proximity correction, source optimization, and / or source-mask optimization.

[0015] In an embodiment, the method further involves: adjusting the first polygonal portion located at the segment boundary between the first feature segment and the second feature segment so that the difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced; and determining the mask pattern to include a combination of the adjusted first polygonal portion and the second polygonal portion at the segment boundary.

[0016] In an embodiment, the adjustment of the first polygonal portion and / or the second polygonal portion involves: determining a stitching function configured to seamlessly join the first polygonal portion with the second polygonal portion at the fragment boundary, wherein the stitching function is a mathematical shaping function that reduces the difference between the first polygonal portion and the second polygonal portion at the fragment boundary.

[0017] In an embodiment, the difference between the first polygonal portion and the second polygonal portion is a step or a jump.

[0018] In an embodiment, the stitching function moves the polygon portion of the polygon at the segment boundary to convert the step into a sloped line or a curved line.

[0019] In an embodiment, the stitching function is further configured to include a condition for satisfying a manufacturability check specification related to manufacturability of the mask pattern.

[0020] In an embodiment, the initial mask pattern comprises a plurality of segments arranged in a sequence, each segment having a priority value within the sequence.

[0021] In an embodiment, determining the mask pattern also includes an iterative process, which iteration involves: selecting a fragment with a relatively low priority value within the sequence of the multiple fragments; adjusting a polygonal part within the selected fragment and / or another polygonal part within an adjacent fragment of the selected fragment so that the difference between the polygonal parts is reduced; and generating the mask pattern by combining one or more fragments having the same priority with corresponding adjacent one or more fragments of the multiple fragments.

[0022] In an embodiment, the difference is minimized.

[0023] In an embodiment, the first characteristic segment and the second characteristic segment are adjacent to each other.

[0024] In an embodiment, the initial mask pattern and / or the mask pattern is a curvilinear mask pattern.

[0025] In addition, in an embodiment, a method for reconstructing a level set function of a curve mask pattern is provided, the method involving: obtaining (i) the curve mask pattern and a corresponding threshold, (ii) an initial image, the initial image being presented by the curve mask pattern; and via a processor, iteratively modifying the initial image so that the difference between the interpolated value of the curve mask pattern and the threshold is reduced, thereby generating the level set function of the curve mask pattern.

[0026] In an embodiment, the mask image is a pixelated image comprising a plurality of pixels, each pixel having a pixel value representing a feature of the mask pattern.

[0027] In an embodiment, the generation of the level aggregate function involves: identifying a set of positions along the curved mask pattern; determining an output value of the level aggregate function based on pixel values ​​of pixels at the set of positions within the mask image, wherein the level aggregate function is a mathematical function of the curved mask pattern representing the mask image; determining a total difference between the output value of the level aggregate function and the threshold; and modifying one or more pixel values ​​of pixels of the mask image to reduce the total difference.

[0028] In an embodiment, the mask image is a rendered mask image of the curvilinear mask pattern.

[0029] In an embodiment, the method further involves: obtaining polygons of adjacent fragments in the boundary area for a current fragment, wherein the current fragment and the adjacent fragments are part of the curve mask pattern; reconstructing the level set function of the polygons of the adjacent fragments; determining the function value in the boundary area of ​​the current fragment based on the reconstructed level set function; and adjusting the curve mask pattern of the entire current fragment via an optical proximity effect correction process using the function value.

[0030] In an embodiment, obtaining the plurality of segments involves decomposing the curvilinear mask pattern into a plurality of segments, wherein the contour is split at segment boundaries between adjacent segments.

[0031] Furthermore, in an embodiment, a non-transitory computer program product is provided, the non-transitory computer program product comprising machine-readable instructions for causing a processor to perform the steps of any of the aforementioned methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A block diagram showing various subsystems of a lithography system according to an embodiment is shown.

[0033] Figure 2 A flow chart illustrating a method for simulating at least a portion of a pattern or characteristics of a pattern in an image according to an embodiment.

[0034] Figure 3 is a flow chart of a method for generating a final mask pattern to be used in a patterning process based on a fragment of a design layout / initial mask pattern according to an embodiment.

[0035] Figure 4A and Figure 4B Exemplary rectangular parallelepiped mask patterns and curved line mask patterns according to embodiments are respectively illustrated.

[0036] Figure 5A Graphic reference Figure 4A An exemplary segment of a pattern comprising a first contour portion and a second contour portion.

[0037] Figure 5B Graphic reference Figure 5B An exemplary segment of a pattern comprising a first contour portion and a second contour portion.

[0038] Figure 6 An exemplary stitching curve 620 produced by a stitching function is illustrated.

[0039] Fig. 7A and Figure 7B is a flow chart of a method for reconstructing a level set function of a curvilinear mask pattern.

[0040] Figure 8 is a block diagram of an exemplary computer system according to an embodiment.

[0041] Fig. 9 is a schematic diagram of a lithographic projection apparatus according to an embodiment.

[0042] Fig.10 is a schematic diagram of another lithography projection apparatus according to an embodiment.

[0043] Fig.11 According to the embodiment Fig. 9 A more detailed view of the devices in the

[0044] Fig.12 According to the embodiment Fig.10 and Fig.11 A more detailed view of the source collector module of the device SO. DETAILED DESCRIPTION

[0045] Although specific reference may be made herein to the manufacture of ICs, it should be clearly understood that the description herein has many other possible applications. For example, the description may be used to manufacture integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, etc. Those skilled in the art will appreciate that in the context of such alternative applications, any use of the terms "reticle", "wafer" or "die" herein should be considered interchangeable with the more general terms "mask", "substrate" and "target portion", respectively.

[0046] In this document, the terms "radiation" and "beam" are used to cover all types of electromagnetic radiation, including ultraviolet radiation (e.g., having a wavelength of 365 nm, 248 nm, 193 nm, 157 nm or 126 nm) and EUV (extreme ultraviolet radiation, e.g., having a wavelength in the range of about 5 nm to 100 nm).

[0047] The pattern forming device may include or may form one or more design layouts. The design layout may be generated using a CAD (computer-aided design) process, which is generally referred to as EDA (electronic design automation). Most CAD processes follow a predetermined set of design rules to form a functional design layout / pattern forming device. These rules are set by processing and design constraints. For example, the design rules define the spatial tolerance between devices (such as gates, capacitors, etc.) or interconnects to ensure that the devices or lines do not interact with each other in an undesirable manner. One or more of the design rule constraints may be referred to as a "critical dimension" (CD). The critical dimension of a device may be defined as the minimum width of a line or hole or the minimum space between two lines or two holes. Therefore, the CD determines the overall size and density of the designed device. Of course, one of the goals of device fabrication is to faithfully reproduce the original design intent on the substrate (via a pattern forming device).

[0048] As an example, pattern layout design may include the application of resolution enhancement techniques such as optical proximity correction (OPC). OPC addresses the fact that the final size and placement of the image of the design layout projected on the substrate will be different from or simply dependent on the size and placement of the design layout on the patterning device. It should be noted that the terms "mask", "reticle", and "patterning device" are used interchangeably herein. Similarly, those skilled in the art will recognize that the terms "mask", "patterning device", and "design layout" are used interchangeably, such as in the context of RET, without having to use a physical patterning device, but can use a design layout to represent a physical patterning device. For smaller feature sizes and higher feature densities present on a certain design layout, the position of a particular edge of a given feature will be affected to some extent by the presence or absence of other adjacent features. These proximity effects arise from trace amounts of radiation coupled from one feature to another or non-geometric optical effects such as diffraction and interference. Similarly, proximity effects may arise from diffusion and other chemical effects during post-exposure baking (PEB), resist development, and etching that generally follow lithography.

[0049] To increase the chance that the projected image of the design layout is in accordance with the requirements of a given target circuit design, complex numerical models, corrections, or pre-deformations of the design layout can be used to predict and compensate for proximity effects. The paper "Full-Chip Lithography Simulation and DesignAnalysis - How OPC Is Changing IC Design" (C. Spence, Proc. SPIE, Vol. 5751, pp. 1-14 (2005)) provides an overview of current "model-based" optical proximity correction processes. In a typical high-end design, nearly every feature of the design layout has some kind of modification in order to achieve a high fidelity of the projected image to the target design. These modifications can include shifts or offsets of edge locations or line widths, as well as the application of "helper" features designed to assist the projection of other features.

[0050] One of the simplest forms of OPC is selective biasing. Given the relationship between CD and pitch curves, all different pitches can be forced to produce the same CD by changing the CD at the patterning device level, at least at the best focus and exposure. Therefore, if the feature is printed too small at the substrate level, the patterning device level feature will be biased to be slightly larger than the nominal value, and vice versa. Since the pattern transfer process from the patterning device level to the substrate level is nonlinear, the amount of bias is not just the measured CD error at the best focus and exposure multiplied by the reduction ratio, but the appropriate bias can be determined by modeling and experimentation. In particular, selective biasing is an incomplete solution to the problem of proximity effects when it is only applied under nominal process conditions. Although in principle such a bias can be applied to obtain a uniform relationship between CD and pitch curves at the best focus and exposure, once the exposure process changes from the nominal conditions, each biased pitch curve will respond in a different way, thereby producing different process windows for different features. The process window is the range of values ​​of two or more process parameters (e.g., focus and radiation dose in a lithographic apparatus) over which features are adequately formed (e.g., CD of the feature is within a certain range, such as ±10% or ±5%). Therefore, an "optimal" bias for obtaining the same relationship between CD and pitch may even have a negative impact on the overall process window, thereby reducing (rather than enlarging) the focus and exposure range within which all target features are printed on the substrate within the desired process tolerances.

[0051] Other more complex OPC techniques have been developed for applications beyond the one-dimensional biasing example above. A two-dimensional proximity effect is line end shortening. Line ends have a tendency to "pull back" from their desired endpoint position depending on exposure and focus. In many cases, the degree of shortening of the end of a long line end can be several times greater than the corresponding line narrowing. This type of line end pullback can cause serious failures in the manufactured device when the line end cannot completely cross the underlying layer it is intended to cover (such as, the polysilicon gate layer above the source-drain region). Since this type of pattern is highly sensitive to focus and exposure, it is inappropriate to simply bias the line end to be longer than the designed length, because the line at the best focus and exposure or under exposure conditions will be too long, causing short circuits when the extended line end touches adjacent structures, or causing unnecessary larger circuit sizes when more space is added between individual features in the circuit. Since one of the goals of integrated circuit design and manufacturing is to minimize the area required per chip while maximizing the number of functional elements, adding excess spacing is an undesirable solution.

[0052] Two-dimensional OPC methods can help solve the problem of line end pullback. Additional structures such as "hammerheads" or "serifs" (also known as "auxiliary features") can be added to the line ends to effectively anchor the line ends in place and provide reduced pullback over the entire process window. Even at the best focus and exposure, these additional structures are still not resolved, but these additional structures change the appearance of the main features without being fully resolved themselves. "Main features" as used herein mean features intended to be printed on the substrate under some or all conditions in the process window. Auxiliary features can present a more aggressive form than simple hammerheads added to the line ends to the extent that the pattern on the pattern forming device is no longer simply the desired substrate pattern with the size increased by the reduction ratio. Auxiliary features such as serifs can be applied to more situations, rather than just reducing line end pullback. Inner or outer serifs can be applied to any edge (especially two-dimensional edges) to reduce corner rounding or edge extrusion. With the use of sufficient selective bias and auxiliary features of all sizes and polarities, the features on the pattern forming device have a smaller and smaller similarity to the final pattern expected at the substrate level. Typically, the patterning device pattern becomes a pre-deformed version of the substrate level pattern, where the deformation is intended to counteract or reverse the pattern deformation that will occur during the manufacturing process to produce a pattern on the substrate that is as close as possible to the pattern intended by the designer.

[0053] Instead of or in addition to using those auxiliary features (such as serifs) that are connected to the main features, another OPC technique involves also using completely independent and indistinguishable auxiliary features. The term "independent" here means that the edges of these auxiliary features are not connected to the edges of the main features. These independent auxiliary features are not intended or expected to be printed on the substrate as features, but are intended to modify the aerial image of the nearby main features to enhance the printability and process tolerance of the main features. These auxiliary features (often referred to as "scattering bars" or "SBARs") can include: sub-resolution auxiliary features (SRAFs), which are features outside the edges of the main features; and sub-resolution reverse features (SRIFs), which are features taken from inside the edges of the main features. The presence of SBARs adds another layer of complexity to the pattern forming device pattern. A simple example of the use of scattering bars is where a regular array of indistinguishable scattering bars is drawn on both sides of an isolated line feature, which from an aerial image point of view has the effect of making the isolated line appearance more representative of a single line within a dense array of lines, resulting in a process window with focus and exposure tolerances closer to those of the dense pattern. The common process window between such a decorated isolated feature and the dense pattern will have a greater common tolerance to focus and exposure variations than would be the case if the feature were drawn as isolated at the patterning device level.

[0054] Assist features can be considered the difference between features on the patterning device and features in the design layout.The terms "primary feature" and "assistant feature" do not imply that a particular feature on the patterning device must be labeled as a primary feature or an assist feature.

[0055] The terms "mask" or "patterning device" as used herein may be broadly interpreted as referring to a general patterning device that can be used to impart an incident radiation beam with a patterned cross-section corresponding to the pattern to be formed in a target portion of the substrate; the term "light valve" may also be used in this context. In addition to classical masks (transmissive or reflective; binary, phase-shifting, hybrid, etc.), other examples of such patterning devices include:

[0056] - Programmable mirror arrays. An example of such a device is a matrix-addressable surface with a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is, for example, that addressed areas of the reflective surface reflect incident radiation as diffracted radiation, while unaddressed areas reflect incident radiation as undiffracted radiation. Using appropriate filters, the undiffracted radiation can be filtered out of the reflected beam, leaving only the diffracted radiation; in this way, the beam is patterned according to the addressing pattern of the matrix-addressable surface. Suitable electronics can be used to perform the required matrix addressing.

[0057] - Programmable LCD array. An example of such a configuration is given in US Pat. No. 5,229,872, which is incorporated herein by reference.

[0058] As a brief introduction, Figure 1 An exemplary lithographic projection apparatus 10A is illustrated. The main components are a radiation source 12A, which may be a deep ultraviolet excimer laser source or other types of sources including extreme ultraviolet (EUV) sources (as discussed above, the lithographic projection apparatus itself need not have a radiation source); illumination optics, which, for example, define partial coherence and may include optics 14A, 16Aa, and 16Ab that shape the radiation from source 12A; a patterning device 18A; and transmission optics 16Ac that projects an image of the patterning device pattern onto a substrate plane 22A. An adjustable filter or aperture 20A at a pupil plane of the projection optics may limit the range of beam angles impinging on the substrate plane 22A, where the maximum possible angle defines the numerical aperture NA=n sin(Θmax) of the projection optics, where n is the refractive index of the medium between the substrate and the last element of the projection optics, and Θmax is the maximum angle of the beam emerging from the projection optics that may still impinge on the substrate plane 22A.

[0059] In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device, and projection optics direct and shape the illumination onto a substrate via the patterning device. The projection optics may include at least some of components 14A, 16Aa, 16Ab, and 16Ac. An aerial image (AI) is a distribution of radiation intensity at the substrate level. A resist layer on the substrate is exposed, and the aerial image is transferred to the resist layer to serve as a potential "resist image" (RI) therein. A resist image (RI) may be defined as a spatial distribution of the solubility of the resist in the resist layer. A resist model may be used to calculate a resist image from an aerial image, and an example of this situation may be found in U.S. Patent Application Publication No. US 2009-0157360, the entire disclosure of which is hereby incorporated by reference. The resist model is only related to the properties of the resist layer (e.g., the effects of chemical processes occurring during exposure, PEB, and development). The optical properties of the lithographic projection apparatus (e.g., the properties of the source, the patterning device, and the projection optics) specify the aerial image. Since a patterning device used in a lithographic projection apparatus can be varied, it may be desirable to decouple the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the source and projection optics.

[0060] One aspect of understanding the lithography process is understanding the interaction of radiation with the patterning device. The electromagnetic field of the radiation after it passes through the patterning device can be determined from the electromagnetic field of the radiation before it reaches the patterning device and a function that characterizes the interaction. Such a function can be called a mask transmission function (a mask transmission function can be used to describe the interaction of a transmission patterning device and / or a reflection patterning device).

[0061] The mask transmission function can have a variety of different forms. One form is binary. A binary mask transmission function has either of two values ​​(e.g., zero and a positive constant) at any given position on the pattern forming device. A mask transmission function in binary form may be referred to as a binary mask. Another form is continuous. That is, the modulus of the transmittance (or reflectance) of the pattern forming device is a continuous function of the position on the pattern forming device. The phase of the transmittance (or reflectance) may also be a continuous function of the position on the pattern forming device. A mask transmission function in continuous form may be referred to as a continuous transmission mask (CTM). For example, a CTM may be represented as a pixelated image, where each pixel may be assigned a value between 0 and 1 (e.g., 0.1, 0.2, 0.3, etc.) instead of a binary value of 0 or 1. An exemplary CTM process and its details may be found in commonly assigned U.S. Pat. No. 8,584,056, the disclosure of which is incorporated by reference in its entirety.

[0062] According to an embodiment, the design layout can be optimized as a continuous transmission mask ("CTM optimization"). In such an optimization, the transmission at all positions of the design layout is not limited to multiple discrete values. Alternatively, the transmission can take any value within an upper and lower limit. More details can be found in the commonly assigned U.S. Patent No. 8,584,056, the disclosure of which is hereby incorporated by reference in its entirety. Continuous transmission masks are very difficult (if not impossible) to implement on a pattern forming device. However, since not limiting the transmission to multiple discrete values ​​makes the optimization much faster, continuous transmission masks are useful tools. In EUV lithography projection equipment, the pattern forming device can be reflective. The principles of CTM optimization are also applicable to design layouts to be generated on reflective pattern forming devices, where the reflectivity at all positions of the design layout is not limited to multiple discrete values. Therefore, as used herein, the term "continuous transmission mask" can refer to a design layout to be generated on a reflective pattern forming device or a transmission pattern forming device. CTM optimization can be based on a three-dimensional mask model that takes into account the thick mask effect. Thick mask effects arise from the vector nature of light and may be evident when the feature size on the design layout is smaller than the wavelength of light used in the lithography process. Thick mask effects include: polarization dependence due to different boundary conditions for electric and magnetic fields; transmittance, reflectivity, and phase errors in smaller openings; edge diffraction (or scattering) effects; or electromagnetic coupling. More details of three-dimensional mask models can be found in commonly assigned U.S. Patent No. 7,703,069, the disclosure of which is hereby incorporated by reference in its entirety.

[0063] In an embodiment, assist features (sub-resolution assist features and / or printable resolution assist features) may be placed into a design layout based on a design layout optimized for a continuous transmission mask. This allows assist features to be identified and designed from a continuous transmission mask.

[0064] Figure 2 An exemplary flow chart of a method for modeling and / or simulating a portion of a patterning process is illustrated in FIG. 1 , such as modeling and / or simulating at least a portion of a pattern in an image (e.g., a resist image, an aerial image, an etch image) or a characteristic of a pattern. As will be appreciated, the model may represent different patterning processes and need not include all of the models described below.

[0065] As described above, in a lithographic projection apparatus, an illumination system provides illumination (i.e., radiation) to a pattern forming device, and projection optics direct the illumination from the pattern forming device onto a substrate. Thus, in an embodiment, the projection optics enable the formation of an aerial image (AI), which is a distribution of radiation intensity at the substrate. A resist layer on the substrate is exposed, and the aerial image is transferred to the resist layer as a potential "resist image" (RI) therein. The resist image (RI) can be defined as the spatial distribution of the solubility of the resist in the resist layer. In an embodiment, the simulation of the lithographic process can simulate the generation of an aerial image and / or a resist image.

[0066] The illumination model 31 represents the optical characteristics of the illumination mode (including the radiation intensity distribution and / or the phase distribution) used to produce the patterned radiation beam. The illumination model 31 can represent the optical characteristics of the illumination, including but not limited to: numerical aperture setting, illumination mean square deviation (σ) setting, and any specific illumination mode shape (e.g., off-axis radiation shape, such as toroidal, quadrupole, dipole, etc.), where the mean square deviation (or σ) is the outer radial extent of the illuminator.

[0067] The projection optics model 32 represents the optical properties of the projection optics (including changes in the radiation intensity distribution and / or phase distribution caused by the projection optics). The projection optics model 32 may include optical aberrations caused by various factors, such as heating of components of the projection optics, stress caused by mechanical connections of components of the projection optics, etc. The projection optics model 32 may represent the optical properties of the projection optics, including one or more items selected from the following: aberrations, deformations, refractive index, physical size, physical dimension, absorptivity, etc. The optical properties of the lithographic projection apparatus (e.g., properties of the illumination, pattern forming device pattern, and projection optics) specify the aerial image. Since the pattern forming device pattern used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the pattern forming device pattern from the optical properties of the rest of the lithographic projection apparatus including at least the illumination and projection optics. The illumination model 31 and the projection optics model 32 may be combined into a transmission cross coefficient (TCC) model.

[0068] The patterning device pattern model 33 represents the optical properties (including changes to the radiation intensity distribution and / or phase distribution caused by a given patterning device pattern) of a patterning device pattern (e.g., a device design layout corresponding to features of an integrated circuit, memory, electronic device, etc.), which is a representation of the arrangement of features on or formed by a patterning device. The patterning device model 33 captures how the design features are laid out in the pattern of the patterning device, and may include a representation of the detailed physical properties of the patterning device and patterning device patterns as described, for example, in U.S. Patent No. 7,587,704, which is incorporated herein by reference in its entirety.

[0069] The resist model 37 can be used to calculate the resist image from the aerial image. An example of such a resist model can be found in U.S. Pat. No. 8,200,468, which is incorporated herein by reference in its entirety. The resist model typically describes the effects of chemical processes occurring during resist exposure, post-exposure baking (PEB), and development in order to predict, for example, the profile of resist features formed on the substrate, and therefore it is typically only related to such properties of the resist layer (e.g., the effects of chemical processes occurring during exposure, post-exposure baking, and development). In an embodiment, optical properties of the resist layer such as refractive index, film thickness, propagation, and polarization effects can be captured as part of the projection optics model 32.

[0070] With these models, an aerial image 36 can be simulated from the illumination model 31, the projection optics model 32 and the patterning device pattern model 33. The aerial image (AI) is the radiation intensity distribution at the substrate level. The optical properties of the lithographic projection apparatus (e.g., the properties of the illumination, patterning device and projection optics) dictate the aerial image.

[0071] As mentioned above, the resist layer on the substrate is exposed by an aerial image, and the aerial image is transferred to the resist layer to be in the resist layer as a potential "resist image" (RI). The resist image 38 can be simulated based on the aerial image 36 using a resist model 37. Therefore, in general, the connection between the optical model and the resist model is the simulated aerial image intensity within the resist layer, which originates from the projection of the radiation on the substrate, the refraction at the resist interface, and the multiple reflections in the resist film stack. The radiation intensity distribution (aerial image intensity) is transformed into a potential "resist image" by the absorption of the incident energy, and the potential "resist image" is further modified by diffusion processes and various loading effects. An effective simulation method that is fast enough for full-chip applications approximates the actual 3D intensity distribution in the resist stack through a 2D aerial (and resist) image.

[0072] In an embodiment, the resist image may be used as an input to a post-pattern transfer process model 39. The post-pattern transfer process model 39 defines the performance of one or more post-resist development processes (e.g., etching, CMP, etc.) and may generate a post-etch image 40. That is, the post-pattern transfer process model 39 may be used to simulate an etch image 40 based on the resist image 36.

[0073] Thus, such a model formulation describes most, if not all, of the known physics and chemistry of the overall process, and each of the model parameters desirably corresponds to a different physical or chemical effect. The model formulation thus sets an upper limit on how well the model can be used to simulate the overall manufacturing process.

[0074] For example, the simulation of the patterning process can predict the contour, CD, edge placement (e.g., edge placement error), pattern shift, etc. in the aerial, resist and / or etch images. That is, the characteristics of the pattern (e.g., the presence, location, type, shape, etc. of the pattern) can be determined using the aerial image 34, the resist image 36, or the etch image 40. Therefore, the goal of the simulation is to accurately predict, for example, the edge placement and / or contour of the printed pattern, and / or the pattern shift, and / or the aerial image intensity slope, and / or the CD, etc. These values ​​can be compared to the expected design to, for example, correct the patterning process, identify locations where defects are predicted to occur, etc. The expected design is generally defined as a pre-OPC design layout that can be provided in a standardized digital file format such as GDSII or OASIS or other file formats.

[0075] Techniques and models for converting pattern forming device patterns into various lithographic images (e.g., aerial images, resist images, etc.), and details of using those techniques and models to apply OPC and evaluate performance (e.g., in terms of process windows) are described in U.S. patent application publication numbers US 2008-0301620, 2007-0050749, 2007-0031745, 2008-0309897, 2010-0162197, 2010-0180251, and 2011-0099526, the disclosures of each of which are incorporated herein by reference in their entirety.

[0076] As lithography nodes continue to shrink, more and more complex patterning device patterns (which may be interchangeably referred to as masks for preferred readability) (e.g., curved masks) are required. The present method may be used in critical layers using DUV scanners, EUV scanners, and / or other scanners. The method according to the present disclosure may be included in different aspects of a mask optimization process including source mask optimization (SMO), mask optimization, and / or OPC. For example, a source mask optimization process is described in U.S. Patent No. 9,588,438, entitled "Optimization Flows of Source, Mask and Projection Optics," which is hereby incorporated by reference in its entirety.

[0077] In an embodiment, the pattern forming device pattern is a curved mask including a curved SRAF having a polygonal shape, as opposed to a Manhattan pattern having a rectangular or stepped shape. A curved mask can produce a more accurate pattern on a substrate than a Manhattan pattern. However, the geometry of the curved SRAF, its position relative to the target pattern, or other related parameters may create manufacturing limitations, since such a curved shape may not be suitable for manufacturing. Therefore, designers may not consider such limitations during the mask design process. A detailed discussion of the limitations and challenges in manufacturing curved masks is discussed in Spence et al., "Manufacturing Challenges for Curvilinear Masks" (Proceeding of SPIE Vol. 10451, Photomask Technology, 1045104 (October 16, 2017); doi: 10.1117 / 12.2280470), the entire text of which is incorporated herein by reference.

[0078] In an embodiment, the initial mask pattern used in the method herein may be obtained by a CTM process, a CTM+ process using a level set method on a curve mask based on the initial CTM, a CTM+ process using a sigmoid transform on a curve mask based on the initial CTM, etc. The method is not limited to a specific mask pattern. In particular at segment boundaries, the initial mask is further processed during CTM / CTM+ optimization to incorporate contour modifications according to the present disclosure.

[0079] In an embodiment, a curved mask pattern may be obtained from a continuous transmission mask (CTM+) process (an extension of a CTM process) that employs a level set method to generate a curved shape of an initial mask pattern. An example of a CTM process is discussed in the earlier mentioned U.S. Patent No. 8,584,056. In an embodiment, the CTM+ process involves determining one or more characteristics of the auxiliary features of the initial mask pattern (or the general mask pattern) based on a portion of the auxiliary features or one or more characteristics thereof using any suitable method. For example, one or more characteristics of the auxiliary features may be determined using the method described in U.S. Patent No. 9,111,062, the entire disclosure of which is hereby incorporated by reference, or in "Level-Set-Based Inverse Lithography For Photomask Synthesis" described by Y. Shen et al. (Optics Express, Vol. 17, pp. 23690-23701 (2009)). For example, the one or more characteristics may include one or more geometric characteristics of the auxiliary feature (e.g., absolute position, relative position, or shape), one or more statistical characteristics of the auxiliary feature, or a parameterization of the auxiliary feature. Examples of statistical characteristics of the auxiliary feature may include a mean or variance of a geometric dimension of the auxiliary feature.

[0080] In an example, a CTM image generated by a CTM process can be used to initialize mask variables that can be used as an initial mask pattern (initial image), which is iteratively modified as discussed below with respect to methods 400 and 700 in Figures 4 and 7 discussed later. In the CTM generation technique, the reverse or inverse lithography problem is formulated as an optimization problem. The variables are related to the pixel values ​​in the mask image, and lithography indicators such as EPE or sidelobe printing are used as cost functions. In the iteration of the optimization, a mask image is constructed from the mask image based on the values ​​of the modified mask variables, and then an application model (e.g., a Tachyon model) is applied to obtain an optical or resist image and a cost function is calculated. The cost calculation then gives a gradient value, which is used in an optimization solver to update the variables (e.g., pixel intensity) to obtain a mask image. After several iterations during the optimization, a curve mask image is generated, which is further used as a guidance map for pattern extraction (e.g., as implemented in the Tachyon SMO software). Such a mask image (eg, a CTM image) may include one or more features corresponding to a target pattern to be printed on a substrate via a patterning process (eg, features of the target pattern, SRAF, SRIF, etc.).

[0081] The chip layout is relatively large (e.g., on the order of 10 mm×10 mm), and the chip layout includes millions or even billions of features. The full chip layout cannot be processed on a single computer system or processor because the single processor does not have sufficient processing power to process patterning process-related simulations (e.g., SMO, OPC, etc.) for the full layout. Therefore, the full layout is decomposed into multiple feature fragments, and process simulations (e.g., SMO, OPC, etc.) are performed on separate feature fragments of the multiple feature fragments. The simulation results (e.g., OPC) are combined to determine the simulation results of the entire layout.

[0082] For example, the mask layout can be decomposed into a grid-like pattern, where each rectangular segment of the grid is a fragment. In an embodiment, a feature fragment (also referred to as a fragment) refers to a portion of a mask layout containing one or more features on which OPC-related calculations or simulations can be performed to improve the performance of the patterning process. The OPC simulation of the target feature does not generate or generates one or more auxiliary features and modified main features (e.g., the main feature is the target feature). OPC-related features are represented by polygonal shapes. Therefore, the feature fragment includes a plurality of polygons, wherein the polygon represents the geometric shape of the features (e.g., auxiliary features) of the mask pattern. The term "polygon" is used herein to refer to a feature (e.g., OPC-related or target feature). In an embodiment, the layout may have different sizes (e.g., 50 μm×50 μm, 100 μm×100 μm, 110 μm×110 μm, 50 μm×100 μm, 50 μm×120 μm, 10 mm×10 mm, 50 mm×50 mm, 100 mm×100 mm, etc.) that may be decomposed into multiple segments (e.g., 10 segments, 20 segments, 50 segments, etc.), where each segment may be the same size or a different size (20 μm×20 μm, 20 μm×10 μm, etc.). The present disclosure is not limited to the size of the pattern.

[0083] In an embodiment, a design layout or mask layout may be decomposed based on feature criticality, feature size, feature location, or other grouping properties. The fragments are then distributed across different computers (or processors) for parallel computation or simulation. The simulation results associated with each fragment are then combined to obtain simulation results for the entire chip layout. However, combining the results of adjacent / neighboring fragments (also referred to as stitching) may create problems (e.g., misalignment) at fragment boundaries because the results on either side of the fragment boundary may be different. A fragment boundary refers to a portion of a layout that separates adjacent fragments (e.g., a left fragment and a right fragment). For example, a rectangular feature may be cut or split (e.g., as Figure 5A and Figure 5B) is divided into two parts: a rectangular part included in the left fragment and a second rectangular part included in the second fragment, and the part around the crack is the fragment boundary. A feature or several features can exist completely in the boundary area because the feature or several features are within a certain influence range from the fragment boundary. The influence range of a given fragment is the distance from the fragment boundary, within which the results of the adjacent fragments affect the polygonal shape of the features of the given fragment. For example, for contact layout, the target features are mainly rectangles with a size less than 100 nm, while the influence range of the boundary (or the influence range of the model) can be on the order of microns. Therefore, when generating results for adjacent fragments, the simulation results of the target features in the boundary area of ​​the given fragment can be considered.

[0084] At a fragment boundary shared by two adjacent / neighboring fragments, a polygon of a layout may be cut or split into two parts - a first polygon part included in a first fragment and a second polygon part included in a second fragment. During aspects of simulating a patterning process using the first and second fragments (e.g., OPC), a first feature part (e.g., an auxiliary feature) of the first fragment may be different from a second feature part (e.g., a main feature and an auxiliary feature) of the second fragment at the boundary of the second fragment. Therefore, in an embodiment, information of the first feature part of the first fragment (e.g., a polygon part at a fragment boundary) is used during simulation of the second fragment so that the first fragment and the second fragment can be seamlessly combined. In other words, during the combination or stitching process, the first feature part and the second feature part at the boundary area are modified to be consistent or smoothly blended at the fragment boundary. In an embodiment, a feature part (e.g., OPC) within a fragment that is relatively far from the fragment boundary is intact and unmodified. In an embodiment, the fragment boundary processing process described herein is particularly suitable for generating a curved mask pattern for full chip layout.

[0085] In application, the segment boundary processing method can be integrated with the OPC optimization process (e.g., CTM, CTM+) so that the first feature portion of the first segment is used to generate the second feature portion of the second segment (e.g., auxiliary feature or main feature) at the segment boundary. In other words, the second feature portion of the second segment at the boundary is forced to follow the first feature portion at the segment boundary.

[0086] Figure 3 300 is a flow chart of a method 300 for generating a mask pattern to be used in a patterning process based on a segment. In process P301, method 300 involves: obtaining (i) a first feature segment 301, the first feature segment comprising a first polygonal portion of a mask pattern (e.g., an input pattern or an initial mask pattern); and (ii) a second feature segment 302, the second feature segment comprising a second polygonal portion of the initial mask pattern. Figure 5A and Figure 5B An example of a first characteristic segment including a first polygonal portion 450L / 460L and a second characteristic segment including a second polygonal portion 510 / 570 is illustrated.

[0087] In an embodiment, the initial mask pattern and / or the mask pattern is a straight line pattern or a curved line mask pattern (e.g., the output of a CTM / CTM+ process). In an embodiment, the initial mask pattern is a design layout that includes a plurality of features to be imaged on a substrate undergoing a patterning process. In an embodiment, a first feature segment and a second segment of the initial mask pattern are adjacent to each other. For example, a left segment is adjacent to a right segment separated by a segment boundary 455 / 465, as shown in FIG. Figure 5A and Figure 5B However, adjacent is not limited to left-right, but may also include other adjacent segments, such as the top segment, bottom segment or other side segments of a given segment.

[0088] The first polygonal portion refers to a first portion of one or more features of an initial mask pattern. The second polygonal portion refers to a second portion of a feature of the initial mask pattern. The initial mask pattern may be, for example, a design layout or an intermediate mask pattern generated during a mask optimization or OPC simulation process. According to an embodiment, the polygon is an aspect corresponding to a feature of the initial mask pattern. The aspect may be an auxiliary feature or a modified main feature obtained during a simulation of an optical proximity correction, source optimization, and / or source mask optimization process.

[0089] Figure 4A and 4B An exemplary straight line mask pattern and a curved line mask pattern obtained from an OPC simulation process corresponding to a target feature 410 (also referred to as a master pattern) are shown. Figure 4A In the embodiment of the present invention, the linear mask pattern includes a main mask feature 450 (surrounding the main feature 410), first auxiliary features 451 and 452 surrounding the main mask feature 450. When such a linear mask pattern including features 450, 451 and 452 is used in a patterning process, the printed feature profile 430 is imaged on the substrate. It is desirable that the printed feature 430 closely matches the target feature 410.

[0090] Similarly, in Figure 4B, the curvilinear mask pattern includes a main curvilinear feature 460 (surrounding the main feature 410), first curvilinear auxiliary features 461 and 462 surrounding the main curvilinear feature 460. When used in a patterning process, the curvilinear mask pattern including features 460, 461, and 462 prints a printed feature profile 430' on a substrate. It is desirable that the printed pattern 430' closely matches the target pattern 410. Typically, the printed feature 430' may more closely match the target pattern than the printed feature 430 using a straight mask pattern.

[0091] However, during simulation of aspects of the patterning process (e.g., OPC, mask optimization, etc.), for example, the mask pattern may be split into segments that produce different polygons in the first segment and the second segment. For example, as shown in FIG. 5 a, the left segment includes a first feature segment that includes a first contour portion 450L ( Figure 5B 460L in); and the right segment includes a second characteristic segment, the second characteristic segment includes a second contour portion 510 ( Figure 5B 570 in ). However, the desired contour part should have Figure 4A (4B) shows the shape of 450R (460R). Therefore, in process P303, the portion at the segment boundary 455 (or 465) should be modified or adjusted so that the contour portions are smoothly joined.

[0092] In process P303, the method involves: adjusting the second polygonal portion at the segment boundary between the first feature segment and the second feature segment so that the difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced (in an embodiment, minimized) (e.g., the cost function below). Alternatively or additionally, the process P303 involves: adjusting the first polygonal portion at the segment boundary so that the difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced (in an embodiment, minimized).

[0093] In an embodiment, a cost for mask differences may be used to help approximate the results for neighboring fragments. It can be defined as:

[0094]

[0095] In the above equation, are the weights at different locations (e.g., image pixels), is the pixel value of the current (or considered fragment, e.g. the first fragment) pixel at position i, and is the pixel value of the result of an adjacent fragment (eg, the second fragment) at the same position or within the range of influence. Adjusting includes changing the pixel value such that the cost function is reduced (in an embodiment, minimized).

[0096] In an embodiment, adjusting the first portion and / or the second portion involves: determining a stitching function configured to seamlessly join the first polygonal portion and the second polygonal portion at a segment boundary. The stitching function is a mathematical shaping function that generates a curve between the first polygonal portion and the second polygonal portion based on their corresponding geometric shapes. The curve is generated so that the difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced (e.g., the cost function above).

[0097] For example, the first polygonal portion and the second polygonal portion may be two parallel lines with a spacing (or difference) therebetween. When such polygonal portions are directly joined, there will be a step or abrupt jump between the polygons. In an embodiment, the splicing function moves one or more polygonal portions that are close (e.g., within the range of influence) to the segment boundary to convert the step into a slope or curve. Thus, the splicing function smoothes the difference and connects the result from the left segment to the right segment. For example, the result may include two parallel lines separated by 0.1 nm; the splicing function smoothes such a 0.1 nm step.

[0098] In an embodiment, a polygon may be represented by a set of points placed along the edges of the polygon. Subsequently, the stitching function may be configured to move the points at the boundaries so that the differences between the polygons are reduced and smooth connections are established between the polygons. This smoothing also lends itself to more preferably processing polygons in other subsequent simulations of patterning processes (e.g., optical, resist, etchant, etc.) related to the patterning process.

[0099] Furthermore, abrupt steps of the curved mask pattern at segment boundaries may cause manufacturing difficulties for the mask.Therefore, in an embodiment, the stitching function is further configured to include conditions that satisfy manufacturability check specifications related to the manufacturability of the mask pattern.

[0100] In an embodiment, process P303 is integrated into a CTM+ boundary processing process that modifies the curve pattern so as to improve the performance index. In an embodiment, the boundary processing is part of a CTM or CTM+ optimization process for determining a curve mask pattern and an OPC associated with the mask pattern. In an embodiment, the boundary processing includes modifying certain features or aspects (e.g., OPC) associated therewith at a specific location (e.g., a hot spot) within a segment, while other features or aspects associated therewith are not modified during the CTM process. According to the present disclosure, the boundary processing process is also configured to perform modifications on features at the boundaries of the segment.

[0101] Therefore, in the present disclosure, the boundary processing is limited or restricted to the area around the segment boundary. The boundary processing is based on the formulation of a cost function that makes the baseline image (e.g., Figure 5A and Figure 5B ) with the current image (e.g. Figure 5A and Figure 5B The comparison between the right fragment in the right fragment (in the right fragment) is limited to the fragment boundary area. In other words, features far from the fragment boundary (e.g., hot spots) or uncut or split features close to the fragment boundary will not be modified during the optimization process. Therefore, the results at the boundary of the right fragment are forced to match the results of the left fragment. In an embodiment, the boundary processing includes a stitching function and a corresponding cost term to produce a smooth mask polygon outline across the fragment boundary. Such stitching also involves MRC to be satisfied.

[0102] Figure 6 An exemplary stitching curve 620 generated by the stitching function is shown. Figure 6 , the reference curve polygon is split by a segment boundary 615 into (i) a left polygon portion 610L (dashed line), the left polygon portion being generated by a patterning process (e.g., OPC) that simulates a feature of the left segment; and (ii) a right polygon portion 610R, the right polygon portion being generated by using information from the left segment, particularly the left polygon portion 610L, to simulate a patterning process (e.g., OPC) of the right segment. When processing separate segments, the left segment and the right segment include polygon portions that are smaller but substantially different relative to each other. The stitching function generates a curve 620 to reduce the difference between the polygon portions 610L and 610R. In addition, the right segment result is adjusted by the curve 620. In an embodiment, a portion of the left segment at the segment boundary region may also be adjusted. Therefore, when the left polygon portion 610L and the right polygon portion 610R are combined (e.g., in process P305), a modified feature 620 is obtained as its mask pattern. In an embodiment, the stitching function may be applied exactly at the segment boundary or at a distance from the segment boundary.

[0103] In process P305, the method involves: determining that the mask pattern includes a combination of the first polygonal portion of the feature and the adjusted second polygonal portion at the segment boundary.Alternatively or additionally, the process P305 involves: determining that the mask pattern includes a combination of the adjusted first polygonal portion of the feature and the second polygonal portion at the segment boundary.

[0104] In an embodiment, the method 300 may also be based on the prioritized segments, where the initial mask pattern includes a plurality of segments arranged in a certain sequence, and each segment has a priority value within the sequence (e.g., from 0 to n, where 0 is the highest priority and n is the lowest priority). In addition, the combination of the results of adjacent segments is based on the priority value of each segment.

[0105] In an embodiment, the CTM+ process uses the level set method to generate a curve mask pattern. In the level set method, the contour (the curve mask pattern in the CTM+ process) is traced from the level set where the contour is equal to the threshold. The level set function can be represented as a level set image, and the threshold can be represented as a plane that intersects the level set image, where the contour is traced at the intersection point therebetween. Once the contour is obtained, the original level set image used may not be back-mapped. In other words, since the contour does not have enough information to determine the original level set function, the original level set image used may not be back-mapped.

[0106] Since the contour characterizes the features in the curve mask pattern herein, a mathematical description of such a contour can be defined, for example, based on the level set function. An exemplary level set function representing the curve mask pattern A function having the following properties: (1) Along the contour, each = C, where C is the threshold; (2) Inside the region (e.g., those regions corresponding to the chromium part of the mask), >C; and (3) <C, or outside the region (e.g., those regions corresponding to the transparent quartz part of the mask), <C. In an embodiment, depending on the choice of reference, the inequality signs in (2) and (3) may be reversed.

[0107] The contour is defined by a "level set" (i.e., a set of points in the (x,y) plane) where = C. In an embodiment, the level set function can be represented as a pixelated image, where some pixels have pixel values corresponding to the contour. Thus, the threshold corresponds to the pixel value defining the contour. In an embodiment, the optimization involves adjusting such pixel values at the segment boundaries based on a cost function that reduces the difference of the polygon part as described above.

[0108] In an aspect of the present invention, it is found that the level set function for deriving the target pattern , such that the level set = C defines a set of contours or polygons that, when interpreted as a mask pattern of features at the boundaries, produces a wafer pattern with very small deformations and artifacts compared to the target pattern. The wafer pattern is produced by a lithography process using the mask pattern obtained in this paper. The optimization is calculated based on the performance index by the level set function The degree to which the set of contours is defined, such as to reduce the difference in edge placement error between the predicted wafer pattern and the target pattern.

[0109] Given a curve mask polygon p (or contour), we want to reconstruct e.g. an image that is approximately the level set function / image of polygon p , which means that with the image The corresponding polygon is very close to the original polygon, . Here C is the threshold for contour tracing.

[0110]

[0111] In the embodiments, reference Fig. 7A , an exemplary method 700 of reconstructing a level set function of a contour of a curved mask pattern is provided. In other words, an input level set image is generated from a reverse mapping (not discussed rigorously) of the contour. The method 700 can be used to generate an image to initialize CTM+ optimization in regions near segment boundaries.

[0112] In process P701, the method involves: obtaining (i) a curved mask pattern 701 and a threshold value C, (ii) an initial image 702, such as a mask image rendered by the curved mask pattern 701. In an embodiment, the mask image 702 is a pixelated image including a plurality of pixels, each pixel having a pixel value representing a feature of the mask pattern. The image 702 may be a rendered mask image of the curved mask pattern 701.

[0113] In process P703, the method involves: via a processor (e.g., processor 104), by iteratively modifying the image pixels so that the difference between the interpolated value and the threshold at each point of the curve mask pattern is reduced, thereby generating a level set function. This can be represented by a cost function given as follows:

[0114]

[0115] In an embodiment, generation of a level set function involves identifying a set of positions along a curved mask pattern, determining a level set function value using pixel values ​​of an initial image interpolated at the set of positions, calculating the difference between the value and a threshold C and modifying one or more pixel values ​​of pixels of the image so as to reduce the difference (e.g., the cost function f above).

[0116] In an embodiment, the method 700 can be further extended in the boundary processing of the curve mask, as shown in Figure 7b. In process P710, for the current segment, the final result of the adjacent segments is obtained as the priority polygon in the boundary area. In addition, as in process P703, process P712 involves calculating the level set image of the priority polygon. Process P714 involves determining the image value of the boundary area based on the reconstructed level set image. And another optical proximity effect correction 750 (for example, using CTM / CTM+) optimizes the mask of the entire current segment (including the boundary area).

[0117] Figure 8 1 is a block diagram illustrating a computer system 100 that can assist in implementing the methods, processes, or apparatus disclosed herein. The computer system 100 includes a bus 102 or other communication mechanism for communicating information and a processor 104 (or multiple processors 104 and 105) coupled to the bus 102 for processing information. The computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 102 for storing information and instructions to be executed by the processor 104. The main memory 106 can also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 104. The computer system 100 also includes a read-only memory (ROM) 108 or other static storage device coupled to the bus 102 for storing static information and instructions for the processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to the bus 102 for storing information and instructions.

[0118] The computer system 100 can be coupled by bus 102 to a display 112 for displaying information to a computer user, such as a cathode ray tube (CRT) or a flat panel display or a touch panel display. An input device 114 including alphanumeric keys and other keys is coupled to bus 102 for communicating information and command selections to processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to processor 104 and for controlling cursor movement on display 112. Such an input device typically has two degrees of freedom on two axes (a first axis (e.g., x) and a second axis (e.g., y)), which allow the device to specify a position in a plane. A touch panel (screen) display can also be used as an input device.

[0119] According to one embodiment, portions of one or more methods described herein may be performed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. Such instructions may be read from another computer-readable medium (such as storage device 110) into main memory 106. Execution of the sequence of instructions contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequence of instructions contained in main memory 106. In alternative embodiments, hard-wired circuits may be used instead of or in combination with software instructions. Therefore, the description herein is not limited to any specific combination of hardware circuitry and software.

[0120] As used herein, the term "computer-readable medium" refers to any medium that participates in providing instructions to the processor 104 for execution. Such media can be in many forms, including (but not limited to) non-volatile media, volatile media, and transmission media. Non-volatile media include (for example) optical disks or magnetic disks, such as storage devices 110. Volatile media include volatile memories, such as main memory 106. Transmission media include coaxial cables, copper wires, and optical fibers, including wires containing bus 102. Transmission media can also take the form of sound waves or light waves, such as sound waves or light waves generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include (for example) floppy disks, floppy disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, DVDs, any other optical media, punch cards, paper tapes, any other physical media with hole patterns, RAM, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cartridges, carriers as described below, or any other media that can be read by a computer.

[0121] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to the processor 104 for execution. For example, the instructions may be initially carried on a disk of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions via a telephone line using a modem. A modem local to the computer system 100 may receive data on the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector coupled to the bus 102 may receive the data carried in the infrared signal and place the data on the bus 102. The bus 102 carries the data to the main memory 106, from which the processor 104 retrieves and executes the instructions. The instructions received by the main memory 106 may optionally be stored on the storage device 110 before or after being executed by the processor 104.

[0122] The computer system 100 may also include a communication interface 118 coupled to the bus 102. The communication interface 118 provides a bidirectional data communication coupling to a network link 120, which is connected to a local area network 122. For example, the communication interface 118 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection with a corresponding type of telephone line. As another example, the communication interface 118 may be a local area network (LAN) card to provide a data communication connection with a compatible LAN. A wireless link may also be implemented. In any such embodiment, the communication interface 118 sends and receives electrical, electromagnetic, or optical signals carrying digital data streams representing various types of information.

[0123] The network link 120 typically provides data communications to other data devices via one or more networks. For example, the network link 120 may provide a connection to a host computer 124 or to data devices operated by an Internet Service Provider (ISP) 126 via a local area network 122. The ISP 126 in turn provides data communication services via a global packet data communications network, now commonly referred to as the "Internet" 128. Both the local area network 122 and the Internet 128 use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on the network link 120 and through the communication interface 118 are exemplary forms of carrier waves that transport the information, carrying the digital data to and from the computer system 100.

[0124] The computer system 100 can send messages and receive data including program code via one or more networks, network link 120, and communication interface 118. In the Internet example, server 130 can transmit the requested code for the application via Internet 128, ISP 126, local area network 122, and communication interface 118. For example, one such downloaded application can provide all or part of the methods described herein. The received code can be executed by processor 104 when it is received, and / or stored in storage device 110 or other non-volatile storage for later execution. In this way, computer system 100 can obtain application code in the form of a carrier wave.

[0125] Fig. 9 An exemplary lithographic projection apparatus incorporating the techniques described herein that may be utilized is schematically depicted. The apparatus comprises:

[0126] - an illumination system IL, said illumination system being used to condition the radiation beam B. In such a particular case, the illumination system also comprises a radiation source SO;

[0127] - a first object table (eg patterning device table) MT having a patterning device holder for holding a patterning device MA (eg a reticle) and connected to a first positioner for accurately positioning the patterning device relative to the item PS;

[0128] - a second object table (substrate table) WT provided with a substrate holder for holding a substrate W (e.g. a silicon wafer coated with resist) and connected to a second positioner for accurately positioning the substrate relative to the item PS;

[0129] - a projection system ("lens") PS (eg a refractive, reflective or catadioptric optical system) for imaging the irradiated portion of the patterning device MA onto a target portion C of the substrate W (eg comprising one or more dies).

[0130] As depicted herein, the device is of the transmissive type (i.e., has a transmissive patterning device). However, in general, for example, the device may also be of the reflective type (have a reflective patterning device). The device may employ a different kind of patterning device than a classical mask; examples include a programmable mirror array or an LCD matrix.

[0131] A source SO (e.g. a mercury lamp or an excimer laser, an LPP (laser produced plasma) EUV source) generates a radiation beam. This beam is fed into an illumination system (illuminator) IL, for example directly or after having traversed an adjustment device such as a beam expander Ex. The illuminator IL may comprise an adjustment device AD ​​for setting the outer radial extent and / or the inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, the illuminator IL will typically comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam B incident on the patterning device MA has a desired uniformity and intensity distribution in its cross section.

[0132] about Fig. 9 It should be noted that the source SO can be within the housing of the lithographic projection apparatus (which is often the case when the source SO is, for example, a mercury lamp), but it can also be remote from the lithographic projection apparatus, into which the radiation beam generated by the lithographic projection apparatus is directed (for example, with the aid of suitable directing mirrors); this latter situation is often the case when the source SO is an excimer laser (for example, based on KrF, ArF or F2 laser action).

[0133] The beam PB then intercepts the patterning device MA which is held on the patterning device table MT. Having traversed the patterning device MA, the beam B passes through a lens PL which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning device (and the interferometry device IF) the substrate table WT can be accurately moved, for example, so that a different target portion C is positioned in the path of the beam PB. Similarly, the first positioning device can be used to accurately position the patterning device MA relative to the path of the beam B, for example after mechanical acquisition of the patterning device MA from a patterning device library or during scanning. Typically, the patterning device MA will be accurately positioned with the aid of the second positioning device (and the interferometry device IF) which is not in the path of the beam PB. Fig. 9 Movement of the object tables MT, WT is achieved by a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) explicitly depicted in FIG. 2. However, in the case of a stepper (as opposed to a step-and-scan tool), the patterning device table MT may be connected to the short-stroke actuator only, or may be fixed.

[0134] The Paint tool can be used in two different modes:

[0135] - in step mode, the patterning device table MT is kept substantially stationary and the entire patterning device image is projected at once (i.e. a single "flash") onto a target portion C. The substrate table WT is subsequently shifted in the x and / or y direction so that a different target portion C can be irradiated by the beam PB;

[0136] - In scan mode, essentially the same situation applies, except that a given target portion C is not exposed in a single "flash". Alternatively, the patterning device table MT can be moved in a given direction (the so-called "scanning direction", e.g. the y-direction) at a speed v, so as to cause the projection beam B to scan across the patterning device image; simultaneously with the simultaneous movement of the substrate table WT in the same or opposite direction at a speed V=Mv, where M is the magnification of the lens PL (typically M=1 / 4 or =1 / 5). In this way, a relatively large target portion C can be exposed without having to compromise resolution.

[0137] Fig.10 Another exemplary lithographic projection apparatus 1000 that may be utilized in conjunction with the techniques described herein is schematically depicted.

[0138] The lithography projection apparatus 1000 comprises:

[0139] - Source collector module SO;

[0140] - an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. EUV radiation);

[0141] - a support structure (e.g. patterning device table) MT configured to support a patterning device (e.g. mask or reticle) MA and connected to a first positioner PM configured to accurately position the patterning device;

[0142] - a substrate table (eg wafer stage) WT configured to hold a substrate (eg resist coated wafer) W and connected to a second positioner PW configured to accurately position the substrate; and

[0143] - a projection system (eg a reflective projection system) PS configured to project the pattern imparted to the radiation beam B by the patterning device MA onto a target portion C of the substrate W (eg comprising one or more dies).

[0144] As depicted here, the apparatus 1000 is of the reflective type (e.g., employing a reflective patterning device). It should be noted that since most materials are absorptive in the EUV wavelength range, the patterning device can have a multilayer reflector comprising, for example, multiple overlapping layers of molybdenum and silicon. In one example, the multiple overlapping layer reflector has 40 layer pairs of molybdenum and silicon, where each layer is a quarter wavelength thick. Even smaller wavelengths can be produced by x-ray lithography. Since most materials are absorptive at EUV and x-ray wavelengths, a thin piece of patterned absorbing material on the patterning device topography (e.g., a TaN absorber on top of a multilayer reflector) defines where features will be printed (positive resist) or where they will not be printed (negative resist).

[0145] refer to Fig.10 , the illuminator IL receives a beam of extreme ultraviolet radiation from a source collector module SO. Methods for generating EUV radiation include, but are not necessarily limited to, converting a material into a plasma state having at least one element (e.g., xenon, lithium, or tin) through one or more emission lines in the EUV range. In one such method, often referred to as laser produced plasma ("LPP"), a plasma may be generated by irradiating a fuel (e.g., a droplet, stream, or cluster of material having the line emitting element) with a laser beam. The source collector module SO may be a laser ( Fig.10 The laser is used to provide a laser beam for exciting the fuel. The resulting plasma emits output radiation, such as EUV radiation, which is collected using a radiation collector disposed in a source collector module. For example, when a CO2 laser is used to provide a laser beam for fuel excitation, the laser and the source collector module may be separate entities.

[0146] In such cases, the laser is not considered to form part of the lithographic apparatus, and the radiation beam is delivered from the laser to the source collector module by means of a beam delivery system comprising, for example, suitable directing mirrors and / or a beam expander. In other cases, for example, when the source is a discharge produced plasma EUV generator (often referred to as a DPP source), the source may be an integral part of the source collector module.

[0147] The illuminator IL may include an adjuster for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer radial extent and / or the inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. In addition, the illuminator IL may include various other components, such as a faceted field mirror arrangement and a faceted pupil mirror arrangement. The illuminator may be used to adjust the radiation beam to have a desired uniformity and intensity distribution in its cross-section.

[0148] The radiation beam B is incident on a patterning device (e.g. a mask) MA held on a support structure (e.g. a patterning device table) MT and is patterned by the patterning device. After reflection from the patterning device (e.g. a mask) MA, the radiation beam B passes through a projection system PS which focuses the beam onto a target portion C of a substrate W. With the aid of a second positioner PW and a position sensor PS2 (e.g. an interferometric device, a linear encoder or a capacitive sensor), the substrate table WT can be accurately moved, for example, so that a different target portion C is positioned in the path of the radiation beam B. Similarly, a first positioner PM and a further position sensor PS1 can be used to accurately position the patterning device (e.g. a mask) MA relative to the path of the radiation beam B. The patterning device (e.g. a mask) MA and the substrate W can be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2.

[0149] The depicted device 1000 may be used in at least one of the following modes:

[0150] 1. In step mode, the support structure (e.g. patterning device table) MT and substrate table WT are kept substantially stationary (i.e. a single static exposure) while the entire pattern imparted to the radiation beam is projected at one time onto a target portion C. The substrate table WT is subsequently shifted in the X and / or Y direction so that a different target portion C can be exposed.

[0151] 2. In scan mode, the support structure (e.g. patterning device table) MT and substrate table WT are scanned synchronously (i.e. single dynamic exposure) as a pattern imparted to the radiation beam is projected onto a target portion C. The velocity and direction of the substrate table WT relative to the support structure (e.g. patterning device table) MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS.

[0152] 3. In another mode, the support structure (e.g. patterning device table) MT holding the programmable patterning device is kept substantially stationary and the substrate table WT is moved or scanned while a pattern imparted to the radiation beam is projected onto a target portion C. In such a mode, a pulsed radiation source is typically employed and the programmable patterning device is updated as required after each movement of the substrate table WT or between successive radiation pulses during a scan. This mode of operation may be readily applicable to maskless lithography using a programmable patterning device such as a programmable mirror array of the type mentioned above.

[0153] Fig.11 The apparatus 1000 is shown in more detail and includes a source collector module SO, an illumination system IL, and a projection system PS. The source collector module SO is constructed and arranged so that a vacuum environment can be maintained in an enclosure 220 of the source collector module SO. An EUV radiation emitting plasma 210 can be formed by a discharge-generated plasma source. EUV radiation can be generated by a gas or vapor (e.g., Xe gas, Li vapor, or Sn vapor) in which a very hot plasma 210 is formed to emit radiation in the EUV range of the electromagnetic spectrum. For example, the very hot plasma 210 is formed by a discharge that produces an at least partially ionized plasma. For efficient generation of radiation, Xe, Li, Sn vapor, or any other suitable gas or vapor may be required with a partial pressure of, for example, 10 Pa. In an embodiment, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0154] The radiation emitted by the hot plasma 210 is transferred from the source chamber 211 to the collector chamber 212 via an optional gas barrier or contaminant trap 230 (also referred to as a contaminant barrier or foil trap in some cases) positioned in or behind an opening in the source chamber 211. The contaminant trap 230 may include a channel structure. The contaminant trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. As known in the art, the contaminant trap or contaminant barrier 230 further indicated herein includes at least a channel structure.

[0155] The collector chamber 211 may include a radiation collector CO which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation traversing the collector CO may be reflected from the grating spectral filter 240 to be focused into a virtual source point IF along the optical axis indicated by the dotted line "O". The virtual source point IF is often referred to as an intermediate focus, and the source collector module is arranged so that the intermediate focus IF is located at or near an opening 221 in the enclosure structure 220. The virtual source point IF is an image of the radiation emitting plasma 210.

[0156] The radiation then traverses an illumination system IL which may include a faceted field mirror arrangement 22 and a faceted pupil mirror arrangement 24 arranged to provide a desired angular distribution of the radiation beam 21 at the patterning device MA, and a desired uniformity of the radiation intensity at the patterning device MA. Upon reflection of the radiation beam 21 at the patterning device MA held by the support structure MT, a patterned beam 26 is formed, and the patterned beam 26 is imaged by the projection system PS via reflective elements 28, 30 onto a substrate W held by a substrate table WT.

[0157] There may generally be more elements present in the illumination optics unit IL and the projection system PS than those shown. Depending on the type of lithographic apparatus, a grating spectral filter 240 may optionally be present. Furthermore, there may be more mirrors than shown in the figures, for example, there may be more than 200 mirrors in the projection system PS. Fig.11 The reflective elements shown in the figure may have 1 to 6 additional reflective elements.

[0158] Just as an example of a collector (or collector reflector), Fig.11 The collector optics CO illustrated in FIG. 5 is depicted as a nested collector with grazing incidence reflectors 253, 254 and 255. The grazing incidence reflectors 253, 254 and 255 are arranged axially symmetrically around the optical axis O, and this type of collector optics CO can be used in combination with a discharge produced plasma source, often referred to as a DPP source.

[0159] Alternatively, the source collector module SO may be as follows Fig.12 . The laser LA is arranged to deposit laser energy into a fuel such as xenon (Xe), tin (Sn) or lithium (Li), thereby forming a highly ionized plasma 210 with an electron temperature of several 10 eV. The high-energy radiation generated during the deexcitation and recombination of these ions is emitted from the plasma, collected by the near normal incidence collector optics CO, and focused onto an opening 221 in the enclosure structure 220.

[0160] The embodiments may be further described using the following aspects:

[0161] 1. A method for determining a mask pattern to be used in a patterning process, the method comprising:

[0162] Obtaining (i) a first feature segment and (ii) a second feature segment, wherein the first feature segment includes a first polygonal portion of an initial mask pattern and the second feature segment includes a second polygonal portion of the initial mask pattern;

[0163] adjusting the second polygonal portion located at a segment boundary between the first feature segment and the second feature segment so that a difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced; and

[0164] The first polygonal portion is combined with the adjusted second polygonal portion at the segment boundary to form the mask pattern.

[0165] 2. The method of clause 1, wherein the initial mask pattern is a design layout comprising a plurality of features to be imaged on a substrate undergoing the patterning process.

[0166] 3. The method according to any one of aspects 1 to 2, wherein the first polygonal portion and the second polygonal portion are aspects corresponding to features of the initial mask pattern.

[0167] 4. The method according to aspect 3, wherein the aspect is an auxiliary feature corresponding to the target feature, the auxiliary feature being obtained via optical proximity effect correction, source optimization and / or source mask optimization.

[0168] 5. The method according to any one of aspects 1 to 4, further comprising:

[0169] adjusting the first polygonal portion located at the segment boundary between the first feature segment and the second feature segment so that the difference between the first polygonal portion and the second polygonal portion at the segment boundary is reduced; and

[0170] The mask pattern is determined to include a combination of the adjusted first polygonal portion and the second polygonal portion at the segment boundary.

[0171] 6. The method according to any one of aspects 1 to 5, wherein the adjusting of the first polygonal portion and / or the second polygonal portion comprises:

[0172] A stitching function configured to seamlessly join the first polygonal portion and the second polygonal portion at the segment boundary is determined, wherein the stitching function is a mathematically shaped function that reduces the difference between the first polygonal portion and the second polygonal portion at the segment boundary.

[0173] 7. A method according to aspect 6, wherein the difference between the first polygonal portion and the second polygonal portion is a step or a jump.

[0174] 8. The method of clause 7, wherein the stitching function moves the polygon portion of the polygon at the fragment boundary to convert the step into a sloped line or a curved line.

[0175] 9. The method according to any one of clauses 6 to 8, wherein the stitching function is further configured to include a condition for satisfying a manufacturability check specification related to manufacturability of the mask pattern.

[0176] 10. The method of any one of clauses 1 to 9, wherein the initial mask pattern comprises a plurality of segments arranged in a sequence, each segment having a priority value within the sequence.

[0177] 11. The method according to any one of aspects 1 to 10, wherein determining the mask pattern further comprises an iterative process, the iteration comprising:

[0178] selecting a fragment having a relatively lower priority value within said sequence of said plurality of said fragments;

[0179] adjusting a polygonal portion within the selected segment and / or another polygonal portion within a segment adjacent to the selected segment such that the difference between the polygonal portions is reduced; and

[0180] The mask pattern is generated by combining one or more segments having the same priority with corresponding adjacent one or more segments of the plurality of segments.

[0181] 12. A method according to any one of aspects 1 to 11, wherein the difference is minimized.

[0182] 13. The method according to any one of aspects 1 to 12, wherein the first feature segment and the second feature segment are adjacent to each other.

[0183] 14. The method according to any one of aspects 1 to 13, wherein the initial mask pattern and / or the mask pattern is a curvilinear mask pattern.

[0184] 15. A method for reconstructing a level set function of a curved mask pattern, the method comprising:

[0185] obtaining (i) the curved mask pattern and a corresponding threshold, and (ii) an initial image represented by the curved mask pattern; and

[0186] The level set function of the curvilinear mask pattern is generated by iteratively modifying the initial image via a processor so that a difference between an interpolated value of the curvilinear mask pattern and the threshold value decreases.

[0187] 16. A method according to clause 15, wherein the mask image is a pixelated image comprising a plurality of pixels, each pixel having a pixel value representing a feature of the mask pattern.

[0188] 17. The method according to any one of aspects 15 to 16, wherein the generating of the level aggregate function comprises:

[0189] identifying a set of locations along the curvilinear mask pattern;

[0190] determining an output value of the level set function based on pixel values ​​of pixels corresponding to the set of locations within the mask image, wherein the level set function is a mathematical function representing the curvilinear mask pattern of the mask image;

[0191] determining a total difference between the output value of the level aggregate function and the threshold value; and

[0192] One or more pixel values ​​of pixels of the mask image are modified to reduce the total difference.

[0193] 18. A method according to any one of clauses 15 to 17, wherein the initial mask pattern is a rendered mask image of the curvilinear mask pattern.

[0194] 19. The method according to any one of aspects 15 to 18, further comprising:

[0195] For a current fragment, obtaining polygons of adjacent fragments in the boundary region, wherein the current fragment and the adjacent fragments are parts of the curved mask pattern;

[0196] reconstructing the level set functions of the polygons of the adjacent fragments;

[0197] determining a function value in the boundary region of the current segment based on the reconstructed level set function; and

[0198] The curvilinear mask pattern throughout the current segment is adjusted via an optical proximity effect correction process employing the function value.

[0199] 20. The method of aspect 19, wherein obtaining the plurality of fragments comprises:

[0200] The curvilinear mask pattern is decomposed into a plurality of segments, wherein the curvilinear mask pattern is split at segment boundaries between adjacent segments.

[0201] 21. A non-transitory computer program product comprising machine-readable instructions for causing a processor to perform the method according to any one of aspects 1 to 20.

[0202] The concepts disclosed herein can simulate or mathematically model any general imaging system for imaging sub-wavelength features, and can be particularly useful for emerging imaging technologies that can produce shorter and shorter wavelengths. Emerging technologies already in use include EUV (extreme ultraviolet), DUV lithography that can produce 193 nm wavelengths by using ArF lasers and even 157 nm wavelengths by using fluorine lasers. In addition, EUV lithography can produce wavelengths in the range of 20 nm to 5 nm by using a synchrotron or by firing high-energy electrons at a material (either solid or plasma) to produce photons in this range.

[0203] Although the concepts disclosed herein may be used for imaging on substrates such as silicon wafers, it should be understood that the disclosed concepts may be used with any type of lithography imaging system, for example, a lithography imaging system for imaging on substrates other than silicon wafers.

[0204] The above description is intended to be illustrative, rather than restrictive. Therefore, it will be appreciated by those skilled in the art that modifications may be made in the manner as described without departing from the scope of the claims set forth hereinafter.

Claims

1. A method for reconstructing a level set function of a curved mask pattern, the method comprising: Obtaining (i) the curved mask pattern and a corresponding threshold, and (ii) an initial image represented by the curved mask pattern; as well as The level set function of the curvilinear mask pattern is generated by iteratively modifying the initial image via a processor so that a difference between an interpolated value of the curvilinear mask pattern and the threshold value decreases.

2. The method according to claim 1, wherein: The mask image is a rendered mask image of the curvilinear mask pattern.

3. The method according to claim 2, wherein: The mask image is a pixelated image including a plurality of pixels, each pixel having a pixel value representing a feature of the mask pattern.

4. The method of claim 2, wherein the generating of the level aggregate function comprises: identifying a set of locations along the curvilinear mask pattern; determining an output value of the level set function based on pixel values ​​of pixels corresponding to the set of locations within the mask image, wherein the level set function is a mathematical function representing the curvilinear mask pattern of the mask image; determining a total difference between the output value of the level aggregate function and the threshold value; and One or more pixel values ​​of pixels of the mask image are modified to reduce the total difference.

5. The method according to any one of claims 1 to 4, further comprising: For a current fragment, obtaining polygons of adjacent fragments in a boundary region, wherein the current fragment and the adjacent fragments are parts of the curved mask pattern; reconstructing the level set functions of the polygons of the adjacent fragments; determining a function value in the boundary region of the current segment based on the reconstructed level set function; and The curvilinear mask pattern throughout the current segment is adjusted via an optical proximity effect correction process employing the function value.

6. The method according to claim 5, wherein: Obtaining polygons of neighboring fragments in the boundary region involves: The curvilinear mask pattern is decomposed into a plurality of segments, wherein the curvilinear mask pattern is split at segment boundaries between adjacent segments.

7. The method according to claim 1, wherein: The curvilinear mask pattern further includes a main curvilinear feature and curvilinear auxiliary features surrounding the main curvilinear feature.

8. The method according to claim 1, further comprising: The curvilinear mask pattern is modified by a boundary processing process to improve performance metrics, wherein the boundary processing process is limited or confined to regions surrounding segment boundaries.

9. The method according to claim 5, further comprising: For the current fragment, obtain the final result of the neighboring fragments as the priority polygon in the boundary area.

10. A non-transitory computer program product comprising machine-readable instructions for causing a processor to perform the method according to any one of claims 1 to 9.

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