Error compensation determination method, semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides an error compensation determination method, a semiconductor structure and a manufacturing method of the semiconductor structure, and the error compensation determination method is applied to the manufacturing process of the semiconductor structure. The semiconductor structure comprises a substrate, at least two measurement photoetching layers formed on the substrate and alignment photoetching layers formed on the sides, away from the substrate, of the measurement photoetching layers. The error compensation determination method comprises the following steps: giving a measurement compensation weight to measurement error compensation of each measurement photoetching layer according to a process window corresponding to each measurement photoetching layer; the measurement compensation weight is determined according to the ratio of the process window corresponding to one measurement photoetching layer to the process windows corresponding to all measurement photoetching layers; and performing weighted summation on the measurement error compensation of the at least two measurement photoetching layers, and taking a weighted summation result as the measurement alignment error compensation of the alignment photoetching layer. According to the embodiment of the invention, the compensation capability of measurement alignment error compensation is improved, and the alignment precision between different photoetching layers is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a method for determining error compensation, a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As semiconductor devices develop towards high integration and miniaturization, multiple photolithography layers with different photolithography patterns may need to be superimposed during semiconductor processing to achieve multiple exposures of different photolithography patterns on the same wafer. In order to improve the performance of highly integrated semiconductor devices, multiple photolithography layers need to be precisely aligned.

[0003] The alignment accuracy between multiple lithography layers can be measured by the overlay (OVL) error. Specifically, in a multi-layer lithography process, the overlay error can be the alignment error of the lithography layer being processed relative to the lithography layer that has been processed. In order to meet the alignment accuracy requirements of advanced process technology, the overlay error needs to be compensated.

[0004] In the prior art, overlay error compensation is usually determined based on measurement alignment error compensation and process alignment error compensation. However, researchers have found that in the process of processing some special semiconductor structures, applying the overlay error compensation determined by the existing method to the photolithography layer being processed still cannot make the processed semiconductor structure meet the alignment accuracy requirements. Summary of the invention

[0005] In view of this, multiple embodiments of the present application provide a method for determining error compensation, a semiconductor structure and a manufacturing method thereof, so as to improve the alignment accuracy during the manufacturing process of the semiconductor structure.

[0006] In one aspect, an embodiment of the present application provides a method for determining error compensation, which is applied to a manufacturing process of a semiconductor structure; the semiconductor structure includes a substrate, at least two measurement lithography layers formed on the substrate, and an alignment lithography layer formed on a side of the measurement lithography layer away from the substrate; the method includes: according to the process window corresponding to each of the measurement lithography layers, assigning a measurement compensation weight to the measurement error compensation of each of the measurement lithography layers; wherein the measurement compensation weight is determined according to the ratio of the process window corresponding to one of the measurement lithography layers to the process windows corresponding to all of the measurement lithography layers; performing a weighted summation on the measurement error compensations of the at least two measurement lithography layers, and using the weighted summation result as the measurement alignment error compensation of the alignment lithography layer.

[0007] Optionally, the measurement compensation weight corresponding to each of the measurement photolithography layers is negatively correlated with the size of the process window corresponding to each of the measurement photolithography layers.

[0008] Optionally, the semiconductor structure is manufactured according to a structural coordinate system; wherein the structural coordinate system includes a first direction and a second direction perpendicular to each other; accordingly, the process window includes a first process window along the first direction and a second process window along the second direction; the measurement error compensation includes a first measurement error compensation along the first direction and a second measurement error compensation along the second direction; the measurement compensation weight includes a first measurement compensation weight along the first direction and a second measurement compensation weight along the second direction; the step of assigning a measurement compensation weight to the measurement error compensation of each measurement lithography layer according to the process window corresponding to each measurement lithography layer comprises: assigning a first measurement compensation weight to the first measurement error compensation corresponding to one measurement lithography layer according to a ratio of one first process window to all the first process windows; and assigning a second measurement compensation weight to the second measurement error compensation corresponding to one measurement lithography layer according to a ratio of one second process window to all the second process windows.

[0009] Optionally, the method also includes: using an advanced process control model to assign a process compensation weight to the process error compensation of each of the measurement photolithography layers; performing a weighted summation on the process error compensations of the at least two measurement photolithography layers, and using the weighted summation result as the process alignment error compensation of the alignment photolithography layer; and determining the overlay error compensation of the alignment photolithography layer based on the measurement alignment error compensation and the process alignment error compensation.

[0010] In another aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; wherein the substrate comprises a substrate and at least two measurement lithography layers formed on the substrate; an alignment lithography layer formed on a side of the measurement lithography layer away from the substrate; wherein the measurement alignment error compensation of the alignment lithography layer is determined by the error compensation determination method as described in the above embodiment.

[0011] Optionally, each of the measurement photolithography layers includes an alignment mark; during the process of exposing the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

[0012] Optionally, the spacing distances between the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction are all less than 1 um.

[0013] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; wherein the substrate comprises a substrate and at least two measurement photolithography layers formed on the substrate; forming an alignment photolithography layer on a side of the measurement photolithography layer away from the substrate; wherein the measurement alignment error compensation of the alignment photolithography layer is determined by the error compensation determination method as described in the above embodiment.

[0014] Optionally, the step of providing a substrate includes: providing a substrate; sequentially forming at least two measurement photolithography layers on one side of the substrate; wherein each of the measurement photolithography layers includes an alignment mark; and during exposure of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

[0015] Optionally, the step of sequentially forming the at least two measurement photolithography layers on one side of the substrate includes: repeatedly performing the following sub-steps until the at least two measurement photolithography layers are formed; wherein the spacing distances between the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction are all less than 1um; the sub-steps include: forming a photolithography material layer; preparing alignment marks in the photolithography material layer to obtain a measurement photolithography layer.

[0016] Optionally, the photolithography material layer includes a bottom anti-reflective coating close to the substrate and a photoresist layer away from the substrate; the step of preparing an alignment mark in the photolithography material layer to obtain a measurement photolithography layer formed on the surface of the substrate includes: exposing the photoresist layer to form an alignment mark in the photoresist layer; transferring the pattern of the alignment mark from the photoresist layer to the bottom anti-reflective coating; removing the photoresist layer, and using the bottom anti-reflective coating with the alignment mark as the measurement photolithography layer.

[0017] In multiple embodiments of the present application, for a semiconductor structure including a substrate, at least two measurement lithography layers formed on the substrate, and an alignment lithography layer formed on a side of the measurement lithography layer away from the substrate, a measurement compensation weight is assigned to the measurement error compensation of the measurement lithography layer according to the ratio of the process window corresponding to a single measurement lithography layer to the process windows corresponding to all the measurement lithography layers, and then the measurement error compensations of the at least two measurement lithography layers are weighted summed, and the weighted summation result is used as the measurement alignment error compensation of the alignment lithography layer, and unexpected effects achieved include: in the process of determining the measurement alignment error compensation, the influence of the process windows of multiple measurement lithography layers on the measurement alignment error compensation is introduced, the compensation capability of the measurement alignment error compensation is improved, and the alignment accuracy between different lithography layers in the semiconductor structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic block diagram of a method for determining overlay error compensation provided in the related art.

[0020] Figure 2 A flowchart of a method for determining error compensation provided in one embodiment of the present application.

[0021] Figure 3 A schematic block diagram of a method for determining overlay error compensation provided in accordance with an embodiment of the present application.

[0022] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0023] Figure 5 A schematic diagram of a process for providing a substrate is provided for one embodiment of the present application.

[0024] Figure 6 A schematic diagram of forming a first photolithography material layer on a substrate is provided for one embodiment of the present application.

[0025] Figure 7 A schematic diagram of exposing a first photoresist layer to form a first alignment mark is provided for one embodiment of the present application.

[0026] Figure 8 A schematic diagram of transferring a first alignment mark to a first bottom anti-reflective coating is provided according to an embodiment of the present application.

[0027] Fig. 9 A schematic diagram of forming a second photoresist material layer on a first metrology photoresist layer is provided according to an embodiment of the present application.

[0028] Fig.10 A schematic diagram of exposing a second photoresist layer to form a second alignment mark is provided for one embodiment of the present application.

[0029] Fig.11 A schematic diagram of transferring a second alignment mark to a second bottom anti-reflective coating is provided according to an embodiment of the present application.

[0030] Fig.12 A schematic diagram of forming an alignment photolithography layer on a second metrology photolithography layer is provided for one embodiment of the present application.

[0031] Structure number description 10. Exposure machine; 11. Alignment mark of the second finished photolithography layer; 12. Measurement alignment error of the second finished photolithography layer; 13. Measurement alignment error compensation; 14. APC model; 15. Process error compensation of the first finished photolithography layer; 16. Process compensation weight of the first finished photolithography layer; 17. Process error compensation of the second finished photolithography layer; 18. Process compensation weight of the second finished photolithography layer; 19. Process alignment error compensation; 20. Alignment mark of the first measured photolithography layer; 21. Measurement alignment error of the first measured photolithography layer; 22. Measurement error compensation of the first measured photolithography layer; 23. Alignment mark of the second measured photolithography layer; 24. Measurement alignment error of the second measured photolithography layer; 25. Measurement error compensation of the second measured photolithography layer; 26. Process window of the first measured photolithography layer; 27. Measurement compensation weight of the measurement photolithography layer; 28, process window of the second measurement photolithography layer; 29, measurement compensation weight of the second measurement photolithography layer; 30, overlay error compensation solution model; 31, overlay error compensation; 41, process error compensation of the first measurement photolithography layer; 42, process compensation weight of the first measurement photolithography layer; 43, process error compensation of the second measurement photolithography layer; 44, process compensation weight of the second measurement photolithography layer; 100, base; 110, substrate; 120, first photolithography material layer; 121, first bottom anti-reflective coating; 122, first photoresist layer; 130, first alignment mark; 140, second photolithography material layer; 141, second bottom anti-reflective coating; 142, second photoresist layer; 150, second alignment mark; 160, alignment photolithography layer; 161, alignment bottom anti-reflective coating; 162, alignment photoresist layer. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0033] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0034] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0035] As semiconductor process nodes continue to shrink, in the process of achieving alignment between multiple lithography layers, the range of alignment deviation between different lithography layers is constantly narrowing, that is, the overlay error window between different lithography layers is constantly decreasing. Especially in advanced process nodes below 40nm, even a small overlay error may lead to a significant drop in production yield, or a significant reduction in semiconductor device performance. Therefore, in the relevant technology, on the basis of multiple lithography layers that have been processed, it is necessary to use overlay error compensation to compensate for the overlay error of the lithography layer being processed, so as to improve the alignment accuracy of semiconductor devices.

[0036] In the related art, an exposure machine is usually used to determine overlay error compensation based on measurement alignment error compensation and process alignment error compensation. Taking the process alignment error compensation as an example, in which the process alignment error compensation is calculated based on the process alignment error of two processed photoresist layers, the photoresist layer that is processed first is the first processed photoresist layer, and the processed photoresist layer adjacent to the photoresist layer being processed is the second processed photoresist layer, the exposure machine can determine the overlay error compensation through the following process.

[0037] See also Figure 1 Since each of the processed photoresist layers has an alignment mark, the exposure machine 10 can measure the alignment mark 11 of the second processed photoresist layer to obtain the measurement position information of the alignment mark 11 of the second processed photoresist layer on the second processed photoresist layer, obtain the measurement alignment error 12 of the second processed photoresist layer based on the measurement position information and the designed position of the alignment mark 11 of the second processed photoresist layer on the second processed photoresist layer, and then calculate the measurement alignment error compensation 13 based on the measurement alignment error 12 of the second processed photoresist layer.

[0038] In addition, the exposure machine 10 can use a preset APC (Advanced Process Control) model 14 to calculate the process error compensation 15 of the first completed photolithography layer and the process error compensation 17 of the second completed photolithography layer, and assign process compensation weights to the process error compensations of the two completed photolithography layers according to a preset weighting algorithm, that is, the process compensation weight 16 of the first completed photolithography layer and the process compensation weight 18 of the second completed photolithography layer, perform weighted summation of the process error compensation 15 of the first completed photolithography layer and the process error compensation 17 of the second completed photolithography layer, and use the weighted summation result as the process alignment error compensation 19.

[0039] Finally, the measurement alignment error compensation 13 and the process alignment error compensation 19 may be inputted into a preset overlay error compensation solution model 30 , and the output result of the overlay error compensation solution model 30 may be used as the overlay error compensation 31 .

[0040] For some semiconductor devices that need to realize special functions, their structural design requires the exposure machine to control the overlay error between the photolithography layer being processed and the multiple photolithography layers that have been processed. However, from the above-mentioned determination process of overlay error compensation, it can be known that the process alignment error compensation can be calculated based on the process alignment error of multiple photolithography layers that have been processed, while the measurement alignment error compensation can only be calculated based on the measurement alignment error of a single photolithography layer that has been processed, and it is impossible to calculate the measurement alignment error compensation based on the measurement alignment error of multiple photolithography layers that have been processed, so that the compensation ability of the measurement alignment error compensation is weak, resulting in a reduction in the control ability of the exposure machine on the overlay error, and further resulting in the alignment accuracy of the semiconductor device manufactured after the overlay error compensation determined by the above process is performed still unable to meet the alignment accuracy requirements of the device.

[0041] Therefore, it is necessary to provide a method for determining error compensation. For a semiconductor structure including a substrate, at least two measurement lithography layers formed on the substrate, and an alignment lithography layer formed on a side of the measurement lithography layer away from the substrate, a measurement compensation weight is assigned to the measurement error compensation of the measurement lithography layer according to the ratio of the process window corresponding to a single measurement lithography layer to the process windows corresponding to all the measurement lithography layers. The measurement error compensation of the at least two measurement lithography layers is weightedly summed, and the weighted summation result is used as the measurement alignment error compensation of the alignment lithography layer. Therefore, in the process of determining the measurement alignment error compensation, the influence of the process windows of multiple measurement lithography layers on the measurement alignment error compensation is introduced to enhance the compensation capability of the measurement alignment error compensation and improve the alignment accuracy of the semiconductor structure.

[0042] An embodiment of the present application provides a method for determining error compensation, which can be applied to a manufacturing process of a semiconductor structure. The semiconductor structure may include a substrate, at least two measurement photolithography layers formed on the substrate, and an alignment photolithography layer formed on a side of the measurement photolithography layer away from the substrate.

[0043] In this embodiment, the substrate can be used as the basis for the formation of a semiconductor structure. Specifically, the substrate can be made of semiconductor materials, insulating materials, conductive materials or any combination thereof. For example, the substrate can be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), and silicon carbide (SiC). The substrate can be a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer is used as the substrate based on factors such as dielectric loss requirements, manufacturing process, and manufacturing cost.

[0044] In this embodiment, the measurement photolithography layer may be a formed photolithography layer. Specifically, a photolithography pattern may be formed in the measurement photolithography layer. The photolithography pattern may include a circuit pattern and an alignment mark. The circuit patterns formed on different measurement photolithography layers may be different, and the alignment marks may be the same. The number of measurement photolithography layers is at least two, and the specific number may be determined according to the design requirements of the semiconductor structure.

[0045] In this embodiment, the alignment photolithography layer may be a photolithography layer being processed. Specifically, to meet the design requirements of the semiconductor structure, the alignment accuracy of the alignment photolithography layer and at least two measurement photolithography layers needs to meet a specified alignment accuracy requirement.

[0046] See also Figure 2 The error compensation determination method may include S110 and S120.

[0047] S110: assigning a measurement compensation weight to measurement error compensation for each measured photolithography layer according to a process window corresponding to each measured photolithography layer.

[0048] Due to the limitation of the photolithography process precision, the actual position of the photolithography pattern on the measurement photolithography layer will be offset relative to the reference position determined according to the design requirements. In this embodiment, the process window corresponding to the measurement photolithography layer can represent the offset range allowed for the photolithography pattern on the measurement photolithography layer under the process node corresponding to the semiconductor structure.

[0049] In this embodiment, the measurement error compensation can be calculated by the exposure machine according to the measurement alignment error. Specifically, for each measurement photolithography layer, the exposure machine can first measure the alignment mark in the measurement photolithography layer, obtain the measurement position information of the alignment mark in the measurement photolithography layer, compare the measurement position represented by the measurement position information with the design position of the alignment mark on the measurement photolithography layer, and use the offset of the measurement position relative to the design position as the measurement alignment error of the measurement photolithography layer. Subsequently, the exposure machine can use a preset measurement error compensation solution algorithm to calculate the measurement error compensation based on the measurement alignment error.

[0050] In order to introduce the influence of process windows of different measurement photoresist layers in the measurement alignment error compensation, in this embodiment, the measurement compensation weight can be determined according to the ratio of the process window corresponding to one measurement photoresist layer to the process windows corresponding to all measurement photoresist layers.

[0051] The process window can be used as a measure of the dimensional accuracy requirement. The smaller the process window, the higher the dimensional accuracy requirement. Therefore, in order to improve the compensation capability of the measurement alignment error compensation and improve the alignment accuracy of the semiconductor structure, in some embodiments, the measurement compensation weight corresponding to each measurement lithography layer is negatively correlated with the size of the process window corresponding to each measurement lithography layer. Specifically, the measurement compensation weight corresponding to the measurement lithography layer with a smaller process window is larger, and conversely, the measurement compensation weight corresponding to the measurement lithography layer with a larger process window is smaller.

[0052] In order to improve the quality of semiconductor manufacturing process, in some embodiments, the semiconductor structure can be manufactured according to the structural coordinate system. Specifically, the structural coordinate system can use a selected point on the wafer, for example, the center point of the wafer, as the coordinate origin, and extend a first direction and a second direction perpendicular to each other from the coordinate origin. Limited by the accuracy of the photolithography process and the measurement accuracy, the dimensional deviation of the photolithography pattern along different directions is different. For example, the photolithography pattern includes a circle with a designed diameter of 10nm. After measurement, the R&D personnel found that the actual diameter of the circle along the first direction is 9.8nm, and the actual diameter along the second direction is 10.5nm.

[0053] Since the dimensional deviations of the photolithographic pattern are different along different directions, in order to control the dimensional accuracy and alignment accuracy of the photolithographic pattern along different directions, in this embodiment, the process window may include a first process window along the first direction and a second process window along the second direction. The measurement error compensation may include a first measurement error compensation along the first direction and a second measurement error compensation along the second direction. The measurement compensation weight may include a first measurement compensation weight along the first direction and a second measurement compensation weight along the second direction.

[0054] Accordingly, in this embodiment, according to the process window corresponding to each measured lithography layer, the step of assigning a measurement compensation weight to the measurement error compensation of each measured lithography layer may include: assigning a first measurement compensation weight to the first measurement error compensation corresponding to a measured lithography layer according to the ratio of a first process window to all first process windows; assigning a second measurement compensation weight to the second measurement error compensation corresponding to a measured lithography layer according to the ratio of a second process window to all second process windows. Specifically, in each direction, the sum of the measurement compensation weights of all measured lithography layers is 1, that is, the sum of the first measurement compensation weights of all measured lithography layers is 1, and the sum of the second measurement compensation weights of all measured lithography layers is 1.

[0055] Taking the example of two measurement lithography layers formed on a substrate, wherein the measurement lithography layer close to the substrate is the first measurement lithography layer, and the measurement lithography layer far from the substrate is the second measurement lithography layer, the first measurement compensation weight and the second measurement compensation weight can be assigned to the first measurement lithography layer according to the following formulas 1 and 2, and the second measurement lithography layer can be assigned to the first measurement compensation weight and the second measurement compensation weight according to the following formulas 3 and 4.

[0056] Formula 1 Formula 2 Formula 3 Formula 4 in, is a first measurement compensation weight for a first measurement lithography layer, is a second measurement compensation weight for the first measurement lithography layer, is a first measurement compensation weight of a second measurement lithography layer, is a second measurement compensation weight for the second measurement lithography layer, is a first process window for measuring a first lithography layer, is a second process window for measuring the first lithography layer, is the first process window of the second metrology lithography layer, The second process window is a second measurement lithography layer.

[0057] In the case where three or more metrology lithography layers are formed on the substrate, the above formula may be adjusted, and the first metrology compensation weights and the second metrology compensation weights of different metrology lithography layers may be calculated according to the adjusted formula.

[0058] S120: Performing weighted summation on the measurement error compensations of at least two measurement lithography layers, and using the weighted summation result as the measurement alignment error compensation of the alignment lithography layer.

[0059] By assigning measurement compensation weights to the measurement error compensation corresponding to each measurement lithography layer, performing weighted summation, and using the weighted summation result as the measurement alignment error compensation for the alignment lithography layer, it is possible to determine the overall measurement alignment error compensation based on the measurement alignment error of each measurement lithography layer, thereby improving the compensation capability of the measurement alignment error compensation.

[0060] In some embodiments, the error compensation determination method also includes: using an advanced process control model to assign a process compensation weight to the process error compensation of each measured photolithography layer; performing a weighted summation on the process error compensations of at least two measured photolithography layers, and using the weighted summation result as the process alignment error compensation for the aligned photolithography layer; and determining the overlay error compensation for the aligned photolithography layer based on the measurement alignment error compensation and the process alignment error compensation.

[0061] In this embodiment, the determination method of the process alignment error compensation and the overlay error compensation is similar to the determination method used in the related art, and will not be described in detail here.

[0062] See also Figure 3 Taking the case where both the measurement alignment error compensation and the process alignment error compensation are calculated based on two measurement lithography layers, where the measurement lithography layer close to the substrate is the first measurement process lithography layer and the measurement lithography layer far from the substrate is the second measurement lithography layer as an example, in this embodiment, the exposure machine can determine the overlay error compensation applied to the alignment lithography layer through the following process.

[0063] First, the exposure machine 10 can measure the alignment mark 20 of the first measurement photolithography layer to obtain the measurement position information of the alignment mark 20 of the first measurement photolithography layer on the first measurement photolithography layer, obtain the measurement alignment error 21 of the first measurement photolithography layer based on the measurement position information and the designed position of the alignment mark 20 of the first measurement photolithography layer on the first measurement photolithography layer, and then calculate the measurement error compensation 22 of the first measurement photolithography layer based on the measurement alignment error 21 of the first measurement photolithography layer. The exposure machine 10 can adopt a similar method to obtain the measurement alignment error 24 of the second measurement photolithography layer according to the measurement of the alignment mark 23 of the second measurement photolithography layer, and then calculate the measurement error compensation 25 of the second measurement photolithography layer based on the measurement alignment error 24 of the second measurement photolithography layer.

[0064] Subsequently, the exposure machine 10 can determine the measurement compensation weight 27 of the first measurement lithography layer and the measurement compensation weight 29 of the second measurement lithography layer according to the process window 26 of the first measurement lithography layer and the process window 28 of the second measurement lithography layer. The measurement error compensation 22 of the first measurement lithography layer and the measurement error compensation 25 of the second measurement lithography layer are weightedly summed, and the weighted sum result is used as the measurement alignment error compensation 13.

[0065] In addition, the exposure machine 10 can use the APC model 14 to calculate the process error compensation 41 of the first measurement photolithography layer and the process error compensation 43 of the second measurement photolithography layer, and assign process compensation weights to the process error compensation of the two measurement photolithography layers according to a preset weighting algorithm, that is, the process compensation weight 42 of the first measurement photolithography layer and the process compensation weight 44 of the second measurement photolithography layer, perform weighted summation on the process error compensation 41 of the first measurement photolithography layer and the process error compensation 43 of the second measurement photolithography layer, and use the weighted summation result as the process alignment error compensation 19.

[0066] Finally, the measurement alignment error compensation 13 and the process alignment error compensation 19 may be inputted into the overlay error compensation solution model 30 , and the output result of the overlay error compensation solution model 30 may be used as the overlay error compensation 31 .

[0067] contrast Figure 1 and Figure 3 It can be seen that since the influence of the process window of all measured photolithography layers is introduced in the measurement alignment error compensation 13, the compensation capability of the measurement alignment error compensation 13 is improved, thereby improving the compensation capability of the overlay error compensation 31 determined based on the measurement alignment error compensation 13, and improving the alignment accuracy between different photolithography layers in the semiconductor structure.

[0068] See also Figure 4 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure can be used to manufacture a semiconductor structure including at least two metrology lithography layers and an alignment lithography layer.

[0069] The method for manufacturing a semiconductor structure may include steps S210 and S220.

[0070] S210: providing a substrate.

[0071] In this embodiment, the base may include a substrate and at least two metrology lithography layers formed on the substrate. To reduce process complexity, each metrology lithography layer may be formed using the same process.

[0072] See also Figure 5 In some embodiments, the step of providing a substrate may include S211 and S212.

[0073] S211: providing a substrate.

[0074] S212: forming at least two metrology photolithography layers in sequence on one side of the substrate.

[0075] In some embodiments, the step of sequentially forming at least two measurement lithography layers on one side of the substrate may include: repeatedly performing the following sub-steps until at least two measurement lithography layers are formed; the sub-steps may include: forming a photolithography material layer; preparing alignment marks in the photolithography material layer to obtain a measurement lithography layer.

[0076] In order to reduce the standing wave effect and other optical interference caused by the reflection of the wafer surface during the photolithography process and improve the photolithography accuracy, in this embodiment, the photolithography material layer may include a bottom anti-reflective coating (BARC) close to the substrate and a photoresist layer (PR) away from the substrate. Specifically, the thickness of the photoresist layer and the thickness of the bottom anti-reflective coating can match each other, and the embodiment of the present application does not specifically limit the thickness of the photoresist layer and the bottom anti-reflective coating.

[0077] In this embodiment, the alignment mark can be used to assist the exposure machine in obtaining the measurement alignment error of each measured photolithography layer. Specifically, in order to reduce the difficulty of the exposure machine in identifying the alignment mark, the structure of the alignment mark can be different from the structure of the circuit pattern. For example, the alignment mark can be composed of a plurality of spaced-apart strip structures, or the alignment mark can be an irregular structure. The structure of the alignment mark in the embodiment of the present application is not specifically limited.

[0078] In order to reduce the number of exposures of the exposure machine and reduce the process cost, in the present embodiment, each measurement lithography layer may include an alignment mark. In the process of exposing the substrate, the alignment marks in different measurement lithography layers may be located in the same exposure window, so that the measurement position information of the alignment marks in all measurement lithography layers may be obtained by a single exposure. Specifically, the exposure window may be the range that can be covered by a single exposure of the exposure machine. The size of the exposure window may be determined by the equipment parameters of the exposure machine. In order to adapt to a variety of exposure machine equipment parameters, the spacing distance of the alignment marks in different measurement lithography layers along the horizontal direction or the vertical direction may be less than 1um.

[0079] In order to facilitate the exposure machine to identify the alignment marks in different measurement photolithography layers in a single exposure, in this embodiment, the structures of the alignment marks in different measurement photolithography layers can be the same. In some cases, in order to meet the design requirements of special structures, the structures of the alignment marks in different measurement photolithography layers can also be different.

[0080] In order to improve the fidelity of photolithography patterns in the semiconductor structure manufacturing process, reduce the damage to photolithography patterns in subsequent processes, and reduce the adverse effects of damage to photolithography patterns on the alignment accuracy of multiple photolithography layers, in some embodiments, the steps of preparing alignment marks in the photolithography material layer to obtain a measurement photolithography layer formed on the surface of the substrate may include: exposing the photoresist layer to form alignment marks in the photoresist layer; transferring the pattern of the alignment marks from the photoresist layer to the bottom anti-reflective coating; removing the photoresist layer, and using the bottom anti-reflective coating with the alignment marks as the measurement photolithography layer.

[0081] Taking the formation of two measurement photolithography layers on a substrate as an example, the formation process of the substrate is briefly introduced.

[0082] See also Figure 6 First, a first photoresist material layer 120 may be formed on the substrate 110 . Specifically, the first photoresist material layer 120 may include a first bottom anti-reflective coating layer 121 close to the substrate 110 and a first photoresist layer 122 .

[0083] See also Figure 7 Subsequently, the first photoresist layer 122 may be exposed to light, thereby forming the first alignment mark 130 in the first photoresist layer 122. Specifically, during the exposure of the first photoresist layer 122, a photolithography pattern including the pattern of the first alignment mark 130 may be transferred from the mask to the first photoresist layer 122.

[0084] See also Figure 8 Next, the first photoresist layer 122 can be used as a mask for the first bottom anti-reflective coating layer 121, and the photolithography pattern on the first photoresist layer 122 can be transferred to the first bottom anti-reflective coating layer 121, so as to form a first alignment mark 130 in the first bottom anti-reflective coating layer 121. The first photoresist layer 122 is removed by a dry removal process or a wet removal process, and the first bottom anti-reflective coating layer 121 with the first alignment mark 130 formed thereon is retained as a first measurement photolithography layer.

[0085] See also Figures 9 to 11 A second photoresist material layer 140 including a second bottom anti-reflective coating layer 141 and a second photoresist layer 142 may be formed on a side of the first metrology lithography layer away from the substrate 110, the second photoresist layer 142 may be exposed, a second alignment mark 150 may be formed in the second photoresist layer 142, and a pattern of the second alignment mark 150 may be transferred to the second bottom anti-reflective coating layer 141, the second photoresist layer 142 may be removed, and the second bottom anti-reflective coating layer 141 formed with the second alignment mark 150 may be used as a second metrology lithography layer, thereby obtaining a base 100 having two metrology lithography layers formed on the substrate 110.

[0086] In this embodiment, the process parameters used to form the first metrology lithography layer and the process parameters used to form the second metrology lithography layer may be the same.

[0087] S220: forming an alignment photolithography layer on a side of the measurement photolithography layer away from the substrate.

[0088] See also Fig.12 In this embodiment, the alignment photolithography layer 160 may include an alignment bottom anti-reflective coating layer 161 close to the substrate 110 and an alignment photoresist layer 162 away from the substrate 110. The metrology alignment error compensation of the alignment photolithography layer 160 may be determined by the error compensation determination method described in any of the above embodiments.

[0089] An embodiment of the present application provides a semiconductor structure, which may include: a substrate; wherein the substrate may include a substrate and at least two measurement photolithography layers formed on the substrate; and an alignment photolithography layer formed on a side of the measurement photolithography layer away from the substrate. wherein the measurement alignment error compensation of the alignment photolithography layer may be determined by the error compensation determination method described in any of the above embodiments.

[0090] To reduce the number of exposures of the exposure machine, in some embodiments, each measurement photoresist layer may include an alignment mark. During the exposure process of the substrate, the alignment marks in different measurement photoresist layers may be located in the same exposure window.

[0091] To adapt to different exposure machine parameters, in some embodiments, the spacing distances between alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction may be less than 1 um.

[0092] Regarding the manufacturing method of the semiconductor structure described in the above embodiment and other technical effects of the semiconductor structure, reference can be made to other embodiments of the present application for comparative explanation and no further details will be given here.

[0093] In an embodiment of the present application, for a semiconductor structure including a substrate, at least two measurement lithography layers formed on the substrate, and an alignment lithography layer formed on a side of the measurement lithography layer away from the substrate, a measurement compensation weight is assigned to the measurement error compensation of the measurement lithography layer according to the ratio of the process window corresponding to a single measurement lithography layer to the process windows corresponding to all the measurement lithography layers, and then the measurement error compensations of the at least two measurement lithography layers are weighted summed, and the weighted summation result is used as the measurement alignment error compensation of the alignment lithography layer, and unexpected effects achieved include: in the process of determining the measurement alignment error compensation, the influence of the process windows of multiple measurement lithography layers on the measurement alignment error compensation is introduced, thereby improving the compensation capability of the measurement alignment error compensation and the overall compensation capability of the overlay error compensation, and improving the alignment accuracy of the semiconductor structure.

[0094] In some embodiments of the present application, the overlay error determined by the error compensation determination method described in the above embodiments can be applied to the manufacturing process of multiple batches of the semiconductor structure described in the above embodiments.

[0095] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0096] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0097] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0098] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0099] In several embodiments provided in this application, it should be understood that the disclosed pixel structure and image sensor can be implemented in other ways. For example, the embodiments of the pixel structure and image sensor described above are merely illustrative.

[0100] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for determining error compensation, characterized in that: The method is applied to the manufacturing process of a semiconductor structure; the semiconductor structure comprises a substrate, at least two measurement photolithography layers formed on the substrate, and an alignment photolithography layer formed on a side of the measurement photolithography layer away from the substrate; the method comprises: According to the process window corresponding to each of the measured photolithography layers, a measurement compensation weight is assigned to the measurement error compensation of each of the measured photolithography layers; wherein the measurement compensation weight is determined according to the ratio of the process window corresponding to one of the measured photolithography layers to the process windows corresponding to all of the measured photolithography layers; A weighted sum is performed on the measurement error compensations of the at least two measurement lithography layers, and a weighted sum result is used as the measurement alignment error compensation of the alignment lithography layer.

2. The method according to claim 1, characterized in that The measurement compensation weight corresponding to each of the measurement photolithography layers is negatively correlated with the size of the process window corresponding to each of the measurement photolithography layers.

3. The method according to claim 1, characterized in that The semiconductor structure is manufactured according to a structural coordinate system; wherein the structural coordinate system includes a first direction and a second direction perpendicular to each other; accordingly, the process window includes a first process window along the first direction and a second process window along the second direction; the measurement error compensation includes a first measurement error compensation along the first direction and a second measurement error compensation along the second direction; the measurement compensation weight includes a first measurement compensation weight along the first direction and a second measurement compensation weight along the second direction; the step of assigning a measurement compensation weight to the measurement error compensation of each measurement lithography layer according to the process window corresponding to each measurement lithography layer comprises: assigning a first measurement compensation weight to the first measurement error compensation corresponding to one of the measurement lithography layers according to a ratio of one of the first process windows to all of the first process windows; According to a ratio of one of the second process windows to all of the second process windows, a second measurement compensation weight is assigned to the second measurement error compensation corresponding to one of the measurement lithography layers.

4. The method according to claim 1, characterized in that The method further comprises: Using an advanced process control model, assigning a process compensation weight to the process error compensation of each measured photolithography layer; Performing weighted summation on the process error compensations of the at least two measurement lithography layers, and using the weighted summation result as the process alignment error compensation of the alignment lithography layer; An overlay error compensation for the alignment lithography layer is determined according to the measurement alignment error compensation and the process alignment error compensation.

5. A semiconductor structure, characterized in that: include: A substrate; wherein the substrate comprises a substrate and at least two measurement lithography layers formed on the substrate; An alignment photolithography layer is formed on a side of the metrology photolithography layer away from the substrate; wherein the metrology alignment error compensation of the alignment photolithography layer is determined by the error compensation determination method according to any one of claims 1 to 4.

6. The semiconductor structure according to claim 5, characterized in that: Each of the measurement photolithography layers includes an alignment mark; during the exposure process of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

7. The semiconductor structure according to claim 6, characterized in that: The spacing distances between the alignment marks in the different measurement photolithography layers along the horizontal direction or the vertical direction are all less than 1 um.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate; wherein the substrate comprises a substrate and at least two metrology lithography layers formed on the substrate; An alignment photolithography layer is formed on a side of the metrology photolithography layer away from the substrate; wherein the metrology alignment error compensation of the alignment photolithography layer is determined by the error compensation determination method according to any one of claims 1 to 4.

9. The method according to claim 8, characterized in that The step of providing a substrate comprises: providing a substrate; The at least two measurement photolithography layers are sequentially formed on one side of the substrate; wherein each of the measurement photolithography layers comprises an alignment mark; and during the exposure process of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

10. The method according to claim 9, characterized in that The step of sequentially forming the at least two metrology lithography layers on one side of the substrate comprises: Repeat the following sub-steps until at least two measurement photolithography layers are formed; wherein the spacing distances between the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction are all less than 1 um; the sub-steps include: forming a photoresist material layer; Alignment marks are prepared in the photolithography material layer to obtain a measurement photolithography layer.

11. The method according to claim 10, characterized in that The photolithography material layer includes a bottom anti-reflection coating close to the substrate and a photoresist layer away from the substrate; the step of preparing alignment marks in the photolithography material layer to obtain a measurement photolithography layer formed on the surface of the substrate includes: Exposing the photoresist layer to form an alignment mark on the photoresist layer; transferring the pattern of the alignment mark from the photoresist layer to the bottom anti-reflective coating; The photoresist layer is removed, and the bottom anti-reflection coating layer formed with the alignment mark is used as the measurement photoresist layer.

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