Voltage stabilizing circuit and arithmetic unit, chip, computing power board and computing equipment applying same

Abstract

The invention provides a voltage stabilizing circuit and an arithmetic unit, a chip, a computing power board and computing equipment applying the same. The voltage stabilizing circuit comprises an LDO (Low Dropout Regulator) voltage stabilizing unit; the transient enhancement unit is coupled with the LDO voltage stabilization unit, the first node is arranged between the transient enhancement unit and the LDO voltage stabilization unit, and the transient enhancement unit is used for providing a feedback voltage when the voltage of the first node deviates from a reference voltage so as to adjust the voltage of the first node to return to the reference voltage value. The voltage stabilizing circuit directly controls the magnitude of the output current of the LDO through negative feedback so as to achieve the effect of enhancing the response speed of the LDO to the sudden change of the load current, and therefore the purposes of reducing jitter of the output voltage and stabilizing the output voltage are achieved.

Description

Technical Field

[0001] The present invention relates to the field of voltage stabilization control technology, and in particular to a voltage stabilization circuit, an operation unit, a chip, a computing board and a computing device using the same. Background Art

[0002] The traditional low-dropout linear regulator (LDO) structure is usually composed of an error amplifier and an output driver. In order to fan out a large current and drive the equivalent large capacitance of the subsequent circuit, the loop bandwidth of the LDO is usually relatively low, and the response capability to large changes at the output end is insufficient, and the recovery and stabilization time is long. When the load circuit switch is turned off and the current is quickly drawn, the output voltage will have a large up and down overshoot due to the inability of the loop to respond in time, resulting in a rapid change in the load current.

[0003] In the prior art, in response to changes in output load current, an external large capacitor (uF level) is usually used to stabilize the LDO output port. This method uses the charging and discharging characteristics of the large capacitor to supplement and absorb the dynamically changing load current, thereby reducing the LDO output voltage jitter to obtain a stable output voltage. This traditional external large capacitor method requires the chip to provide additional output PIN pins and board-level capacitors, which increases additional production costs. This method is usually used in scenarios where LDO dedicated chips are used to power the PCB system level. Inside the integrated chip, the fan-out current capability required by the LDO is usually not large, and the capacitive load requirement is relatively low. At the same time, due to the relatively tight PIN pin resources of the integrated chip, this method is generally less cost-effective for LDO as a power supply for the internal modules of the integrated chip. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention proposes a voltage stabilizing circuit for reducing the jitter phenomenon of the output voltage value of the LDO circuit under the condition of rapid load current changes, thereby obtaining a relatively stable LDO output voltage value.

[0005] In order to achieve the above object, the present invention provides a voltage stabilizing circuit, comprising:

[0006] A plurality of nodes, including a first node, a second node, and a third node;

[0007] an LDO voltage stabilizing unit, wherein the LDO voltage stabilizing unit is connected between the second node and the third node;

[0008] a transient enhancement unit, coupled to the LDO voltage stabilizing unit, and connected between the second node and the third node;

[0009] The first node is provided between the transient enhancement unit and the LDO voltage stabilizing unit. The transient enhancement unit is used to provide a feedback voltage when the voltage of the first node deviates from the reference voltage, so as to adjust the voltage of the first node to return to the reference voltage value.

[0010] In one embodiment of the present invention, the plurality of nodes further include a fourth node connected to the input end of the transient enhancement unit;

[0011] The LDO voltage stabilizing unit includes an error amplifier and a first switch, wherein the fourth node is provided between the output end of the error amplifier and the gate of the first switch; the output end of the error amplifier and the first switch are also connected to the first node;

[0012] The transient enhancement unit provides the feedback voltage to the fourth node to adjust the output current of the first switch, so as to adjust the voltage of the first node to return to a reference voltage value.

[0013] In one embodiment of the present invention, the transient enhancement unit includes an N-stage amplifier circuit, N is greater than or equal to 1, the input end of the N-stage amplifier circuit is connected to the first node, and different stages of the N-stage amplifier circuit are inter-stage coupled and connected between the second node and the third node;

[0014] The N-stage amplifier circuit provides the feedback voltage to the first node.

[0015] In one embodiment of the present invention, the N-stage amplifier circuit includes a first-stage amplifier circuit, including a second switch, a third switch, and a fourth switch connected in series;

[0016] the second switch is connected to the second node;

[0017] The source of the third switch is connected to the first node, and the drain is connected to the fourth node;

[0018] The fourth switch is connected to the third node.

[0019] In one embodiment of the present invention, the second switch is a PMOS, and the third switch and the fourth switch are NMOS, or the second switch and the third switch are PMOS, and the fourth switch is NMOS;

[0020] The second switch source is connected to the second node, and the fourth switch source is connected to the third node.

[0021] In one embodiment of the present invention, the N-stage amplifier circuit further comprises: a second-stage amplifier circuit comprising a fifth switch, a sixth switch, and a seventh switch connected in series;

[0022] The second switch and the fifth switch are connected to the second node;

[0023] The third switch is connected to the sixth switch via a common gate.

[0024] In one embodiment of the present invention, the second switch is connected to the fifth switch in a cascode manner;

[0025] The fourth switch is connected to the seventh switch in a cascode manner.

[0026] In one embodiment of the present invention, when the second switch and the fifth switch are PMOS, and the third switch, the fourth switch, the sixth switch, and the seventh switch are NMOS:

[0027] The gate of the fifth switch is connected to the first node and the drain of the third switch, and the fifth switch and the first switch form a current mirror;

[0028] The fourth switch is connected to the seventh switch in cascode;

[0029] or

[0030] In the case where the fourth switch and the seventh switch select NMOS switches, and the second switch, the third switch, the fifth switch, and the sixth switch select PMOS switches:

[0031] The second switch is connected with the fifth switch in cascode;

[0032] The gate of the seventh switch is connected to the first node and the drain of the third switch, and the seventh switch and the first switch form a current mirror.

[0033] In one embodiment of the present invention, the N-stage amplifier circuit further comprises:

[0034] The third-stage amplifier circuit includes an eighth switch, a ninth switch, and a tenth switch connected in series;

[0035] When the second switch, the fifth switch, and the eighth switch are PMOS, and the third switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch, and the tenth switch are NMOS:

[0036] The gate of the eighth switch is connected to the fourth node and the drain of the third switch, and the eighth switch and the first switch form a current mirror;

[0037] The ninth switch is connected to the sixth switch in common gate connection, and the tenth switch is connected to the seventh switch in common gate connection;

[0038] or

[0039] In the case where the fourth switch, the seventh switch, and the tenth switch select NMOS switches, and the second switch, the third switch, the fifth switch, the sixth switch, the eighth switch, and the ninth switch select PMOS switches:

[0040] The gate of the tenth switch is connected to the fourth node and the drain of the third switch, and the eighth switch and the first switch form a current mirror;

[0041] The ninth switch is connected to the sixth switch in common gate connection, and the eighth switch is connected to the fifth switch in common gate connection.

[0042] In one embodiment of the present invention, the transient enhancement unit further comprises:

[0043] a first capacitor connected between the first node and the source of the third switch;

[0044] A second capacitor is connected between the fourth node and the drain of the third switch.

[0045] In one embodiment of the present invention, the error amplifier further comprises:

[0046] A third capacitor is connected between the output terminal of the error amplifier and the positive input terminal of the error amplifier, and two ends of the third capacitor are connected to the fourth node and the first node respectively.

[0047] In one embodiment of the present invention, the LDO voltage stabilizing unit further comprises: a mirror current source, comprising:

[0048] an eleventh switch, a drain of the eleventh switch being connected to the drain of the first switch;

[0049] a twelfth switch, wherein a gate of the twelfth switch is connected to the eleventh switch in common source and gate, and a drain of the twelfth switch is connected to its own gate and the second node;

[0050] A source of the eleventh switch is connected to the third node.

[0051] Another aspect of the present invention provides a data operation unit, comprising a control circuit, an operation circuit, a storage circuit, and one or more voltage stabilizing circuits that are interconnected, wherein the voltage stabilizing circuit is the voltage stabilizing circuit described above.

[0052] Another aspect of the present invention provides a chip, comprising any one of the above-mentioned data operation units.

[0053] Another aspect of the present invention provides a computing board for use in a computing device, comprising a plurality of any one of the above-mentioned chips.

[0054] Yet another aspect of the present invention provides a computing device, comprising a power board, a control board, a connecting board, a radiator, and a plurality of computing boards, wherein the control board is connected to the computing board through the connecting board, the radiator is arranged around the computing board, and the power board is used to provide power to the connecting board, the control board, the radiator, and the computing board, wherein the computing board is any one of the computing boards described above.

[0055] It can be seen from the above scheme that the advantages of the present invention are:

[0056] The present invention provides a voltage stabilizing circuit, in which a transient enhancement unit is connected to the output end of an LDO voltage stabilizing unit through negative feedback, and the LDO output current is directly adjusted by the feedback voltage to achieve the effect of enhancing the response speed of the LDO to a sudden change in load current, thereby achieving the purpose of reducing output voltage jitter and stabilizing the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 The overall structural diagram of the voltage stabilizing circuit of the first embodiment is shown;

[0058] Figure 2 A schematic diagram showing the structure of a voltage stabilizing circuit provided in Embodiment 2 is shown;

[0059] Figure 3 A schematic diagram of the structure of the LDO voltage regulator provided in the third embodiment is shown;

[0060] FIG. 4( a ) and FIG. 4( b ) show circuit topology diagrams of the voltage stabilizing circuit of the fourth embodiment;

[0061] FIG. 5( a ) and FIG. 5( b ) show circuit topology diagrams of the voltage stabilizing circuit of the fifth embodiment;

[0062] FIG. 6( a ) and FIG. 6( b ) show circuit topology diagrams of the voltage stabilizing circuit of the sixth embodiment;

[0063] FIG. 7( a) shows a circuit topology diagram of a voltage stabilizing circuit according to Embodiment 7;

[0064] FIG7( b) is a simulation waveform diagram of Embodiment 7;

[0065] Figure 8 is a circuit topology diagram of the voltage stabilizing circuit of Embodiment 8;

[0066] Fig. 9 This is a schematic diagram of a data operation unit of the present invention;

[0067] Fig.10 It is a schematic diagram of the chip of the present invention;

[0068] Fig.11 This is a schematic diagram of the computing board of the present invention;

[0069] Fig.12 Schematic diagram of the computing device of the present invention.

[0070] Wherein, the reference numerals are:

[0071] 100: voltage stabilizing circuit 100;

[0072] 110: LDO voltage regulator unit;

[0073] 120: transient enhancement unit;

[0074] 120-1, 120-2...120-n: N-stage amplifier circuit;

[0075] 120-1: first stage amplifier circuit;

[0076] 120-2: the second stage amplifier circuit;

[0077] 120-3: the third stage amplifier circuit;

[0078] P1 / P2 / P3 / P4: first node / second node / third node / fourth node;

[0079] M1 / M2 / M3 / M4 / M5 / M6 / M7 / M8 / M9 / M10 / M11 / M12: first switch / second switch / third switch / fourth switch / fifth switch / sixth switch / seventh switch / eighth switch / ninth switch / tenth switch / eleventh switch / twelfth switch;

[0080] C1 / C2 / C3: first capacitor / second capacitor / third capacitor;

[0081] OA1: error amplifier;

[0082] 700: Data processing unit

[0083] 701: Control circuit

[0084] 702: Operational Circuit

[0085] 703: Storage Circuit

[0086] 800: Chip

[0087] 801: Control unit

[0088] 900: Hash board

[0089] 1000: Computing Devices

[0090] 1001: Connecting plate

[0091] 1002: Control Panel

[0092] 1003: Radiator

[0093] 1004: Power board. DETAILED DESCRIPTION

[0094] The terms "first", "second", etc. used in this application do not specifically refer to the order or sequence, nor are they used to limit the present invention. They are only used to distinguish between elements or operations described with the same technical terms. Secondly, the terms "comprise", "include", "have", "contain", etc. used in this application are all open terms, which mean including but not limited to. In addition, "coupled" or "electrically connected" used in this application may refer to two or more elements making direct physical or electrical contact, or making indirect physical or electrical contact with each other. In addition, in this application, unless the text specifically limits the articles, "one" and "the" may refer to a single or multiple.

[0095] As mentioned above, in the prior art, the traditional low-dropout linear regulator (LDO) has the problem of jitter instability in the output voltage value under the condition of rapid load current changes. Based on this, the voltage stabilization circuit provided by the present invention adds a transient enhancement unit, and the output voltage value of the low-dropout linear regulator is controlled by feedback of the transient enhancement unit to stabilize the output voltage.

[0096] Embodiment 1

[0097] like Figure 1 As shown in Figure 1 The overall schematic diagram of the voltage stabilizing circuit provided in the first embodiment is shown. The voltage stabilizing circuit 100 includes a plurality of nodes, an LDO voltage stabilizing unit 110, and a transient enhancement unit 120. The plurality of nodes include a first node P1, a second node P2, and a third node P3. In one embodiment, the second node is a power supply terminal VDD, and the third node is a ground terminal VSS. The LDO voltage stabilizing unit 110 is connected between the second node P2 and the third node P3. The transient enhancement unit 120 is coupled to the LDO voltage stabilizing unit 110, and the transient enhancement unit 120 is also connected between the second node P2 and the third node P3. In one embodiment, the first node P1 is provided between the transient enhancement unit 120 and the LDO voltage stabilizing unit 110, and the first node is the output terminal of the LDO voltage stabilizing unit, and is also connected to the input terminal of the transient enhancement unit 120. The output end of the transient enhancement unit 120 is also feedback-connected to the first node P1. When the voltage of the first node P1 (i.e., the output voltage VLDO of the LDO voltage stabilizing unit) deviates from the reference voltage, the transient enhancement unit 120 provides a feedback voltage Vfb. The feedback voltage Vfb acts on the LDO voltage stabilizing unit to adjust the voltage of the first node to return to the reference voltage value.

[0098] In this embodiment, the voltage of the first node is adjusted by negative feedback of the transient enhancement unit to enhance the response speed of the LDO to a sudden change in load current, thereby achieving the purpose of reducing output voltage jitter and stabilizing the output voltage.

[0099] Embodiment 2

[0100] refer to Figure 2 As shown in Figure 2 The schematic diagram of the voltage stabilizing circuit provided in the second embodiment is shown. In this embodiment, the plurality of nodes further include a fourth node P4, the LDO voltage stabilizing unit is formed with an error amplifier OA1 and a first switch M1, the first switch is a PMOS transistor and / or an NMOS transistor, and if necessary, the LDO voltage stabilizing unit can also form other types of devices such as resistors and capacitors. The negative input terminal VREF of the error amplifier is clamped to the positive input terminal, the gate of the first switch M1 is connected to the output terminal of the error amplifier OA1, and the fourth node P4 is provided between the output terminal of the error amplifier and the gate of the first switch M1. The output terminal of the error amplifier OA and a source or drain of the first switch M1 are also connected to the first node P1.

[0101] The transient enhancement unit 120 is formed with a plurality of PMOS transistors and / or NMOS transistors, etc. The transient enhancement unit 120 includes N-stage amplifier circuits 120-1, 120-2, ..., 120-n. In one embodiment, the N-stage amplifier circuits are at least one-stage amplifier circuit, the input end of the N-stage amplifier circuit is connected to the first node P1, and different stages of the N-stage amplifier circuits are inter-stage coupled and connected between the second node P2 and the third node P3, that is, each stage of the amplifier circuit is connected between the power supply terminal VDD and the ground terminal VSS.

[0102] In one embodiment, each amplifier circuit 120 - 1 , 120 - 2 . . . 120 - n is formed with PMOS transistors and / or NMOS transistors, where n is a positive integer greater than 1. If necessary, other types of devices such as resistors and capacitors may also be formed.

[0103] When the LDO voltage regulator unit is powered on, the internal circuit starts working, and the error amplifier continuously compares the difference between the output voltage VLDO and the reference voltage VREF and generates an error signal. If the output voltage is lower than the reference voltage, the error amplifier will increase the bias current that controls the first switch, so that more current flows from the input to the output, thereby increasing the output voltage. Conversely, if the output voltage is higher than the reference voltage, the error amplifier will reduce the bias current that controls the first switch, reduce the current flowing to the output, and reduce the output voltage. The transient enhancement unit continuously monitors the voltage of the first node P1 (i.e., the output voltage of the LDO voltage regulator unit). When the output voltage deviates from the reference voltage, the transient enhancement unit will respond quickly. Through multiple internal PMOS transistors and / or NMOS transistors and other components, the transient enhancement unit generates a feedback voltage. The polarity and magnitude of this feedback voltage depend on the difference between the output voltage and the reference voltage. The feedback voltage is applied to the fourth node, i.e., the input end of the first switch, to adjust the output voltage.

[0104] For example, in one embodiment, the first switch is a PMOS, a gate is connected to the fourth node P4, a source is connected to the second node P2, and a drain is connected to the first node P1. The feedback voltage generated by the transient enhancement unit is fed back to the gate of the first switch. If the polarity of the feedback voltage is a positive voltage, the gate voltage of the first switch increases, that is, the absolute value of the gate voltage decreases, the absolute value of Vgs (gate-source voltage, that is, the difference between the gate voltage and the source voltage) decreases, and the conduction degree of the PMOS decreases, that is, the conductive channel between the drain and the source becomes narrower, and the current passing through is reduced, thereby reducing the output current of the first switch, thereby reducing the output voltage of the first node; if the polarity of the feedback voltage is a negative voltage, the gate voltage of the first switch decreases, that is, the absolute value of the gate voltage increases, and the absolute value of Vgs (gate-source voltage, that is, the difference between the gate voltage and the source voltage) increases, that is, the negative value of Vgs is increased, making the PMOS more conductive, and Vgs becomes more negative, resulting in an increase in the conduction degree of the first open PMOS, that is, the conductive channel between the drain and the source becomes wider, allowing more current to pass, thereby increasing the output current of the first switch, thereby increasing the output voltage of the first node.

[0105] In this embodiment, the transient enhancement unit can quickly respond to changes in the output voltage and provide the necessary feedback voltage, so it significantly improves the transient response capability of the LDO voltage stabilization unit when the load current changes rapidly. In this embodiment, the gate of the first switch is directly controlled by negative feedback, and the output current of the first switch is adjusted corresponding to the enhanced or weakened conduction degree, so as to adjust the voltage of the first node and enhance the response speed of the LDO to the sudden change of the load current, thereby achieving the purpose of reducing the output voltage jitter and stabilizing the output voltage.

[0106] Embodiment 3

[0107] On the basis of the second embodiment, the LDO voltage stabilizing unit of this embodiment further adds a mirror current mirror. Figure 3 As shown in Figure 3 A circuit topology diagram of an LDO voltage stabilizing unit is shown. The LDO voltage stabilizing unit also includes: a mirror current mirror, which is composed of an eleventh switch M11 and a twelfth switch M12. In one embodiment, the first switch M1 selects PMOS, and the eleventh switch M11 and the second switch M12 select NMOS accordingly. The mirror current mirror is composed of the eleventh switch M11 and the twelfth switch M12, and the source of the twelfth switch M12 is connected to the second node P2 (VDD), and the drain is connected to the source of M11. In this way, the current of the twelfth switch M12 will be copied to the eleventh switch M11, ensuring that the drain current of the eleventh switch M11 is consistent with the current of the twelfth switch M12, providing a stable tail current source for the circuit. In addition, the drain of the eleventh switch M11 is also connected to the drain of the first switch M1, adjusting the bias current of the first switch M11, and then adjusting the operating point of the first switch M1 to adjust the voltage of the first node.

[0108] In one embodiment, the LDO voltage stabilizing unit further includes a third capacitor C3, wherein two ends of the third capacitor C3 are respectively connected to the first node P1 and the fourth node P4, and the third capacitor C3 is a compensation capacitor to ensure loop stability.

[0109] Embodiment 4

[0110] Compared with the second and third embodiments, in this embodiment, the N-stage amplifier circuit includes a first-stage amplifier circuit 120-1, and the first-stage amplifier circuit 120-1 includes a second switch M2, a third switch M3, and a fourth switch M4 connected in series. The second switch M2 is connected to the second node P2; the source of the third switch M3 is connected to the first node P1, and the drain is connected to the fourth node P4; the fourth switch M4 is connected to the third node P3.

[0111] Referring to FIG. 4(a), in one embodiment, the second switch is a PMOS, and the third switch and the fourth switch are NMOS. The second switch M2, the third switch M3, and the fourth switch M4 are connected in series between the second node P2 and the third node P3, and can carry a larger current, drive a larger load, and improve the switching speed. The source of the third switch M3 is connected to the first node P1, the drain of the third switch M3 is connected to the fourth node, and the third switch M3 and the second switch M2 are co-gate, the source of the second switch M2 is connected to the second node P2, the source of the fourth switch M4 is connected to the third node P3, and the gate is connected to its own drain. In this embodiment, taking the increase of the voltage of the first node P1 as an example, the source potential of the third switch M3 also increases. Since the second switch M2 and the third switch M3 are co-gate connected, their gate potentials are the same. The source potential of the third switch M3 increases, while the gate potential remains unchanged, so the Vgs of the third switch M3 is relatively reduced, and the conduction degree of the third switch M3 may be reduced, allowing less current to pass, and the driving capability is further enhanced. For the second switch, its source is connected to the second node P2 (VDD), and the gate potential remains unchanged, so the absolute value of Vgs of the second switch M2 is actually reduced (because Vgs = Vg-Vs, Vg remains unchanged, Vs (i.e., VDD) increases relative to the gate potential, so the absolute value of Vgs decreases). The conduction of the second switch M2 depends on the relationship between its Vgs and the threshold voltage Vth. If the second switch is originally in the on state, it may gradually enter the off state or the degree of conduction decreases (the leakage current decreases) due to the decrease in the absolute value of Vgs. If the second switch M2 is originally in the off state, then the further decrease in the absolute value of Vgs will not change its off state. Since the second switch M2 and the third switch M3 are connected in common drain, the drain potential of the third switch is also the drain potential of the second switch. The source potential of the third switch decreases, and the drain potential (also the drain potential of the second switch) may be affected by the conduction state of the second switch due to the series connection. The second switch gradually enters the cut-off state or the degree of conduction weakens, so its pull-down effect on the drain potential of the third switch will decrease, and the drain potential of the third switch will rise. Since the drain of the third switch is connected to the fourth node P4, the pull-up potential is fed back to the gate of the first switch M1, and its gate voltage Vg increases relative to the source voltage Vs. If the PMOS is originally in the on state (that is, Vgs is less than or equal to Vth), then the increase in the gate voltage may cause Vgs to increase (that is, the absolute value of Vgs decreases), which may make the PMOS closer to the cut-off state (that is, Vgs is greater than Vth), that is, the conductive channel between the drain and the source becomes narrower, allowing less current to pass, reducing the output current of the first switch, and then reducing the output voltage of the first node P1.

[0112] As shown in FIG4(b), in one embodiment, the second switch M2 and the third switch M3 are PMOS, and the fourth switch M4 is NMOS. The second switch is connected to the third switch in common gate and connected to the second node, the second switch source is connected to the second node P2, the second switch drain is connected to the third switch source, and the fourth switch source is connected to the third node P3.

[0113] In this embodiment, taking the case where the voltage of the first node P1 decreases as an example, when the voltage of the first node decreases, the potential of the source of the second PMOS decreases. Similarly, since the gate voltage does not change, the absolute value of Vgs of the second switch increases, resulting in an increase in the conduction degree of the second switch, an increase in the drain current, and an unchanged drain resistance, so the drain potential decreases. At this time, since the fourth node is connected to the drain of the third switch, the gate potential of the first switch decreases. If the PMOS is originally in the on state (i.e., Vgs is less than or equal to Vth), the decrease in the gate voltage may cause Vgs to decrease (i.e., the absolute value of Vgs increases), thereby increasing the conduction degree of the PMOS, i.e., the conductive channel between the drain and the source becomes wider, allowing more current to pass through, thereby increasing the output current of the first switch, and further increasing the output voltage of the first node P1.

[0114] If the voltage of the first node P1 increases, the source potential of the third switch increases. Since the second switch and the third switch are in common gate and the gate voltage does not change, the absolute value of VGS of the third switch decreases, resulting in a weakened conduction degree of the third switch, a reduced drain current, and an unchanged drain resistance, so the drain potential increases. At this time, since the drain of the third switch is connected to the fourth node P4, the pull-up potential is fed back to the gate of the first switch M1, and its gate voltage Vg increases relative to the source voltage Vs. If the PMOS is originally in the on state (i.e., Vgs is less than or equal to Vth), then the increase in the gate voltage may cause Vgs to increase (i.e., the absolute value of Vgs decreases), which may make the PMOS closer to the cut-off state (i.e., Vgs is greater than Vth), that is, the conductive channel between the drain and the source becomes narrower, allowing less current to pass through, reducing the output current of the first switch, and then reducing the output voltage of the first node P1.

[0115] In this embodiment, the transient enhancement unit can be provided with only one-stage amplification circuit. In this embodiment, the second switch, the third switch, and the fourth switch are not limited to the connection method of the above embodiment. The conduction conditions of different switches can be controlled and coordinated with each other to achieve the adjustment of the drain potential of the third switch, thereby achieving the adjustment of the first node voltage. This adjustment method is simple.

[0116] Embodiment 5

[0117] The transient change amplification range of the single-stage amplifier circuit is limited, and the single-stage amplifier circuit may not be able to achieve the required amplification factor. The single-stage amplifier circuit is more sensitive to interference from external factors, which may cause the instability of the circuit operating point, thereby affecting the stability and accuracy of the output signal. The single-stage amplifier circuit has relatively low design flexibility and is difficult to meet the needs of different application scenarios through simple adjustments. In this regard, this embodiment adds a second-stage amplifier circuit on the basis of the fourth embodiment, as shown in Figure 5, which shows a schematic diagram of the structure of the transient enhancement unit 120. Compared with the fourth embodiment, in this embodiment, the N-stage amplifier circuit includes a first-stage amplifier circuit 120-1 and a second-stage amplifier circuit 120-2, wherein the first-stage amplifier circuit 120-1 is used as a previous stage circuit relative to the second-stage amplifier circuit 120-2, and includes a second switch M2, a third switch M3, and a fourth switch M4 connected in series; the second-stage amplifier circuit 120-2 is used as a subsequent stage circuit, and includes a fifth switch M5, a sixth switch M6, and a seventh switch M7 connected in series. Among them, the second switch M2 is connected to the fifth switch M5 in common source and gate, the third switch M3 is connected to the sixth switch M6 in common gate, the fourth switch M4 is connected to the seventh switch M7 in common source and gate, the second switch M2 and the fifth switch M5 are connected to the second node P2; the source or drain of the third switch M3 is connected to the first node P1 and the fourth node P4, and the fourth switch M4 and the seventh switch M7 are connected to the third node P3.

[0118] In this embodiment, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6, and the seventh switch M7 of the transient enhancement unit form a common source and common gate current mirror, mirroring the current of the second switch M2, the third switch M3, and the fourth switch M4 of the first stage amplifier circuit. For example, when the second switch M2 is turned on, the fifth switch M3 is also turned on with the same current ratio; when the third switch M3 is turned on, the sixth switch M6 is also turned on with the same current ratio; when the fourth switch is turned on, the sixth switch M6 is also turned on with the same current ratio, and the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6, and the seventh switch M7 establish a suitable static operating point for the transient enhancement circuit.

[0119] In one embodiment, as shown in FIG5(a), in one embodiment, the second switch M2 and the fifth switch M5 can select PMOS, and the third switch M3, the fourth switch M4, the sixth switch M6, and the seventh switch M7 can select NMOS. The source of the second switch M2 is connected to the second node, and the drain is connected to the fourth node and the drain of the third switch; the drain of the third switch M3 is connected to the fourth node, and the source is connected to the first node; the drain of the fourth switch M4 is connected to the first node P1, and the source is connected to the third node.

[0120] In one embodiment, as shown in FIG5(b), the second switch M2 and the fifth switch M5 can select PMOS, the third switch M3 and the sixth switch M6 can select PMOS, and the fourth switch M4 and the seventh switch M7 can select NMOS. The source of the second switch M2 is connected to the second node P2, and the drain is connected to the fourth node P4 and the source of the third switch M3; the drain of the third switch M3 is connected to the drain of the fourth switch M4, and the source of the fourth switch M4 is connected to the third node P3.

[0121] Compared with the fourth embodiment, a two-stage amplifier circuit is provided in this embodiment to improve the amplification effect and response speed of transient changes, thereby reducing the output voltage change value and shortening the recovery and stabilization time.

[0122] Embodiment 6

[0123] In the specific implementation, in the voltage stabilizing circuits of Embodiment 4 and Embodiment 5, the conduction of the third switch M3 is easily affected by other switch tubes, and the dynamic current is not clearly controllable, resulting in a situation where the voltage change of the first node cannot be effectively responded to. In this regard, in this embodiment, a mirror switch of the first switch is added, and the mirror switch accurately replicates the output current of the first switch, so that the dynamic current is clearly controllable, so as to improve the effective response to the voltage of the first node.

[0124] Compared with the fifth embodiment, in this embodiment, the N-stage amplifier circuit also includes a first-stage amplifier circuit 120-1 and a second-stage amplifier circuit 120-2, wherein relative to the second-stage amplifier circuit 120-2, the first-stage amplifier circuit 120-1 is a previous stage circuit, which includes a second switch M2, a third switch M3, and a fourth switch M4 connected in series; the second-stage amplifier circuit 120-2 is a subsequent stage circuit, which includes a fifth switch M5, a sixth switch M6, and a seventh switch M7 connected in series. Different from the fifth embodiment, in this embodiment, the gate of the fifth switch M5 or the seventh switch M7 in the second-stage amplifier circuit is connected to the fourth node P4 and the drain of the third switch M3, and forms a current mirror with the first switch M1.

[0125] Referring to FIG6(a), the second switch M2 and the fifth switch M5 can select PMOS, and the third switch M3, the fourth switch M4, the sixth switch M6, and the seventh switch M7 can select NMOS. Compared with FIG5(a), in this embodiment, the fifth switch M5 is no longer connected to the second switch M2 in a common source and common gate manner, but the gate of the fifth switch M5 is connected to the fourth node P4 and the drain of the third switch M3, and forms a current mirror with the first switch M1. The connection between other switch tubes is consistent with FIG5(a). Taking the voltage drop of the first node as an example, when the voltage of the first node drops, the source voltage Vs of the third switch M3 drops; in addition, the fourth node also detects a voltage drop. Since the first switch and the fifth switch are current mirrors, the gate voltages of the first switch M1 and the fifth switch M5 drop, the absolute value of the fifth switch (PMOS) Vgs increases, and the degree of conduction increases, so that the current flowing into the sixth switch M6 and the seventh switch M7 increases. Since the third switch and the sixth switch form a current mirror, the current of the sixth switch and the third switch increases, and the gate voltage Vg rises. As a result, the Vgs (Vg-Vs) of the third switch M3 (NMOS) increases, and the driving capability is further enhanced, driving the drain voltage of the third switch to be quickly pulled down, and the pull-down voltage is fed back to the gate of the first switch M1. The absolute value of the Vgs of the first switch M1 increases, so that the driving capability of the first switch M1 is enhanced, thereby providing a larger output current and alleviating the voltage reduction trend of the first node P1. The voltage rise of the first node is similar to the voltage drop, and this embodiment will not be further analyzed.

[0126] Referring to FIG. 6(b), similarly, the second switch M2, the fifth switch M5, the third switch M3, and the sixth switch M6 select PMOS, and the fourth switch M4 and the seventh switch M7 can select NMOS as an example. In this embodiment, the seventh switch M7 no longer forms a current mirror with the fourth switch M4, and the gate of the seventh switch M7 is connected to the fourth node P4 and is connected to the drain of the third switch M3. The seventh switch M7 and the first switch M1 form a current mirror. The connection between other switch tubes is consistent with FIG. 5(b). Similarly, taking the voltage drop of the first node as an example, when the voltage of the first node drops, the source voltage Vs of the third switch M3 drops; in addition, the fourth node also detects a voltage drop. Since the first switch and the seventh switch are current mirrors, the gate voltage Vg of the first switch M1 and the seventh switch M7 drops, the Vgs of the seventh switch (NMOS) decreases, and the degree of conduction decreases, so that the current flowing into the sixth switch M6 and the fifth switch M5 decreases. Since the third switch and the sixth switch form a current mirror, the current of the sixth switch and the third switch decreases, and the gate voltage Vg decreases. When the current flowing into the third switch M3 decreases and the source voltage decreases, if the gate voltage remains unchanged or decreases, and the reduction is not enough to make Vgs>Vth, the third switch will remain in the on state, but the degree of conduction (i.e., the current magnitude) may decrease. If the gate voltage is reduced to make Vgs>Vth, the third switch will gradually enter the cut-off state, the current will further decrease until it is zero, the drain potential will decrease as the source voltage decreases, and the drain potential is pulled down. This is because PMOS tries to maintain a certain current flow. When the source potential decreases, the drain potential must also decrease accordingly to keep the voltage difference and current unchanged. At this time, the pull-down voltage is fed back to the gate of the first switch M1, and the absolute value of Vgs of the first switch M1 increases, so that the driving ability of the first switch M1 is enhanced, thereby providing a larger output current and alleviating the voltage reduction trend of the first node P1. For the voltage rise of the first node, similar to the voltage drop, this embodiment will not be repeated for analysis.

[0127] In this embodiment, compared with the voltage stabilizing circuits of the fourth and fifth embodiments, a mirror switch (fifth switch or seventh switch) of the first switch is added, the dynamic current is clearly controllable, the mirror switch accurately replicates the output current of the first switch, the current magnitude is controlled by the width-to-length ratio of the two, and the overall static current introduced is small. The feedback voltage is adjusted through the synchronous action of the first node and the fourth node voltage on the transient enhancement circuit, thereby adjusting the output voltage of the first node.

[0128] Embodiment 7

[0129] This embodiment adds a third-stage amplifier circuit 120-3 on the basis of the above-mentioned embodiment 5. In this embodiment, the first two stages of amplifier circuits are the same as the voltage stabilizing circuit provided in embodiment 5. Different from embodiment 6, in this embodiment, a mirror switch is provided in the third-stage amplifier circuit to improve the amplification effect and response speed to transient changes, and the mirror switch accurately replicates the output current of the first switch, so as to realize clear and controllable dynamic current, so as to improve the effective response to the output voltage change.

[0130] Compared with the fifth embodiment, in this embodiment, the N-stage amplifier circuit includes a first-stage amplifier circuit 120-1, a second-stage amplifier circuit 120-2, and a third-stage amplifier circuit 120-3, wherein relative to the second-stage amplifier circuit 120-2, the first-stage amplifier circuit 120-1 serves as a previous-stage circuit, the second-stage amplifier circuit is an intermediate-stage circuit, and the third-stage amplifier circuit is a subsequent-stage circuit, and the third-stage amplifier circuit includes an eighth switch M8, a ninth switch M9, and a tenth switch M10 connected in series.

[0131] In this embodiment, the gate of the eighth switch M8 in the third stage amplifier circuit is connected to the fourth node P4 and the drain of the third switch M3, and forms a current mirror with the first switch M1.

[0132] Referring to FIG. 7(a), taking the second switch M2, the fifth switch M5, and the eighth switch as PMOS, and the third switch M3, the fourth switch M4, the sixth switch M6, the seventh switch M7, the ninth switch M9, and the tenth switch M10 as NMOS as an example, in this embodiment, the gate of the eighth switch M8 is connected to the fourth node P4 and the drain of the third switch M3, and forms a current mirror with the first switch M1. The ninth switch M9 is connected to the sixth switch M6 in cascode, and the gate of the ninth switch M9 is connected to its own drain; the tenth switch M10 is connected to the seventh switch M7 in cascode, and the gate of the tenth switch M10 is connected to its own drain. At this time, the gate of the fifth switch M5 is connected to its own drain.

[0133] In this embodiment, the third switch M3, the fourth switch M4, the sixth switch M6, the seventh switch M7, the ninth switch M9, and the tenth switch M10 of the transient enhancement unit form a common source and common gate current mirror, and the second switch M2 and the fifth switch M5 form a current mirror. The second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6, the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 establish a suitable static operating point for the transient amplifier circuit.

[0134] In addition, in one embodiment, the first node P1 is connected in series with a first capacitor C1 and connected to the source of the third switch M3, the fourth node P1 is connected in series with a second capacitor C2 and connected to the drain of the third switch M3, and the third capacitor C3 is connected between the first node and the fourth node. The first capacitor C1 and the second capacitor C2 are added to utilize the principle that the voltage across the capacitor cannot change suddenly, so as to detect the instantaneous change of the voltage of the fourth node and the first node and adjust the instantaneous change of the voltage of the first node.

[0135] For example, when the load current of the output node of the LDO voltage regulator unit suddenly changes from 0 to 1 mA, the LDO voltage regulator unit cannot respond to the increase of the output current in time due to the low loop bandwidth, resulting in a drop in the VLDO voltage, that is, a drop in the potential of the first node. At this time, path 1: the first capacitor C1 detects a drop in the left plate voltage (that is, a drop in the first node potential). Since the voltage difference across the capacitor cannot suddenly change, the voltage on the right plate of the first capacitor C1 follows the drop in the VLDO voltage, and the potential of the first capacitor C1 drops. At this time, the source voltage of the third switch M3 drops. Path 2: Since the third capacitor C3 is connected between the first node P1 and the fourth node P4, the third capacitor C3 detects that the potential of the first node drops, and the potential of the fourth node drops, so that the gate potentials of the first switch M1 and the eighth switch M8 drop, the absolute value of the Vgs of the eighth switch M8 increases, and the driving capability is enhanced, so that the current flowing into the ninth switch M9 and the tenth switch M10 increases, and the gate potentials of the third switch M3, the sixth switch M6, and the ninth switch M9 rise. At the same time, due to the effect of the path 1, the drain potential of the third switch M3 is also reduced, and the Vgs of the third switch M3 becomes larger, and the driving capability is further enhanced, driving the drain potential of the third switch M3 to be quickly pulled down. At this time, the second capacitor C2 detects that the drain potential of the third switch M2 is quickly pulled down, that is, the potential of the fourth node P4 drops. Since the first node P1 is connected to the output terminal of the error amplifier OA1 and the gate of the first switch M1, the pull-down voltage is fed back to the gate of the first switch M1, and the absolute value of the first switch Vgs increases, so that the driving capability of the first switch M1 is enhanced, thereby providing a larger output current, alleviating the potential decreasing trend of the first node, that is, alleviating the VLDO voltage decreasing trend of the LDO voltage stabilizing unit.

[0136] The situation in which the output voltage of the LDO voltage stabilizing unit rises is similar to the situation in which it falls, that is, when the first capacitor C1 detects that the potential of the first node P1 rises, the voltage of the first capacitor rises, and the source potential of the third switch M3 rises. At this time, when the third capacitor C3 detects that the potential of the first node P1 rises, the gate potentials of the first switch M3 and the eighth switch M8 rise, the currents of the ninth switch M9 and the tenth switch M10 increase, the gate potentials of the third switch M3, the sixth switch M6, and the ninth switch M9 decrease, and the driving voltage of the third switch M3 increases, driving the drain potential of the third switch M3 to be quickly pulled up. The second capacitor C2 detects that the drain potential of the third switch M3 is quickly pulled up, and feeds back the pull-up voltage to the gate of the first switch M1, and the output current of the first switch decreases, alleviating the rising trend of the potential of the first node P1.

[0137] FIG7(b) shows the VLDO waveform change diagram when the load current changes from 0 to 1mA, where the green ILOAD is the output load current jump from 0 to 1mA, the red is the VLDO output waveform after adding the circuit of this embodiment, and the yellow is the original VLDO output waveform schematic diagram without adding the circuit of the present invention. It can be seen from the figure that the load current ILOAD changes from 0 to 1mA suddenly, which takes 100ps, and the normal output voltage of VLDO is 800mv. By comparing the VLDO output voltage change waveform, it can be seen that after adding the transient enhancement unit to the voltage stabilizing circuit of this embodiment, the VLDO output waveform of the LDO voltage stabilizing unit recovers to the stable voltage of 800mv in a shorter time, and the VLDO voltage drop difference after the load current mutation is smaller.

[0138] Referring to FIG. 7(a), taking the second switch M2, the fifth switch M5, and the eighth switch as PMOS, and the third switch M3, the fourth switch M4, the sixth switch M6, the seventh switch M7, the ninth switch M9, and the tenth switch M10 as NMOS as an example, in this embodiment, the gate of the eighth switch M8 is connected to the fourth node P4 and the drain of the third switch M3, and forms a current mirror with the first switch M1. The ninth switch M9 is connected to the sixth switch M6 in cascode, and the gate of the ninth switch M9 is connected to its own drain; the tenth switch M10 is connected to the seventh switch M7 in cascode, and the gate of the tenth switch M10 is connected to its own drain. At this time, the gate of the fifth switch M5 is connected to its own drain.

[0139] The voltage stabilizing circuit provided in this embodiment is connected to the transient enhancement unit through negative feedback at the output end of the LDO voltage stabilizing unit, and the first switch gate is directly controlled through negative feedback, correspondingly enhancing or weakening the LDO output current to achieve the effect of enhancing the response speed of the LDO to the load current mutation, thereby achieving the purpose of reducing the output voltage jitter and stabilizing the output voltage, and improving the response speed of the LDO loop in the face of the load current mutation, so that the output voltage change value is reduced and the recovery and stability time is shortened. At the same time, the present invention sets pF-level capacitors at the first node, the fourth node, and between the first node and the fourth node to detect the instantaneous change of the output voltage, which saves more resource consumption compared to the external large capacitor. At the same time, in this embodiment, the introduced dynamic current is clearly controllable, the seventh switch tube accurately replicates the output current of the first switch, the current size is controlled by the width-to-length ratio of the two, and the overall static current introduced is small.

[0140] Embodiment 8

[0141] Embodiment 8 is a variation of embodiment 7. In this embodiment, the third-stage amplifier circuit includes an eighth switch M8, a ninth switch M9, and a tenth switch M10 connected in series. Different from embodiment 7, in this embodiment, the gate of the tenth switch M10 in the third-stage amplifier circuit is connected to the fourth node P4 and the drain of the third switch M3, and forms a current mirror with the first switch M1. The eighth switch M8 is connected to the fifth switch M5 in common source and gate, the gate of the fifth switch M5 is connected to its own drain, and the gate of the eighth switch is connected to its own drain. The ninth switch M9 is connected to the sixth switch M6 in common source and gate, and the gate of the ninth switch M9 is connected to its own drain. In this embodiment, the fourth switch M4, the seventh switch M7, and the tenth switch M10 select NMOS switches, and the second switch M2, the third switch M3, the fifth switch M5, the sixth switch M6, the eighth switch M8, and the ninth switch M9 select PMOS switches.

[0142] In this embodiment, when the load current of the output node of the LDO voltage regulator unit suddenly changes from 1mA to 0mA, the LDO voltage regulator unit cannot respond to the decrease of the output current in time due to the low loop bandwidth, resulting in an increase in the VLDO voltage, that is, the potential of the fourth node increases. At this time, path 1: the first capacitor C1 detects the increase in the left plate voltage (that is, the first node potential increases). Since the voltage difference across the capacitor cannot suddenly change, the voltage on the right plate of the first capacitor C1 follows the VLDO voltage to rise, and the potential of the first capacitor C1 rises. At this time, the source voltage of the third switch M3 rises. Path 2: Since the third capacitor C3 is connected between the first node P1 and the fourth node P4, when the third capacitor C3 detects that the voltage of the first node rises (VLDO voltage), the gate potential of the first switch M1 and the tenth switch M10 rises, the Vgs of the tenth switch increases, the driving capability of the tenth switch M10 is enhanced, the current of the eighth switch M8 and the ninth switch M9 increases, and the gate potential of the third switch M3, the sixth switch M6, and the ninth switch M9 decreases. At the same time, due to the effect of the first path, the source voltage of the third switch M3 rises, the absolute value of the driving voltage Vgs of the third switch M3 increases, and the driving capability of the third switch M3 is further enhanced, driving the drain potential of the third switch M3 to be quickly pulled up. The second capacitor C2 detects that the drain of the third switch M3 is quickly pulled up, and feeds back the pull-up voltage to the gate of the first switch, the gate voltage increases, so that the absolute value of the Vgs of the first switch M1 decreases, the driving capability is weakened, and the output current is reduced. The output current of the first switch M1 decreases, and the potential rising trend of the first node is alleviated.

[0143] The situation in which the output voltage of the LDO voltage regulator unit drops is similar to the situation in which the output voltage rises, that is, when the first capacitor detects that the potential of the first node drops, the voltage of the first capacitor drops, and the potential of the source of the third switch drops; at this time, when the third capacitor detects that the potential of the fourth node drops, the gate potentials of the first switch and the tenth switch drop, the currents of the eighth switch and the ninth switch increase, the gate potentials of the third switch, the sixth switch, and the ninth switch rise, and the driving voltage of the third switch increases, driving the drain potential of the third switch to be quickly pulled down. The second capacitor detects that the drain voltage of the third switch is quickly pulled down, and feeds back the pull-down voltage to the gate of the first switch, and the output current of the first switch increases, alleviating the potential drop trend of the fourth node.

[0144] In addition, it should be noted that the transient enhancement circuit in the present invention is not limited to the first stage amplifier circuit, the second stage amplifier circuit, and the third stage amplifier circuit. The number of stages can be increased, and the mirror switch with the first switch is not limited to the last stage amplifier circuit. It can also be set in the intermediate stage amplifier circuit or set up multiple stages of amplifier circuits including mirror switches as needed; in addition, each stage amplifier circuit is not limited to three transistors. Based on the above embodiments of the present invention, any modified method for implementing the LDO output voltage regulation of the present invention belongs to the protection scope of the present invention.

[0145] In summary, the voltage stabilizing circuit provided by the present invention connects the transient enhancement unit through the negative feedback of the output end of the LDO voltage stabilizing unit, thereby improving the response speed of the LDO loop in the case of a sudden change in load current, reducing the output voltage change value and shortening the recovery and stabilization time. At the same time, the present invention sets a pF capacitor between the first node, the fourth node, and the first node and the fourth node to detect the instantaneous change of the output voltage, which saves more resource consumption compared to an external large capacitor.

[0146] The present invention also provides a data operation unit. Fig. 9 Schematic diagram of the data operation unit of the present invention. Fig. 9 As shown, the data operation unit 700 includes a control circuit 701 , an operation circuit 702 , a storage circuit 703 , and one or more voltage stabilization circuits 100 that are interconnected.

[0147] The present invention also provides a chip. Fig.10 FIG. 2 is a schematic diagram of the chip of the present invention. Fig.10 As shown, the chip 800 includes a control unit 801 and one or more data operation units 700. The control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.

[0148] The present invention also provides a computing board. Fig.11 This is a schematic diagram of the computing board of the present invention. Fig.11 As shown, each computing board 900 includes one or more chips 800.

[0149] The present invention also provides a computing device, Fig.12 FIG. 1 is a schematic diagram of a computing device according to the present invention. Fig.12 As shown, each computing device 1000 includes a connection board 1001, a control board 1002, a radiator 1003, a power board 1004, and one or more computing boards 900. The control board 1002 is connected to the computing board 900 through the connection board 1001, and the radiator 1003 is arranged around the computing board 900. The power board 1004 is used to provide power to the connection board 1001, the control board 1002, the radiator 1003 and the computing board 900.

[0150] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A voltage stabilizing circuit, characterized in that: Include: A plurality of nodes, including a first node, a second node, and a third node; an LDO voltage stabilizing unit, wherein the LDO voltage stabilizing unit is connected between the second node and the third node; a transient enhancement unit, coupled to the LDO voltage stabilizing unit, and connected between the second node and the third node; The first node is provided between the transient enhancement unit and the LDO voltage stabilizing unit. The transient enhancement unit is used to provide a feedback voltage when the voltage of the first node deviates from the reference voltage, so as to adjust the voltage of the first node to return to the reference voltage value.

2. The voltage stabilizing circuit according to claim 1, characterized in that: The plurality of nodes further include a fourth node connected to an input end of the transient enhancement unit; The LDO voltage stabilizing unit includes an error amplifier and a first switch, wherein the fourth node is provided between the output terminal of the error amplifier and the gate of the first switch; the output terminal of the error amplifier and the first switch are also connected to the first node; The transient enhancement unit provides the feedback voltage to the fourth node to adjust the output current of the first switch, so as to adjust the voltage of the first node to return to a reference voltage value.

3. The voltage stabilizing circuit according to claim 2, characterized in that: The transient enhancement unit comprises an N-stage amplifier circuit, N is greater than or equal to 1, an input end of the N-stage amplifier circuit is connected to the first node, and different stages of the N-stage amplifier circuit are inter-stage coupled and connected between the second node and the third node; The N-stage amplifier circuit provides the feedback voltage to the first node.

4. The stabilized voltage according to claim 3, characterized in that: The N-stage amplifier circuit includes a first-stage amplifier circuit, including a second switch, a third switch, and a fourth switch connected in series; the second switch is connected to the second node; The source of the third switch is connected to the first node, and the drain is connected to the fourth node; The fourth switch is connected to the third node.

5. The voltage stabilizing circuit according to claim 4, characterized in that: The second switch is a PMOS, and the third switch and the fourth switch are NMOS, or the second switch and the third switch are PMOS, and the fourth switch is NMOS; The second switch source is connected to the second node, and the fourth switch source is connected to the third node.

6. The voltage stabilizing circuit according to claim 4, characterized in that: The N-stage amplifier circuit further comprises: a second-stage amplifier circuit comprising a fifth switch, a sixth switch, and a seventh switch connected in series; The second switch and the fifth switch are connected to the second node; The third switch is connected to the sixth switch via a common gate.

7. The voltage stabilizing circuit according to claim 6, characterized in that: in, The second switch is connected with the fifth switch in cascode; The fourth switch is connected to the seventh switch in a cascode manner.

8. The voltage stabilizing circuit according to claim 6, characterized in that: When the second switch and the fifth switch are PMOS, and the third switch, the fourth switch, the sixth switch, and the seventh switch are NMOS: The gate of the fifth switch is connected to the first node and the drain of the third switch, and the fifth switch and the first switch form a current mirror; The fourth switch is connected to the seventh switch in cascode; or In the case where the fourth switch and the seventh switch select NMOS switches, and the second switch, the third switch, the fifth switch, and the sixth switch select PMOS switches: The second switch is connected with the fifth switch in cascode; The gate of the seventh switch is connected to the first node and the drain of the third switch, and the seventh switch and the first switch form a current mirror.

9. The stabilized voltage according to claim 7, characterized in that: The N-stage amplifier circuit further comprises: The third-stage amplifier circuit includes an eighth switch, a ninth switch, and a tenth switch connected in series; When the second switch, the fifth switch, and the eighth switch are PMOS, and the third switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch, and the tenth switch are NMOS: The gate of the eighth switch is connected to the fourth node and the drain of the third switch, and the eighth switch and the first switch form a current mirror; The ninth switch is connected to the sixth switch in common gate connection, and the tenth switch is connected to the seventh switch in common gate connection; or In the case where the fourth switch, the seventh switch, and the tenth switch select NMOS switches, and the second switch, the third switch, the fifth switch, the sixth switch, the eighth switch, and the ninth switch select PMOS switches: The gate of the tenth switch is connected to the fourth node and the drain of the third switch, and the eighth switch and the first switch form a current mirror; The ninth switch is connected to the sixth switch in common gate connection, and the eighth switch is connected to the fifth switch in common gate connection.

10. The stabilized voltage according to claim 4, characterized in that: The transient enhancement unit further comprises: a first capacitor connected between the first node and the source of the third switch; A second capacitor is connected between the fourth node and the drain of the third switch.

11. The voltage stabilizing circuit according to claim 2, characterized in that: The error amplifier further comprises: A third capacitor is connected between the output terminal of the error amplifier and the positive input terminal of the error amplifier, and two ends of the third capacitor are connected to the fourth node and the first node respectively.

12. The voltage stabilizing circuit according to claim 2, characterized in that: The LDO voltage stabilizing unit further comprises: A mirror current source, comprising: an eleventh switch, a drain of the eleventh switch being connected to the drain of the first switch; a twelfth switch, wherein a gate of the twelfth switch is connected to the eleventh switch in common source and gate, and a drain of the twelfth switch is connected to its own gate and the second node; A source of the eleventh switch is connected to the third node.

13. A data operation unit, comprising a control circuit, an operation circuit, a storage circuit, and one or more voltage stabilizing circuits connected to each other, characterized in that: The voltage stabilizing circuit is the voltage stabilizing circuit described in any one of claims 1-12.

14. A chip, characterized in that: The method comprises at least one data operation unit as claimed in any one of claim 13.

15. A power board used in a computing device, characterized in that: Comprising a plurality of chips described in any one of claims 14.

16. A computing device, comprising a power board, a control board, a connection board, a radiator and a plurality of computing boards, wherein the control board is connected to the computing board through the connection board, the radiator is arranged around the computing board, and the power board is used to provide power to the connection board, the control board, the radiator and the computing board, wherein: The computing board is any one of the computing boards described in claim 15.

Images