Self-modulation high-voltage linear voltage stabilizer

Abstract

The invention discloses a self-modulation high-voltage linear voltage stabilizer, through the high-voltage linear voltage stabilizer provided by the invention, the voltage end of an error amplifier is electrically connected with a voltage output port, so that the error amplifier can work under the self-modulation output voltage, the requirement on an additional pre-voltage-stabilizing module is avoided, and the self-modulation high-voltage linear voltage stabilizer has the advantages that the self-modulation high-voltage linear voltage stabilizer is simple in structure and convenient to use. And meanwhile, the number of high-voltage tubes required by the circuit is also reduced. According to the self-modulation LDO structure, under the condition that no pre-voltage-stabilizing circuit module is adopted, the number of needed high-voltage MOS tubes can be reduced, the restraining capacity of output voltage on power source changes is improved, and therefore the stability and accuracy of the output voltage are improved.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a self-modulating high-voltage linear regulator. Background Art

[0002] High-voltage linear regulators (LDOs) play a vital role in power management systems. High-voltage LDOs need to provide relatively low power supply voltages for internal modules of the chip. Typically, high-voltage LDOs not only need to adapt to a wide input voltage range, but also need to have excellent power supply rejection capabilities to minimize output voltage changes caused by input voltage fluctuations, ensuring the stability and reliability of system power supply.

[0003] The topology of existing high voltage linear regulators is as follows: Figure 1 As shown, VIN is a high-voltage power rail higher than 5V and with a wide range, and VOUT is the output voltage of the LDO. VBG is a temperature-independent bandgap reference voltage, which is usually 1.2V. The bias circuit works between VIN and GND to provide a bias voltage or current for the error amplifier. The advantage of this topology is that the structure of the LDO is simple, and only part of the low-voltage MOS tubes in the low-voltage LDO need to be replaced with high-voltage MOS tubes, which reduces the complexity of the design. However, the disadvantage is that because the error amplifier also works between the high voltage VIN and GND, many high-voltage MOS tubes are required to implement the error amplifier. The area occupied by a high-voltage MOS tube is usually dozens or even hundreds of times that of a low-voltage MOS tube with the same width-to-length ratio, which will greatly increase the area overhead of the high-voltage LDO; another topology such as Figure 2 As shown in the figure, the error amplifier of this structure no longer works directly between VIN and GND, but first generates a pre-regulated voltage of about 5V or less by the pre-regulated module directly working under VIN, and then the error amplifier works under the pre-regulated voltage. At this time, the error amplifier can be implemented by a low-voltage MOS tube, reducing the circuit area overhead. However, the disadvantage of this solution is that an additional pre-regulated circuit is required, which increases the complexity of the circuit. In addition, a Zener diode is usually required to implement a pre-regulated module, which increases the requirements for the process. Summary of the invention

[0004] The present application provides a self-modulating high-voltage linear regulator, which is used to solve the technical problems of large area and high circuit complexity of the existing high-voltage linear regulator.

[0005] In order to solve the above technical problems, the first aspect of the present application provides a self-modulating high-voltage linear regulator, including: a high-voltage input voltage, a bias circuit, an error amplifier, a power load tube, a feedback resistor network and a voltage output port, including:

[0006] The voltage terminal of the error amplifier is electrically connected to the voltage output port.

[0007] Preferably, the feedback resistor network specifically comprises: a first resistor and a second resistor connected in series.

[0008] Preferably, the bias circuit specifically comprises: 3 high-voltage PMOS tubes, 3 low-voltage PMOS tubes, a high-voltage NMOS tube (MN10), a low-voltage NMOS tube (MN9) and 3 resistance elements, wherein the 3 low-voltage PMOS tubes comprise: a low-voltage PMOS tube (MP9), a low-voltage PMOS tube (MP10) and a low-voltage PMOS tube (MP11), the 3 high-voltage PMOS tubes comprise: a high-voltage PMOS tube (MP12), a high-voltage PMOS tube (MP13) and a high-voltage PMOS tube (MP14), and the 3 resistance elements comprise: a third resistor, a fourth resistor and a fifth resistor;

[0009] The source of each low-voltage PMOS tube is connected to the high-voltage input voltage, and the drain of each low-voltage PMOS tube is connected to the source of a high-voltage PMOS tube, wherein the drain of the high-voltage PMOS tube (MP12) is connected to the drain of the high-voltage NMOS tube (MN10) through the fifth resistor, and the drains of the other two high-voltage PMOS tubes are led out as bias current output ports, wherein the two ends of the fifth resistor are respectively led out and connected to the gates of the low-voltage PMOS tube and the high-voltage PMOS tube;

[0010] The source of the high-voltage NMOS tube (MN10) is grounded via the third resistor, and the gate of the high-voltage NMOS tube (MN10) is connected to the high-voltage input voltage via the fourth resistor;

[0011] The drain of the low-voltage NMOS tube (MN9) is connected to the high-voltage input voltage via the fourth resistor, the gate of the low-voltage NMOS tube (MN9) is connected to the source of the high-voltage NMOS tube, and the source of the low-voltage NMOS tube (MN9) is grounded.

[0012] Preferably, the error amplifier specifically comprises: 7 low-voltage NMOS tubes (MN1~MN6, MN8), a high-voltage NMOS tube (MN7), 6 low-voltage PMOS tubes (MP1~MP5, MP8) and a compensation capacitor (Cc);

[0013] The gate of the low-voltage PMOS tube (MP1) is connected to the feedback resistor network, the source of the low-voltage PMOS tube (MP1) is respectively connected to the source of the low-voltage PMOS tube (MP2) and the drain of the low-voltage PMOS tube (MP8), the drain of the low-voltage PMOS tube (MP1) is connected to the drain of the low-voltage NMOS tube (MN2), and the source of the low-voltage NMOS tube (MN2) is grounded;

[0014] The gate of the low-voltage PMOS tube (MP2) is used to access the input reference voltage, the drain of the low-voltage PMOS tube (MP2) is respectively connected to the drain and gate of the low-voltage NMOS tube (MN3) and the gate of the low-voltage NMOS tube (MN4), and the source of the low-voltage NMOS tube (MN3) is grounded;

[0015] The source of the low-voltage NMOS tube (MN2) is grounded, the gates of the low-voltage NMOS tube (MN2) and the low-voltage NMOS tube (MN1) are both connected to the drain of the low-voltage PMOS tube (MP1), and the drain of the low-voltage NMOS tube (MN1) is respectively connected to the gate and drain of the low-voltage PMOS tube (MP3) and the gate of the low-voltage PMOS tube (MP4);

[0016] The source electrodes of the low voltage PMOS tube (MP3) and the low voltage PMOS tube (MP4) are connected to the first bias current output port;

[0017] The drain of the low-voltage PMOS tube (MP4) is connected to the drain of the low-voltage NMOS tube (MN4), and the source of the low-voltage NMOS tube (MN4) is grounded;

[0018] The gate of the low-voltage PMOS tube (MP5) is connected to the drain of the low-voltage PMOS tube (MP4), the source of the low-voltage PMOS tube (MP5) is connected to the first bias current output port, and the drain of the low-voltage PMOS tube (MP5) is connected to the drain of the low-voltage NMOS tube (MN5);

[0019] The source of the low-voltage PMOS tube (MP8) is connected to the first bias current output port, and the gate of the low-voltage PMOS tube (MP8) is connected to the drain of the low-voltage PMOS tube (MP8);

[0020] One end of the compensation capacitor (Cc) is connected between the drain of the low-voltage PMOS tube (MP4) and the drain of the low-voltage NMOS tube (MN4), and the other end is connected between the drain of the low-voltage PMOS tube (MP5) and the drain of the low-voltage NMOS tube (MN5);

[0021] The gate of the low-voltage NMOS tube (MN8) is connected between the drain of the low-voltage PMOS tube (MP5) and the drain of the low-voltage NMOS tube (MN5), the drain of the low-voltage NMOS tube (MN8) is connected to the voltage output port, and the source of the low-voltage NMOS tube (MN8) is grounded;

[0022] The high-voltage NMOS tube (MN7) and the low-voltage NMOS tube (MN6) are common-source and common-gate tubes; the drain of the high-voltage NMOS tube (MN7) is connected to the second bias current output port; the source of the high-voltage NMOS tube (MN7) is connected to the drain of the low-voltage NMOS tube (MN6); and the source of the low-voltage NMOS tube (MN6) is connected to the gate of the low-voltage NMOS tube (MN8).

[0023] Preferably, the power load tube is a high-voltage PMOS tube.

[0024] Preferably, the compensation capacitor is specifically a Miller compensation capacitor.

[0025] It can be seen from the above technical solutions that this application has the following advantages:

[0026] The voltage end of the error amplifier is electrically connected to the voltage output port through the high-voltage linear regulator provided by the present application, so that the error amplifier can operate under the self-modulated output voltage, which not only avoids the need for an additional pre-stabilization module, but also reduces the number of high-voltage tubes required for the circuit. The self-modulating LDO structure provided by the present application can reduce the number of required high-voltage MOS tubes without using any pre-stabilization circuit module, and improve the output voltage's ability to suppress power supply changes, thereby improving the stability and accuracy of the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0028] Figure 1 The figure is a schematic diagram of the structure of an existing high-voltage linear regulator.

[0029] Figure 2 It is a schematic diagram of the structure of another existing high-voltage linear regulator.

[0030] Figure 3 A schematic diagram of the structure of a self-modulating high-voltage linear regulator provided in this application.

[0031] Figure 4 A specific circuit diagram of an error amplifier of a self-modulating high-voltage linear regulator provided in the present application.

[0032] Figure 5 A specific circuit diagram of a bias circuit of a self-modulating high-voltage linear regulator provided in the present application.

[0033] Figure 6 This is a diagram of power supply rejection simulation results obtained based on a self-modulating high-voltage linear regulator provided in the present application.

[0034] Figure 7 The following is a linear regulation rate simulation result obtained based on a self-modulating high-voltage linear regulator provided in this application. DETAILED DESCRIPTION

[0035] The topology of existing high voltage linear regulators is as follows: Figure 1 As shown in the figure, VIN is a high voltage power rail higher than 5V and has a wide range, V OUT is the output voltage of the LDO. V BG It is a temperature-independent bandgap reference voltage, which is usually 1.2V. The bias circuit operates at V IN Between VIN and GND, a bias voltage or current is provided to the error amplifier. The advantage of this topology is that the structure of the LDO is simple. It only needs to replace a part of the low-voltage MOS tubes in the low-voltage LDO with high-voltage MOS tubes, which reduces the complexity of the design. But the disadvantage is that because the error amplifier also works between the high voltage VIN and the voltage of GND, many high-voltage MOS tubes are needed to implement the error amplifier. The area occupied by a high-voltage MOS tube is usually dozens or even hundreds of times that of a low-voltage MOS tube with the same width-to-length ratio, which will greatly increase the area overhead of the high-voltage LDO. The representative solution is a high-voltage linear regulator proposed in the patent CN103955251A. The high-voltage LDO structure proposed in this patent belongs to Figure 1 The structure shown. Because the amplifier as a whole works under a high voltage power supply, it is necessary to use a large number of high voltage tubes to implement the circuit, which increases the area cost, representing;

[0036] Another topology is Figure 2 As shown in the figure, the error amplifier of this structure no longer works directly between VIN and GND, but first generates a pre-regulated voltage of about 5V or less by the pre-regulated module working directly under VIN, and then the error amplifier works under the pre-regulated voltage. At this time, the error amplifier can be implemented by a low-voltage MOS tube, reducing the circuit area overhead. However, the disadvantage of this solution is that an additional pre-regulated circuit is required, which increases the complexity of the circuit. Moreover, a Zener diode is usually required to realize the pre-regulated module, which increases the requirements for the process. The representative solution is a high-voltage LDO circuit with a clamping current limiting function proposed in the patent CN113434002A. This solution belongs to Figure 2 The topology mentioned above uses three Zener diodes in series at the input end to reduce the input high voltage to a low voltage range. The circuit is designed with lower voltage components to achieve the purpose of simple circuit and low cost. Figure 1The structure effectively reduces the number of high-voltage tubes and the large circuit area, but it is impossible to further reduce the area.

[0037] The present application provides a self-modulating high-voltage linear regulator, which is used to solve the technical problems of large area and high circuit complexity of the existing high-voltage linear regulator.

[0038] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described below are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0040] Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] First, a detailed description of an embodiment of a self-modulating high-voltage linear regulator provided by the present application is as follows:

[0042] like Figure 3 As shown, a self-modulating high-voltage linear regulator provided in an embodiment of the present application includes: a high-voltage input voltage, a bias circuit, an error amplifier, a power load tube, a feedback resistor network and a voltage output port, including:

[0043] The voltage terminal of the error amplifier is electrically connected to the voltage output port.

[0044] Preferably, the bias circuit specifically includes: 3 high-voltage PMOS tubes, 3 low-voltage PMOS tubes, a high-voltage NMOS tube MN10, a low-voltage NMOS tube MN9 and 3 resistance elements, wherein the 3 low-voltage PMOS tubes include: a low-voltage PMOS tube MP9, a low-voltage PMOS tube MP10 and a low-voltage PMOS tube MP11, the 3 high-voltage PMOS tubes include: a high-voltage PMOS tube MP12, a high-voltage PMOS tube MP13 and a high-voltage PMOS tube MP14, and the 3 resistance elements include: a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

[0045] The source of each low-voltage PMOS tube is connected to the high-voltage input voltage, and the drain of each low-voltage PMOS tube is connected to the source of a high-voltage PMOS tube, wherein the drain of the high-voltage PMOS tube MP12 is connected to the drain of the high-voltage NMOS tube MN10 through the fifth resistor R5, and the drains of the other two high-voltage PMOS tubes are led out as bias current output ports, wherein the two ends of the fifth resistor R5 are respectively led out and connected to the gates of the low-voltage PMOS tube and the high-voltage PMOS tube;

[0046] The source of the high-voltage NMOS transistor MN10 is grounded through the third resistor R3, and the gate of the high-voltage NMOS transistor MN10 is connected to the high-voltage input voltage through the fourth resistor R4;

[0047] The drain of the low voltage NMOS tube MN9 is connected to the high voltage input voltage through the fourth resistor R4, the gate of the low voltage NMOS tube MN9 is connected to the source of the high voltage NMOS tube, and the source of the low voltage NMOS tube MN9 is grounded.

[0048] Preferably, the error amplifier specifically comprises: 7 low-voltage NMOS tubes MN1-MN6, MN8, a high-voltage NMOS tube MN7, 6 low-voltage PMOS tubes MP1-MP5, MP8 and a compensation capacitor Cc;

[0049] The gate of the low-voltage PMOS tube MP1 is connected to the feedback resistor network, the source of the low-voltage PMOS tube MP1 is respectively connected to the source of the low-voltage PMOS tube MP2 and the drain of the low-voltage PMOS tube MP8, the drain of the low-voltage PMOS tube MP1 is connected to the drain of the low-voltage NMOS tube MN2, and the source of the low-voltage NMOS tube MN2 is grounded;

[0050] The gate of the low-voltage PMOS tube MP2 is used to access the input reference voltage, the drain of the low-voltage PMOS tube MP2 is respectively connected to the drain and gate of the low-voltage NMOS tube MN3 and the gate of the low-voltage NMOS tube MN4, and the source of the low-voltage NMOS tube MN3 is grounded;

[0051] The source of the low-voltage NMOS tube MN2 is grounded, the gates of the low-voltage NMOS tube MN2 and the low-voltage NMOS tube MN1 are both connected to the drain of the low-voltage PMOS tube MP1, and the drain of the low-voltage NMOS tube MN1 is respectively connected to the gate and drain of the low-voltage PMOS tube MP3 and the gate of the low-voltage PMOS tube MP4;

[0052] The source electrodes of the low voltage PMOS tube MP3 and the low voltage PMOS tube MP4 are connected to the first bias current output port;

[0053] The drain of the low voltage PMOS tube MP4 is connected to the drain of the low voltage NMOS tube MN4, and the source of the low voltage NMOS tube MN4 is grounded;

[0054] The gate of the low-voltage PMOS tube MP5 is connected to the drain of the low-voltage PMOS tube MP4, the source of the low-voltage PMOS tube MP5 is connected to the first bias current output port, and the drain of the low-voltage PMOS tube MP5 is connected to the drain of the low-voltage NMOS tube MN5;

[0055] The source of the low-voltage PMOS tube MP8 is connected to the first bias current output port, and the gate of the low-voltage PMOS tube MP8 is connected to the drain of the low-voltage PMOS tube MP8;

[0056] One end of the compensation capacitor Cc is connected between the drain of the low-voltage PMOS tube MP4 and the drain of the low-voltage NMOS tube MN4, and the other end is connected between the drain of the low-voltage PMOS tube MP5 and the drain of the low-voltage NMOS tube MN5;

[0057] The gate of the low-voltage NMOS tube MN8 is connected between the drain of the low-voltage PMOS tube MP5 and the drain of the low-voltage NMOS tube MN5, the drain of the low-voltage NMOS tube MN8 is connected to the voltage output port, and the source of the low-voltage NMOS tube MN8 is grounded;

[0058] The high-voltage NMOS tube MN7 and the low-voltage NMOS tube MN6 are common-source and common-gate tubes. The drain of the high-voltage NMOS tube MN7 is connected to the second bias current output port, the source of the high-voltage NMOS tube MN7 is connected to the drain of the low-voltage NMOS tube MN6, and the source of the low-voltage NMOS tube MN6 is connected to the gate of the low-voltage NMOS tube MN8.

[0059] More specifically, the feedback resistor network includes: a first resistor R1 and a second resistor R2 connected in series.

[0060] More specifically, the power load is a high-voltage PMOS tube MP6.

[0061] More specifically, the compensation capacitor Cc is a Miller compensation capacitor.

[0062] It should be noted that the high voltage LDO topology structure used in the present invention is as follows: Figure 3 As shown in the figure, the bias circuit, error amplifier, power load tube M are included. POW and the feedback resistor network R 2 , R 1 . V IN is a wide range high voltage input voltage, V OUT is the output voltage of the LDO, and its specific size is determined by R 2 and R 1 In the application scenario of this embodiment, V IN The input voltage range is 7-20V, V OUT The output voltage is 5V. In the figure, the error amplifier works at the 5V output generated by self-modulation instead of working at V IN Input voltage.

[0063] Figure 4 This is a schematic diagram of the main circuit structure of the self-modulating high-voltage linear regulator provided in this application. Figure 4 The structure of the error amplifier mainly shows the connection relationship between the error amplifier and other components, such as the bias circuit, power load tube and feedback resistor network, as shown in the figure. REF The input reference voltage of the LDO can generally be a bandgap reference voltage V BG Among them, the error amplifier composed of NMOS tubes MN1~MN8, PMOS tubes MP1~MP5, MP8 and compensation capacitor Cc works at the self-modulated output voltage V OUT MN7 and MN6 are common source and common gate transistors, where MN7 is a high voltage cascode transistor, its purpose is to isolate MN6 from the high voltage power supply to prevent the low voltage MN6 from breaking down and failing. MN6 is a low voltage cascode, its purpose is to clamp and fold the small signal current output by MP5 into the current bias current I bias MP6 is a high voltage PMOS tube. This component corresponds to Figure 3 The power load tube M POW , used to provide a stronger output current capability. R 1 and R 2 The voltage divider resistor network determines V OUT The output voltage of C Miller compensation capacitor is used for frequency compensation, making the main pole of LDO located in the low frequency band and improving the stability of LDO loop.

[0064] in, Figure 4 The bias current I bias Specifically generated by the bias circuit, the circuit structure of the bias circuit of this embodiment is as follows Figure 5As shown, the bias circuit shown in the figure includes two NMOS tubes MN9 and MN10, six PMOS tubes MP9~MP14 and three resistor elements, R3~R5, among which MP12, MP13, MP14 and MN10 are high-voltage tubes LDMOS.

[0065] pass Figure 4 and Figure 5 It can be seen from the circuit structure shown that the LDO structure adopted in this embodiment only requires 6 high-voltage tubes and does not require pre-stabilization circuits such as Zener tubes, which can effectively reduce the area overhead and cost of the circuit.

[0066] like Figure 6 and Figure 7 As shown, Figure 6 This is a power supply rejection simulation result diagram based on the self-modulating high-voltage linear regulator structure of the present application. From the content in the figure, it can be seen that the self-modulating structure of the high-voltage LDO effectively improves the power supply rejection effect of the LDO. At low frequencies, the power supply rejection of the LDO is -92dB. Figure 7 This is a simulation result diagram of the linear regulation rate of the self-modulating high-voltage linear regulator structure based on the present application. From the content in the figure, it can be seen that when the high-voltage input power changes from 7-20V, the output of the LDO only changes by 330uV. Figure 6 and Figure 7 It can be seen that the self-modulating high-voltage linear regulator structure provided by the present application not only has a simple circuit structure and does not require many high-voltage LDMOS tubes to implement the circuit, but also can ensure the ability to suppress power supply changes, thereby improving the stability and accuracy of the output voltage.

[0067] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A self-modulating high-voltage linear regulator, comprising: A high voltage input voltage, a bias circuit, an error amplifier, a power load tube, a feedback resistor network and a voltage output port, characterized in that it includes: The voltage terminal of the error amplifier is electrically connected to the voltage output port.

2. A self-modulating high-voltage linear regulator according to claim 1, characterized in that: The feedback resistor network specifically includes: a first resistor and a second resistor connected in series.

3. The self-modulating high-voltage linear regulator according to claim 1, characterized in that: The bias circuit specifically comprises: 3 high-voltage PMOS tubes, 3 low-voltage PMOS tubes, a high-voltage NMOS tube (MN10), a low-voltage NMOS tube (MN9) and 3 resistance elements, wherein the 3 low-voltage PMOS tubes comprise: a low-voltage PMOS tube (MP9), a low-voltage PMOS tube (MP10) and a low-voltage PMOS tube (MP11), the 3 high-voltage PMOS tubes comprise: a high-voltage PMOS tube (MP12), a high-voltage PMOS tube (MP13) and a high-voltage PMOS tube (MP14), and the 3 resistance elements comprise: a third resistor, a fourth resistor and a fifth resistor; The source of each low-voltage PMOS tube is connected to the high-voltage input voltage, and the drain of each low-voltage PMOS tube is connected to the source of a high-voltage PMOS tube, wherein the drain of the high-voltage PMOS tube (MP12) is connected to the drain of the high-voltage NMOS tube (MN10) through the fifth resistor, and the drains of the other two high-voltage PMOS tubes are led out as bias current output ports, wherein the two ends of the fifth resistor are respectively led out and connected to the gates of the low-voltage PMOS tube and the high-voltage PMOS tube; The source of the high-voltage NMOS tube (MN10) is grounded via the third resistor, and the gate of the high-voltage NMOS tube (MN10) is connected to the high-voltage input voltage via the fourth resistor; The drain of the low-voltage NMOS tube (MN9) is connected to the high-voltage input voltage via the fourth resistor, the gate of the low-voltage NMOS tube (MN9) is connected to the source of the high-voltage NMOS tube, and the source of the low-voltage NMOS tube (MN9) is grounded.

4. The self-modulating high-voltage linear regulator according to claim 1, characterized in that: The error amplifier specifically includes: 7 low-voltage NMOS tubes (MN1~MN6, MN8), a high-voltage NMOS tube (MN7), 6 low-voltage PMOS tubes (MP1~MP5, MP8) and a compensation capacitor (Cc); The gate of the low-voltage PMOS tube (MP1) is connected to the feedback resistor network, the source of the low-voltage PMOS tube (MP1) is respectively connected to the source of the low-voltage PMOS tube (MP2) and the drain of the low-voltage PMOS tube (MP8), the drain of the low-voltage PMOS tube (MP1) is connected to the drain of the low-voltage NMOS tube (MN2), and the source of the low-voltage NMOS tube (MN2) is grounded; The gate of the low-voltage PMOS tube (MP2) is used to access the input reference voltage, the drain of the low-voltage PMOS tube (MP2) is respectively connected to the drain and gate of the low-voltage NMOS tube (MN3) and the gate of the low-voltage NMOS tube (MN4), and the source of the low-voltage NMOS tube (MN3) is grounded; The source of the low-voltage NMOS tube (MN2) is grounded, the gates of the low-voltage NMOS tube (MN2) and the low-voltage NMOS tube (MN1) are both connected to the drain of the low-voltage PMOS tube (MP1), and the drain of the low-voltage NMOS tube (MN1) is respectively connected to the gate and drain of the low-voltage PMOS tube (MP3) and the gate of the low-voltage PMOS tube (MP4); The source electrodes of the low voltage PMOS tube (MP3) and the low voltage PMOS tube (MP4) are connected to the first bias current output port; The drain of the low-voltage PMOS tube (MP4) is connected to the drain of the low-voltage NMOS tube (MN4), and the source of the low-voltage NMOS tube (MN4) is grounded; The gate of the low-voltage PMOS tube (MP5) is connected to the drain of the low-voltage PMOS tube (MP4), the source of the low-voltage PMOS tube (MP5) is connected to the first bias current output port, and the drain of the low-voltage PMOS tube (MP5) is connected to the drain of the low-voltage NMOS tube (MN5); The source of the low-voltage PMOS tube (MP8) is connected to the first bias current output port, and the gate of the low-voltage PMOS tube (MP8) is connected to the drain of the low-voltage PMOS tube (MP8); One end of the compensation capacitor (Cc) is connected between the drain of the low-voltage PMOS tube (MP4) and the drain of the low-voltage NMOS tube (MN4), and the other end is connected between the drain of the low-voltage PMOS tube (MP5) and the drain of the low-voltage NMOS tube (MN5); The gate of the low-voltage NMOS tube (MN8) is connected between the drain of the low-voltage PMOS tube (MP5) and the drain of the low-voltage NMOS tube (MN5), the drain of the low-voltage NMOS tube (MN8) is connected to the voltage output port, and the source of the low-voltage NMOS tube (MN8) is grounded; The high-voltage NMOS tube (MN7) and the low-voltage NMOS tube (MN6) are common-source and common-gate tubes; the drain of the high-voltage NMOS tube (MN7) is connected to the second bias current output port; the source of the high-voltage NMOS tube (MN7) is connected to the drain of the low-voltage NMOS tube (MN6); and the source of the low-voltage NMOS tube (MN6) is connected to the gate of the low-voltage NMOS tube (MN8).

5. The self-modulating high-voltage linear regulator according to claim 1, characterized in that: The power load tube is specifically a high-voltage PMOS tube.

6. The self-modulating high-voltage linear regulator according to claim 3, characterized in that: The compensation capacitor is specifically a Miller compensation capacitor.

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