Constant-voltage-drop large-current active inductance circuit

Abstract

The invention discloses a constant-voltage-drop large-current active inductance circuit which comprises a biasing circuit, a first-stage gain stage, a compensation stage and a second-stage gain stage. The bias circuit generates a fixed voltage difference through a bias resistor and is used for keeping a constant voltage drop of the active inductor when the loop is locked; the first gain stage is used for providing gain, so that a loop has certain precision when being locked; the compensation stage compensates the stability of the loop and is matched with the high output impedance of the first gain stage, so that the output end of the first gain stage shows inductance characteristics in a broadband range; and the second gain stage is an output stage and an active inductor, so that the current of the active inductor flows from the positive end to the negative end, thereby ensuring the normal working point of the active device. Application simplification is achieved, and particularly in a large-current application scene, the inductance effect can be achieved only by consuming small voltage drop.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a constant voltage drop and high current active inductor circuit. Background Art

[0002] like Figure 1a The inductor shown is widely used in circuits, mainly for functions including current blocking, frequency selection, and providing impedance that increases with frequency. Taking the current blocking function as an example, it is required to maintain high impedance for AC signals of a certain frequency to block the passage of high-frequency signal energy; at the same time, a certain DC current can flow through and contribute as little voltage drop as possible, that is, low impedance for low-frequency signals. Discrete passive inductor components often have large sizes, especially high-current passive inductors, which bring great integration difficulties at the application end. It is difficult for passive inductors integrated on the chip to achieve large inductance values ​​economically. Active inductors can solve the two problems of large inductance values ​​and large currents at the same time, with low cost, very high integration, and great advantages.

[0003] The traditional solution of active inductor only needs diode and large resistor to realize, such as Figure 1b As shown. Simple active inductors have many disadvantages. For example, the high impedance caused by the resistor often limits the maximum value that the impedance of the simple active inductor can reach, thereby limiting its application; for example, it limits the blocking effect on high-frequency signals in current-blocking applications. In addition, simple active inductors are different from passive inductors. Because active inductors have active circuits, their positive and negative ends (Ind_P, Ind_N) are strictly distinguished, and there must be a certain voltage drop to ensure the normal operation of the active circuit. The end with a higher potential of the active inductor may be called Ind_P, and the end with a lower potential may be called Ind_N. For example Figure 1b The simple active inductor in the figure has a gate-source voltage of one NMOS higher at the Ind_P end than at the Ind_N end during normal operation. Since the gate-source voltage of the active device changes with the current flowing through it during operation, the DC voltage drop of the simple active inductor will change significantly with the current flowing through it, which again limits the application conditions, especially in high-current application scenarios, where a large voltage drop will consume too much voltage, making it difficult to use the application under low power supply voltage conditions. Summary of the invention

[0004] The object of the present invention is to provide a constant voltage drop large current active inductor circuit to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a constant voltage drop large current active inductor circuit, comprising: A bias circuit generates a fixed voltage difference through a bias resistor, which is used to keep a constant voltage drop across the active inductor when the loop is locked; The first gain stage is used to provide gain so that the loop can be locked with a certain accuracy; The compensation stage compensates for loop stability and, in conjunction with the high output impedance of the first gain stage, makes its output exhibit inductive characteristics over a wide frequency band; The second gain stage is both an output stage and an active inductor device, which makes the current of the active inductor flow from the positive end to the negative end, thereby ensuring the normal working point of the active device.

[0006] In one embodiment, the bias circuit includes: a bias resistor Rref for fixing the active inductor voltage drop, voltage regulators MPB1 and MPB2 for adapting the static operating point of the op amp input stage, and bias current elements Ib1, Ib2, and Ib3; The first end of the bias resistor Rref is connected to the positive end Ind_P of the active circuit, and the second end is connected to the source of the voltage regulator MPB1. The gate and drain of the voltage regulator MPB1 are both grounded through the bias current element Ib1; the input end of the bias current element Ib2 is connected to the first-stage gain stage, and the output end is grounded; the input end of the bias current element Ib3 is connected to the gate and drain of the voltage regulator MPB2, and the output end is grounded; the source of the voltage regulator MPB2 is connected to the negative end Ind_N of the active circuit.

[0007] In one embodiment, the first gain stage includes: PMOS tubes MPM1 and MPM2, PMOS tubes MPC1 and MPC2, NMOS tubes MNC1 and MNC2, and NMOS tubes MIN1 and MIN2; The source of the PMOS tube MPM1 and the source of MPM2 are both connected to the positive terminal Ind_P of the active circuit, the drain of the PMOS tube MPM1 is connected to the source of the PMOS tube MPC1, and the gate is connected to the gate of the PMOS tube MPM2 and the drain of the PMOS tube MPC2 at the same time; the drain of the PMOS tube MPM2 is connected to the source of the NMOS tube MPC2, and the gate of the PMOS tube MPC1 and the gate of the PMOS tube MPC2 are interconnected; The drain of NMOS tube MNC1 is connected to the drain of PMOS tube MPC1, and the source is connected to the drain of NMOS tube MIN1; the drain of NMOS tube MNC2 is connected to the drain of PMOS tube MPC2, and the source is connected to the drain of NMOS tube MIN2; the gate of NMOS tube MNC1 and the gate of NMOS tube MNC2 are interconnected; the gate of NMOS tube MIN1 is connected to the gate of voltage regulating device MPB1, and the gate of NMOS tube MIN2 is connected to the second-stage gain stage; the source of NMOS tube MIN1 and the source of NMOS tube MIN2 are both connected to the input end of bias current element Ib2.

[0008] In one embodiment, the compensation stage consists of a capacitor C C Composition, capacitor C CThe first end is connected to the positive end Ind_P of the active circuit, and the second end is connected to the drain of the PMOS tube MPC1 and the drain of the NMOS tube MNC1 at the same time.

[0009] In one embodiment, the second gain stage includes: a PMOS tube MP2; The source of the PMOS tube MP2 is connected to the positive terminal Ind_P of the active circuit, and the gate is connected to the capacitor C C The second end of the voltage regulator is connected to the source of the voltage regulator device MPB2, and the gate and drain of the voltage regulator device MPB2 are connected to the gate of the NMOS tube MIN2 at the same time.

[0010] The present invention provides a constant voltage drop high current active inductor circuit, which realizes the simplification of application, especially in high current application scenarios, only a small voltage drop is required to achieve the inductor effect. Active devices are used to replace passive large resistors to achieve a higher impedance effect. Compared with the larger active inductor current flow capacity, the bias current of the active circuit is smaller, resulting in lower overall static power consumption. The lower DC impedance brought by the loop and the higher AC impedance brought by the active device enable the active inductor of this architecture to obtain a larger equivalent inductance than the simple active inductor, and the inductance can be adjusted according to the compensation capacitor, which is more flexible than the passive inductor when used. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1a It is a schematic diagram of the inductor structure.

[0012] Figure 1b It is a schematic diagram of a simple active inductor structure.

[0013] Figure 2 It is a schematic diagram of the structure of a constant voltage drop and high current active inductor circuit provided by the present invention. DETAILED DESCRIPTION

[0014] The following is a further detailed description of a constant voltage drop high current active inductor circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0015] The present invention provides a constant voltage drop large current active inductor circuit, the structure of which is as follows Figure 2 As shown, the voltage drop of the active inductor is locked by using closed-loop feedback; the active inductor function with a wide frequency range is realized by using a closed-loop circuit. Figure 2The circuit also realizes the equivalent inductance between the positive terminal Ind_P and the negative terminal Ind_N. However, the voltage drop between the positive terminal Ind_P and the negative terminal Ind_N is controlled at a fixed value VREF. Even when a large current flows between the positive terminal Ind_P and the negative terminal Ind_N, the voltage drop can theoretically remain basically unchanged.

[0016] The active inductor circuit comprises a bias circuit, a first gain stage, a compensation stage and a second gain stage; wherein, The bias circuit includes: bias resistor Rref for fixing the voltage drop of the active inductor, voltage regulators MPB1 and MPB2 for adapting the static operating point of the op amp input stage, and bias current elements Ib1, Ib2, and Ib3. The bias resistor Rref generates a reference voltage VREF to ensure that the active inductor maintains a constant voltage drop when the loop is locked.

[0017] The first gain stage includes: PMOS tubes MPM1 and MPM2, PMOS tubes MPC1 and MPC2, NMOS tubes MNC1 and MNC2, NMOS tubes MIN1 and MIN2. The first gain stage is used to provide gain so that the loop has a certain accuracy when locked. The first gain stage cooperates with the voltage regulator devices MPB1 and MPB2 to ensure a reasonable static operating point.

[0018] The compensation stage consists of a capacitor C C Composition to ensure loop stability.

[0019] The second output stage includes: PMOS tube MP2. Similar to an ordinary two-stage op amp, PMOS tube MP2 is used to transmit current, and bias current element Ib3 is only used to provide static bias. When the active inductor needs to flow a large current, the current will flow in from the positive terminal Ind_P and out from the negative terminal Ind_N. The large current only flows through the PMOS tube MP2 and will not flow into other devices.

[0020] The present invention uses a fixed reference voltage to lock the voltage drop of an active inductor, and uses a loop locking method to realize an active inductor with a wide frequency range.

[0021] The bias circuit uses the bias resistor Rref to generate a voltage with a fixed voltage difference VREF relative to the positive terminal Ind_P. The reference voltage is used for loop locking. After the loop is locked, a constant voltage drop is maintained between the positive terminal Ind_P and the negative terminal Ind_N. The active inductor consumes only an almost constant voltage when working, especially when working with high current. Therefore, the equivalent parasitic DC resistance is smaller when working with high current, and the transmission efficiency is higher.

[0022] The first gain stage uses a sleeve-type common source and common gate structure to provide sufficient gain for the loop. Compensation capacitors are placed at the output end of the first gain stage to compensate for the stability of the loop. At the same time, with the high output impedance of the first gain stage, its output end exhibits inductive characteristics within a wide bandwidth. The size of the output compensation capacitor of the first gain stage determines the size of the equivalent active inductance. The larger the compensation capacitor value, the larger the active inductance value. Larger active inductance values ​​often require off-chip nF or uF capacitors. Smaller inductance values ​​can often be achieved through on-chip capacitors, and the size of the equivalent active inductance value can be adjusted by controlling the size of the compensation capacitor, achieving more flexible applications.

[0023] The second-stage gain stage is both an output stage and an active inductor device. The two ports Ind_P and Ind_N of the active inductor appear at the source and drain ends of the output stage device of the second-stage gain stage respectively. The current of the active inductor also appears between these two ports. However, since the active inductor uses active devices, the direction of the active inductor current must be from the positive terminal Ind_P to the negative terminal Ind_N, so as to ensure the normal working point of the active device.

[0024] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A constant voltage drop high current active inductor circuit, characterized in that: include: A bias circuit generates a fixed voltage difference through a bias resistor, which is used to keep a constant voltage drop across the active inductor when the loop is locked; The first gain stage is used to provide gain so that the loop can be locked with a certain accuracy; The compensation stage compensates for loop stability and, in conjunction with the high output impedance of the first gain stage, makes its output exhibit inductive characteristics over a wide frequency band; The second gain stage is both an output stage and an active inductor device, which makes the current of the active inductor flow from the positive end to the negative end, thereby ensuring the normal working point of the active device.

2. The constant voltage drop high current active inductor circuit as claimed in claim 1, characterized in that: The bias circuit includes: a bias resistor Rref for fixing the active inductor voltage drop, voltage regulators MPB1 and MPB2 for adapting the static operating point of the operational amplifier input stage, and bias current elements Ib1, Ib2, and Ib3; The first end of the bias resistor Rref is connected to the positive end Ind_P of the active circuit, and the second end is connected to the source of the voltage regulator MPB1. The gate and drain of the voltage regulator MPB1 are both grounded through the bias current element Ib1; the input end of the bias current element Ib2 is connected to the first-stage gain stage, and the output end is grounded; the input end of the bias current element Ib3 is connected to the gate and drain of the voltage regulator MPB2, and the output end is grounded; the source of the voltage regulator MPB2 is connected to the negative end Ind_N of the active circuit.

3. The constant voltage drop high current active inductor circuit as claimed in claim 2, characterized in that: The first gain stage includes: PMOS tubes MPM1 and MPM2, PMOS tubes MPC1 and MPC2, NMOS tubes MNC1 and MNC2, and NMOS tubes MIN1 and MIN2; The source of the PMOS tube MPM1 and the source of MPM2 are both connected to the positive terminal Ind_P of the active circuit, the drain of the PMOS tube MPM1 is connected to the source of the PMOS tube MPC1, and the gate is connected to the gate of the PMOS tube MPM2 and the drain of the PMOS tube MPC2 at the same time; the drain of the PMOS tube MPM2 is connected to the source of the NMOS tube MPC2, and the gate of the PMOS tube MPC1 and the gate of the PMOS tube MPC2 are interconnected; The drain of NMOS tube MNC1 is connected to the drain of PMOS tube MPC1, and the source is connected to the drain of NMOS tube MIN1; the drain of NMOS tube MNC2 is connected to the drain of PMOS tube MPC2, and the source is connected to the drain of NMOS tube MIN2; the gate of NMOS tube MNC1 and the gate of NMOS tube MNC2 are interconnected; the gate of NMOS tube MIN1 is connected to the gate of voltage regulating device MPB1, and the gate of NMOS tube MIN2 is connected to the second-stage gain stage; the source of NMOS tube MIN1 and the source of NMOS tube MIN2 are both connected to the input end of bias current element Ib2.

4. The constant voltage drop high current active inductor circuit as claimed in claim 3, characterized in that: The compensation stage consists of a capacitor C C Composition, capacitor C C The first end is connected to the positive end Ind_P of the active circuit, and the second end is connected to the drain of the PMOS tube MPC1 and the drain of the NMOS tube MNC1 at the same time.

5. The constant voltage drop high current active inductor circuit as claimed in claim 4, characterized in that: The second gain stage includes: a PMOS tube MP2; The source of the PMOS tube MP2 is connected to the positive terminal Ind_P of the active circuit, and the gate is connected to the capacitor C C The second end of the voltage regulator is connected to the source of the voltage regulator device MPB2, and the gate and drain of the voltage regulator device MPB2 are connected to the gate of the NMOS tube MIN2 at the same time.

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