Method and device for emptying assembly line, processor and electronic equipment

Abstract

The invention discloses a method and device for emptying an assembly line, a processor and electronic equipment. The method for emptying the assembly line comprises the steps of obtaining a to-be-emptied instruction interval; obtaining the type and position information of each instruction in the instruction submission queue; based on the type and position information, obtaining a storage address of the instruction of the target type in the instruction interval in a memory used for an instruction submission queue; and recovering the instruction of the target type in the instruction submission queue according to the storage address. According to the method, the instruction submission queue can be read out of order to recycle the instruction, so that the pipeline emptying speed is increased.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method and device for clearing a pipeline, a processor, and an electronic device. Background Art

[0002] The processor can use pipeline technology to improve the performance of the processor in processing instructions. For example, pipeline technology allows the processor to divide the instruction processing process into multiple stages and allows the processor to process multiple instructions simultaneously to improve the instruction throughput of the processor.

[0003] When the processor uses the pipeline to process instructions, an exception may occur. Therefore, it is necessary to clear the pipeline operation to clear the instructions that have not been processed and restore the processor to the correct state to restart the processing of instructions. It can be seen that clearing the pipeline is a mechanism for the processor to handle exceptions, which can ensure the correctness of the processor's instruction processing. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a method for clearing a pipeline, the method comprising: obtaining an instruction interval to be cleared; obtaining type and position information of each instruction in an instruction submission queue; based on the type and position information, obtaining a storage address of instructions of a target type in the instruction interval in a memory used for the instruction submission queue; and according to the storage address, retrieving instructions of the target type in the instruction submission queue.

[0005] For example, in the method for clearing a pipeline provided in at least one embodiment of the present disclosure, obtaining the instruction interval to be cleared includes: obtaining the starting instruction position information and the ending instruction position information of one or more instructions to be cleared in the instruction submission queue.

[0006] For example, in the method for clearing the pipeline provided in at least one embodiment of the present disclosure, the instruction submission queue includes multiple record items respectively used for multiple instructions, and each record item includes type information of the corresponding instruction; obtaining the type and position information of each instruction in the instruction submission queue includes: using the type information of each record item in the instruction submission queue to obtain the type and position information of each instruction in the instruction submission queue.

[0007] For example, in the method for clearing a pipeline provided in at least one embodiment of the present disclosure, the memory includes multiple storage bodies; the storage address of the target type of instruction in the memory includes the corresponding storage address of the target type of instruction in the corresponding storage body.

[0008] For example, in the method for clearing the pipeline provided by at least one embodiment of the present disclosure, the reclaiming of the target type of instructions in the instruction submission queue includes: reading multiple instructions of the target type from the multiple storage bodies in the same read operation to reclaim the multiple target type of instructions.

[0009] For example, in the method for clearing a pipeline provided in at least one embodiment of the present disclosure, the reclaiming of the target type of instructions in the instruction submission queue further includes: reading multiple batches of the target type of instructions from the multiple storage bodies in multiple consecutive read operations to reclaim the multiple batches of the target type of instructions.

[0010] For example, in the method for clearing a pipeline provided in at least one embodiment of the present disclosure, the target type includes a floating-point instruction type or a fixed-point instruction type.

[0011] At least one embodiment of the present disclosure provides a device for clearing a pipeline, the device comprising: a type and position detection unit, configured to obtain type and position information of each instruction in an instruction submission queue; an address generation unit, configured to obtain an instruction interval to be cleared, and based on the type and position information, obtain a storage address of instructions of a target type in the instruction interval in a memory used for the instruction submission queue; a queue recycling unit, configured to recycle instructions of the target type in the instruction submission queue according to the storage address.

[0012] For example, in the device for clearing the pipeline provided by at least one embodiment of the present disclosure, the instruction submission queue includes multiple record items for multiple instructions respectively, and each record item includes type information of the corresponding instruction; the address generation unit is further configured to use the type information of each record item in the instruction submission queue to obtain the type and position information of each instruction in the instruction submission queue.

[0013] For example, in the device for clearing the pipeline provided in at least one embodiment of the present disclosure, the memory is also included, wherein the memory includes multiple storage bodies; the storage address of the target type of instruction in the memory includes the corresponding storage address of the target type of instruction in the corresponding storage body.

[0014] For example, in the apparatus for clearing a pipeline provided by at least one embodiment of the present disclosure, the queue recycling unit is further configured to read multiple instructions of the target type from the multiple storage bodies in the same read operation to recycle the multiple instructions of the target type.

[0015] For example, in the apparatus for clearing a pipeline provided in at least one embodiment of the present disclosure, the queue recycling unit is further configured to read multiple batches of instructions of the target type from the multiple storage bodies in multiple consecutive read operations to recycle the multiple batches of instructions of the target type.

[0016] At least one embodiment of the present disclosure provides a processor, including an instruction submission queue; an instruction submission queue controller, including: a type position detection circuit, configured to obtain type and position information of each instruction in the instruction submission queue; an address generation circuit, configured to obtain an instruction interval to be cleared in the processor, and based on the type and position information, obtain a storage address of an instruction of a target type in the instruction interval in a memory used for the instruction submission queue; a queue recycling circuit, configured to recycle instructions of the target type in the instruction submission queue according to the storage address.

[0017] At least one embodiment of the present disclosure provides an electronic device, including the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0019] Figure 1 A schematic diagram of a pipeline of a processor core;

[0020] Figure 2A A schematic diagram of an instruction submission queue;

[0021] Figure 2B A schematic diagram of an instruction submission queue sequentially retrieving floating-point instructions;

[0022] Figure 3 A schematic flow chart of a method for clearing a pipeline provided for at least one embodiment of the present disclosure;

[0023] Figure 4A A schematic diagram of an instruction submission queue provided for at least one embodiment of the present disclosure;

[0024] Figure 4B A schematic diagram of an instruction submission queue that recycles floating-point instructions out of order according to at least one embodiment of the present disclosure;

[0025] Figure 5 A schematic block diagram of a device for clearing a pipeline provided for at least one embodiment of the present disclosure;

[0026] Figure 6A schematic block diagram of a processor provided for at least one embodiment of the present disclosure; and

[0027] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0029] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0031] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0032] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0033] Processors such as CPU (Central Processing Unit) and GPU (Graphics Processing Unit) (specifically, they can be the core of the processor) can use pipeline technology to realize parallel processing of multiple instructions, and combine branch prediction, out-of-order execution and other technologies to improve the execution efficiency of the pipeline.

[0034] Figure 1 The schematic diagram of a pipeline of a processor core is shown in FIG. The dashed line with an arrow in the figure represents a redirected instruction flow.

[0035] like Figure 1 As shown, the processor core (e.g., CPU core) of a single-core processor or a multi-core processor improves instruction level parallelism through pipeline technology. The processor core includes multiple pipeline stages. For example, after the pipeline feeds program counters from various sources and selects the next program counter (PC) through a multiplexer (Mux), the instruction corresponding to the program counter must go through branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, instruction submission, etc. Waiting queues are set between each pipeline stage as needed, and these queues are usually first-in-first-out (FIFO) queues. For example, after the branch prediction unit, a branch prediction (BP) FIFO queue is set to store branch prediction results; after the instruction fetch unit, an instruction cache (IC) FIFO is set to cache the fetched instructions; after the instruction decoding unit, a decoding (DE) FIFO is set to cache the decoded instructions; after the instruction emission and renaming unit, a submission (RT) FIFO is set to cache the instructions waiting for confirmation after execution. These instructions have completed execution and are waiting to be submitted to the system status (such as updating registers, memory, etc.).

[0036] In order to support high operating frequencies, each pipeline stage may contain multiple pipeline stages (clock cycles). Although each pipeline stage performs limited operations, each clock can be minimized, thereby improving the performance of the CPU core by increasing the CPU operating frequency. Each pipeline stage can also further improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology).

[0037] The processor core translates each architecture instruction into one or more micro-instructions (micro-op, uop) within the micro-architecture. Each micro-instruction performs only limited operations, which ensures that each pipeline stage is short to increase the operating frequency of the processor core. For example, a memory read instruction (load) can be translated into an address generation micro-instruction and a memory read micro-instruction. The second micro-instruction depends on the result of the first micro-instruction, so the second micro-instruction will only start to execute after the first micro-instruction is executed. Micro-instructions contain multiple micro-architecture-related fields, which are used to pass relevant information between pipeline stages.

[0038] In a program, if two instructions access the same register or memory address, and at least one of the two instructions is a write instruction, then the two instructions are data dependent. Data dependency can be divided into three cases according to the order of reading and writing in conflicting accesses: RAW (read after write), WAW (write after write), and WAR (write after read). For RAW (read after write), the following instruction needs to use the data written by the previous instruction, which is also called true dependency; for WAW (write after write), the two instructions write the same target address, which is also called output dependency; for WAR (read after write), the following instruction overwrites the target address read by the previous instruction, which is also called anti-dependency. The possible pipeline conflicts of WAW (write after write) and WAR (read after write) can be resolved by register renaming technology. This technology does not increase the number of architectural registers in the instruction set, but redefines the physical registers (PR) inside the processor. The architectural registers defined in the instruction set are also called logical registers (LR).

[0039] Out-of-order execution (OOO) is a processor instruction execution technology that allows instructions to be executed out of the order specified in the program, thereby improving processor performance. The core of OOO is the dynamic scheduling mechanism. The processor determines the execution order of instructions based on whether the operands of the instructions are ready and whether other resources (such as execution units) are available. The reorder buffer (Re-Order Buffer) is a key structure in OOO, which is used to record the original order of instructions, save the execution results of instructions, and update the results to the system state (such as registers and memory) in the correct order during the instruction submission phase.

[0040] Speculative execution is another technique to improve processor performance. This technique executes the instructions following an instruction before it has finished executing. The branch prediction unit (branch predictor) at the front end of the processor core predicts the jump direction of the branch instruction, pre-fetches and executes the instructions in that direction; another speculative execution technique is to execute a memory read instruction before the addresses of all the previous memory write instructions are obtained. Speculative execution further improves the parallelism between instructions, thereby greatly improving the performance of the processor core. When a speculative execution error occurs, such as a branch prediction error is found, or a write instruction before the memory read instruction rewrites the same address, all instructions in the instruction submission queue after the erroneous instruction need to be flushed (or "cleared"), and then the program jumps to the error point and re-executes to ensure the correctness of the program execution. To support speculative execution, the processor core microarchitecture also needs to support the architectural register recovery mechanism to ensure that the architectural registers always have the correct value during speculative execution.

[0041] When committing (retire) after the instruction is executed, the processor can update the commit register mapping table, and record the mapping relationship between the logical register and the physical register of the committed instruction through the commit register mapping table, so that the processor can restore the correct state through the mapping relationship recorded in the commit register mapping table in an abnormal situation or other situations where rollback is required. If the instruction is executed, and the physical register guessed by the register renaming unit when the instruction is issued is correct (that is, the new physical register allocated to the instruction by the register renaming unit when the instruction is issued is correct), then when the instruction is committed, the processor can submit the mapping relationship of the instruction recorded in the guessed register mapping table to the commit register mapping table to update the commit register mapping table.

[0042] The above describes the pipeline process of the processor (i.e., the process of the processor using the pipeline to process instructions). During the pipeline process, an abnormal situation may occur in the processor and the pipeline needs to be cleared. After the pipeline is cleared, the processor is rolled back to the state before the abnormal situation occurred to restart the process of processing instructions. The processor pipeline clearing operation generally includes clearing the instructions being executed, clearing the instruction submission queue, recycling the physical registers, clearing the instruction prediction module, and restoring the guess register mapping table.

[0043] As described above, the microstructure of the processor core includes an instruction submission queue for sequential submission after out-of-order execution. The instruction submission queue caches instructions waiting for the instruction execution unit to execute instructions after the instruction is issued and renamed; the instruction submission queue is usually a first-in-first-out (FIFO) queue. The instruction submission queue stores the information of instructions that have not been submitted. Each entry of the queue can store the relevant information of an instruction, for example, the stored information includes the destination logical register of the current instruction and the corresponding old physical register and new physical register allocated for this logical register. Therefore, the instruction submission queue entry may include information such as the destination logical register, new physical register and old physical register of the current instruction. When the processor clears the pipeline, it reads the instruction submission queue sequentially, recycles one or more instructions within a predetermined range in the instruction sequence processed in the processor recorded in the instruction submission queue, that is, recycles the resources such as physical registers recorded in the record items corresponding to these instructions, and then deletes the record items of these instructions from the instruction submission queue.

[0044] For example, the instruction submission queue is implemented by a memory (such as a dynamic random access memory (DRAM)), which can be divided into multiple memory banks that can be read and written independently of each other, and the memory includes a memory bank selection logic to determine which memory bank the access request should be assigned to. For example, each memory bank has its own row address, column address and data path, and can perform read and write operations independently. For example, each memory bank includes multiple storage units, and these storage units share the same read and write port; multiple storage units of the memory can be read and written simultaneously, thereby improving the access efficiency and parallel processing capability of the memory. For example, each storage unit stores a record item of the instruction submission queue.

[0045] Figure 2A A schematic diagram of an instruction submission queue.

[0046] like Figure 2AAs shown, the memory corresponding to the instruction submission queue includes 8 memory banks (bank0 to bank7), and the address generation logic of the instruction submission queue is used to receive the starting instruction position information and the end instruction position information, and generate the storage address of the instruction to be read in each memory bank based on this information. When the instruction submission queue is clearing the pipeline, the instruction submission queue is read sequentially to recycle the instruction. First, when the processor determines to clear the pipeline, the starting instruction position information and the end instruction position information to be cleared are determined in the instruction sequence, that is, the instruction interval to be cleared is determined in the instruction sequence; the storage unit of each memory bank in the memory for the instruction submission queue stores the contents of the instruction submission queue record items to be recovered. The address generation logic generates the storage address of the instruction to be cleared in each memory bank in the memory of the instruction submission queue through the starting instruction position information and the end instruction position information, and sequentially reads the instruction submission queue to recycle the contents of the instruction queue record items corresponding to each instruction falling in the instruction interval to be cleared.

[0047] In the instruction processing process of the processor, the instruction sequence includes various types of instructions, and the instruction submission queue accordingly includes various types of instructions, such as floating-point instructions and fixed-point instructions. In the process of clearing the pipeline, there is a situation where instructions of the same type are recycled first. For example, the registers used for fixed-point instructions are located in one register file, and the registers used for floating-point instructions are located in another register file, so usually the same type of instructions are recycled in the same operation cycle or multiple consecutive operation cycles. For another example, in a multi-threaded environment, if an error occurs or is interrupted in the floating-point operation part of a thread, the processor may want to give priority to recycling the floating-point instructions in this thread, and temporarily retain the fixed-point instructions, because the fixed-point instructions may still be in the normal processing flow, or are related to other unaffected parts.

[0048] Figure 2B A schematic diagram of an instruction submission queue sequentially retrieving floating-point instructions.

[0049] like Figure 2B As shown, corresponding to Figure 2A , the memory used for the instruction submission queue includes 8 storage banks (bank0~bank7), and the current instruction submission queue includes 4*8 instruction submission queue record items to be recycled. Each instruction queue record item stores the corresponding fixed-point instruction content or floating-point instruction content, and each storage unit in each storage bank is used to store the instruction queue record item. A read operation can read the content of 1 storage unit in each of the 8 storage banks at the same time, that is, 8 instruction submission queue record items. As shown in the figure, floating-point instructions are stored in each storage bank, and the first 4 storage banks (bank0~bank4) each have a floating-point instruction, which are distributed in 4 different rows.

[0050] like Figure 2B As shown, when it is necessary to recycle floating-point instructions, the above-mentioned method of sequentially reading the instruction submission queue is adopted, that is, the above-mentioned reading operation is performed in the order of Figures 1-4, that is, to read the content of 1 row in the instruction submission queue shown in the figure, 4 reading operations are required to read all 8 floating-point instructions and complete the recycling. For example, each reading operation reads the instruction content stored in each row in each bank; the first reading operation reads 5 floating-point instructions in the first row, the second reading operation reads 1 floating-point instruction in the second row, the third reading operation reads 1 floating-point instruction in the third row, and the fourth reading operation reads 1 floating-point instruction in the fourth row. A total of 4 reading operations are required to read all floating-point instructions in the instruction submission queue.

[0051] As can be seen from the above, when instructions of the same type need to be recycled, the sequential read instruction submission queue requires multiple read operations to read all instructions of the same type, resulting in the speed of instruction recycling being unable to be improved.

[0052] The embodiment of the present disclosure provides a method and device for clearing a pipeline. The method obtains the position information of different types of instructions in the instruction submission queue and reads the instruction submission queue out of order, thereby achieving the purpose of improving the instruction recovery speed.

[0053] At least one embodiment of the present disclosure provides a method and device for clearing a pipeline, a processor, and an electronic device. The method for clearing a pipeline includes: obtaining an instruction interval to be cleared; obtaining the type and position information of each instruction in an instruction submission queue; based on the type and position information, obtaining the storage address of the target type of instruction in the instruction interval in a memory used for the instruction submission queue; and retrieving the target type of instruction in the instruction submission queue according to the storage address.

[0054] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0055] Figure 3 A schematic flowchart of a method for clearing a pipeline is provided for at least one embodiment of the present disclosure.

[0056] like Figure 3 As shown, the method for clearing a pipeline provided by this embodiment includes at least steps S10-S40.

[0057] Step S10: Obtain the instruction interval to be cleared.

[0058] For example, in the pipeline of a processor (core), each instruction in the instruction sequence is processed according to instruction fetching, decoding, execution, etc.; the instruction interval to be cleared refers to the instruction sequence interval that needs to be cleared due to instruction execution exception or branch prediction failure. Instruction execution exception refers to, for example, a calculation exception (such as division by zero error, access to illegal memory, etc.) that occurs when the processor executes instructions using the pipeline.

[0059] For example, in some embodiments, obtaining the instruction interval to be cleared includes: obtaining the starting instruction position information and the ending instruction position information of one or more instructions to be cleared in the instruction submission queue. The one or more instructions in the instruction interval to be cleared are arranged in sequence, the first instruction is the starting instruction, and the last instruction is the ending instruction; the instruction interval to be cleared includes all instructions included in the interval from the starting instruction to the ending instruction.

[0060] For example, the starting instruction position may be the position of the currently transmitted instruction, and the ending instruction position may be the position of the instruction where the instruction execution exception occurs. The instruction position information may include the relative position or absolute position of the instruction in the instruction sequence, for example, the relative position refers to the position of an instruction relative to other instructions in the instruction interval, such as an offset.

[0061] For example, the location information of the instruction can be obtained through the status information of each instruction execution of the processor, and the status information of each instruction execution can be stored in a status register or memory. For example, the status register can be used to record whether the instruction has been interrupted or abnormal; when it is determined that the pipeline needs to be cleared, it can be started from the front end of the instruction submission queue (the location of the currently emitted instruction) and searched backward in the instruction submission queue along the direction of the instruction submission queue until an instruction that has an exception or does not meet the conditions for continued execution is found. For example, the status information of the instruction execution can be stored in a specific location in the memory, and the processor can read the corresponding data through the memory address. By checking the status information of each instruction, the starting instruction location and the end instruction location can be determined.

[0062] For another example, the position information of the instruction can be obtained by indicating the pointer of the instruction stored in the instruction submission queue. For example, the instruction submission queue usually has a pointer to manage the instructions in the queue, and when the pipeline starts to be emptied, the instruction position pointed to by the head pointer can be used as a reference for the starting instruction position.

[0063] For another example, the location information of the instruction may be obtained through a hardware monitoring unit. For example, the hardware monitoring unit may record the pipeline stage where the instruction is located when the exception occurs and the instruction submission queue position corresponding to the instruction.

[0064] S20: Obtain the type and location information of each instruction in the instruction submission queue.

[0065] For example, in some embodiments, the instruction submission queue includes multiple record items for multiple instructions respectively, and each record item includes type information of the corresponding instruction. For example, the record item may include type information, opcode information, register information, execution status information, priority, and other information of the corresponding instruction. For example, 1 bit is used to record the type information, that is, the type of the recorded instruction is a floating-point instruction or a fixed-point instruction. For example, if the bit is 0, it indicates a floating-point instruction, and if it is 1, it indicates a fixed-point instruction.

[0066] For example, in some embodiments, obtaining type and position information of each instruction in the instruction submission queue includes: using type information of each record item in the instruction submission queue to obtain type and position information of each instruction in the instruction submission queue.

[0067] For example, the type and position information of the instruction may include the type of instruction and the corresponding position information in the instruction submission queue, for example, the position of the Nth record item from the head of the instruction submission queue and its corresponding instruction type (N is a positive integer).

[0068] For example, the type of each instruction in the instruction submission queue can be obtained through the flag recorded when the instruction is issued. For example, when an instruction enters the issuance queue, the instruction type can be determined according to the instruction opcode, and the corresponding flag is set, and the instruction type can be quickly determined by reading the flag.

[0069] For example, the position of each instruction in the instruction submission queue can be obtained through the sequence number field in the record item. For example, the sequence number field includes the instruction sequence number, and the instruction sequence number can be an integer counted from the beginning of a program and increases in sequence according to the order in which the instructions appear. The position information can be obtained by reading the instruction sequence number in the record item.

[0070] For example, the position of each instruction in the instruction submission queue may be obtained through the operation pointer (head pointer, tail pointer) of the instruction submission queue.

[0071] For example, the type and location information of an instruction correspond one-to-one to its record item in the instruction submission queue.

[0072] S30: Based on the type and position information, obtain the storage address of the target type of instruction in the instruction interval in the memory used for the instruction submission queue.

[0073] For example, in some embodiments, the target type includes a floating point instruction type or a fixed point instruction type.

[0074] For example, in some embodiments, the memory includes a plurality of banks, each of which includes a plurality of storage units. For example, the address space of the memory used for the instruction submission queue may be divided and mapped according to the banks, for example, each bank is responsible for a specific address range. For example, the Nth entry from the head of the instruction submission queue may be mapped to the xth storage unit in the mth bank (m and x are natural numbers).

[0075] For example, in some embodiments, the storage address of the target type instruction in the memory includes the corresponding storage address of the target type instruction in the corresponding storage bank. For example, in a memory including 8 storage banks (bank 0 to bank 7) each including 4 (or 4 rows) storage units, the storage address of an instruction of a target type of floating point type may be, for example, in the 0th storage unit in bank 0. That is, the storage address includes the serial number (column) of the storage bank and the serial number (row) in the storage bank, that is, it can be expressed as a row and column address.

[0076] S40: Retrieving instructions of the target type in the instruction submission queue according to the storage address.

[0077] For example, according to the storage address, the clear instruction submission queue operation pointer can skip non-target type instructions and directly recycle the target type instructions.

[0078] For example, recycling includes deleting instructions of the target type in the instruction submission queue, updating the operation pointers (head pointer, tail pointer) of the instruction submission queue, releasing the storage space occupied by the instruction submission queue record items, and releasing the physical registers occupied by these instructions.

[0079] For example, in some embodiments, retrieving instructions of the target type in the instruction submission queue includes: reading multiple instructions of the target type from multiple storage bodies in the same read operation to retrieve the multiple instructions of the target type. For example, the same read operation may include reading the instructions of the target type from each storage body in parallel once in one clock cycle, and the instructions of the target type read once include multiple instructions of the target type, which are also referred to as a batch of instructions of the target type.

[0080] For example, in some embodiments, retrieving instructions of the target type in the instruction submission queue further includes: reading multiple batches of instructions of the target type from multiple storage bodies in multiple consecutive read operations to retrieve the multiple batches of instructions of the target type. For example, the multiple consecutive read operations may include reading multiple batches of instructions of the target type from each storage body in parallel within multiple clock cycles, which is also referred to as multiple batches of instructions of the target type.

[0081] It should be noted that the above embodiments of the present disclosure do not limit the sequence of S10 - S40 .

[0082] Figure 4A A schematic diagram of an instruction submission queue provided for at least one embodiment of the present disclosure; Figure 4B A schematic diagram of an instruction submission queue that retrieves floating-point instructions out of order according to at least one embodiment of the present disclosure.

[0083] The following will be combined Figure 4A and Figure 4B right Figure 3 S10-S40 are further explained.

[0084] like Figure 4A As shown, the memory corresponding to the instruction submission queue includes 8 storage bodies (bank0 to bank7); the floating point fixed point position detection circuit of the instruction submission queue is used to obtain the type and position information of each instruction in the instruction submission queue to obtain the floating point instruction and the fixed point instruction position information; the address generation logic of the instruction submission queue is used to receive the starting point instruction position information and the end point instruction position information, and generate the storage address of the instruction to be read in each storage body based on the starting point instruction position information, the end point instruction position information and the above floating point instruction and fixed point instruction position information. Through step S10, the instruction interval to be cleared is obtained, that is, the starting point instruction position information and the end point instruction position information are obtained; the floating point fixed point position detection circuit of the instruction submission queue is used to implement step S20 to obtain the floating point instruction and the fixed point instruction position information. The address generation logic implements step S30 based on the starting point instruction position information, the end point instruction position information and the floating point instruction and the fixed point instruction position information to obtain the storage address of the floating point instruction or the fixed point instruction in the instruction interval in each storage body in the memory. For example, if the content of a floating-point instruction needs to be recovered, the storage address of the floating-point instruction in bank 0 to bank 7 is obtained; if the content of a fixed-point instruction needs to be recovered, the storage address of the fixed-point instruction in bank 0 to bank 7 is obtained, and the embodiments of the present disclosure do not limit this.

[0085] like Figure 4B As shown, corresponding to Figure 4A , the memory used for the instruction submission queue includes 8 storage banks (bank0 to bank7), the current instruction submission queue includes 4*8 instruction submission queue record items to be recycled, each instruction queue record item stores the corresponding fixed-point instruction content or floating-point instruction content, each storage unit in each storage bank is used to store the instruction queue record item, and a read operation can simultaneously read the content of one storage unit in each of the 8 storage banks, that is, 8 instruction submission queue record items. Figure 4BAs shown, each memory bank stores floating-point instructions, and the first four memory banks (bank0 to bank4) each have a floating-point instruction, which are distributed in four different rows.

[0086] like Figure 4B As shown, when it is necessary to recycle floating-point instructions, according to the storage addresses of floating-point instructions in bank 0 to bank 7 obtained through steps S10 to S30 of the above embodiment, when reading floating-point instructions, the pointer of the instruction submission queue operation is cleared to skip the fixed-point instructions and directly point to the position of the floating-point instructions, so that 8 floating-point instructions can be read through one read operation, and the out-of-order recycling of floating-point instructions is completed to implement step S40. For example, in one read operation, the pointer can point to the first row in bank 7 to bank 4, the fourth row in bank 3, the second row in bank 2, the third row in bank 1, and the first row in bank 0, so that all floating-point instructions in the instruction submission queue can be read with only one read operation.

[0087] Figure 5 A schematic block diagram of a device for clearing a pipeline is provided for at least one embodiment of the present disclosure.

[0088] like Figure 5 As shown, the device 100 for clearing a pipeline includes: a type position detection unit 110 , an address generation unit 120 and a queue recovery unit 130 .

[0089] For example, the type and position detection unit 110 is configured to obtain the type and position information of each instruction in the instruction submission queue.

[0090] For example, the address generation unit 120 is configured to: obtain an instruction interval to be cleared, and based on the type and location information, obtain a storage address of an instruction of a target type in the instruction interval in a memory used for an instruction submission queue.

[0091] For example, the queue recycling unit 130 is configured to: recycle instructions of the target type in the instruction submission queue according to the storage address.

[0092] For example, in some embodiments, the instruction submission queue includes multiple record items for multiple instructions respectively, and each record item includes type information of the corresponding instruction; the address generation unit 120 is further configured to: use the type information of each record item in the instruction submission queue to obtain the type and position information of each instruction in the instruction submission queue.

[0093] For example, in some embodiments, the apparatus 100 for flushing a pipeline may further include a memory 140; for example, the memory includes multiple storage bodies; the storage address of the target type of instruction in the memory includes the corresponding storage address of the target type of instruction in the corresponding storage body.

[0094] For example, in some embodiments, the queue reclaim unit 130 is further configured to read instructions of multiple target types from multiple memory banks in the same read operation to reclaim instructions of the multiple target types.

[0095] For example, in some embodiments, the queue reclaim unit 130 is further configured to read multiple batches of instructions of the target type from multiple storage banks in multiple consecutive read operations to reclaim the multiple batches of instructions of the target type.

[0096] For example, the type position detection unit 110 can be used to implement Figure 3 In step S20 shown in FIG. 1 , the address generation unit 120 may be used to implement Figure 3 In step S10 and step S30 shown in FIG. 1 , the queue recovery unit 130 may be used to implement Figure 3 Step S40 is shown. Therefore, for the specific description of the functions that can be implemented by the type position detection unit 110, the address generation unit 120 and the queue recovery unit 130, reference can be made to the relevant description of steps S10 to S40 in the above-mentioned embodiment of clearing the pipeline, and the repeated parts will not be repeated. In addition, the device 100 for clearing the pipeline can achieve a technical effect similar to that of the method for clearing the pipeline, which will not be repeated here.

[0097] It should be noted that in at least one embodiment of the present disclosure, the device 100 for clearing a pipeline may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or can be composed in other applicable ways.

[0098] Figure 6 A schematic block diagram of a processor provided for at least one embodiment of the present disclosure.

[0099] like Figure 6 As shown, the processor 200 includes an instruction submission queue 210 and an instruction submission queue controller 220 .

[0100] For example, the instruction submission queue 210 includes a plurality of record items respectively used for a plurality of instructions, and each record item includes type information of a corresponding instruction.

[0101] For example, the instruction submission queue controller may include a type detection circuit 221 , an address generation circuit 222 , and a queue recycling circuit 223 .

[0102] For example, the type detection circuit 221 is configured to obtain the type and position information of each instruction in the instruction submission queue.

[0103] For example, the address generation circuit 222 is configured to obtain an instruction interval to be cleared in the processor, and based on the type and location information, obtain a storage address of an instruction of a target type in the instruction interval in a memory used for an instruction submission queue.

[0104] For example, the queue recycling circuit 223 is configured to, based on the storage address, recycle instructions of the target type in the instruction submission queue.

[0105] For example, the processor 200 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities.

[0106] For example, in the case where the processor 200 is a central processing unit (CPU), the CPU includes a pipeline, which includes units or components such as branch prediction, instruction fetching, decoding, emission and renaming, execution unit, and instruction submission, and the instruction submission unit includes the above-mentioned instruction submission queue 210 and instruction submission queue controller 220. For example, the central processing unit (CPU) can adopt X86 architecture, ARM architecture, RISC architecture (such as RISC-V), MIPS architecture, etc. The processor 200 can be a general-purpose processor or a special-purpose processor. The processor of the embodiment of the present disclosure can be a processor of any architecture and any instruction set, and the present disclosure does not limit it.

[0107] It should be noted that the type position detection circuit 221 can be used to implement Figure 3 In step S20 shown in FIG. 1 , the address generation circuit 222 can be used to implement Figure 3 In step S10 and step S30 shown in FIG. 1 , the queue recycling circuit 223 can be used to implement Figure 3 The step S40 shown. Therefore, the specific description of the functions that can be implemented by the type position detection circuit 221, the address generation circuit 222 and the queue recycling circuit 223 can refer to the relevant description of steps S10 to S40 in the above-mentioned embodiment of clearing the pipeline, and the repeated parts will not be repeated. In addition, the processor 200 can achieve a technical effect similar to the method of clearing the pipeline, which will not be repeated here.

[0108] At least some embodiments of the present disclosure also provide an electronic device, which includes the processor of any of the above embodiments.

[0109] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0110] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The electronic device 300 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0111] For example, Figure 7 As shown, in some examples, the electronic device 300 includes a processing device 301 (e.g., a central processing unit, a graphics processing unit, etc.), which may include a processor 3011 of any of the above-mentioned embodiments, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 to a random access memory (RAM) 303. In RAM 303, various programs and data required for the operation of the computer system are also stored. The processing device 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0112] For example, the following components may be connected to the I / O interface 305: an input device 306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 309 may allow the electronic device 300 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 310 is also connected to the I / O interface 305 as needed. Removable media 311, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 310 as needed, so that the computer programs read therefrom are installed into the storage device 308 as needed. Although Figure 7 The electronic device 300 including various devices is shown, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0113] For example, the electronic device 300 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 309 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0114] For example, the electronic device 300 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0115] In addition to the above exemplary descriptions, the following points need to be explained for this disclosure:

[0116] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0117] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0118] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A method for clearing a pipeline, comprising: Get the instruction range to be cleared; Obtain the type and location information of each instruction in the instruction submission queue; Based on the type and location information, obtaining a storage address of an instruction of a target type in the instruction interval in a memory used for the instruction submission queue; Retrieving instructions of the target type from the instruction submission queue according to the storage address.

2. The method according to claim 1, wherein: The obtaining of the instruction interval to be cleared includes: The starting point instruction position information and the ending point instruction position information of one or more instructions to be cleared in the instruction submission queue are obtained.

3. The method according to claim 1, wherein: The instruction submission queue includes a plurality of record items for a plurality of instructions respectively, and each record item includes type information of a corresponding instruction; The obtaining of the type and location information of each instruction in the instruction submission queue includes: The type information of each record item in the instruction submission queue is used to obtain the type and position information of each instruction in the instruction submission queue.

4. The method according to any one of claims 1 to 3, wherein: The memory includes multiple storage bodies; the storage address of the target type of instruction in the memory includes the corresponding storage address of the target type of instruction in the corresponding storage body.

5. The method according to claim 4, wherein: The step of retrieving the target type of instruction from the instruction submission queue comprises: A plurality of instructions of the target type are read from the plurality of memory banks in a same read operation to retrieve the plurality of instructions of the target type.

6. The method according to claim 5, wherein: The step of recycling the target type of instruction in the instruction submission queue further includes: A plurality of batches of instructions of the target type are read from the plurality of memory banks in a plurality of consecutive read operations to retrieve the plurality of batches of instructions of the target type.

7. The method according to any one of claims 1 to 3, wherein: The target type includes a floating point instruction type or a fixed point instruction type.

8. A device for emptying a pipeline, comprising: A type and position detection unit, configured to obtain type and position information of each instruction in the instruction submission queue; An address generating unit is configured to obtain an instruction interval to be cleared, and based on the type and position information, obtain a storage address of an instruction of a target type in the instruction interval in a memory used for the instruction submission queue; The queue recycling unit is configured to recycle the target type of instructions in the instruction submission queue according to the storage address.

9. The device according to claim 8, wherein: The instruction submission queue includes a plurality of record items for a plurality of instructions respectively, and each record item includes type information of a corresponding instruction; The address generation unit is further configured to obtain type and position information of each instruction in the instruction submission queue using type information of each record item in the instruction submission queue.

10. The apparatus according to claim 8, further comprising the memory, wherein: The memory includes a plurality of memory banks; The storage address of the target type of instruction in the memory includes the corresponding storage address of the target type of instruction in the corresponding storage bank.

11. The device according to claim 10, wherein: The queue reclaim unit is further configured to read a plurality of instructions of the target type from the plurality of storage banks in a same read operation to reclaim the plurality of instructions of the target type.

12. The device according to claim 11, wherein The queue reclaim unit is further configured to read multiple batches of instructions of the target type from the multiple storage banks in multiple consecutive read operations to reclaim the multiple batches of instructions of the target type.

13. A processor, comprising: Command submission queue; Command submission queue controller, including: A type and position detection circuit is configured to obtain type and position information of each instruction in the instruction submission queue; The address generation circuit is configured to obtain an instruction interval to be cleared in the processor, and based on the type and location information, obtain a storage address of an instruction of a target type in the instruction interval in a memory used for the instruction submission queue; The queue recycling circuit is configured to recycle the target type of instructions in the instruction submission queue according to the storage address.

14. An electronic device comprising the processor according to claim 13.

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