Method, apparatus, processor and electronic device for clearing a pipeline

Abstract

A pipeline emptying method, device, processor and electronic device. The pipeline emptying method comprises: obtaining an instruction interval to be emptied; obtaining type and position information of each instruction in an instruction submission queue; based on the type and position information, obtaining a storage address of an instruction of a target type in the instruction interval in a memory for the instruction submission queue; and recycling the instruction of the target type in the instruction submission queue according to the storage address. The method can read the instruction submission queue out of order to recycle the instruction, thereby improving the speed of emptying the pipeline.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a method and apparatus for pipeline flush, a processor and an electronic device. BACKGROUND

[0002] A processor can use pipeline technology to improve the performance of the processor in processing instructions, for example, pipeline technology allows the processor to divide the processing of instructions into multiple stages, and allows the processor to process multiple instructions simultaneously to improve the instruction throughput of the processor.

[0003] During the processing of instructions using the pipeline, an abnormal situation can occur in the processor, and therefore a pipeline flush operation is needed to clear the instructions that have not been processed and to restore the processor to a correct state to start processing instructions again. It can be seen that pipeline flush is a mechanism for the processor to handle abnormal situations and can guarantee the correctness of the processing of instructions by the processor. SUMMARY

[0004] At least one embodiment of the present disclosure provides a method for pipeline flush, the method comprising: obtaining an instruction interval to be flushed; obtaining type and position information of each instruction in an instruction submission queue; based on the type and position information, obtaining a storage address of a target type of instruction in the instruction interval in a memory used for the instruction submission queue; and recycling the target type of instruction in the instruction submission queue according to the storage address.

[0005] For example, in the method for pipeline flush provided by at least one embodiment of the present disclosure, the obtaining of the instruction interval to be flushed comprises: obtaining start instruction position information and end instruction position information of one or more instructions to be flushed in the instruction submission queue.

[0006] For example, in the method for pipeline flush provided by at least one embodiment of the present disclosure, the instruction submission queue comprises a plurality of record items respectively for a plurality of instructions, each record item comprising type information of a corresponding instruction; and the obtaining of the type and position information of each instruction in the instruction submission queue comprises: using the type information of each record item in the instruction submission queue to obtain the type and position information of each instruction in the instruction submission queue.

[0007] For example, in the method for pipeline flush provided by at least one embodiment of the present disclosure, the memory comprises a plurality of storage banks; and the storage address of the target type of instruction in the memory comprises a corresponding storage address of the target type of instruction in a corresponding storage bank.

[0008] For example, in the method for emptying the pipeline provided in at least one embodiment of the present disclosure, the recycling of the instructions of the target type in the instruction submission queue comprises: reading a plurality of instructions of the target type from the plurality of storage banks in a same read operation to recycle the plurality of instructions of the target type.

[0009] For example, in the method for emptying the pipeline provided in at least one embodiment of the present disclosure, the recycling of the instructions of the target type in the instruction submission queue further comprises: reading a plurality of batches of instructions of the target type from the plurality of storage banks in a plurality of continuous read operations to recycle the plurality of batches of instructions of the target type.

[0010] For example, in the method for emptying the pipeline provided in at least one embodiment of the present disclosure, the target type comprises a floating-point instruction type or a fixed-point instruction type.

[0011] At least one embodiment of the present disclosure provides a device for emptying a pipeline, the device comprising: a type and position detection unit configured to obtain type and position information of each instruction in an instruction submission queue; an address generation unit configured to obtain an instruction interval to be emptied, and obtain storage addresses of instructions of a target type in the instruction interval in a memory for the instruction submission queue based on the type and position information; and a queue recycling unit configured to recycle the instructions of the target type in the instruction submission queue according to the storage addresses.

[0012] For example, in the device for emptying the pipeline provided in at least one embodiment of the present disclosure, the instruction submission queue comprises a plurality of record items respectively for a plurality of instructions, and each record item comprises type information of a corresponding instruction; and the address generation unit is further configured to obtain the type and position information of each instruction in the instruction submission queue using the type information of each record item in the instruction submission queue.

[0013] For example, in the device for emptying the pipeline provided in at least one embodiment of the present disclosure, the device further comprises the memory, wherein the memory comprises a plurality of storage banks; and the storage addresses of the instructions of the target type in the memory comprise corresponding storage addresses of the instructions of the target type in corresponding storage banks.

[0014] For example, in the device for emptying the pipeline provided in at least one embodiment of the present disclosure, the queue recycling unit is further configured to read a plurality of instructions of the target type from the plurality of storage banks in a same read operation to recycle the plurality of instructions of the target type.

[0015] For example, in the device for emptying the pipeline provided by at least one embodiment of the present disclosure, the queue recovery unit is further configured to read multiple batches of instructions of the target type from the multiple memory banks in multiple continuous read operations to recover the multiple batches of instructions of the target type.

[0016] At least one embodiment of the present disclosure provides a processor, comprising an instruction submission queue; an instruction submission queue controller, comprising: a type position detection circuit configured to obtain type and position information of each instruction in the instruction submission queue; an address generation circuit configured to obtain an instruction interval to be emptied in the processor, and obtain a storage address of an instruction of a target type in a memory for the instruction submission queue based on the type and position information; and a queue recovery circuit configured to recover the instruction of the target type in the instruction submission queue according to the storage address.

[0017] At least one embodiment of the present disclosure provides an electronic device comprising the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0019] Figure 1 A schematic diagram of a pipeline of a processor core;

[0020] Figure 2A A schematic diagram of an instruction submission queue;

[0021] Figure 2B A schematic diagram of sequentially recovering a floating point instruction in an instruction submission queue;

[0022] Figure 3 A schematic flow chart of a method for emptying a pipeline provided by at least one embodiment of the present disclosure;

[0023] Figure 4A A schematic diagram of an instruction submission queue provided by at least one embodiment of the present disclosure;

[0024] Figure 4B A schematic diagram of out-of-order recovering a floating point instruction in an instruction submission queue provided by at least one embodiment of the present disclosure;

[0025] Figure 5 A schematic block diagram of a device for emptying a pipeline provided by at least one embodiment of the present disclosure;

[0026] Figure 6a schematic block diagram of a processor provided for at least one embodiment of the present disclosure; and

[0027] Figure 7 a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with specific embodiments thereof, it will be understood that no limitation intended thereon is meant by the description itself nor by the drawings, which are meant to provide illustrations of examples of the present disclosure. That is, specific embodiments are examples used to enable those of ordinary skill in the art to better understand the benefits and advantages of the present disclosure and to put the present disclosure into practical use. It will be understood that the drawings are not intended to limit the concept of the present disclosure to any particular, but are merely meant to be illustrative and an aid to understanding the present disclosure.

[0029] In order for those skilled in the art to better understand the present disclosure, the present disclosure will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] Note that the examples to be introduced next are merely specific examples, and are not intended to limit the embodiments of the present disclosure to specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can construct more embodiments not mentioned in the present specification by reading the present specification using the concept of the present disclosure.

[0031] The terms used in the present disclosure are those general terms currently widely used in consideration of functions in the art, but these terms can vary according to the intention of those skilled in the art, precedents, or new technology in the art. Also, specific terms can be chosen by the applicant, and in this case, the detailed meaning thereof will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should be understood not as simple names but based on the meaning of the terms and the overall description of the present disclosure.

[0032] Flowcharts have been used in the present disclosure to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the foregoing or following operations are not necessarily performed in the order as it is. Rather, various steps can be processed in reverse order or at the same time, as needed. Also, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0033] Processors such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units) (specifically, processor cores) can use pipelining technology to achieve parallel processing of multiple instructions, and combine this with techniques such as branch prediction and out-of-order execution to improve the execution efficiency of the pipeline.

[0034] Figure 1 This is a schematic diagram of a processor core pipeline. The dashed lines with arrows in the diagram represent redirected instruction flows.

[0035] like Figure 1 As shown, processor cores (such as CPU cores) in single-core or multi-core processors improve instruction-level parallelism through pipeline technology. The processor core internally includes multiple pipeline stages. For example, after program counters from various sources are fed into the pipeline, a multiplexer (Mux) selects the next program counter (PC). The instruction corresponding to that program counter then undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retire. Waiting queues are set up between each pipeline stage as needed; these queues are typically first-in-first-out (FIFO) queues. For example, after the branch prediction unit, a branch prediction (BP) FIFO queue is set up to store the branch prediction results; after the instruction fetch unit, an instruction cache (IC) FIFO is set up to cache the fetched instructions; after the instruction decode unit, a decode (DE) FIFO is set up to cache the decoded instructions; after the instruction issue and rename unit, a commit (RT) FIFO is set up to cache instructions that have been executed and are waiting for confirmation of completion. These instructions have been completed and are waiting to be committed to the system state (such as updating registers, memory, etc.).

[0036] To support high operating frequencies, each pipeline stage may contain multiple pipeline stages (clock cycles). Although each pipeline stage performs a limited number of operations, this minimizes the time per clock cycle, thereby increasing the CPU core's performance by raising the CPU's operating frequency. Each pipeline stage can also further enhance processor core performance by accommodating more instructions (i.e., superscalar technology).

[0037] A processor core translates each architectural instruction into one or more micro-ops (uops) within the micro-architecture, each of which performs a limited number of operations, which allows for very short pipelines to increase the core's operating frequency. For example, a memory load instruction can be translated into an address generation uop and a memory read uop, the second of which depends on the results of the first. Thus, the second uop cannot begin execution until the first has completed. The uops contain micro-architectural dependent fields to pass information between the stages of the pipeline.

[0038] In a program, two instructions are data dependent if they access the same register or memory location and at least one of the two instructions is a write instruction. Data dependencies can be classified into three cases according to the order of read and write in the conflicting access: RAW (read after write), WAW (write after write), and WAR (write after read). For RAW (read after write), the later instruction needs to use the data written by the former, which is called a true dependency. For WAW (write after write), two instructions write to the same location, which is called an output dependency. For WAR (write after read), the later instruction overwrites the data read by the former, which is called an anti-dependency. WAW (write after write) and WAR (write after read) can be resolved by register renaming, which does not increase the number of architectural registers in the instruction set, but redefines the physical registers (PRs) within the processor. The architectural registers defined in the instruction set are also called logical registers (LRs).

[0039] Out-of-Order Execution is a technique for executing instructions in a processor, which allows instructions to be executed out of the order specified in the program, improving the performance of the processor. The core of Out-of-Order Execution is the dynamic scheduling mechanism. The processor decides the order of execution of instructions based on whether the operands are ready and other resources (such as execution units) are available. The Re-Order Buffer (ROB) is a key structure in Out-of-Order Execution, which records the original order of instructions, saves the results of the execution of instructions, and updates the results to the system state (such as registers and memory) in the correct order during the instruction commit stage.

[0040] Speculative execution is another technique to improve the performance of a processor. This technique executes instructions following a given instruction before the given instruction is completed. A branch prediction unit (branch predictor) in the front end of a processor core predicts the direction of a branch instruction, prefetches and executes instructions in the predicted direction. Another technique of speculative execution is to execute a memory read instruction before the addresses of all preceding memory write instructions are known. Speculative execution further improves the instruction level parallelism, and thus greatly improves the performance of a processor core. When a speculative execution error occurs, such as a branch prediction error, or a memory read instruction is preceded by a write instruction that overwrites the same address, all instructions in the instruction commit queue following the erroneous instruction need to be flushed, and the program jumps back to the error point to re-execute, in order to ensure the correctness of the program execution. To support speculative execution, the micro-architecture of a processor core also needs to support an architectural register recovery mechanism to ensure that the architectural registers always have correct values during speculative execution.

[0041] When an instruction is retired after the instruction is completed, the processor can update the commit register mapping table to record the mapping relationship between the logical registers and the physical registers of the retired instruction, so that the processor can recover the correct state through the mapping relationship recorded in the commit register mapping table in the case of an exception or other rollback cases. If an instruction is completed and the physical register guessed by the register renaming unit at the time of instruction issue is correct (i.e., the new physical register allocated by the register renaming unit to the instruction at the time of instruction issue is correct), the processor can update the commit register mapping table by committing the mapping relationship of the instruction recorded in the guessed register mapping table to the commit register mapping table at the time of instruction retirement.

[0042] The above describes the pipeline process of a processor (i.e., the process in which the processor processes instructions using a pipeline), and the processor can empty the pipeline in the pipeline process due to an exception, and then roll back to the state before the exception occurs after emptying the pipeline to start the process of processing instructions again. The processor pipeline emptying operation generally includes emptying the executing instructions, emptying the instruction commit queue, recycling the physical registers, emptying the instruction prediction module, and restoring the guessed register mapping table.

[0043] As mentioned above, the micro-architecture of the processor core includes an instruction commit queue for in-order commit after out-of-order execution, which buffers the pending instructions for execution by the instruction execution unit after instruction issue and renaming; the instruction commit queue is usually a first-in-first-out (FIFO) queue. The instruction commit queue stores the information of the instructions that have not been committed, each entry of the queue can store the information of one instruction, for example, the information stored includes the destination logical register of the current instruction and the corresponding old and new physical registers allocated for the logical register. Therefore, the instruction commit queue entry can include the information of the destination logical register, the new physical register and the old physical register of the current instruction. When the processor clears the pipeline, the processor sequentially reads the instruction commit queue, recycles one or more instructions within a predetermined range in the sequence of instructions processed in the processor from the instruction commit queue entry, i.e. recycles the physical registers recorded in the corresponding entry of the instructions and then deletes the entry of the instructions from the instruction commit queue.

[0044] For example, the instruction commit queue is implemented by a memory (e.g. dynamic random access memory (DRAM)), which can be divided into a plurality of banks that can be independently read and written, the memory includes bank selection logic to determine to which bank the access request should be allocated. For example, each bank has its own row address, column address and data path, and can independently perform read and write operations, for example, each bank includes a plurality of memory cells that share the same read and write port; the memory can perform read and write operations on a plurality of banks simultaneously, thus improving the access efficiency and parallel processing capability of the memory. For example, each memory cell stores one entry of the instruction commit queue.

[0045] Figure 2A A schematic diagram of an instruction commit queue.

[0046] As Figure 2AAs shown, the memory corresponding to the instruction submission queue includes eight memory banks (bank0 to bank7). The address generation logic of the instruction submission queue receives the start instruction location information and the end instruction location information, and generates the storage address of the instruction to be read in each memory bank based on this information. When the instruction submission queue is clearing the pipeline, it sequentially reads the instruction submission queue to reclaim instructions. First, when the processor determines that it needs to clear the pipeline, it determines the start instruction location information and the end instruction location information to be cleared in the instruction sequence, that is, it determines the instruction range to be cleared in the instruction sequence. Each memory bank in the memory used for the instruction submission queue stores the contents of the instruction submission queue record entries to be reclaimed. The address generation logic generates the storage address of the instruction to be cleared in the instruction submission queue memory in each memory bank using the start instruction location information and the end instruction location information, and sequentially reads the instruction submission queue to reclaim the contents of the instruction queue record entries corresponding to each instruction falling within the instruction range to be cleared.

[0047] During processor instruction processing, the instruction sequence includes various types of instructions, and correspondingly, the instruction submission queue includes various types of instructions, such as floating-point instructions and fixed-point instructions. During pipeline cleanup, there is a tendency to prioritize the reclamation of instructions of the same type. For example, registers used for fixed-point instructions may reside in one register file, while registers used for floating-point instructions may reside in another. Therefore, instructions of the same type are typically reclaimed within the same operation cycle or multiple consecutive operation cycles. Furthermore, in a multi-threaded environment, if an error occurs or is interrupted in the floating-point operation section of a thread, the processor may prefer to prioritize the reclamation of floating-point instructions in that thread, while temporarily retaining fixed-point instructions, because fixed-point instructions may still be in the normal processing flow or related to other unaffected parts.

[0048] Figure 2B This is a schematic diagram illustrating the sequential recycling of floating-point instructions in an instruction submission queue.

[0049] like Figure 2B As shown, corresponding to Figure 2A The memory used for the instruction submission queue consists of eight memory banks (bank0 to bank7). The current instruction submission queue includes 4*8 instruction submission queue entries awaiting recycling. Each instruction queue entry stores the corresponding fixed-point instruction or floating-point instruction content. Each storage unit in each memory bank is used to store the instruction queue entry. A single read operation can simultaneously read the contents of one storage unit from each of the eight memory banks, i.e., eight instruction submission queue entries. As shown in the figure, each memory bank stores floating-point instructions, and the first four memory banks (bank0 to bank4) each contain one floating-point instruction, distributed across four different rows.

[0050] As shown in Figure 2B When the floating-point instructions need to be recycled, the above method of sequentially reading the instruction submission queue is adopted, that is, the above reading operation is performed in the order shown in FIG. 1-4, that is, to read the contents of row 1 in the illustrated instruction submission queue, 4 reading operations are needed to read all 8 floating-point instructions and complete recycling. For example, each reading operation is to read the instruction contents stored in each row in each bank; the first reading operation reads 5 floating-point instructions in row 1, the second reading operation reads 1 floating-point instruction in row 2, the third reading operation reads 1 floating-point instruction in row 3, and the fourth reading operation reads 1 floating-point instruction in row 4, a total of 4 reading operations are needed to read all floating-point instructions in the instruction submission queue.

[0051] As can be seen from the above, in the case of recycling the same type of instructions, the sequential reading of the instruction submission queue requires multiple reading operations to read all the same type of instructions, which cannot improve the speed of instruction recycling.

[0052] Embodiments of the present disclosure provide a method and device for emptying a pipeline. The method obtains position information of different types of instructions in an instruction submission queue, and reads the instruction submission queue out of order to improve the speed of instruction recycling.

[0053] At least one embodiment of the present disclosure provides a method and device for emptying a pipeline, a processor and an electronic device. The method for emptying the pipeline comprises: obtaining an instruction interval to be emptied; obtaining type and position information of each instruction in the instruction submission queue; based on the type and position information, obtaining a storage address of the instruction of a target type in the instruction interval in a memory for the instruction submission queue; and recycling the instruction of the target type in the instruction submission queue according to the storage address.

[0054] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0055] Figure 3 A method for emptying a pipeline provided by at least one embodiment of the present disclosure is shown in a schematic flowchart.

[0056] As shown in Figure 3 The method for emptying a pipeline provided by the embodiment at least includes steps S10-S40.

[0057] Step S10: obtaining an instruction interval to be emptied.

[0058] For example, in the pipeline of a processor (core), each instruction in an instruction sequence is processed in the order of fetching, decoding, executing, etc.; the instruction interval to be emptied is an instruction sequence interval that needs to be emptied due to an instruction execution exception or a branch prediction failure. The instruction execution exception is, for example, a calculation exception (such as a division by zero error, an illegal memory access, etc.) that occurs in the process of executing instructions using the pipeline.

[0059] For example, in some embodiments, obtaining the instruction interval to be emptied includes obtaining start instruction position information and end instruction position information of one or more instructions to be emptied in the instruction commit queue. The one or more instructions in the instruction interval to be emptied are arranged in sequence, with the first instruction being the start instruction and the last instruction being the end instruction; the instruction interval to be emptied includes all instructions from the start instruction to the end instruction.

[0060] For example, the start instruction position can be the position of the currently emitted instruction, and the end instruction position can be the position of the instruction where the instruction execution exception occurs. The instruction position information can include the relative position or absolute position of the instruction in the instruction sequence, etc. For example, the relative position refers to the position of an instruction relative to other instructions in the instruction interval, such as an offset, etc.

[0061] For example, the position information of the instruction can be obtained by the state information of each instruction execution of the processor, and the state information of each instruction execution can be stored in a state register or a memory. For example, the state register can be used to record whether an interrupt or exception has occurred for the instruction; when it is determined that the pipeline needs to be emptied, the instruction commit queue can be searched backward from the front end of the instruction commit queue (the position of the currently emitted instruction) until the instruction where the exception occurs or the instruction that does not meet the condition for continuing execution is found. For example, the state information of the instruction execution can be stored in a specific location of the memory, and the processor can read the corresponding data through the memory address. By checking the state information of each instruction, the start instruction position and the end instruction position can be determined.

[0062] For another example, the position information of the instruction can be obtained by a pointer indicating the storage of the instruction in the instruction commit queue. For example, the instruction commit queue usually has a pointer to manage the instructions in the queue, and when the pipeline is started to be emptied, the instruction position pointed to by the head pointer can be used as a reference for the start instruction position.

[0063] For another example, the position information of the instruction can be obtained by a hardware monitoring unit. For example, the hardware monitoring unit can record the pipeline stage where the instruction is located when the exception occurs and the instruction commit queue position corresponding to the instruction.

[0064] S20: Obtain the type and position information of each instruction in the instruction commit queue.

[0065] For example, in some embodiments, the instruction submission queue includes a plurality of record items for a plurality of instructions respectively, each record item including type information of the corresponding instruction. For example, the record item can include type information, operation code information, register information, execution state information, priority information, etc. of the corresponding instruction. For example, 1 bit is used to record the type information, i.e. to record the type of the instruction is a floating point instruction or a fixed point instruction, for example, the bit is 0 for a floating point instruction and 1 for a fixed point instruction.

[0066] For example, in some embodiments, the type and position information of each instruction in the instruction submission queue is obtained by using the type information of each record item in the instruction submission queue.

[0067] For example, the type and position information of the instruction can include the type of the instruction and the corresponding position information in the instruction submission queue, for example, the position of the Nth record item from the head of the instruction submission queue and the corresponding instruction type (N is a positive integer).

[0068] For example, the type of each instruction in the instruction submission queue can be obtained by a flag bit recorded when the instruction is launched. For example, when the instruction enters the launch queue, the type of the instruction can be determined according to the operation code of the instruction, and the corresponding flag bit is set, and the type of the instruction can be quickly determined by reading the flag bit.

[0069] For example, the position of each instruction in the instruction submission queue can be obtained by a serial number field in the record item. For example, the serial number field includes an instruction serial number, which can be an integer counted from a certain program start, and sequentially increased according to the order of the instruction, and the position information can be obtained by reading the instruction serial number in the record item.

[0070] For example, the position of each instruction in the instruction submission queue can be obtained by the operation pointer (head pointer, tail pointer) of the instruction submission queue.

[0071] For example, the type and position information of the instruction corresponds to the record item of the instruction in the instruction submission queue one by one.

[0072] S30: Based on the type and position information, obtain the storage address of the instruction of the target type in the instruction interval in the memory for the instruction submission queue.

[0073] For example, in some embodiments, the target type includes a floating point instruction type or a fixed point instruction type.

[0074] For example, in some embodiments, the memory includes a plurality of banks, each bank including a plurality of storage units. For example, the address space of the memory for the instruction commit queue is partitioned and mapped according to the banks, e.g., each bank is responsible for a specific range of addresses. For example, the Nth record item from the head of the instruction commit queue can be mapped to the xth storage unit in the mth bank (m and x are natural numbers).

[0075] For example, in some embodiments, the storage address of the target type of instruction in the memory includes the corresponding storage address of the target type of instruction in the corresponding bank. For example, in a memory including 8 banks (bank 0~bank 7) each bank including 4 (or 4 rows) storage units, the storage address of a target type of instruction, e.g., a floating point type of instruction, can be in the 0th storage unit in bank 0. That is, the storage address includes the serial number (column) of the bank and the serial number (row) in the bank, i.e., can be expressed as a row-column address.

[0076] S40: according to the storage address, recycling the target type of instruction in the instruction commit queue.

[0077] For example, according to the storage address, the emptying instruction commit queue operation pointer can skip the non-target type of instruction and directly recycle the target type of instruction.

[0078] For example, recycling includes deleting the target type of instruction in the instruction commit queue, updating the operation pointer (head pointer, tail pointer) of the instruction commit queue, releasing the storage space occupied by the instruction commit queue record item, and the like, and releasing the physical register occupied by the instruction, and the like.

[0079] For example, in some embodiments, recycling the target type of instruction in the instruction commit queue includes: reading a plurality of target type of instructions from a plurality of banks in the same read operation to recycle a plurality of target type of instructions. For example, the same read operation can include reading a target type of instruction from each bank once in parallel within one clock cycle, and the above-mentioned once read target type of instruction includes a plurality of target type of instructions, also known as a batch of target type of instructions.

[0080] For example, in some embodiments, recycling the target type of instruction in the instruction commit queue further includes: reading a plurality of batches of target type of instructions from a plurality of banks in a plurality of consecutive read operations to recycle a plurality of batches of target type of instructions. For example, the plurality of consecutive read operations can include reading a plurality of times of target type of instructions from each bank in parallel within a plurality of clock cycles, also known as a plurality of batches of target type of instructions.

[0081] It should be noted that the above embodiments of this disclosure do not impose any restrictions on the order of S10-S40.

[0082] Figure 4A A schematic diagram of an instruction submission queue provided for at least one embodiment of this disclosure; Figure 4B This is a schematic diagram illustrating the out-of-order reclamation of floating-point instructions in the instruction submission queue, provided for at least one embodiment of this disclosure.

[0083] The following will combine Figure 4A and Figure 4B right Figure 3 Further explanation is provided for S10-S40.

[0084] like Figure 4A As shown, the memory corresponding to the instruction submission queue includes 8 memory banks (bank0 to bank7). The instruction submission queue floating-point and fixed-point location detection circuit is used to obtain the type and location information of each instruction in the instruction submission queue, so as to obtain the location information of floating-point instructions and fixed-point instructions. The address generation logic of the instruction submission queue is used to receive the start instruction location information and the end instruction location information, and generate the storage address of the instruction to be read in each memory bank based on the start instruction location information, the end instruction location information, and the above floating-point instruction and fixed-point instruction location information. Through step S10, the instruction range to be cleared is obtained, that is, the start instruction location information and the end instruction location information are obtained. The instruction submission queue floating-point and fixed-point location detection circuit is used to implement step S20 to obtain the location information of floating-point instructions and fixed-point instructions. The address generation logic implements step S30 based on the start instruction location information, the end instruction location information, and the location information of floating-point instructions and fixed-point instructions, so as to obtain the storage address of the floating-point instruction or fixed-point instruction in each memory bank in the memory. For example, if it is necessary to reclaim the contents of floating-point instructions, the storage addresses of the floating-point instructions in banks 0 to 7 are obtained; if it is necessary to reclaim the contents of fixed-point instructions, the storage addresses of the fixed-point instructions in banks 0 to 7 are obtained. The embodiments of this disclosure do not limit this.

[0085] like Figure 4B As shown, corresponding to Figure 4A The memory used for the instruction submission queue includes eight memory banks (bank0 to bank7). The current instruction submission queue includes 4*8 instruction submission queue records to be reclaimed. Each instruction queue record stores the corresponding fixed-point instruction content or floating-point instruction content. Each storage unit in each memory bank is used to store the instruction queue record. A single read operation can read the contents of one storage unit from each of the eight memory banks simultaneously, that is, the contents of all eight instruction submission queue records. Figure 4BAs shown, each memory bank stores a floating-point instruction, and the first four memory banks (bank0 to bank4) each have one floating-point instruction, which are distributed in four different rows.

[0086] like Figure 4B As shown, when it is necessary to reclaim floating-point instructions, based on the storage addresses of the floating-point instructions in banks 0 to 7 obtained through steps S10 to S30 of the above embodiments, when reading floating-point instructions, the instruction submission queue operation pointer is cleared, skipping fixed-point instructions and directly pointing to the location of the floating-point instructions. In this way, all 8 floating-point instructions can be read in one read operation, completing the out-of-order reclamation of floating-point instructions to achieve step S40. For example, in one read operation, the pointer can point to the first row in banks 7 to 4, the fourth row in bank 3, the second row in bank 2, the third row in bank 1, and the first row in bank 0, respectively. Thus, all floating-point instructions in the instruction submission queue can be read in only one read operation.

[0087] Figure 5 A schematic block diagram of an apparatus for emptying a production line, provided for at least one embodiment of the present disclosure.

[0088] like Figure 5 As shown, the device 100 for clearing the pipeline includes: a type location detection unit 110, an address generation unit 120, and a queue recycling unit 130.

[0089] For example, the type and position detection unit 110 is configured to: obtain the type and position information of each instruction in the instruction submission queue.

[0090] For example, the address generation unit 120 is configured to: obtain the instruction range to be cleared, and based on type and location information, obtain the storage address of the instruction of the target type in the instruction range in the memory used for the instruction submission queue.

[0091] For example, queue reclamation unit 130 is configured to reclaim instructions of the target type from the instruction submission queue based on the storage address.

[0092] For example, in some embodiments, the instruction submission queue includes multiple record items for multiple instructions, each record item including type information of the corresponding instruction; the address generation unit 120 is further configured to: use the type information of each record item in the instruction submission queue to obtain the type and position information of each instruction in the instruction submission queue.

[0093] For example, in some embodiments, the apparatus 100 for emptying the pipeline can further include a memory 140; for example, the memory includes a plurality of memory banks; the storage address of the instructions of the target type in the memory includes the corresponding storage address of the instructions of the target type in the corresponding memory bank.

[0094] For example, in some embodiments, the queue recycling unit 130 is further configured to read the plurality of instructions of the target type from the plurality of memory banks in the same read operation to recycle the plurality of instructions of the target type.

[0095] For example, in some embodiments, the queue recycling unit 130 is further configured to read the plurality of batches of instructions of the target type from the plurality of memory banks in a plurality of continuous read operations to recycle the plurality of batches of instructions of the target type.

[0096] For example, the type location detection unit 110 can be configured to implement Figure 3 The address generation unit 120 can be configured to implement Figure 3 The queue recycling unit 130 can be configured to implement Figure 3 The steps S40. Therefore, the specific description of the functions that can be implemented by the type location detection unit 110, the address generation unit 120, and the queue recycling unit 130 can refer to the related description of steps S10 to S40 in the above-mentioned embodiments of emptying the pipeline, and the repeated parts will not be described here. In addition, the apparatus 100 for emptying the pipeline can achieve similar technical effects as the method of emptying the pipeline, which will not be described here.

[0097] It should be noted that, in at least one embodiment of the present disclosure, the apparatus 100 for emptying the pipeline can include more or fewer circuits or units, and the connection relationship between the circuits or units is not limited, and can be determined according to actual needs. The specific constituting mode of each circuit or unit is not limited, which can be constituted by analog devices according to the circuit principle, or can be constituted by digital chips, or constituted in other applicable ways.

[0098] Figure 6 A schematic block diagram of a processor provided for at least one embodiment of the present disclosure.

[0099] As Figure 6 The processor 200 includes an instruction submission queue 210 and an instruction submission queue controller 220.

[0100] For example, the instruction submission queue 210 includes a plurality of record items for a plurality of instructions respectively, and each record item includes type information of the corresponding instruction.

[0101] For example, the instruction submission queue controller can include a type detection circuit 221, an address generation circuit 222, and a queue recycling circuit 223.

[0102] For example, the type detection circuit 221 is configured to obtain type and position information of each instruction in the instruction submission queue.

[0103] For example, the address generation circuit 222 is configured to obtain an instruction range to be emptied in the processor, and obtain a storage address of an instruction of a target type in the instruction range in a memory for the instruction submission queue based on the type and position information.

[0104] For example, the queue recycling circuit 223 is configured to recycle the instruction of the target type in the instruction submission queue according to the storage address.

[0105] For example, the processor 200 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capability and / or program execution capability.

[0106] For example, in the case that the processor 200 is a central processing unit (CPU) including a pipeline including units or components such as branch prediction, instruction fetch, decoding, issue and renaming, execution unit, instruction submission, etc., the instruction submission unit includes the above-mentioned instruction submission queue 210 and instruction submission queue controller 220. For example, the central processing unit (CPU) can adopt X86 architecture, ARM architecture, RISC architecture (such as RISC-V), MIPS architecture, etc. The processor 200 can be a general-purpose processor or a special-purpose processor. The processor of the embodiments of the present disclosure can be a processor of any architecture, any instruction set, which is not limited by the present disclosure.

[0107] It should be noted that the type position detection circuit 221 can be used to implement Figure 3 The address generation circuit 222 can be used to implement Figure 3 The queue recycling circuit 223 can be used to implement Figure 3 The steps S40 shown. Thus, the specific description of the functions that can be achieved by the type position detection circuit 221, the address generation circuit 222, and the queue recycling circuit 223 can refer to the related description of steps S10 to S40 in the above-mentioned embodiments of the pipeline emptying method, and the repeated parts will not be described herein. In addition, the processor 200 can achieve similar technical effects as the pipeline emptying method, which will not be described herein.

[0108] At least some embodiments of the present disclosure also provide an electronic device including the processor of any of the above-mentioned embodiments.

[0109] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0110] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The electronic device 300 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0111] For example, such as Figure 7 As shown, in some examples, electronic device 300 includes processing device 301 (e.g., central processing unit, graphics processor, etc.), which may include processor 3011 of any of the above embodiments, capable of performing various appropriate actions and processes according to a program stored in read-only memory (ROM) 302 or a program loaded from storage device 308 into random access memory (RAM) 303. RAM 303 also stores various programs and data required for the operation of the computer system. Processing device 301, ROM 302, and RAM 303 are connected via bus 304. Input / output (I / O) interface 305 is also connected to bus 304.

[0112] For example, the following components can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309, such as network interface cards like LAN cards and modems, etc. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage device 308 as needed. Although Figure 7 An electronic device 300 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0113] For example, the electronic device 300 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, such as a USB interface, a lighting interface, and the like. The communication device 309 can communicate with networks and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any of a plurality of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0114] For example, the electronic device 300 can be any device such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, and the like, or any combination of data processing apparatuses and hardware, and embodiments of the present disclosure are not limited thereto.

[0115] For the present disclosure, in addition to the above exemplary descriptions, the following points need to be explained:

[0116] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0117] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0118] The above description is only exemplary embodiments of the present disclosure, and is not intended to limit the protection scope of the present disclosure, and the protection scope of the present disclosure is determined by the appended claims.

Claims

1. A method for pipeline flushing, comprising: obtaining an instruction range to be flushed; obtaining type and position information of each instruction in an instruction submission queue; based on the type and position information, obtaining a storage address of a target type instruction in the instruction range in a memory used for the instruction submission queue; recycling the target type instruction in the instruction submission queue according to the storage address; wherein the obtaining of the instruction range to be flushed comprises: obtaining start instruction position information and end instruction position information of one or more instructions to be flushed in the instruction submission queue.

2. The method of claim 1, wherein, The instruction submission queue comprises a plurality of record items respectively for a plurality of instructions, and each record item comprises type information of a corresponding instruction; The obtaining of the type and position information of each instruction in the instruction submission queue comprises: obtaining the type and position information of each instruction in the instruction submission queue using the type information of each record item in the instruction submission queue.

3. The method of claim 1 or 2, wherein, The memory comprises a plurality of storage banks; and the storage address of the target type instruction in the memory comprises a corresponding storage address of the target type instruction in a corresponding storage bank.

4. The method of claim 3, wherein, The recycling of the target type instruction in the instruction submission queue comprises: reading a plurality of the target type instructions from the plurality of storage banks in a same read operation to recycle the plurality of target type instructions.

5. The method of claim 4, wherein, The recycling of the target type instruction in the instruction submission queue further comprises: reading a plurality of batches of the target type instructions from the plurality of storage banks in a plurality of continuous read operations to recycle the plurality of batches of target type instructions.

6. The method of claim 1 or 2, wherein, The target type comprises a floating point instruction type or a fixed point instruction type. 7.An apparatus for pipeline flushing, comprising: a type and position detection unit configured to obtain type and position information of each instruction in an instruction submission queue; an address generation unit configured to obtain an instruction range to be flushed, and based on the type and position information, obtain a storage address of a target type instruction in the instruction range in a memory used for the instruction submission queue; a queue recycling unit configured to recycle the target type instruction in the instruction submission queue according to the storage address; wherein the address generation unit is further configured to obtain start instruction position information and end instruction position information of one or more instructions to be flushed in the instruction submission queue.

8. The apparatus of claim 7, wherein, The instruction submission queue comprises a plurality of record items respectively for a plurality of instructions, and each record item comprises type information of a corresponding instruction; The address generation unit is further configured to obtain the type and position information of each instruction in the instruction submission queue using the type information of each record item in the instruction submission queue.

9. The apparatus of claim 7, further comprising the memory wherein, The memory comprises a plurality of storage banks; The storage address of the target type instruction in the memory comprises a corresponding storage address of the target type instruction in a corresponding storage bank.

10. The apparatus of claim 9, wherein, The queue recycling unit is further configured to read a plurality of the target type instructions from the plurality of storage banks in a same read operation to recycle the plurality of target type instructions.

11. The apparatus of claim 10, wherein, The queue recycling unit is further configured to read a plurality of batches of instructions of the target type from the plurality of memory banks in a plurality of consecutive read operations to recycle the plurality of batches of instructions of the target type.

12. A processor comprising: an instruction issue queue; an instruction issue queue controller comprising: a type and location detection circuit configured to obtain type and location information of instructions in the instruction issue queue; an address generation circuit configured to obtain a storage address of instructions of a target type in a memory for the instruction issue queue based on the type and location information and an instruction range to be emptied in the processor; a queue recycling circuit configured to recycle the instructions of the target type in the instruction issue queue according to the storage address; wherein the address generation circuit is further configured to obtain start instruction location information and end instruction location information of one or more instructions to be emptied in the instruction issue queue.

13. An electronic device comprising the processor of claim 12.

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