A DPU device initialization method

Abstract

This invention provides a DPU device initialization method, relating to the field of computer equipment. The invention executes a BAR space mapping process, a PCI device initialization process, a PF data channel initialization process, and a VP data channel initialization process, respectively. First, the invention performs an IO remap operation on the BAR register, mapping the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space. Then, PCI device initialization is performed through the BAR space. Next, the PCI driver and kernel timer are initialized, and based on this, a work queue task is maintained and port status polling is performed periodically. Finally, an interrupt vector is allocated to the VP data channel, and the on / off state of the VP data channel is managed through the interrupt vector. This invention provides a complete and systematic initialization processing solution for a high-speed DPU daughter card based on domestically produced chips, which helps improve the development efficiency of domestically produced equipment.

Description

Technical Field

[0001] This invention relates to the field of computer equipment, and more particularly to a method for initializing a DPU device. Background Technology

[0002] A DPU (Data Processing Unit) is a dedicated processor that provides virtualization services for data center infrastructure such as networking, storage, security, and management, all centered around data processing. It is typically a computing architecture composed of a CPU based on architectures such as ARM / X86 and dedicated hardware acceleration engines such as ASIC / NP / FPGA, forming a physical network interface card (NIC) that provides virtualization functionality.

[0003] A high-speed DPU daughter card is a form of DPU network card, configured as an independent small board. It has the technical advantages of low power consumption, low cost, and high reliability. Currently, the demand for massive storage and computing in airborne and laboratory environments for high-performance networking, simulation, data acquisition, and monitoring in the avionics field is growing rapidly, and the demand for diversified communication products is increasing. This is also accompanied by the increasingly frequent and widespread use of high-speed DPU daughter cards in the avionics field.

[0004] In the past, high-speed DPU daughter cards from international brands were often used, and their firmware programs were pre-packaged and ready to use. While this brought convenience, it also limited the development of technology.

[0005] Therefore, when initializing DPU devices, a complete and systematic initialization solution has not yet been proposed for high-speed DPU daughter cards based on domestically produced chips; therefore, a DPU device initialization method is needed to solve the above-mentioned technical problems. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a DPU device initialization method, aiming to offer a complete and systematic initialization process for high-speed DPU daughter cards based on domestically produced chips, thereby filling the gaps in the existing technology.

[0007] This invention provides a DPU device initialization method for a high-speed DPU daughter card based on a single DPU chip. The DPU chip is connected to a PCI device, which has multiple BAR registers. A Linux kernel is loaded into the DPU chip, and the following processes are executed: BAR space mapping, PCI device initialization, PF data channel initialization, and VP data channel initialization.

[0008] BAR space mapping process: Perform IO remap mapping operation on the BAR register to map the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space;

[0009] PCI device initialization process: PCI device initialization is performed through the BAR space;

[0010] PF data channel initialization process: Initialize the PCI driver and kernel timer, and on this basis, maintain the work queue tasks and periodically perform port status polling;

[0011] VP data channel initialization process: Set up and assign interrupt vectors to the VP data channel, and manage the on / off state of the VP data channel through interrupt vectors.

[0012] As a further solution, during the BAR space mapping process: the BAR register stores the physical base address of the MEM / IO space. After enabling the PCI device, the BAR register is periodically remapped, and the mapped BAR registers are combined into a BAR space; mbus message sending and receiving are performed through the shared memory space of the BAR space.

[0013] As a further solution, the PCI device initialization process is performed through the following steps:

[0014] The command reads the chip's EEPROM information by sending an mbus message through the BAR4 space; if the retrieval fails, the default configuration information is used.

[0015] Clear the vport channel data in the BAR4 space and reset the vport channel data;

[0016] Retrieve the port parameter configuration of the port map;

[0017] Obtain mbus messages through BAR4 space and read the NIC status settings of the DPU high-speed daughter card;

[0018] Perform a NIC status setting check; if there is a NIC status setting, proceed to set the network card feature information;

[0019] The command sends an mbus message through the BAR4 space to write the port parameter configuration into the DPU chip.

[0020] Read the write status; if the write times out or fails, issue an alarm and terminate the BAR space device initialization process;

[0021] Configure network card characteristics and complete the PCI device initialization process.

[0022] As a further solution, the network interface card (NIC) feature information includes enabling the PF function and configuring function parameters; wherein, the PF function includes PF RSS, PF SRIOV, PF IP checksum, PF TSO, and PF LRO, and the function parameters include RSS table size, RSS table entry width, RSS hash key block size, and NIC CQsize.

[0023] As a further solution, the PF data channel initialization process is performed through the following steps:

[0024] Initialize the kernel timer of the DPU chip and bind the timer timeout task;

[0025] Set the timer timeout period and activate the kernel timer;

[0026] Initialize the work queue tasks and bind them to the work tasks;

[0027] Set the number of PF queues and the number of PFs;

[0028] Create a debugfs file; the debugfs file is used to record historical operation records.

[0029] As a further solution, after the PF data channel initialization process is completed, the timer timeout task starts timing and determines whether it is a timeout task based on the timer timeout period; if so, the timer timeout period of the timeout task is modified, the timing is restarted, and it is added to the work queue task; the work queue task is implemented according to the bound work task and periodically performs port status polling.

[0030] As a further solution, port status polling is performed through the following steps:

[0031] Save the existing link settings and read the link status;

[0032] If the data is read successfully or link_status.link is empty, initialize the phy information to the default value and set the phy link status to link down;

[0033] If the read fails and link_status.link is not empty, set the phy link status to link up, get the link_status.speed level, and set the phy type and link_speed.

[0034] Read the optical module status and determine if it is the same as the original value;

[0035] If they are the same, check if the optical module status is empty; if yes, print "Optical module unplugged"; if no, print "Optical module connected"; proceed to the next step.

[0036] If they are different, proceed directly to the next step;

[0037] Determine if the current link state is the same as the old_link;

[0038] If they are the same, then one port status poll is completed;

[0039] If they are different, determine whether the current state is "link up"; if yes, execute the "link up" process; if no, execute the "link down" process.

[0040] As a further solution, the link-up process is executed through the following steps:

[0041] The notification enables the Linux kernel's protocol stack link;

[0042] Wake up the protocol stack transmission queue;

[0043] Update the VSI link status and link_speed;

[0044] Synchronous optical module link_speed parameter;

[0045] Print link up information, actual port speed, and auto-negotiation status.

[0046] As a further solution, the link-down process is executed through the following steps:

[0047] The notification disconnects the Linux kernel's protocol stack link;

[0048] Stop the protocol stack transmission queue;

[0049] Update the VSI link status and link_speed;

[0050] Print the link down message.

[0051] As a further solution, the VP data channel initialization process is as follows:

[0052] Allocate the msix_entry array and, after successful allocation, write the entries into the msix_entry array;

[0053] pf->state sets the MSIX flag;

[0054] Request an MSI-x interrupt vector; whereby the requested interrupt vector number is written into the vector of the msix_entry array, memory is allocated for pf->irq_pile, and the actual number of interrupt vectors allocated is stored in pf->irq_pile;

[0055] If successful, pf->state is set to the INTX DOWN flag;

[0056] If it fails, pf->state clears the MSIX flag and enables the INTX interrupt;

[0057] If the interrupt is successful, pf->state is set to the INTX DOWN flag; otherwise, the VP data channel initialization process ends.

[0058] Write the distribution configuration into the registers of the DPU chip to end the VP data channel initialization process.

[0059] Compared with the prior art, the DPU device initialization method provided by the present invention has the following advantages:

[0060] This invention first performs an IO remap operation on the BAR register, mapping the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space; then, it initializes the PCI device through the BAR space; next, it initializes the PCI driver and kernel timers, and on this basis, it maintains the work queue tasks and periodically performs port status polling; finally, it allocates interrupt vectors to the VP data channel and manages the on / off state of the VP data channel through the interrupt vectors. This invention provides a complete and systematic initialization processing solution for DPU high-speed daughter cards based on domestically produced chips, which helps to improve the development efficiency of domestic equipment. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of a DPU device initialization method provided by the present invention;

[0062] Figure 2 This is a schematic diagram of the BAR space mapping process provided by the present invention;

[0063] Figure 3 This is a schematic diagram of the PCI device initialization process provided by the present invention;

[0064] Figure 4 This is a schematic diagram of the PF data channel initialization process provided by the present invention;

[0065] Figure 5 A schematic diagram of the port status polling process provided by the present invention;

[0066] Figure 6A schematic diagram of the VP data channel initialization process provided by the present invention. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0068] Please see Figure 1 This invention provides a DPU device initialization method for a high-speed DPU daughter card based on a single DPU chip. The DPU chip is connected to a PCI device, which has multiple BAR registers. A Linux kernel is loaded into the DPU chip, and the BAR space mapping process, PCI device initialization process, PF data channel initialization process, and VP data channel initialization process are executed respectively.

[0069] BAR space mapping process: Perform IO remap mapping operation on the BAR register to map the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space;

[0070] PCI device initialization process: PCI device initialization is performed through the BAR space;

[0071] PF data channel initialization process: Initialize the PCI driver and kernel timer, and on this basis, maintain the work queue tasks and periodically perform port status polling;

[0072] VP data channel initialization process: Set up and assign interrupt vectors to the VP data channel, and manage the on / off state of the VP data channel through interrupt vectors.

[0073] It should be noted that: This invention first performs an IO remap operation on the BAR register, mapping the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space; then, it initializes the PCI device through the BAR space; next, it initializes the PCI driver and kernel timer, and on this basis, it maintains the work queue tasks and periodically performs port status polling; finally, it allocates interrupt vectors to the VP data channel and manages the on / off state of the VP data channel through the interrupt vectors; this invention provides a complete and systematic initialization processing solution for DPU high-speed daughter cards based on domestically produced chips, which helps to improve the development efficiency of domestic equipment.

[0074] During the BAR space mapping process: the BAR register stores the physical base address of the MEM / IO space. After enabling the PCI device, the BAR register is periodically remapped, and the mapped BAR registers are combined to form the BAR space. mbus message sending and receiving are performed through the shared memory space of the BAR space.

[0075] It should be noted that: such as Figure 2 As shown, the PCI device connected to the domestically produced DPU chip has at least 256 bytes of address space, with the first 64 bytes being standard. In a specific embodiment, the PCI device contains 6 BAR registers, which store the physical base addresses of 6 MEM / IO spaces. Here, we only use BAR0, BAR2, and BAR4, and they are all base addresses of the MEM space. After enabling the PCI device, we map the physical addresses in BAR0, BAR2, and BAR4 to the kernel virtual address space.

[0076] After the BAR space is successfully mapped, the software can read and write registers through the BAR space, and send and receive mbus messages through the shared memory space of the BAR space.

[0077] like Figure 3 As shown, the PCI device initialization process proceeds through the following steps:

[0078] The command reads the chip's EEPROM information by sending an mbus message through the BAR4 space; if the retrieval fails, the default configuration information is used.

[0079] Clear the vport channel data in the BAR4 space and reset the vport channel data;

[0080] Retrieve the port parameter configuration of the port map;

[0081] Obtain mbus messages through BAR4 space and read the NIC status settings of the DPU high-speed daughter card;

[0082] Perform a NIC status setting check; if there is a NIC status setting, proceed to set the network card feature information;

[0083] The command sends an mbus message through the BAR4 space to write the port parameter configuration into the DPU chip.

[0084] Read the write status; if the write times out or fails, issue an alarm and terminate the BAR space device initialization process;

[0085] Configure network card characteristics and complete the PCI device initialization process.

[0086] It should be noted that in this embodiment, the chip's EEPROM information is read by issuing commands through the BAR space. If the acquisition fails, the default configuration information is used to clear the vport channel data, ensuring that the vport channel data is reset during the driver probe stage.

[0087] Then, based on the obtained device type, set the port parameter; obtain the device's status as a standard Ethernet card; if the NIC status has not been set, write the port parameter to the chip via an mbus message, and determine whether the writing takes effect.

[0088] The network interface card (NIC) characteristic information includes enabling the PF function and configuring function parameters; wherein, the PF function includes PFRSS, PF SRIOV, PF IP checksum, PF TSO, and PF LRO, and the function parameters include RSS table size, RSStable entry width, RSS hash key block size, and NIC CQ size.

[0089] It should be noted that: PF RSS: Receiver Scaling; PF SRIOV: Single Root I / O Virtualization; PF IPchecksum: Interface IP Header Check; PF TSO: Network Interface Card Bulk Forwarding, used to reduce the load of transmitted data packets; the function parameters are some specific specification limitations, which will not be elaborated here.

[0090] like Figure 4 As shown, the PF data channel initialization process is executed through the following steps:

[0091] Initialize the kernel timer of the DPU chip and bind the timer timeout task;

[0092] Set the timer timeout period and activate the kernel timer;

[0093] Initialize the work queue tasks and bind them to the work tasks;

[0094] Set the number of PF queues and the number of PFs;

[0095] Create a debugfs file; the debugfs file is used to record historical operation records.

[0096] It should be noted that the pf data structure type is struct nce_pf, which is a private driver handle for the device driver. This data structure maintains all global information about the device driver, including the driver configuration files such as pci_dev, hw, (interrupt vector table, timers, and timer tasks), as well as mutexes and spinlocks that protect these resources from race conditions. Specifically, the timer task only enters the polling state when the timer setting expires; it does not enter the polling state during the initialization phase.

[0097] like Figure 4 As shown, after the PF data channel initialization process is completed, the timer timeout task starts timing and determines whether it is a timeout task based on the timer timeout period; if so, the timer timeout period of the timeout task is modified, the timing is restarted, and it is added to the work queue task; the work queue task is implemented according to the bound work task and periodically performs port status polling.

[0098] like Figure 5 As shown, port status polling is performed through the following steps:

[0099] Save the existing link settings and read the link status;

[0100] If the data is read successfully or link_status.link is empty, initialize the phy information to the default value and set the phy link status to link down;

[0101] If the read fails and link_status.link is not empty, set the phy link status to link up, get the link_status.speed level, and set the phy type and link_speed.

[0102] Read the optical module status and determine if it is the same as the original value;

[0103] If they are the same, check if the optical module status is empty; if yes, print "Optical module unplugged"; if no, print "Optical module connected"; proceed to the next step.

[0104] If they are different, proceed directly to the next step;

[0105] Determine if the current link state is the same as the old_link;

[0106] If they are the same, then one port status poll is completed;

[0107] If they are different, determine whether the current state is "link up"; if yes, execute the "link up" process; if no, execute the "link down" process.

[0108] The link-up process is executed through the following steps:

[0109] The notification enables the Linux kernel's protocol stack link;

[0110] Wake up the protocol stack transmission queue;

[0111] Update the VSI link status and link_speed;

[0112] Synchronous optical module link_speed parameter;

[0113] Print link up information, actual port speed, and auto-negotiation status.

[0114] The link-down process is executed through the following steps:

[0115] The notification disconnects the Linux kernel's protocol stack link;

[0116] Stop the protocol stack transmission queue;

[0117] Update the VSI link status and link_speed;

[0118] Print the link down message.

[0119] like Figure 6 As shown, the VP data channel initialization process is as follows:

[0120] Allocate the msix_entry array and, after successful allocation, write the entries into the msix_entry array;

[0121] pf->state sets the MSIX flag;

[0122] Request an MSI-x interrupt vector; whereby the requested interrupt vector number is written into the vector of the msix_entry array, memory is allocated for pf->irq_pile, and the actual number of interrupt vectors allocated is stored in pf->irq_pile;

[0123] If successful, pf->state is set to the INTX DOWN flag;

[0124] If it fails, pf->state clears the MSIX flag and enables the INTX interrupt;

[0125] If the interrupt is successful, pf->state is set to the INTX DOWN flag; otherwise, the VP data channel initialization process ends.

[0126] Write the distribution configuration into the registers of the DPU chip to end the VP data channel initialization process.

[0127] It should be noted that since the device supports a maximum of 72 VP data channels, 72 interrupt vectors need to be requested to meet the data processing needs of different channels. The Linux kernel maintains the allocated interrupt vectors through the data structure struct msix_entry. Therefore, the memory space of this data structure needs to be pre-allocated before requesting MSI-x interrupt vectors. Here we need 72 interrupt vectors, so the driver is responsible for allocating an array with 72 of these data structures as elements.

[0128] The struct msix_entry has two data members: vector and entry. The entry is filled in by the driver and only specifies an entry number to distinguish different interrupt vectors. The vector member is the interrupt vector number that the kernel allocates after the interrupt vector is successfully requested. Based on this interrupt vector number, the interrupt handling function can be registered to the interrupt vector using request_irq.

[0129] The actual request and allocation of interrupt vectors is implemented through the kernel interface pci_enable_msix_range(). This function requires four parameters: the first parameter is the pointer to the pci_dev data structure passed to the probe function of pci_driver; the second parameter is the address of the allocated struct msix_entry type array; the third parameter is the minimum number of interrupt vectors to be requested; and the fourth parameter is the maximum number of interrupt vectors expected to be requested, which is 72. If the number of interrupt vectors allocated is less than the minimum number of interrupt vectors, the interface returns -ENOSPC; otherwise, it returns the total number of interrupt vectors actually allocated.

[0130] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this invention, and these all fall within the protection scope of this invention.

Claims

1. A DPU device initialization method for a high-speed DPU daughter card based on a single DPU chip, wherein the DPU chip is connected to a PCI device, and the PCI device is configured with multiple BAR registers, characterized in that, The Linux kernel is loaded into the DPU chip, and the BAR space mapping process, PCI device initialization process, PF data channel initialization process, and VP data channel initialization process are executed respectively; among them, BAR space mapping process: Perform IO remap mapping operation on the BAR register to map the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space; PCI device initialization process: PCI device initialization is performed through the BAR space; PF data channel initialization process: Initialize the PCI driver and kernel timer, and on this basis, maintain the work queue tasks and periodically perform port status polling; VP data channel initialization process: Set up and assign interrupt vectors to the VP data channel, and manage the on / off state of the VP data channel through interrupt vectors.

2. The DPU device initialization method according to claim 1, characterized in that, During the BAR space mapping process: the BAR register stores the physical base address of the MEM / IO space. After enabling the PCI device, the BAR register is periodically remapped, and the mapped BAR registers are combined into a BAR space. mbus message sending and receiving are performed through the shared memory space of the BAR space.

3. The DPU device initialization method according to claim 2, characterized in that, The PCI device initialization process is performed through the following steps: The command reads the chip's EEPROM information by sending an mbus message through the BAR4 space; if the retrieval fails, the default configuration information is used. Clear the vport channel data in the BAR4 space and reset the vport channel data; Retrieve the port parameter configuration of the port map; Obtain mbus messages through BAR4 space and read the NIC status settings of the DPU high-speed daughter card; Perform a NIC status setting check; if there is a NIC status setting, proceed to set the network card feature information; The command sends an mbus message through the BAR4 space to write the port parameter configuration into the DPU chip. Read the write status; if the write times out or fails, issue an alarm and terminate the BAR space device initialization process; Configure network card characteristics and complete the PCI device initialization process.

4. The DPU device initialization method according to claim 3, characterized in that, The network interface card (NIC) characteristic information includes enabling the PF function and configuring function parameters; wherein, the PF function includes PF RSS, PF SRIOV, PF IP checksum, PF TSO, and PF LRO, and the function parameters include RSS table size, RSS table entry width, RSS hashkey block size, and NIC CQ size.

5. The DPU device initialization method according to claim 4, characterized in that, The PF data channel initialization process is executed through the following steps: Initialize the kernel timer of the DPU chip and bind the timer timeout task; Set the timer timeout period and activate the kernel timer; Initialize the work queue tasks and bind them to the work tasks; Set the number of PF queues and the number of PFs; Create a debugfs file; the debugfs file is used to record historical operation records.

6. The DPU device initialization method according to claim 5, characterized in that, After the PF data channel initialization process is completed, the timer timeout task starts timing and determines whether it is a timeout task based on the timer timeout period. If it is, the timer timeout period of the timeout task is modified, the timing is restarted, and it is added to the work queue task. The work queue task is implemented according to the bound work task and periodically performs port status polling.

7. A DPU device initialization method according to claim 6, characterized in that, Port status polling is performed through the following steps: Save the existing link settings and read the link status; If the data is read successfully or link_status.link is empty, initialize the phy information to the default value and set the phy link status to link down; If the read fails and link_status.link is not empty, set the phy link status to link up, get the link_status.speed level, and set the phy type and link_speed. Read the optical module status and determine if it is the same as the original value; If they are the same, check if the optical module status is empty; if yes, print "Optical module unplugged"; if no, print "Optical module connected"; proceed to the next step. If they are different, proceed directly to the next step; Determine if the current link state is the same as the old_link; If they are the same, then one port status poll is completed; If they are different, determine whether the current state is "link up"; if yes, execute the "link up" process; if no, execute the "link down" process.

8. The DPU device initialization method according to claim 7, characterized in that, The link-up process is executed through the following steps: The notification enables the Linux kernel's protocol stack link; Wake up the protocol stack transmission queue; Update the VSI link status and link_speed; Synchronous optical module link_speed parameter; Print link up information, actual port speed, and auto-negotiation status.

9. A DPU device initialization method according to claim 7, characterized in that, The link-down process is executed through the following steps: The notification disconnects the Linux kernel's protocol stack link; Stop the protocol stack transmission queue; Update the VSI link status and link_speed; Print the link down message.

10. A DPU device initialization method according to claim 1, characterized in that, VP data channel initialization process: Allocate the msix_entry array and, after successful allocation, write the entries into the msix_entry array; pf->state sets the MSIX flag; Request an MSI-x interrupt vector; whereby the requested interrupt vector number is written into the vector of the msix_entry array, memory is allocated for pf->irq_pile, and the actual number of interrupt vectors allocated is stored in pf->irq_pile; If successful, pf->state is set to the INTX DOWN flag; If it fails, pf->state clears the MSIX flag and enables the INTX interrupt; If the interrupt is successful, pf->state is set to the INTX DOWN flag; otherwise, the VP data channel initialization process ends. Write the distribution configuration into the registers of the DPU chip to end the VP data channel initialization process.

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