High-reliability chip starting method and chip

Abstract

The invention relates to a high-reliability chip starting method and a chip. The method comprises the steps that for any target chip to be started, at least a boot module is arranged in the target chip, when the target chip is started, at least a Flash memory is configured to be in a continuous reading mode, then the boot module is controlled to enter an instruction reading execution operation state, and for any instruction reading request, the Flash memory is configured to be in a continuous reading mode; the on-chip bus reads a starting instruction at a corresponding address from the Flash memory based on the instruction reading request, and returns the read starting instruction to the boot module; and for any start instruction returned by the on-chip bus, the boot module immediately analyzes the start instruction, and initiates a corresponding start configuration execution request to the on-chip bus after analysis, so as to perform start configuration on the chip assembly hung on the on-chip bus based on the start configuration execution request. According to the invention, the starting reliability and starting efficiency of the chip can be improved, and the area of the target chip can be saved.

Description

Technical Field

[0001] The present invention relates to a chip startup method and a chip, in particular to a high-reliability chip startup method and a chip. Background Art

[0002] With the rapid development of semiconductor industry, microelectronics and electronic information technology, the market and users have higher and higher demands on the reliability, security, flexibility and compatibility of chip systems. As we all know, when using a chip, the chip must be started first, but chip startup is not a simple matter. Chip startup is a complicated process. Whether the chip can be started stably and smoothly is related to whether the chip can be used later. If the startup fails, the chip cannot be used. It can be seen that the chip startup operation plays a vital role.

[0003] At present, there is only one startup mode commonly used by chips, that is, to start the chip through a mode or means. Specifically, the chip startup program is solidified in Flash. After the chip is powered on and reset, the MCU moves the startup program in Flash to the memory, and then jumps to the memory address to execute. Among them, the startup program includes initialization of various components, including: clearing registers, configuring specific values ​​for some functional registers, resetting the clock configuration of each component, initializing PCIE cards and link training and linking, training HBM, configuring internal modules and peripheral interfaces, starting the core, and loading the operating system, etc. It can be seen that when the chip is started, many operations need to be performed, which requires the design scheme of chip startup to be flexible and reliable, so as to have strong compatibility.

[0004] For SPI (Serial Peripheral Interface) type Flash, when you want to access Flash, you need to configure the SPI controller and Flash. After the configuration is completed, you can operate Flash in the configured way. The operations on Flash include: reading Flash, writing falsh, and erasing Flash. Since the configuration program is fixed in the ROM of the MCU and cannot be changed, once the fixed program has an error, the chip cannot be started, that is, the chip startup fails.

[0005] From the above description, it can be seen that after the chip is taped out, the firmware in the ROM cannot be modified, and the capital cost and time cost of chip taping out are quite expensive. Therefore, before taping out, the firmware in the MCU and ROM needs to be fully and comprehensively verified to ensure its correctness. If an error occurs after taping out, the chip will not be able to start successfully, which will cause huge financial and time losses, and even lead to the failure of the chip project. At present, there is only one way to start the chip, which is relatively simple and rigid, and lacks flexibility, making it difficult to ensure that the chip is effectively started. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a high-reliability chip startup method and chip, which can improve the reliability and startup efficiency of the chip startup.

[0007] According to the technical solution provided by the present invention, a high-reliability chip startup method is provided, and the chip startup method comprises:

[0008] For any target chip to be started, a boot module is at least set in the target chip, wherein the boot module is adaptively connected to a Flash memory storing a startup program through an on-chip bus;

[0009] When starting the target chip, at least the Flash memory is configured in continuous read mode, after which the boot module is controlled to enter the instruction read and execute operation state, wherein:

[0010] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a startup configuration execution request corresponding to the instruction read request;

[0011] For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module;

[0012] For any startup instruction returned via the on-chip bus, the boot module immediately parses the startup instruction, and after parsing, initiates a corresponding startup configuration execution request to the on-chip bus, so as to perform startup configuration on the chip component connected to the on-chip bus based on the startup configuration execution request;

[0013] When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state.

[0014] The Flash memory is connected to the on-chip bus through the Qspi controller, where

[0015] When the Flash memory is configured in a continuous read mode via the Qspi controller, the Flash memory is at least configured in a four-wire fast continuous read mode via the boot module or the Jtag interface, wherein after the Flash memory is configured in the four-wire fast continuous read mode, the Qspi controller is configured in the Xip mode;

[0016] When the Flash memory is configured as four-wire fast continuous read mode through the Jtag interface, the boot module is in reset state.

[0017] The instruction read execution request initiated by the boot module to the on-chip bus is a serial protocol request, in which:

[0018] When the instruction read execution request initiated by the boot module to the on-chip bus is an instruction read request, the boot module can initiate the next instruction read request or startup configuration execution request to the on-chip bus only after receiving the startup instruction read response returned by the on-chip bus;

[0019] When the instruction read execution request initiated by the boot module to the on-chip bus is a startup configuration execution request, the boot module can initiate the next instruction read request or startup configuration execution request to the on-chip bus only after receiving the startup configuration execution response returned by the on-chip bus.

[0020] 4. The high-reliability chip startup method according to claim 3, characterized in that: the instruction read execution request includes a request valid identification signal xx2yy_req_valid, a request address xx2yy_req_addr, a request data xx2yy_req_data, a request write granularity status signal xx2yy_req_strb, a request type signal xx2yy_req_type and a request read granularity status signal xx2yy_req_rsize;

[0021] When the request type signal xx2yy_req_type is in the first valid level state, the instruction read execution request is an instruction read request;

[0022] When the request type signal xx2yy_req_type is in the second effective level state, the instruction read execution request is a startup configuration execution request.

[0023] For the startup configuration execution response and the startup command read response, there are:

[0024] It includes a response valid identification signal yy2xx_ack_valid, response data yy2xx_ack_data and a response abnormal identification signal yy2xx_ack_excp, wherein:

[0025] For any startup configuration execution response and startup instruction read response, when the response valid identification signal yy2xx_ack_valid is in the valid state, the response data yy2xx_ack_data and the response exception identification signal yy2xx_ack_excp are maintained until the request valid identification signal xx2yy_req_valid in the next instruction read execution request is in the valid state.

[0026] The startup instructions stored in the Flash memory also include NOP empty instructions, SETBASEH instructions, SETBASEL instructions, DELAY instructions, SETW instructions, WR.1 instructions, WR.2 instructions, WR.4 instructions and / or WR.8 instructions, wherein:

[0027] After receiving and parsing the NOP instruction, based on the data in the NOP instruction, the boot module initiates a next instruction read request to the on-chip bus after the next clock cycle;

[0028] After receiving and parsing the SETBASEH instruction, the boot module obtains the high base address of the write IO device;

[0029] After receiving and parsing the SETBASEL instruction, the boot module obtains the low base address of the write IO device;

[0030] After receiving and parsing the DELAY instruction, the boot module counts and waits until the count value corresponds to the delay time in the DELAY instruction. After that, the boot module initiates the next instruction read request to the on-chip bus;

[0031] After receiving and parsing the SETW instruction, the boot module continuously writes to the chip components connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0032] After receiving and parsing the WR.1 instruction, the boot module performs a 1-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0033] After receiving and parsing the WR.2 instruction, the boot module performs a 2-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0034] After receiving and parsing the WR.4 instruction, the boot module performs a 4-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0035] After receiving and parsing the WR.8 instruction, the boot module performs an 8-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus.

[0036] When the target chip cannot be started based on the boot module, the Jtag interface is used to configure the chip components in the target chip until the startup requirements of the target chip are met.

[0037] A high-reliability chip, the chip is started using the chip starting method described above, and the chip comprises:

[0038] Flash memory, storing at least a boot program, and connected to the on-chip bus via a Qspi controller;

[0039] The boot module is connected to the on-chip bus and can configure the Flash memory in a four-wire fast continuous read mode, wherein after the Flash memory is configured in the four-wire fast continuous read mode, the Qspi controller is configured in the Xip mode;

[0040] When the control chip starts, the control boot module enters the instruction reading and execution operation state, where:

[0041] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a startup configuration execution request corresponding to the instruction read request;

[0042] For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module;

[0043] For any startup instruction returned via the on-chip bus, the boot module immediately parses the startup instruction, and after parsing, initiates a corresponding startup configuration execution request to the on-chip bus, so as to perform startup configuration on the chip component connected to the on-chip bus based on the startup configuration execution request;

[0044] When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state.

[0045] The boot module includes a configuration unit and a read execution unit, wherein:

[0046] When the configuration chip is started, the reset of the boot module is cancelled by using the off-chip MCU unit, and thereafter, the Flash memory is configured in the four-wire fast continuous read mode via the on-chip bus by using the configuration unit in the boot module, and the Qspi controller is configured in the Xip mode, or, the boot module is controlled to be in the reset state by using the off-chip MCU unit, and thereafter, the Flash memory is configured in the four-wire fast continuous read mode and the Qspi controller is configured in the Xip mode by at least using the Jtag interface;

[0047] When the Flash memory is configured in the four-wire fast continuous read mode and the Qspi controller is in the Xip mode, the MCU unit cancels the reset of the boot module to at least configure the read execution unit to enter the instruction read execution operation state.

[0048] The invention has the advantages that a boot module is arranged in the target chip, the boot module is connected with the Qspi controller via an on-chip bus, the Qspi controller is configured to be in Xip mode via the boot module or by means of a Jtag interface, and the Flash memory enters a four-line fast continuous read mode, after which the startup program in the Flash memory can be read quickly and continuously, and the boot module is used to parse the read startup instruction, and data is written to the chip assembly connected to the on-chip bus, so as to realize the initialization configuration of the chip assembly, save the program handling time, and shorten the chip startup time. In addition, the boot module or by means of a Jtag interface can be used to control the startup of the target chip, so as to improve the reliability and startup efficiency of the chip startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of an embodiment of a chip startup method of the present invention.

[0050] Figure 2 This is a flow chart of another embodiment of the present invention in which the chip is started without using the boot module.

[0051] Figure 3 The present invention is a schematic diagram of an embodiment of the boot module cooperating with the on-chip bus and the Flash memory.

[0052] Figure 4 It is a schematic diagram of the state machine corresponding to the boot module of the present invention.

[0053] Figure 5 A schematic diagram of an embodiment of an instruction read execution request and a startup configuration execution response of the present invention. DETAILED DESCRIPTION

[0054] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0055] In order to improve the reliability and efficiency of chip startup, the present invention provides a high-reliability chip startup method. Specifically, the chip startup method includes:

[0056] For any target chip to be started, a boot module is at least set in the target chip, wherein the boot module is adaptively connected to a Flash memory storing a startup program through an on-chip bus;

[0057] When starting the target chip, at least the Flash memory is configured in continuous read mode, after which the boot module is controlled to enter the instruction read and execute operation state, wherein:

[0058] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a startup configuration execution request corresponding to the instruction read request;

[0059] For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module;

[0060] For any startup instruction returned via the on-chip bus, the boot module immediately parses the startup instruction, and after parsing, initiates a corresponding startup configuration execution request to the on-chip bus, so as to perform startup configuration on the chip component connected to the on-chip bus based on the startup configuration execution request;

[0061] When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state.

[0062] It should be understood that the chip startup method of the present invention is specifically for the startup of the target chip. The type of the target chip can be determined according to the actual application requirements, and will not be repeated here. When the target chip is started, a boot module should be set at least in the target chip. After the boot module is set in the target chip, the boot module can be used to control the startup of the target chip. Compared with the prior art, the area of ​​the boot module can be smaller than the area of ​​the logic module used for the startup of the target chip in the prior art, thereby reducing the area of ​​the target chip and reducing the cost of the target chip. In addition, since the boot module is dedicated to the startup of the target chip, the startup efficiency of the target chip can be higher.

[0063] Figure 3An embodiment of connecting the boot module to the on-chip bus in the target chip is shown in FIG. As can be seen from the figure, the boot module should be connected to the on-chip bus. Thereafter, the boot module can be connected to the Flash memory through the on-chip bus to read the startup program stored in the Flash memory. It should be understood that the startup program in the Flash memory should be compatible with the target chip. For example, a corresponding startup program can be designed according to the type of the target chip, and the designed startup program can be burned into the Flash memory. The startup program in the Flash memory can generally be composed of a number of startup instructions. The startup instructions in the startup program can be used to initialize the chip components in the target chip. It should be noted that the initialization configuration of the chip components is mainly for the startup initialization of the target chip. For details, please refer to the description of the chip startup configuration in the above background technology.

[0064] In order to enable the target chip to start quickly, the Flash memory should at least be configured in continuous read mode. Only when the Flash memory is configured in continuous read mode can the boot module be controlled to enter the instruction read and execute operation state. The method of configuring the Flash memory in continuous read mode can be selected according to actual needs, and an example is given below.

[0065] In one embodiment of the present invention, the Flash memory is connected to the on-chip bus via a Qspi controller, wherein:

[0066] When the Flash memory is configured in a continuous read mode via the Qspi controller, the Flash memory is at least configured in a four-wire fast continuous read mode via the boot module or the Jtag interface, wherein after the Flash memory is configured in the four-wire fast continuous read mode, the Qspi controller is configured in the Xip mode;

[0067] When the Flash memory is configured as four-wire fast continuous read mode through the Jtag interface, the boot module is in reset state.

[0068] Figure 3An embodiment of connecting the Flash memory to the on-chip bus through the Qspi (Queued SPI) controller is shown in the figure. At this time, the Flash memory should meet the QSPI working mode so as to be adaptable and connected with the Qspi controller. The Flash memory, the Qspi controller and the on-chip bus can adopt the existing commonly used forms. For example, the Flash memory should at least adopt a memory that meets the four-line fast continuous read mode. When the Flash memory is configured in the four-line fast continuous read mode, it is 4 times the normal reading speed of Flash data and can be read continuously. It can be seen that data can be read quickly from the Flash memory, which greatly improves the efficiency of starting the target chip and greatly shortens the time of starting the target chip.

[0069] It should be noted that when configuring the Flash memory to enter the four-wire fast continuous read mode, the Flash command should generally be used to configure the Flash memory, and the configuration methods of different types of Flash memories will be different. For a certain Flash memory, the mode configuration of the Flash memory can be achieved in different ways in conjunction with the Qspi controller, and the configuration method should be related to the type of Flash memory, etc. For example, after determining the type of Flash memory, the boot module can cooperate with the on-chip bus and the Qspi controller to implement the mode configuration of the Flash memory, or cooperate with the on-chip bus and the Qspi controller through the Jtag interface to implement the mode configuration of the Flash memory. The specific method and process of configuring the Flash memory to enter the four-wire fast continuous read mode can be consistent with the prior art and will not be repeated here.

[0070] In a specific implementation, when the Flash memory is configured in the four-wire fast continuous read mode, the Flash memory is first configured in the four-wire fast continuous read mode, and then the Qspi controller is configured in the Xip (Execute In Place) mode.

[0071] From the above description, it can be seen that in the design stage of the target chip, when the type of Flash memory is determined, the boot module to be set is generally determined accordingly, that is, the boot module should be related to the type of Flash memory in the target chip. However, in the tape-out stage, when the type of Flash memory in the target chip changes, the boot module will not be able to adapt to the Flash memory, thereby causing the boot module to be unable to configure the Flash memory, that is, the Flash memory cannot be configured to the four-wire fast continuous read mode.

[0072] When the type of Flash memory changes, resulting in the boot module being unable to configure the Flash memory, but since the startup program in the Flash memory is still consistent with the design phase, it can be seen that the startup instructions in the Flash memory can still be read and parsed by the boot module, that is, when the Flash memory is configured in four-wire fast continuous read mode, the boot module can read the startup instructions in the Flash memory via the on-chip bus, and then parse the startup instructions returned by the on-chip bus.

[0073] When the above-mentioned Flash memory type changes, in one embodiment of the present invention, the Flash memory can be configured to enter the four-wire fast continuous read mode through the Jtag interface. Specifically, when the Flash memory is configured to enter the four-wire fast continuous read mode through the Jtag interface, the Jtag operation can be performed by an off-chip MCU, and then the Flash memory can be configured through the Jtag interface so that the Flash memory enters the four-wire fast continuous read mode. Specifically, when the Flash memory is configured using the Jtag interface, the working mode configuration of the Flash memory should be implemented according to the configuration method of the Flash memory. It can be seen from the above description that the Flash memory can be configured in mode through the Flash command, and the Flash command used for configuration can be obtained from the working manual of the Flash memory and other methods. Similar to the above-mentioned use of the boot module to configure the Flash memory to enter the four-wire fast continuous read mode, when the Flash memory is configured to enter the four-wire fast continuous read mode through the Jtag interface, the Qspi controller should also be configured to enter the Xip mode. Among them, when configuring the Qspi controller to enter the Xip mode, the method and process of configuring the Qspi controller to enter the Xip mode can generally be consistent with the prior art based on the type of the Qspi controller and the datasheet manual of the Qspi controller, and will not be repeated here.

[0074] When the Flash memory is configured to enter the four-wire fast continuous read mode through the Jtag interface, the boot module should be in a non-working state, such as the boot module is in a reset state. Specifically, when the target chip is started, it must be reset first. At this time, the boot module should also be reset under the boot module reset control signal i_boot_rst_n. After the reset of the boot module is canceled, the boot module can enter the working state and the boot module can enter the instruction read and execute operation state. When the boot module is in a reset state, the boot module reset control signal i_boot_rst_n should be in an invalid state. At this time, the boot module is in a non-working state.

[0075] It should be noted that when the Flash memory is configured to enter the four-wire fast continuous read mode through the boot module, the boot module will enter the instruction read and execute operation state after the Flash memory enters the four-wire fast continuous read mode, and when the Flash memory is configured to enter the four-wire fast continuous read mode through the Jtag interface, the boot module should be configured to enter the cancel reset state from the reset state after the Flash memory enters the four-wire fast continuous read mode, and enter the instruction read and execute operation state after canceling the reset. Of course, it can be seen from the above description that before the boot module enters the instruction read and execute operation state, the Qspi controller should also be configured to enter the Xip mode.

[0076] Since the chip components need to be initialized and configured, after entering the instruction read and execute operation state, the boot module should initiate an instruction read and execute request to the on-chip bus, and first read the startup instruction from the Flash memory based on the instruction read and execute request, and initialize and configure the chip components based on the read startup instruction. In specific implementation, each instruction read and execute request should include an instruction read request and / or a startup configuration execution request corresponding to the instruction read request. Specifically,

[0077] For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module; specifically, according to the instruction read request, the Flash memory returns the startup instruction to the on-chip bus via the Qspi controller, after which the on-chip bus generates a startup instruction read response, and returns the startup instruction read response to the boot module, that is, the returned startup instruction is returned to the boot module in the form of a startup instruction read response. It can be seen that the instruction read request specifically refers to a request to read the startup instruction in the Flash memory. In specific implementation, when the startup program is burned into the Flash memory, the storage address of each startup instruction in the Flash memory can be determined. Therefore, according to the type of the target chip and the startup requirements, the boot module can generate a corresponding instruction read request, so that the corresponding startup instruction can be read based on the generated instruction read request.

[0078] In specific implementation, after entering the instruction read and execute operation state, the boot module uses a given address as the starting address, and reads the startup instruction corresponding to the starting address through the on-chip bus; thereafter, for the next instruction read request, the boot module will update the address corresponding to the previous instruction read request to obtain a new address, such as adding 4 to the address corresponding to the previous instruction read request, and update it as a new address, and then read the startup instruction corresponding to the new address through the on-chip bus according to the new address, that is, to realize the reading of the startup instruction at the corresponding address from the Flash memory. It can be understood that when the new address is updated, the specific update method is related to the storage setting of the startup instruction in the Flash memory, and the specific method of updating the new address is based on the ability to effectively read the corresponding startup instruction.

[0079] After the on-chip bus reads the startup instruction in response to the startup instruction, the boot module immediately parses the startup instruction. When parsing the startup instruction, it mainly obtains the instruction information corresponding to the startup instruction. Thereafter, the boot module generates a startup configuration execution request based on the analysis of the startup instruction. The generated startup configuration execution request should be used to start the chip component connected to the on-chip bus through the on-chip bus. Specifically, the startup configuration of the chip component is to initialize the corresponding chip component.

[0080] In specific implementation, multiple startup instructions in the Flash memory can be read one by one through multiple instruction read requests. Thereafter, the corresponding startup instruction is executed based on the startup configuration execution request. When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters a stop working state, which means that the boot module has completed the configuration or initialization of the chip components of the target chip.

[0081] From the above description, it can be seen that when starting the target chip, there is no need to move the startup program in the Flash memory to the Rom and then jump to the Rom for execution. Instead, it is directly read from the Flash memory and executed directly by the boot module. After executing one startup instruction, the next startup instruction is read. This saves the program moving time and shortens the startup time of the target chip.

[0082] In one embodiment of the present invention, the instruction read execution request initiated by the boot module to the on-chip bus is a serial protocol request, wherein:

[0083] When the instruction read execution request initiated by the boot module to the on-chip bus is an instruction read request, the boot module can initiate the next instruction read request or startup configuration execution request to the on-chip bus only after receiving the startup instruction read response returned by the on-chip bus;

[0084] When the instruction read execution request initiated by the boot module to the on-chip bus is a startup configuration execution request, the boot module can initiate the next instruction read request or startup configuration execution request to the on-chip bus only after receiving the startup configuration execution response returned by the on-chip bus.

[0085] It can be understood that when the instruction read execution request is a serial protocol request, the above-mentioned state can be satisfied: after executing one startup instruction, the next startup instruction is read, thereby improving the reliability of the startup process of the target chip; when there is a startup failure, the startup process of the target chip can be traced.

[0086] In specific implementation, the chip startup process in which the boot module configures the Flash memory to enter the four-wire fast continuous read mode is called the self-start mode, and the chip startup process in which the Jtag interface configures the Flash memory to enter the four-wire fast continuous read mode is called the semi-interactive startup mode. Figure 1 and Figure 3 The following examples illustrate the automatic startup mode and the semi-interactive startup mode.

[0087] Specifically, the boot module detects the mode control signal i_boot_mcu_sel input from outside the chip to determine the type of startup mode selected by the target chip this time, and then chooses whether to skip the configuration part of the boot module. Specifically, if the mode control signal i_boot_mcu_sel is 0, the self-start mode is selected, and the boot module configures the Flash memory to enter the four-line fast continuous read mode, and configures the Qspi controller to enter the Xip mode. Thereafter, the boot module is controlled to enter the instruction read and execute operation state; if the mode control signal i_boot_mcu_sel is 1, the semi-interactive startup mode is selected, and the Flash memory is configured to enter the four-line fast continuous read mode with the help of the Jtag interface, and the Qspi controller is configured to enter the Xip mode. Thereafter, the boot module is controlled to enter the instruction read and execute operation state.

[0088] Depend on Figure 1 It can be seen that when the target chip is started based on the self-start mode, the startup process includes:

[0089] Step 1, inform the boot module that this boot is in self-boot mode through the mode control signal i_boot_mcu_sel=0, and then check the reset state control signal i_boot_rst_n loaded into the boot module, where when i_boot_rst_n is 0, it indicates the reset state, at this time, the boot module is in a non-working state; when i_boot_rst_n is 1, it indicates the reset state is canceled, at this time, the boot module should enter the working state;

[0090] Depend on Figure 1 It can be seen that when i_boot_rst_n is 1, go to step 2, otherwise, the current state should be maintained, that is, Figure 1 The remain as is.

[0091] Step 2: The boot module configures the Flash memory to enter the four-wire fast continuous read mode, and configures the Qspi controller to enter the Xip mode;

[0092] Step 3, the boot module enters the instruction reading and execution operation state;

[0093] Step 4: The boot module sends a read request to the on-chip bus;

[0094] Step 5: The on-chip bus sends the read request to the Qspi controller;

[0095] Step 6, the Qspi controller sends the request to the Flash memory;

[0096] Step 7, the Flash memory returns the read data to the Qspi controller according to the command;

[0097] Step 8, the Qspi controller returns the read data to the on-chip bus;

[0098] Step 9: The on-chip bus returns the read data to the boot module;

[0099] Step 10: The boot module executes the instruction according to the instruction type of the read data, usually sending a write request to the on-chip bus;

[0100] Step 11: The on-chip bus sends the information of the write request to the corresponding chip component. The chip component is mounted on the on-chip bus. Of course, the chip component can also be mounted on the on-chip bus through a transfer component. The connection state between the chip component and the on-chip bus is based on whether the chip component can be accessed through the on-chip bus.

[0101] Step 12, the chip component returns a write response to the on-chip bus;

[0102] Step 13, the on-chip bus returns the write response to the boot module;

[0103] Step 14: The boot module receives a write response and an instruction is executed;

[0104] Step 15, continue to execute from step 4) again; until the stop state instruction is executed, the boot module finishes running, enters the stop state, and no further operations are performed.

[0105] From the above description, it can be seen that the instruction read request is a read request, which mainly reads the startup instruction from the Flash memory, and the startup configuration execution request is a write request, which mainly writes the data related to the startup instruction into the corresponding chip component.

[0106] Depend on Figure 1 It can be seen that when the target chip is started based on the semi-interactive startup mode, the startup process includes:

[0107] Step 20: The boot module is informed that the current boot is in semi-interactive boot mode through the mode control signal i_boot_mcu_sel=1. After that, the reset state control signal i_boot_rst_n loaded into the boot module is checked. When i_boot_rst_n is 1, step 21 is entered. Otherwise, the current state should be maintained. Figure 1 The remain as is.

[0108] Step 21, the off-chip MCU configures the Flash memory to enter the four-wire fast continuous read mode through the Jtag interface, and configures the Qspi controller to enter the Xip mode;

[0109] Step 22, cancel the reset of the boot module, and configure the boot module to enter the instruction reading and executing operation state;

[0110] Step 23, the boot module sends a read request to the on-chip bus;

[0111] Step 24, the on-chip bus sends the read request to the Qspi controller;

[0112] Step 25, the Qspi controller sends the request to the Flash memory;

[0113] Step 26, the Flash memory returns the read data to the Qspi controller according to the command;

[0114] Step 27, the Qspi controller returns the read data to the on-chip bus;

[0115] Step 28, the on-chip bus returns the read data to the boot module;

[0116] Step 29, the boot module executes the instruction according to the instruction type of the read data, usually sending a write request to the on-chip bus;

[0117] Step 30, the on-chip bus sends the information of the write request to the corresponding chip components, and these chip components are mounted on the on-chip bus;

[0118] Step 31, the chip component returns a write response to the on-chip bus;

[0119] Step 32, the on-chip bus returns the write response to the boot module;

[0120] Step 33, the boot module receives the write response, and an instruction is executed;

[0121] Step 34: Continue to execute from step 23) again until the stop state instruction is executed. The boot module is finished running and enters the stop state. No more operations are performed.

[0122] Furthermore, when the target chip cannot be started based on the boot module, the chip components in the target chip are configured using the Jtag interface until the startup requirements of the target chip are met.

[0123] It is understandable that after the target chip is taped out, there may be errors in the boot module. At this time, the boot module cannot be used to read the boot instructions from the Flash memory to execute the drive of the target chip, that is, the target chip cannot be started based on the boot module. In order to achieve the startup of the target chip, during the specific implementation, the chip components in the target chip can be configured through the Jtag interface using an off-chip MCU until the startup requirements of the target chip are met.

[0124] As can be seen from the above description, after the startup program is stored in the Flash memory, the chip components in the target chip can be configured using the Jtag interface according to the type of the target chip, wherein the configuration of the chip components specifically refers to completing the above-mentioned initialization of the chip components, and the method and process of initializing the chip components in the target chip using the Jtag interface can be consistent with the prior art, and the specific method is based on the startup of the target chip, which will not be repeated here. It should be noted that the working clock frequency of the Jtag interface is relatively low, so the startup speed of the target chip is slow in this way.

[0125] It should be noted that when there is no error in the boot module, but the type of Flash memory used in the tape-out stage is different from the type of Flash memory used in the design stage, the above-mentioned semi-automatic interactive startup mode should be used for the target chip.

[0126] In one embodiment of the present invention, the instruction read execution request includes a request valid identification signal xx2yy_req_valid, a request address xx2yy_req_addr, a request data xx2yy_req_data, a request write granularity status signal xx2yy_req_strb, a request type signal xx2yy_req_type, and a request read granularity status signal xx2yy_req_rsize;

[0127] When the request type signal xx2yy_req_type is in the first valid level state, the instruction read execution request is an instruction read request;

[0128] When the request type signal xx2yy_req_type is in the second effective level state, the instruction read execution request is a startup configuration execution request.

[0129] Specifically, the request valid identification signal xx2yy_req_valid mainly reports the valid status of the instruction read execution request. Figure 5 An embodiment in which the request valid identification signal xx2yy_req_valid is high level valid is shown. Specifically, when the request valid identification signal xx2yy_req_valid is in a valid state, the on-chip bus will confirm that there is a valid instruction read execution request. Thereafter, the instruction read execution request can be sent to the Flash memory via the Qspi controller.

[0130] In order to improve performance, the data bit width of the request data xx2yy_req_data is at least 32 bits. Of course, the data bit width of the request data xx2yy_req_data can also be 64 bits. The address width of the request address xx2yy_req_addr and the data bit width of the request data xx2yy_req_data can generally be selected according to actual needs to meet the interaction requirements between the boot module and the Flash memory and the chip components mounted on the on-chip bus. For example, the address width of the request address xx2yy_req_addr can be 32 bits. Figure 5 FIG. 2 shows an embodiment in which the address width of the request address xx2yy_req_addr and the data bit width of the request data xx2yy_req_data are both 32 bits.

[0131] The request type signal xx2yy_req_type is used to identify the request type of the instruction read execution request, such as identifying the instruction read execution request as a write request or a read request. Figure 5 FIG. 2 shows an embodiment in which when the request type signal xx2yy_req_type is at a high level, the instruction read execution request is identified as a write request, and when the request type signal xx2yy_req_type is at a low level, the instruction read execution request is identified as a read request. Figure 5 In the example, when the request type signal xx2yy_req_type is high and the request valid identification signal xx2yy_req_valid is valid, it can be determined that the instruction read execution request is a valid write request. For other situations, refer to Figure 5 This is explained here and no further examples are given.

[0132] When the request type of the instruction read execution request is a write request, the write request granularity of the write request is set by requesting the write granularity status signal xx2yy_req_strb. In addition, the requesting the write granularity status signal xx2yy_req_strb can be omitted in the instruction read execution request. For example, when the request type of the instruction read execution request is fixed as a read request, the requesting the write granularity status signal xx2yy_req_strb can be omitted. When the instruction read execution request includes the requesting the write granularity status signal xx2yy_req_strb, the data bit width of the requesting the write granularity status signal xx2yy_req_strb can be one eighth of the data bit width of xx2yy_req_data. For example, when the data bit width of the requesting the data xx2yy_req_data is at least 32 bits, the bit width of the requesting the write granularity status signal xx2yy_req_strb can be 4. Figure 5 shown.

[0133] When the request type of the request information is a read request, the read request granularity can be set by requesting the read granularity status signal xx2yy_req_rsize. In addition, the requesting the read granularity status signal xx2yy_req_rsize can be omitted in the instruction read execution request. For example, when the request type of the instruction read execution request is fixed as a write request, the requesting the read granularity status signal xx2yy_req_rsize can be omitted. When the instruction read execution request includes the requesting the read granularity status signal xx2yy_req_rsize, the size of the requesting the read granularity status signal xx2yy_req_rsize can be 2 bits. At this time, when the requesting the read granularity status signal xx2yy_req_rsize is 00, it indicates 1-byte read; when the requesting the read granularity status signal xx2yy_req_rsize is 01, 10, 11, it indicates 2-byte read, 4-byte read, and 8-byte read, respectively.

[0134] In specific implementation, according to the request requirements of the boot module, a corresponding instruction read execution request can be generated, and the corresponding content of the instruction read execution request can be set with reference to the above method. For example, the target object connected via the on-chip bus can be determined according to the request address xx2yy_req_addr.

[0135] Figure 5 An embodiment of starting a configuration execution response is also shown. Figure 5In the figure, yy2xx_ack_valid is a response valid identification signal, and the response valid identification signal yy2xx_ack_valid can be used to identify the validity of the current target object response information. In the figure, when the response valid identification signal yy2xx_ack_valid is at a high level, it indicates that the target object response information is valid response information, otherwise it is invalid response information.

[0136] Figure 5 In the example, yy2xx_ack_excp is a response exception identification signal. When a response exception occurs, the response exception identification signal yy2xx_ack_excp is in a valid state. Figure 5 In the example, the response abnormality identification signal yy2xx_ack_excp is effective at a high level, that is, when a response abnormality occurs, the response abnormality identification signal yy2xx_ack_excp is at a high level. Figure 5 In the example, clk is the clock signal and rst_n is the reset signal.

[0137] It can be seen from the above description that when the boot module reads the boot instruction in the Flash memory, the on-chip bus returns the boot instruction to the boot module in the form of a boot instruction read response. Specifically, the boot instruction read response has the same format as the boot configuration execution response. The situation of the boot instruction read response can be referred to the description of the above-mentioned boot configuration execution response, which will not be repeated here.

[0138] In specific implementation, for any startup configuration execution response and startup instruction read response, when the response valid identification signal yy2xx_ack_valid is in a valid state, the response data yy2xx_ack_data and the response exception identification signal yy2xx_ack_excp are maintained until the request valid identification signal xx2yy_req_valid in the next instruction read execution request is in a valid state.

[0139] In one embodiment of the present invention, the startup instructions stored in the Flash memory further include a NOP empty instruction, a SETBASEH instruction, a SETBASEL instruction, a DELAY instruction, a SETW instruction, a WR.1 instruction, a WR.2 instruction, a WR.4 instruction and / or a WR.8 instruction, wherein:

[0140] After receiving and parsing the NOP instruction, based on the data in the NOP instruction, the boot module initiates a next instruction read request to the on-chip bus after the next clock cycle;

[0141] After receiving and parsing the SETBASEH instruction, the boot module obtains the high base address of the write IO device;

[0142] After receiving and parsing the SETBASEL instruction, the boot module obtains the low base address of the write IO device;

[0143] After receiving and parsing the DELAY instruction, the boot module counts and waits until the count value corresponds to the delay time in the DELAY instruction. After that, the boot module initiates the next instruction read request to the on-chip bus;

[0144] After receiving and parsing the SETW instruction, the boot module continuously writes to the chip components connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0145] After receiving and parsing the WR.1 instruction, the boot module performs a 1-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0146] After receiving and parsing the WR.2 instruction, the boot module performs a 2-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0147] After receiving and parsing the WR.4 instruction, the boot module performs a 4-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus;

[0148] After receiving and parsing the WR.8 instruction, the boot module performs an 8-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus.

[0149] In specific implementation, when designing a boot program, according to the type of the target chip, the above-mentioned boot instruction can be used to generate a corresponding boot program, and the chip components can be initialized based on each boot instruction. The following takes the data bit width of the boot instruction as 32 bits as an example to illustrate the above-mentioned boot instruction. It can be understood that the boot module works under the clock signal, and thus, the clock cycle of the boot module can be determined for a certain boot module. When the boot instruction is a NOP empty instruction, the boot module can initiate the next instruction read request to the on-chip bus in the next clock cycle of the boot module.

[0150] Specifically, in all startup instructions, the lower 8 bits (7:0) are the opcode, that is, the instruction type; Inst is the abbreviation of instruction, Inst0 is the first instruction (32-bit custom instruction), Inst1 represents the second instruction (32 bits are write data), and Inst2 represents the third instruction (32 bits are write data).

[0151]

[0152]

[0153]

[0154] In the above table, NOP instruction is NOP empty instruction, STOP instruction is stop state instruction, NOP empty instruction, stop state instruction, SETBASEH instruction, SETBASEL instruction all contain one instruction, SETW instruction may include three instructions, such as in SETW instruction, Inst0 is the first instruction, Inst1 is the second instruction, Inst2 is the third instruction, other situations can refer to the description here, and will not be listed here one by one.

[0155] Figure 4 An embodiment of the state machine of the boot module working state is shown in FIG. Figure 4 The working status of the boot module is described. Specifically,

[0156] IDLE state: The IDLE state is the initial state after the boot module is reset. If it is in self-start mode, that is, boot_mcu_sel is 0, then after releasing the boot reset, when the configuration part of the boot module is completed, a prompt signal spi_done=1 will be given, and the next cycle will enter the READ_INST0 state; if it is in semi-interactive startup mode, that is, boot_mcu_sel is 1, and after releasing the reset, the next cycle will enter the READ_INST0 state;

[0157] READ_INST0 state: read instruction 1 state, the boot module initiates a read request to the on-chip bus to read the startup instruction in the Flash memory. From the above description, it can be seen that depending on the startup instruction, some need to read instruction 2 or instruction 2 and instruction 3. Specifically, the startup instruction read back here is the write data to be written to the suction cup assembly.

[0158] WAIT_INST0 state: waiting for the response data returned by the Flash memory, which is instruction 1, that is, the start instruction mentioned above.

[0159] READ_DATA1 state: If you want to write 1 byte, 2 bytes, or 4 bytes, you need to read instruction 2, which means writing the lower 4 bytes of data.

[0160] WAIT_DATA1 state: waiting for instruction 2, that is, waiting for writing data;

[0161] READ_DATA2 state: If writing 8 bytes, you need to read instruction 3, that is, write the high 4 bytes of data;

[0162] WAIT_DATA2 state: waiting for instruction 3, that is, writing the high 4 bytes of data;

[0163] WRITE state: After the boot module receives the returned startup instruction and write data, the boot module initiates a write request to the on-chip bus and writes the data into the register of the chip component connected to the on-chip bus;

[0164] WRITE_RESP state: waiting for write response; if there is no response exception and writing is completed, it will jump to READ_INST0 state to read the next instruction; if there is no response exception and writing is not completed, it will jump back to READ_DATA1 and read the data to be written;

[0165] ERROR state: error state. In each state of waiting for response, if an abnormal response is received, it will jump to this state and always remain in this state;

[0166] STOP state: When the instruction read back is a STOP instruction, it will jump to this state and remain in this state;

[0167] DELAY state: When the start instruction read is the DELAY instruction, it will jump to this state and keep counting. When the count reaches the value in the DELAY instruction, it will jump to the READ_ISNT0 state and read the next instruction. Otherwise, it will continue to maintain this state.

[0168] based on Figure 4 As can be seen from the above description, the boot module works according to the state machine described above to start the target chip.

[0169] From the above description, a high-reliability chip of the present invention can be obtained. Specifically, the chip is started by using the chip starting method described above. The chip includes:

[0170] Flash memory, storing at least a boot program, and connected to the on-chip bus via a Qspi controller;

[0171] The boot module is connected to the on-chip bus and can configure the Flash memory in a four-wire fast continuous read mode, wherein after the Flash memory is configured in the four-wire fast continuous read mode, the Qspi controller is configured in the Xip mode;

[0172] When the control chip starts, the control boot module enters the instruction reading and execution operation state, where:

[0173] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a startup configuration execution request corresponding to the instruction read request;

[0174] For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module;

[0175] For any startup instruction returned via the on-chip bus, the boot module immediately parses the startup instruction, and after parsing, initiates a corresponding startup configuration execution request to the on-chip bus, so as to perform startup configuration on the chip component connected to the on-chip bus based on the startup configuration execution request;

[0176] When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state.

[0177] Specifically, the chip is the target chip mentioned above. In addition, there is generally an MCU unit outside the chip, and the MCU unit can adopt an existing commonly used form. The role of the Flash memory and boot module in the chip, and the cooperation can realize the startup of the chip. The specific cooperation method and process of realizing the startup of the chip can refer to the above description.

[0178] In one embodiment of the present invention, the boot module includes a configuration unit and a read execution unit, wherein:

[0179] The boot module includes a configuration unit and a read execution unit, wherein:

[0180] When the configuration chip is started, the off-chip MCU is used to cancel the reset of the boot module, and thereafter, the configuration unit in the boot module is used to configure the Flash memory in a four-wire fast continuous read mode via the on-chip bus, and the Qspi controller is configured in the Xip mode, or, the off-chip MCU unit is used to control the boot module to be in a reset state, and thereafter, the Flash memory is configured in a four-wire fast continuous read mode and the Qspi controller is configured in the Xip mode at least by means of the Jtag interface;

[0181] When the Flash memory is configured in the four-wire fast continuous read mode and the Qspi controller is in the Xip mode, the MCU unit cancels the reset of the boot module to at least configure the read execution unit to enter the instruction read execution operation state.

[0182] Figure 3 An embodiment of the boot module is shown in FIG. 1 . As can be seen from the figure, the boot module should include a configuration unit and a read execution unit, wherein the configuration unit is used to configure the Flash memory in a four-wire fast continuous read mode and the Qspi controller in a Xip mode via the on-chip bus. The manner and process of configuring the Flash memory in a four-wire fast continuous read mode can refer to the above description and will not be repeated here. In addition, as can be seen from the above description, the Flash memory can also be configured in a four-wire fast continuous read mode and the Qspi controller can be configured in a Xip mode by means of a Jtag interface.

[0183] Specifically, the read execution unit enters the instruction read execution operation state, which specifically means that the read execution unit executes the read execution operation corresponding to the instruction read execution operation state. The specific process of the instruction read execution operation state can be referred to the above description, which will not be repeated here.

Claims

1. A high reliability chip startup method, characterized in that: The chip startup method comprises: For any target chip to be started, a boot module is at least set in the target chip, wherein the boot module is adaptively connected to a Flash memory storing a startup program through an on-chip bus; When starting the target chip, at least the Flash memory is configured in continuous read mode, after which the boot module is controlled to enter the instruction read and execute operation state, wherein: After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a startup configuration execution request corresponding to the instruction read request; For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module; For any startup instruction returned via the on-chip bus, the boot module immediately parses the startup instruction, and after parsing, initiates a corresponding startup configuration execution request to the on-chip bus, so as to perform startup configuration on the chip component connected to the on-chip bus based on the startup configuration execution request; When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state.

2. The high-reliability chip startup method according to claim 1, characterized in that: The Flash memory is connected to the on-chip bus through the Qspi controller, where When the Flash memory is configured in a continuous read mode via the Qspi controller, the Flash memory is at least configured in a four-wire fast continuous read mode via the boot module or the Jtag interface, wherein after the Flash memory is configured in the four-wire fast continuous read mode, the Qspi controller is configured in the Xip mode; When the Flash memory is configured as four-wire fast continuous read mode through the Jtag interface, the boot module is in reset state.

3. The high-reliability chip startup method according to claim 1, characterized in that: The instruction read execution request initiated by the boot module to the on-chip bus is a serial protocol request, in which: When the instruction read execution request initiated by the boot module to the on-chip bus is an instruction read request, the boot module can initiate the next instruction read request or startup configuration execution request to the on-chip bus only after receiving the startup instruction read response returned by the on-chip bus; When the instruction read execution request initiated by the boot module to the on-chip bus is a startup configuration execution request, the boot module can initiate the next instruction read request or startup configuration execution request to the on-chip bus only after receiving the startup configuration execution response returned by the on-chip bus.

4. The high-reliability chip startup method according to claim 3, characterized in that: The instruction read execution request includes a request valid identification signal xx2yy_req_valid, a request address xx2yy_req_addr, a request data xx2yy_req_data, a request write granularity status signal xx2yy_req_strb, a request type signal xx2yy_req_type and a request read granularity status signal xx2yy_req_rsize; When the request type signal xx2yy_req_type is in the first valid level state, the instruction read execution request is an instruction read request; When the request type signal xx2yy_req_type is in the second effective level state, the instruction read execution request is a startup configuration execution request.

5. The high-reliability chip startup method according to claim 4, characterized in that: For the startup configuration execution response and the startup command read response, there are: It includes a response valid identification signal yy2xx_ack_valid, response data yy2xx_ack_data and a response abnormal identification signal yy2xx_ack_excp, wherein: For any startup configuration execution response and startup instruction read response, when the response valid identification signal yy2xx_ack_valid is in the valid state, the response data yy2xx_ack_data and the response exception identification signal yy2xx_ack_excp are maintained until the request valid identification signal xx2yy_req_valid in the next instruction read execution request is in the valid state.

6. The high-reliability chip startup method according to claim 3, characterized in that: The startup instructions stored in the Flash memory also include NOP empty instructions, SETBASEH instructions, SETBASEL instructions, DELAY instructions, SETW instructions, WR.1 instructions, WR.2 instructions, WR.4 instructions and / or WR.8 instructions, wherein: After receiving and parsing the NOP instruction, based on the data in the NOP instruction, the boot module initiates a next instruction read request to the on-chip bus after the next clock cycle; After receiving and parsing the SETBASEH instruction, the boot module obtains the high base address of the write IO device; After receiving and parsing the SETBASEL instruction, the boot module obtains the low base address of the write IO device; After receiving and parsing the DELAY instruction, the boot module counts and waits until the count value corresponds to the delay time in the DELAY instruction. After that, the boot module initiates the next instruction read request to the on-chip bus; After receiving and parsing the SETW instruction, the boot module continuously writes to the chip components connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus; After receiving and parsing the WR.1 instruction, the boot module performs a 1-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus; After receiving and parsing the WR.2 instruction, the boot module performs a 2-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus; After receiving and parsing the WR.4 instruction, the boot module performs a 4-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus; After receiving and parsing the WR.8 instruction, the boot module performs an 8-byte write operation on the chip component connected to the on-chip bus through the on-chip bus, and waits for the startup configuration execution response returned by the on-chip bus.

7. The high-reliability chip startup method according to any one of claims 1 to 6, characterized in that: When the target chip cannot be started based on the boot module, the Jtag interface is used to configure the chip components in the target chip until the startup requirements of the target chip are met.

8. A high reliability chip, characterized in that: The chip is started by using the chip starting method according to any one of claims 1 to 7, and the chip comprises: Flash memory, storing at least a boot program, and connected to the on-chip bus via a Qspi controller; The boot module is connected to the on-chip bus and can configure the Flash memory in a four-wire fast continuous read mode, wherein after the Flash memory is configured in the four-wire fast continuous read mode, the Qspi controller is configured in the Xip mode; When the control chip starts, the control boot module enters the instruction reading and execution operation state, where: After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a startup configuration execution request corresponding to the instruction read request; For any instruction read request, the on-chip bus reads the startup instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read startup instruction to the boot module; For any startup instruction returned via the on-chip bus, the boot module immediately parses the startup instruction, and after parsing, initiates a corresponding startup configuration execution request to the on-chip bus, so as to perform startup configuration on the chip component connected to the on-chip bus based on the startup configuration execution request; When the startup instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state.

9. The high reliability chip according to claim 8, characterized in that: The boot module includes a configuration unit and a read execution unit, wherein: When the configuration chip is started, the reset of the boot module is cancelled by using the off-chip MCU unit, and thereafter, the Flash memory is configured in the four-wire fast continuous read mode via the on-chip bus by using the configuration unit in the boot module, and the Qspi controller is configured in the Xip mode, or, the boot module is controlled to be in the reset state by using the off-chip MCU unit, and thereafter, the Flash memory is configured in the four-wire fast continuous read mode and the Qspi controller is configured in the Xip mode by at least using the Jtag interface; When the Flash memory is configured in the four-wire fast continuous read mode and the Qspi controller is in the Xip mode, the MCU unit cancels the reset of the boot module to at least configure the read execution unit to enter the instruction read execution operation state.

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