Computer channel fault monitoring method and device comprising instruction-monitoring branch

Abstract

The invention provides a computer channel fault monitoring method and device comprising an instruction-monitoring branch circuit, and the method comprises the steps: 1, carrying out the comprehensive obtaining of a channel fault reset (RESET) signal according to a power ON Reset Pulse (PORP) signal and a digital fault reset (DPFR) signal, and carrying out the comprehensive obtaining of a channel fault reset (RESET) signal according to the PORP signal and the DPFR signal; and 2, according to the RESET signal, through instruction branch fault judgment, monitoring branch fault judgment, monitoring branch state judgment, remote channel fault judgment, inter-branch fault judgment and channel state judgment, channel state judgment is realized.

Description

Technical Field

[0001] The invention belongs to system redundancy management and fault tolerance technology, and in particular relates to a computer channel fault monitoring method and device including an instruction-monitoring branch. Background Art

[0002] Redundancy management strategy is the core of redundancy technology. The quality of the strategy plays a decisive role in the reliability and availability of the redundancy system. For redundant computers, in addition to designing related redundancy management software to identify, isolate and report faults in computer signals, it is also necessary to introduce a monitoring system at the hardware level to detect the status of each channel, locate and isolate faults, and support the switching of control channels and system reconstruction.

[0003] The existing computer channel fault monitoring is designed for the architecture with only one instruction branch or two main instruction branches in a redundant channel. With the development of technology, computer architectures with self-monitoring capabilities have emerged, that is, a channel contains instruction branches and monitoring branches, and the reliability of computers is improved from the architectural perspective through self-monitoring. However, the more complex structure requires more factors to be considered when designing channel fault monitoring strategies, and the original channel fault monitoring method is no longer applicable. Summary of the invention

[0004] The present invention provides a computer channel fault monitoring method and device including an instruction-monitoring branch, which can solve the problem of monitoring computer channel faults of a complex architecture including an instruction-monitoring branch.

[0005] In a first aspect, the present application provides a computer channel fault monitoring method including an instruction-monitoring branch, the method comprising:

[0006] Step 1: According to the power-on reset pulse (PORP) signal and the digital processor fault reset (DPFR) signal, a channel fault reset (RESET) signal is obtained by synthesizing the channel fault reset (RESET) signal;

[0007] Step 2: According to the RESET signal, the channel status is judged through command branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment and channel status judgment.

[0008] Furthermore, step 1 includes:

[0009] Step 11: Collect PORP signal and DPFR signal;

[0010] Step 12: Determine the signal status of the PORP signal and the DPFR signal; when powered on, the PORP signal is valid; if fault recovery is required, the DPFR signal is valid;

[0011] Step 13: If the PORP signal is valid, or the DPFR signal is valid, the output RESET signal is valid.

[0012] Furthermore, step 2 includes:

[0013] Step 21: According to the relevant flags representing the health status of the command branch of this channel, determine the status of the command branch valid (Local Channel Valid_Command, LCV_CMD) signal;

[0014] Step 22: According to the relevant flags representing the health status of the monitoring branch of this channel, determine the status of the monitoring branch valid (Local Channel Valid_Monitor, LCV_MON) signal;

[0015] Step 23: According to the LCV_MON signal and the RESET signal, determine the status of the monitoring branch digital processor valid (Digital Processor Valid_Monitor, DPV_MON) signal;

[0016] Step 24: judging the status of the remote channel comprehensive valid (Local Channel Valid Remote, LCHVR) signal according to the remote channel's cognitive information on whether the local channel is operating correctly and the PORP signal;

[0017] Step 25: Determine the state of the command channel self-monitoring (In Line Monitor, ILM) signal according to the command branch self-monitoring (In Line Monitor_Command, ILM_COM) signal, the WDV_CMD signal, the PSV signal, the RESET signal, and the DPV_MON signal;

[0018] Step 26: Determine the status of the Channel Valid (CHV) signal based on the LCV_CMD signal, LCHVR signal, RESET signal, ILM signal, and other channel command branch digital processor valid (Digital Processor Valid_Command_From…, DPV_CMD_FX / Y / …) signals.

[0019] Furthermore, step 21 includes:

[0020] Step 211, collect instruction branch health status flags, including instruction branch CPU valid (CPUV_CMD), instruction branch watchdog valid (WDV_CMD) and channel power valid (PSV);

[0021] Step 212, judging the status of CPUV_CMD signal, WDV_CMD signal, and PSV; if the instruction branch software runs correctly, the CPUV_CMD signal is valid; if the instruction branch software runs normally, the WDV_CMD signal is valid; if the computer power supply is normal, the PSV signal is valid;

[0022] Step 213: When the CPUV_CMD signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, the output LCV_CMD signal is valid.

[0023] Further, step 22 includes:

[0024] Step 221, collecting monitoring branch health status flag signals, including monitoring branch CPU valid (CPUV_MON), monitoring branch watchdog valid (WDV_MON), channel power valid (PSV);

[0025] Step 222, judging the status of CPUV_MON signal, WDV_MON signal, and PSV; if the monitoring branch software runs correctly, the CPUV_MON signal is valid; if the monitoring branch software runs normally, the WDV_MON signal is valid; if the computer power supply is normal, the PSV signal is valid;

[0026] Step 223, when the CPUV_MON signal is valid, the WDV_MON signal is valid, and the PSV signal is valid, the output LCV_MON signal is valid.

[0027] Further, step 23 includes:

[0028] Step 231, if the LCV_MON signal is valid, the DPV_MON signal is output as valid; if the LCV_MON signal is invalid and the duration exceeds the set fault delay, the DPV_MON signal is latched as invalid;

[0029] Step 232: If the RESET signal is valid, the DPV_MON signal is released from latching.

[0030] Further, step 24 includes:

[0031] Step 241, collect the cognitive information of the remote channel on whether the channel is running correctly, including the digital machine judgment from other channel instructions (Digital Processor From_X / Y..., DP_FX / Y...);

[0032] Step 242, determine the status of the DP_FX / Y / ... signal. If other channels believe that the status of this channel is good, the DP_FX / Y... signal from this channel is valid.

[0033] Step 243, if any one of the DP_FX / Y / ... signals is valid, the output LCHVR signal is valid;

[0034] Step 244: If the PORP signal is valid, the output LCHVR signal is valid.

[0035] Further, step 25 includes:

[0036] Step 251, collecting ILM_COM signal;

[0037] Step 252, judging the signal state of the ILM_COM signal, comparing the instruction calculated by the instruction branch CPU with the instruction calculated by the monitoring branch CPU, using a mature two-redundancy comparison monitoring algorithm, if there is no fault, the ILM_COM signal is valid;

[0038] Step 253, if the ILM_COM signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output branch comprehensive valid (In Line Monitor_Monitor, ILM_MON) signal is valid;

[0039] Step 254, if the ILM_MON signal is invalid and the duration exceeds the set delay, the ILM_MON signal is latched as invalid;

[0040] Step 255, if the RESET signal is valid, then release the latch of the ILM_MON signal;

[0041] Step 256 , if the DPV_MON signal is valid and the ILM_MON signal is valid, the output ILM signal is valid.

[0042] Further, step 26 includes:

[0043] Step 261, if the LCV_CMD signal is valid and the LCHVR signal is valid, then the output DPV_CMD signal is valid, otherwise it is invalid;

[0044] Step 262, if the DPV_CMD signal is invalid and the duration exceeds the set delay, the DPV_CMD signal is latched as invalid;

[0045] Step 263, if the RESET signal is valid, then release the latch of the DPV_CMD signal;

[0046] Step 264, collect DPV_CMD_FX / Y / ... signals from other channels

[0047] Step 265, determine the state of the DPV_CMD_FX / Y / ... signal. If the state of other channels is valid, then the DPV_CMD_FX / Y... from this channel is valid.

[0048] Step 266, if at least one of the DPV_CMD signal and the DPV_CMD_FX / Y / ... signal is valid, then judge based on the DPV_CMD signal of the current channel; if the DPV_CMD signal is valid, then the output CHV signal is valid; if the DPV_CMD signal is invalid, then the output CHV signal is invalid;

[0049] Step 267, if all signals in DPV_CMD and DPV_CMD_FX / Y / … are invalid or only one signal is valid, judge according to the ILM signal; if the ILM signal is valid, the output CHV signal is valid; if the ILM signal is invalid, the output CHV signal is invalid.

[0050] In a second aspect, the present application provides a computer channel fault monitoring device comprising an instruction-monitoring branch, a channel fault resetting unit and a channel status determination unit, wherein:

[0051] The channel fault reset unit is used to obtain a channel fault reset (RESET) signal based on a power-on reset pulse (PORP) signal and a digital processor fault reset (DPFR) signal;

[0052] The channel status judgment unit is used to judge the channel status according to the RESET signal through instruction branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment and channel status judgment.

[0053] In summary, the present invention proposes a computer channel fault monitoring method and device including an instruction-monitoring branch, and the beneficial effects are:

[0054] 1. When monitoring channel faults, the impact between redundant channels is comprehensively considered and a reasonable comprehensive strategy is designed;

[0055] 2. Comprehensively consider the impact between different branches in the redundancy channel, adapt to the computer architecture of the self-monitoring pair, support subsequent fault isolation, processing, reporting and other work, and improve system reliability;

[0056] 3. Comprehensively consider the recovery and establishment of channel monitoring in different scenarios such as reset and startup;

[0057] 4. Through modular and universal strategy design, it supports configuration of applicable channel fault monitoring methods according to different redundancy level architectures, which improves the flexibility and availability of the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A functional composition diagram of a redundant computer channel fault monitoring method including an instruction-monitoring branch;

[0059] Figure 2 This is a schematic diagram of channel fault reset;

[0060] Figure 3 This is a schematic diagram for judging faults in the instruction branch;

[0061] Figure 4 This is a schematic diagram for monitoring branch fault judgment;

[0062] Figure 5 It is a schematic diagram for judging the state of the monitoring branch;

[0063] Figure 6 This is a schematic diagram for judging remote channel faults;

[0064] Figure 7 This is a schematic diagram for judging faults between branches;

[0065] Figure 8 This is a schematic diagram of channel status judgment. DETAILED DESCRIPTION

[0066] like Figure 1 As shown, the present invention proposes a computer channel fault monitoring method including an instruction-monitoring branch, comprising:

[0067] Step 1: According to the power-on reset pulse (PORP) signal and the digital processor fault reset (DPFR) signal, a channel fault reset (RESET) signal is obtained.

[0068] Further, such as Figure 2As shown, step 1 includes:

[0069] Step 11: Collect PORP signal and DPFR signal;

[0070] Step 12: Determine the signal status of the PORP signal and the DPFR signal; when powered on, the PORP signal is valid; if fault recovery is required, the DPFR signal is valid;

[0071] Step 13: If the PORP signal is valid, or the DPFR signal is valid, the output RESET signal is valid.

[0072] Step 2: According to the RESET signal, the channel status is judged through command branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment and channel status judgment.

[0073] Furthermore, step 2 includes:

[0074] Step 21: According to the relevant flags representing the health status of the command branch of this channel, determine the status of the command branch valid (Local Channel Valid_Command, LCV_CMD) signal;

[0075] Specifically, Figure 3 As shown, step 21 includes:

[0076] Step 211, collect instruction branch health status flags, including instruction branch CPU valid (CPUV_CMD), instruction branch watchdog valid (WDV_CMD) and channel power valid (PSV);

[0077] Step 212, judging the states of the CPUV_CMD signal, the WDV_CMD signal, and the PSV signal; if the instruction branch software runs correctly, the CPUV_CMD signal is valid; if the instruction branch software runs normally, the WDV_CMD signal is valid; if the computer power supply is normal, the PSV signal is valid;

[0078] Step 213, when the CPUV_CMD signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, the output LCV_CMD signal is valid;

[0079] Step 22: According to the relevant flags representing the health status of the monitoring branch of this channel, determine the status of the monitoring branch valid (Local Channel Valid_Monitor, LCV_MON) signal;

[0080] Specifically, Figure 4 As shown, step 22 includes:

[0081] Step 221, collect monitoring branch health status flag signals, including monitoring branch CPU valid (CPUV_MON), monitoring branch watchdog valid (WDV_MON), and channel power valid (PSV).

[0082] Step 222, judging the status of the CPUV_MON signal, the WDV_MON signal, and the PSV signal; if the monitoring branch software runs correctly, the CPUV_MON signal is valid; if the monitoring branch software runs normally, the WDV_MON signal is valid; if the computer power supply is normal, the PSV signal is valid;

[0083] Step 223, when the CPUV_MON signal is valid, the WDV_MON signal is valid, and the PSV signal is valid, the output LCV_MON signal is valid;

[0084] Step 23: According to the LCV_MON signal and the RESET signal, determine the status of the monitoring branch digital processor valid (Digital Processor Valid_Monitor, DPV_MON) signal.

[0085] Specifically, Figure 5 As shown, step 23 includes:

[0086] Step 231, if the LCV_MON signal is valid, the DPV_MON signal is output as valid; if the LCV_MON signal is invalid and the duration exceeds the set fault delay, the DPV_MON signal is latched as invalid;

[0087] Step 232: If the RESET signal is valid, the DPV_MON signal is released from latching.

[0088] Step 24: Based on the remote channel's cognitive information on whether the local channel is operating correctly and the PORP signal, determine the status of the remote channel comprehensive valid (Local Channel Valid Remote, LCHVR) signal.

[0089] Specifically, Figure 6 As shown, step 24 includes:

[0090] Step 241, collect the cognitive information of the remote channel on whether the channel is running correctly, including the digital machine judgment from other channel instructions (Digital Processor From X / Y..., DP_FX / Y...);

[0091] If the digital machine judges the instruction from other channels as Digital Processor From X, it means the judgment of the X channel CPU on the status of this channel.

[0092] It should be noted that the method provided in this application is applied to a redundant computer. The redundant computer includes multiple channels, and the number of command digital machine judgment signals from other channels is related to the redundancy number, and the specific number should be the current redundancy number minus 1.

[0093] Step 242, determine the status of the DP_FX / Y / ... signal. If other channels believe that the status of this channel is good, the DP_FX / Y... signal from this channel is valid.

[0094] Step 243, if any one of the DP_FX / Y / ... signals is valid, the output LCHVR signal is valid;

[0095] Step 244: If the PORP signal is valid, the output LCHVR signal is valid.

[0096] Step 25: Determine the state of the command channel self-monitoring (In Line Monitor, ILM) signal according to the command branch self-monitoring (In Line Monitor_Command, ILM_COM) signal, WDV_CMD signal, PSV signal, RESET signal, and DPV_MON signal.

[0097] It should be noted that the comprehensive consideration of the inter-branch faults mainly considers the impact of the comparative monitoring between the instruction branch and the monitoring branch in the presence of a self-monitoring pair, and the monitoring effect of the monitoring branch on the instruction branch.

[0098] Specifically, Figure 7 As shown, step 25 includes:

[0099] Step 251, collecting ILM_COM signal;

[0100] Step 252, judging the signal state of the ILM_COM signal, comparing the instruction calculated by the instruction branch CPU with the instruction calculated by the monitoring branch CPU, using a mature two-redundancy comparison monitoring algorithm, if there is no fault, the ILM_COM signal is valid;

[0101] Step 253, if the ILM_COM signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output branch comprehensive valid (In Line Monitor_Monitor, ILM_MON) signal is valid;

[0102] Step 254, if the ILM_MON signal is invalid and the duration exceeds the set delay, the ILM_MON signal is latched as invalid;

[0103] Step 255, if the RESET signal is valid, then release the latch of the ILM_MON signal;

[0104] Step 256, if the DPV_MON signal is valid and the ILM_MON signal is valid, the output ILM signal is valid;

[0105] Step 26: Determine the status of the channel valid (Channel Valid, CHV) signal based on the LCV_CMD signal, LCHVR signal, RESET signal, ILM signal, and other channel command branch digital processor valid (Digital ProcessorValid_Command_FromX / Y…, DPV_CMD_FX / Y / …) signals.

[0106] If the digital processor of the command branch of other channels is valid as Digital Processor Valid_Command_From X, it means that the X channel sends its digital processor status to this channel.

[0107] It should be noted that the method provided in this application is applied to a redundant computer. The redundant computer includes multiple channels, and the number of valid signals of the other channel instruction digital machine is related to the redundancy number, and the specific number should be the current redundancy number minus 1.

[0108] Specifically, Figure 8 As shown, step 26 includes:

[0109] Step 261, if the LCV_CMD signal is valid and the LCHVR signal is valid, then the output DPV_CMD signal is valid, otherwise it is invalid;

[0110] Step 262, if the DPV_CMD signal is invalid and the duration exceeds the set delay, the DPV_CMD signal is latched as invalid;

[0111] Step 263, if the RESET signal is valid, then release the latch of the DPV_CMD signal;

[0112] Step 264, collect DPV_CMD_FX / Y / ... signals from other channels

[0113] Step 265, determine the state of the DPV_CMD_FX / Y / ... signal. If the state of other channels is valid, then the DPV_CMD_FX / Y... from this channel is valid.

[0114] Step 266, if at least one of the DPV_CMD signal and the DPV_CMD_FX / Y / … signal is valid, judge based on the DPV_CMD signal of this channel; if the DPV_CMD signal is valid, the output CHV signal is valid; if the DPV_CMD signal is invalid, the output CHV signal is invalid.

[0115] Step 267, if all signals in DPV_CMD and DPV_CMD_FX / Y / … are invalid or only one signal is valid, judge according to the ILM signal; if the ILM signal is valid, the output CHV signal is valid; if the ILM signal is invalid, the output CHV signal is invalid.

[0116] In summary, the present invention proposes a computer channel fault monitoring method and device including an instruction-monitoring branch. For a redundant computer including an instruction-monitoring branch, based on the self-status information provided by each redundant channel and each branch, the mutual influence between redundant channels and between instruction and monitoring branches is comprehensively considered to realize the identification of computer channel faults and output channel status flags to support the switching of control channels and the reconstruction of the system. The purpose of eliminating / reducing the influence of channel faults on computer performance as much as possible and improving system reliability is achieved.

[0117] Embodiment 1

[0118] Take the channel fault monitoring of a certain type of aircraft flight control computer as an example. The flight control computer has a four-redundancy architecture, including four redundant channels A, B, C, and D. Each redundant channel is configured with a command branch and a monitoring branch. At this time, the command branch CPU of the flight control computer channel A is valid, the command branch watchdog is valid, the power supply is valid, the monitoring branch CPU is valid, the monitoring branch watchdog is valid, the power-on reset pulse signal is invalid, the digital machine fault reset signal is invalid, the command from the B channel is judged to be valid, the command from the C channel is judged to be valid, the command from the D channel is judged to be valid, the self-monitoring of the command branch of the A channel is valid, the command from the B channel is invalid, the command from the C channel is invalid, and the command from the D channel is invalid. The channel fault monitoring method of the A channel is as follows:

[0119] 1. If the "power-on reset pulse signal" is "invalid" and the "digital machine fault reset" signal is "invalid", then the "channel fault reset" signal is invalid;

[0120] 2. If the "instruction branch CPU valid" signal is "valid", the "instruction branch watchdog monitoring valid" signal is "valid", and the "channel power valid" signal is "valid", then the "instruction branch valid" signal is "valid";

[0121] 3. If the "monitoring branch CPU valid" signal is "valid", the "monitoring branch watchdog monitoring valid" signal is "valid", and the "channel power valid" signal is "valid", set the "monitoring branch valid" signal to "valid";

[0122] 4. If the "monitoring branch valid" signal is "valid", the output "monitoring branch digital machine valid" signal is "valid";

[0123] 5. "Digital machine judgment of commands from channels B, C, and D" are all "valid", so the "remote channel comprehensive valid" signal is "valid";

[0124] 6. The "command branch self-monitoring" signal is "valid", the "command branch watchdog valid" signal is "valid", and the "channel power valid" signal is "valid", so the "branch comprehensive valid" signal is "valid";

[0125] 7. The "command branch valid" signal is "valid" and the "other channels comprehensive valid" signal is "valid", so the "command branch digital machine valid" signal of channel A is "valid";

[0126] 8. The "command branch digital machine valid" signals of the four redundancy channels A, B, C, and D are all "valid". According to the "command branch digital machine valid" signal of channel A, the current status of channel A is normal, that is, the "channel valid" signal is "valid".

[0127] Embodiment 2

[0128] Take the channel fault monitoring of a certain type of aircraft servo control computer as an example. The servo control computer has a three-redundancy architecture, including three redundant channels A, B, and C. Each redundant channel is configured with a command branch and a monitoring branch. At this time, the command branch CPU of the servo control computer channel A is valid, the command branch watchdog is valid, the power supply is valid, the monitoring branch CPUV is valid, the monitoring branch watchdog is valid, the power-on reset pulse signal is invalid, the digital machine fault reset signal is invalid, the command from the B channel is judged to be invalid, the command from the C channel is judged to be invalid, the self-monitoring of the command branch of the A channel is valid, the command of the B channel is invalid, and the command of the C channel is invalid. The channel fault monitoring method of the A channel is as follows:

[0129] 1. If the "power-on reset pulse" signal is "invalid" and the "digital machine fault recovery" signal is "invalid", the "channel fault reset" signal is invalid;

[0130] 2. If the "instruction branch CPU valid" signal is "valid", the "instruction branch watchdog monitoring valid" signal is "valid", and the "channel power valid" signal is "valid", then the "instruction branch valid" signal is "valid";

[0131] 3. If the "monitoring branch CPU valid" signal is "valid", the "monitoring branch watchdog monitoring valid" signal is "valid", and the "channel power valid" signal is "valid", set the "monitoring branch valid" signal to "valid";

[0132] 4. If the "monitoring branch valid" signal is "valid", the output "monitoring branch digital machine valid" signal is "valid";

[0133] 5. "Digital machine judgment of commands from channels B, C, and D" are all "invalid", so the "remote channel comprehensive validity" signal is "invalid";

[0134] 6. The "command branch self-monitoring" signal is "valid", the "command branch watchdog valid" signal is "valid", and the "channel power valid" signal is "valid", so the "branch comprehensive valid" signal is "valid";

[0135] 7. The "command branch valid" signal is "valid", and the "other channels comprehensive valid" signal is "invalid", so the "command branch digital machine valid" signal of channel A is "invalid";

[0136] 8. The "command branch digital machine valid" signal of channel A is "invalid", and the "command branch digital machine valid" signals of the two redundant channels B and C are both "invalid". It is necessary to judge based on the "branch comprehensive valid" signal. At this time, the "branch comprehensive valid" signal is "valid", so the current state of channel A is normal, that is, the "channel valid" signal is "valid".

Claims

1. A computer channel fault monitoring method including an instruction-monitoring branch, characterized in that: Methods include: Step 1: According to the Power ON Reset Pulse (PORP) signal and the Digital Processor Fault Reset (DPFR) signal, a channel fault reset (RESET) signal is obtained; Step 2: According to the RESET signal, the channel status is judged through command branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment and channel status judgment.

2. The computer channel fault monitoring method according to claim 1, characterized in that: Step 1 includes: Step 11: Collect PORP signal and DPFR signal; Step 12: Determine the signal status of the PORP signal and the DPFR signal; when powered on, the PORP signal is valid; if fault recovery is required, the DPFR signal is valid; Step 13: If the PORP signal is valid, or the DPFR signal is valid, the output RESET signal is valid.

3. The computer channel fault monitoring method according to claim 1, characterized in that: Step 2 includes: Step 21: According to the relevant flags representing the health status of the command branch of this channel, determine the status of the command branch valid (LocalChannel Val id_Command, LCV_CMD) signal; Step 22: According to the relevant flags representing the health status of the monitoring branch of this channel, determine the status of the monitoring branch valid (LocalChannel Val id_Monitor, LCV_MON) signal; Step 23: According to the LCV_MON signal and the RESET signal, determine the status of the monitoring branch digital processor valid (Digital Processor Valid_Monitor, DPV_MON) signal; Step 24: judging the status of the local channel comprehensive valid (Local Channel Val id Remote, LCHVR) signal according to the remote channel's cognitive information on whether the local channel is operating correctly and the PORP signal; Step 25: Determine the state of the command channel self-monitoring (In Line Monitor, ILM) signal according to the command branch self-monitoring (In Line Monitor_Command, ILM_COM) signal, the WDV_CMD signal, the PSV signal, the RESET signal, and the DPV_MON signal; Step 26: According to the LCV_CMD signal, LCHVR signal, RESET signal, ILM signal, other channel command branch digital machine is effective (Digital Processor Val id_Command_From X / Y / …,DPV_CMD_FX / Y / …) signal to determine the status of the channel valid (Channel Valid, CHV) signal.

4. The computer channel fault monitoring method according to claim 3, characterized in that: Step 21 includes: Step 211, collect instruction branch health status flags, including instruction branch CPU valid (CPUV_CMD), instruction branch watchdog valid (WDV_CMD) and channel power valid (PSV); Step 212, judging the states of the CPUV_CMD signal, the WDV_CMD signal, and the PSV signal; if the instruction branch software runs correctly, the CPUV_CMD signal is valid; if the instruction branch software runs normally, the WDV_CMD signal is valid; if the computer power supply is normal, the PSV signal is valid; Step 213: When the CPUV_CMD signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, the output LCV_CMD signal is valid.

5. The computer channel fault monitoring method according to claim 3, characterized in that: Step 22 includes: Step 221, collecting monitoring branch health status flag signals, including monitoring branch CPU valid (CPUV_MON), monitoring branch watchdog valid (WDV_MON), channel power valid (PSV); Step 222, judging the status of the CPUV_MON signal, the WDV_MON signal, and the PSV signal; if the monitoring branch software runs correctly, the CPUV_MON signal is valid; if the monitoring branch software runs normally, the WDV_MON signal is valid; if the computer power supply is normal, the PSV signal is valid; Step 223, when the CPUV_MON signal is valid, the WDV_MON signal is valid, and the PSV signal is valid, the output LCV_MON signal is valid.

6. The computer channel fault monitoring method according to claim 3, characterized in that: Step 23 includes: Step 231, if the LCV_MON signal is valid, the DPV_MON signal is output as valid; if the LCV_MON signal is invalid and the duration exceeds the set fault delay, the DPV_MON signal is latched as invalid; Step 232: If the RESET signal is valid, the DPV_MON signal is released from latching.

7. The computer channel fault monitoring method according to claim 3, characterized in that: Step 24 includes: Step 241, collect the cognitive information of the remote channel on whether the channel is running correctly, including the digital machine judgment from other channel instructions (Digital Processor From..., DP_FX / Y...); Step 242, judging the status of the DP / FX / Y / ... signal, if other channels consider that the status of this channel is good, then the DP / F... signal from this channel is valid; Step 243, if any one of the DP_FX / Y / ... signals is valid, the output LCHVR signal is valid; Step 244: If the PORP signal is valid, the output LCHVR signal is valid.

8. The computer channel fault monitoring method according to claim 3, characterized in that: Step 25 includes: Step 251, collecting ILM_COM signal; Step 252, judging the signal state of the ILM_COM signal, comparing the instruction calculated by the instruction branch CPU with the instruction calculated by the monitoring branch CPU, using a mature two-redundancy comparison monitoring algorithm, if there is no fault, the ILM_COM signal is valid; Step 253, if the ILM_COM signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output branch comprehensive valid (In Line Monitor_Monitor, ILM_MON) signal is valid; Step 254, if the ILM_MON signal is invalid and the duration exceeds the set delay, the ILM_MON signal is latched as invalid; Step 255, if the RESET signal is valid, then release the latch of the ILM_MON signal; Step 256 , if the DPV_MON signal is valid and the ILM_MON signal is valid, the output ILM signal is valid.

9. The computer channel fault monitoring method according to claim 3, characterized in that: Step 26 includes: Step 261, if the LCV_CMD signal is valid and the LCHVR signal is valid, the output DPV_CMD signal is valid, otherwise it is invalid; Step 262, if the DPV_CMD signal is invalid and the duration exceeds the set delay, the DPV_CMD signal is latched as invalid; Step 263, if the RESET signal is valid, then release the latch of the DPV_CMD signal; Step 264, collect DPV_CMD_FX / Y / ... signals from other channels Step 265, determine the state of the DPV_CMD_FX / Y / ... signal. If the state of other channels is valid, then the DPV_CMD_FX / Y... from this channel is valid. Step 266, if at least one of the DPV_CMD signal and the DPV_CMD_FX / Y / ... signal is valid, then judge based on the DPV_CMD signal of the current channel; if the DPV_CMD signal is valid, then the output CHV signal is valid; if the DPV_CMD signal is invalid, then the output CHV signal is invalid; Step 267, if all signals in DPV_CMD and DPV_CMD_FX / Y / … are invalid or only one signal is valid, judge according to the ILM signal; if the ILM signal is valid, the output CHV signal is valid; if the ILM signal is invalid, the output CHV signal is invalid.

10. A computer channel fault monitoring device comprising an instruction-monitoring branch, characterized in that: Channel fault reset unit and channel status judgment unit, including: The channel fault reset unit is used to obtain a channel fault reset (RESET) signal based on a power-on reset pulse (PORP) signal and a digital processor fault reset (DPFR) signal; The channel status judgment unit is used to judge the channel status according to the RESET signal through instruction branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment and channel status judgment.

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