Chip debugging method based on controller area network bus, chip, debugger and device

Abstract

The invention relates to the technical field of integrated circuits, and discloses a chip debugging method based on a controller area network bus, which is applied to a chip, the chip is connected with a debugger through the controller area network bus, and the chip debugging method comprises the following steps: receiving a detection sequence transmitted through the controller area network bus and generated by the debugger, activating a serial line debugging protocol function of the chip based on the detection sequence; after the serial line debugging protocol function of the chip is activated, generating a response sequence based on the detection sequence; sending the response sequence to the controller area network bus; and receiving a reset sequence transmitted by the controller area network bus, and resetting the debugging function based on the serial line debugging protocol of the chip based on the reset sequence. According to the method, the automobile chip can be debugged without opening the box, and the debugging difficulty of the automobile chip is reduced. The invention further discloses a chip debugging device based on the controller local area network bus, a chip, a debugger and a device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and for example, to a chip debugging method based on a controller area network bus, a chip, a debugger, and a device. Background Art

[0002] At present, when debugging a chip, JTAG (Joint Test Action Group) or SWD (Serial Wire Debug) protocol is usually used for debugging. Among them, the SWD protocol includes a SWD_CLK port for transmitting the SWD clock and a SWD_DATA port for transmitting the SWD data. The SWD_DATA port is a bidirectional port, which can be used as both an input port and an output port.

[0003] However, there are some types of chips whose JTAG / SWD ports are not easy to connect during use. For example, if a car chip is debugged using a traditional JTAG / SWD port, the car needs to be disassembled, making debugging of the car chip more difficult.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0006] The disclosed embodiments provide a chip debugging method, chip, debugger and device based on a controller area network bus, which can debug an automotive chip without unpacking the chip, thereby reducing the difficulty of debugging the automotive chip.

[0007] In some embodiments, the chip debugging method is applied to a chip, and the chip debugging method includes: the chip is connected to a debugger via a controller local area network bus, and the chip debugging method includes: receiving a detection sequence generated by the debugger and transmitted via the controller local area network bus, and activating a serial wire debugging protocol function of the chip based on the detection sequence; after activating the serial wire debugging protocol function of the chip, generating a response sequence based on the detection sequence; wherein the response sequence includes a slave clock signal; sending the response sequence to the controller local area network bus; receiving a reset sequence transmitted by the controller local area network bus, and resetting the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence; wherein the reset sequence is generated after the debugger receives the response sequence and determines that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

[0008] In some embodiments, the chip includes a serial wire debug port slave circuit, which is connected to a controller local area network bus; activating the serial wire debug protocol function of the chip based on a detection sequence, including: when the validity of the detection sequence is valid, driving the serial wire debug port slave circuit to enable the serial wire debug port slave circuit to activate the serial wire debug protocol function; resetting the debugging function of the chip based on the serial wire debug protocol based on a reset sequence, including: when the validity of the reset sequence is valid, resetting the serial wire debug port slave circuit to enable the serial wire debug port slave circuit to reset the debugging function based on the serial wire debug protocol.

[0009] In some embodiments, the validity of the detection sequence is determined in the following manner: when the detection sequence includes a zero bit of a first duration and a first number of bits of a first time-series continuous first coding unit, a first period difference between the period of each first coding unit and the period of the previous coding unit of each first coding unit is obtained; when all first period differences meet the period deviation condition, the validity of the detection sequence is determined to be valid; wherein the first coding unit includes Manchester-01 or Manchester-10.

[0010] In some embodiments, a response sequence is generated based on a detection sequence, including: decoding the detection sequence in a Manchester decoding manner to obtain a host clock cycle and Manchester data, and parsing the Manchester data to obtain a data phase; generating a slave clock reference signal; performing phase compensation processing on the slave clock reference signal according to the host clock cycle and the data phase to obtain a slave clock signal; encoding the slave clock signal in a Manchester encoding manner to generate a third encoding unit of a third bit number; constructing a response sequence based on a zero bit of a second duration and a first encoding unit of a second bit number, a second encoding unit of a second bit number, and a third encoding unit of a third bit number; wherein the first encoding unit is sequentially continuous with the second encoding unit and the third encoding unit, the first encoding unit is one of Manchester-01 and Manchester-10, and the second encoding unit is the other of Manchester-10 and Manchester-01.

[0011] In some embodiments, the chip debugging method is applied to a debugger, and the chip debugging method includes: generating a detection sequence; sending the detection sequence to a controller local area network bus so that the chip activates a serial wire debugging protocol function based on the detection sequence; receiving a response sequence transmitted by the controller local area network bus, and generating a reset sequence when determining that a slave clock cycle corresponding to a slave clock signal matches a host clock cycle; wherein the response sequence is generated based on the detection sequence after the serial wire debugging protocol function of the chip is activated, and the response sequence includes a slave clock signal; sending a reset sequence to the controller local area network bus so that the chip resets the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence.

[0012] In some embodiments, generating a detection sequence includes: constructing a detection sequence based on a first coding unit with a zero bit of a first duration and a first number of bits that are continuous in time sequence; and / or generating a reset sequence includes: constructing a reset sequence based on a first coding unit with a zero bit of a first duration and a second number of bits that are continuous in time sequence; wherein the first coding unit includes Manchester-01 or Manchester-10, and the second number of bits is greater than the first number of bits.

[0013] In some embodiments, whether the slave clock period corresponding to the slave clock signal matches the host clock period is determined in the following manner: a second cycle difference between the slave clock period and the host clock period is calculated; if the second cycle difference meets the cycle deviation condition, it is determined that the slave clock period matches the host clock period; or, if the second cycle difference does not meet the cycle deviation condition, it is determined that the slave clock period does not match the host clock period.

[0014] In some embodiments, a reset sequence is generated when it is determined that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle, including: generating a successful reply response sequence when the slave clock cycle corresponding to the slave clock signal matches the host clock cycle; sending a successful reply response sequence to the controller LAN bus to notify the chip that its response sequence has been sent successfully; and generating a reset sequence after sending the successful reply response sequence to the controller LAN bus.

[0015] In some embodiments, it also includes: after sending a reset sequence to the controller local area network bus, generating a serial line debug clock and serial line debug data; encoding the serial line debug clock and serial line debug data in Manchester encoding based on the serial line debug protocol to obtain debug data; sending the debug data to the controller local area network bus so that the chip can be debugged based on the debug data.

[0016] In some embodiments, the chip includes: a slave serial communication protocol transceiver, connected to a controller area network bus and configured to receive a detection sequence transmitted by the controller area network bus; a serial wire debug port slave circuit, connected to a slave serial communication protocol transceiver and configured to: activate the serial wire debug protocol function of the chip based on the detection sequence; after activating the serial wire debug protocol function of the chip, generate a response sequence based on the detection sequence, and send the response sequence to the slave serial communication protocol transceiver; receive a reset sequence transmitted by the controller area network bus, and reset the chip's debugging function based on the serial wire debug protocol based on the reset sequence; wherein the response sequence includes a slave clock signal, and the reset sequence is generated after the debugger receives the response sequence and determines that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

[0017] In some embodiments, the chip further includes a serial line debug slave circuit, and the serial line debug port slave circuit includes: an activation sequence detection module, connected to the slave serial communication protocol transceiver, configured to receive a detection sequence and drive the serial line debug port slave circuit when the validity of the detection sequence is valid; a slave decoding module, connected to the serial line debug slave circuit, configured to decode the detection sequence in a Manchester decoding manner, obtain a host clock cycle and Manchester data, and send the Manchester data to the serial line debug slave circuit so that the serial line debug slave circuit parses the Manchester data to obtain a data phase; a clock control module, respectively connected to the serial communication protocol transceiver and the serial line debug slave circuit, configured to generate a slave clock reference signal, And according to the host clock cycle and the data phase sent by the serial line debugging slave circuit, the slave clock reference signal is phase compensated to obtain the slave clock signal; the slave encoding module is connected to the controller local area network bus and the serial line debugging slave circuit respectively, and is configured to encode the slave clock signal in Manchester encoding to generate a third encoding unit of a third bit number, and construct a response sequence based on the zero bit of the second time length and the first encoding unit of the second bit number, the second encoding unit of the second bit number, and the third encoding unit of the third bit number; the reset sequence detection module is connected to the slave serial communication protocol transceiver, and is configured to receive the reset sequence and determine the validity of the reset sequence and reset the debugging function of the serial line debugging port slave circuit when the reset sequence is valid.

[0018] In some embodiments, the debugger includes: a host serial communication protocol transceiver, connected to a controller area network bus, configured to send a detection sequence to the controller area network bus so that the chip activates a serial wire debugging protocol function based on the detection sequence; a serial wire debugging port host circuit, connected to a slave serial communication protocol transceiver, configured to generate a detection sequence, and receive a response sequence transmitted by the controller area network bus, determine that a slave clock cycle corresponding to a slave clock signal matches a host clock cycle, and generate a reset sequence, and send a reset sequence to the controller area network bus so that the chip resets the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence, wherein the response sequence is generated based on the detection sequence after the serial wire debugging protocol function is activated by the chip, and the response sequence includes the slave clock signal.

[0019] In some embodiments, the serial line debug port host circuit includes: an activation sequence generation module, configured to generate a detection sequence; a host decoding module, connected to the host serial communication protocol transceiver, configured to receive a response sequence transmitted by a controller local area network bus, and determine whether the slave clock cycle corresponding to the slave clock signal matches the host clock cycle; a reset sequence generation module, configured to generate a reset sequence when it is determined that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

[0020] In some embodiments, the debugger also includes a serial wire debugging host circuit, and the serial wire debugging port host circuit includes: a host encoding module, connected to the serial wire debugging host circuit, configured to encode the serial wire debugging clock and serial wire debugging data in Manchester encoding based on the serial wire debugging protocol to obtain debugging data, and send the debugging data to the controller local area network bus; wherein the serial wire debugging host circuit is configured to generate a serial wire debugging clock and serial wire debugging data, and send them to the host encoding module.

[0021] In some embodiments, the chip debugging device includes a processor and a memory storing program instructions, and the processor is configured to execute the aforementioned chip debugging method based on the controller area network bus when executing the program instructions.

[0022] The chip debugging method based on the controller area network bus, the chip, the debugger, and the device provided in the embodiments of the present disclosure can achieve the following technical effects:

[0023] In the disclosed embodiment, the chip is connected to the debugger via the controller area network bus. Under this hardware configuration, the chip receives the detection sequence generated by the debugger and transmitted by the controller area network bus, and activates the serial wire debugging protocol function of the chip based on the detection sequence. After the serial wire debugging protocol function is activated, the chip generates a response sequence based on the detection sequence and sends it to the debugger via the controller area network bus so that the debugger learns its slave clock signal and then generates a reset sequence based on the matching of the slave clock cycle and the host clock cycle. After the chip sends the response sequence, the chip receives the reset sequence transmitted by the controller area network bus, and activates the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence so that the chip is in a debugging preparation state. The chip provided in the disclosed embodiment utilizes the interface characteristics of the controller area network bus, and its serial wire debugging protocol function is activated and the debugging function based on the serial wire debugging protocol is reset through interaction with the debugger, so that the automotive chip is debugged without unpacking, reducing the difficulty of debugging the automotive chip.

[0024] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0026] Figure 1 Schematic diagram of the system framework of a chip debugging system based on a controller area network bus provided by an embodiment of the present disclosure;

[0027] Figure 2 is a hardware schematic diagram of a chip provided by an embodiment of the present disclosure;

[0028] Figure 3 is a hardware schematic diagram of a debugger provided by an embodiment of the present disclosure;

[0029] Figure 4 is a schematic diagram of a chip debugging method based on a controller area network bus provided by an embodiment of the present disclosure;

[0030] Figure 5 is a schematic diagram of another chip debugging method based on a controller area network bus provided by an embodiment of the present disclosure;

[0031] Figure 6 is a schematic diagram of another chip debugging method based on a controller area network bus provided by an embodiment of the present disclosure;

[0032] Figure 7 is a schematic diagram of another chip debugging method based on a controller area network bus provided by an embodiment of the present disclosure;

[0033] Figure 8 is a schematic diagram of another chip debugging method based on a controller area network bus provided by an embodiment of the present disclosure;

[0034] Fig. 9 is an application schematic diagram of an embodiment of the present disclosure;

[0035] FIG10( a ) is a schematic diagram of Manchester encoding provided by an embodiment of the present disclosure;

[0036] FIG10( b ) is a schematic diagram of SWD_CLK and SWD_DATA encoding provided by an embodiment of the present disclosure;

[0037] Fig.11 It is a schematic diagram of a chip debugging device based on a controller area network bus provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0039] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0040] Unless otherwise stated, the term "plurality" means two or more.

[0041] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0042] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0043] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0044] Figure 1 FIG. 1 is a schematic diagram of the system framework of a chip debugging system based on a controller area network bus according to an embodiment of the present disclosure. Figure 1 As shown, the chip debugging system includes a chip 10 and a debugger 20. The chip 10 is connected to the debugger 20 via a controller area network bus 30.

[0045] Combination Figure 1 and Figure 2 As shown, the chip 10 provided by the embodiment of the present disclosure includes a slave serial communication protocol transceiver 101 and a serial wire debug port slave circuit 102. Among them, SWDP (Serial Wire Debug Port) Target represents the serial wire debug port slave circuit 102.

[0046] The slave serial communication protocol transceiver 101 is connected to the CAN bus 30 and is configured to receive a detection sequence transmitted by the CAN bus 30 .

[0047] The serial wire debug port slave circuit 102 is connected to the slave serial communication protocol transceiver 101 and is configured to: activate the serial wire debug protocol function of the chip based on the detection sequence; after activating the serial wire debug protocol function of the chip, generate a response sequence based on the detection sequence and send the response sequence to the slave serial communication protocol transceiver; receive a reset sequence transmitted by the controller local area network bus 30, and reset the chip's debugging function based on the serial wire debug protocol based on the reset sequence. The response sequence includes a slave clock signal, and the reset sequence is generated after the debugger 10 receives the response sequence and determines that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

[0048] The chip provided by the embodiment of the present disclosure utilizes the interface characteristics of the controller local area network bus. Through interaction with the debugger, its serial wire debugging protocol function is activated and the debugging function based on the serial wire debugging protocol is reset. The automotive chip can be debugged without unpacking the box, thereby reducing the difficulty of debugging the automotive chip.

[0049] Combination Figure 1 and Figure 2 As shown, the chip further includes a serial wire debug slave circuit 103. The serial wire debug port slave circuit 102 includes an activation sequence detection module 1021, a slave decoding module 1022, a clock control module 1023, a slave encoding module 1024, and a reset sequence detection module 1025. Among them, SWD Target represents the serial wire debug slave circuit 103.

[0050] The activation sequence detection module 1021 is connected to the slave serial communication protocol transceiver 101 and is configured to receive a detection sequence and drive the serial line debug port slave circuit when the validity of the detection sequence is valid.

[0051] The slave decoding module 1022 is connected to the serial line debugging slave circuit 103, and is configured to decode the detection sequence in Manchester decoding mode to obtain the host clock cycle and Manchester data, and send the Manchester data to the serial line debugging slave circuit 103 so that the serial line debugging slave circuit 103 parses the Manchester data to obtain the data phase.

[0052] The clock control module 1023 is connected to the serial communication protocol transceiver 101 and the serial wire debug slave circuit 103 respectively, and is configured to generate a slave clock reference signal, and perform phase compensation processing on the slave clock reference signal according to the host clock cycle and the data phase sent by the serial wire debug slave circuit 103 to obtain the slave clock signal. The slave clock reference signal represents the clock signal of the next cycle of the serial wire debug port slave circuit 102.

[0053] The slave encoding module 1024 is connected to the controller LAN bus 30 and the serial line debugging slave circuit 103 respectively, and is configured to encode the slave clock signal in Manchester encoding, generate a third encoding unit of a third bit number, and construct a response sequence based on the zero bit of the second time length and the first encoding unit of the second bit number, the second encoding unit of the second bit number, and the third encoding unit of the third bit number.

[0054] The reset sequence detection module 1025 is connected to the slave serial communication protocol transceiver 101 and is configured to receive a reset sequence and determine the validity of the reset sequence and reset the debugging function of the serial line debug port slave circuit when the reset sequence is valid.

[0055] Combination Figure 1 and Figure 3 As shown, the debugger 20 provided by the embodiment of the present disclosure includes a host serial communication protocol transceiver 201 and a serial wire debug port host circuit 202. Among them, SWDP Host represents the serial wire debug port host circuit 202.

[0056] The host serial communication protocol transceiver 201 is connected to the controller area network bus and is configured to send a detection sequence to the controller area network bus so that the chip activates the serial wire debugging protocol function based on the detection sequence.

[0057] The serial wire debug port host circuit 202 is connected to the slave serial communication protocol transceiver 201, and is configured to generate a detection sequence and receive a response sequence transmitted by the controller local area network bus, generate a reset sequence when determining that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle, and send a reset sequence to the controller local area network bus to reset the chip based on the reset sequence and the debugging function of the chip based on the serial wire debug protocol, wherein the response sequence is generated based on the detection sequence after the serial wire debug protocol function is activated by the chip, and the response sequence includes the slave clock signal.

[0058] The debugger provided in the embodiment of the present disclosure utilizes the interface characteristics of the controller area network bus to debug the automotive chip without unpacking the chip through interaction with the chip, thereby reducing the difficulty of debugging the automotive chip.

[0059] Optionally, the serial line debug port host circuit 202 includes an activation sequence generation module 2021 , a host decoding module 2022 , and a reset sequence generation module 2023 .

[0060] The activation sequence generation module 2021 is configured to generate a detection sequence.

[0061] The host decoding module 2022 is connected to the host serial communication protocol transceiver 201 and is configured to receive a response sequence transmitted by the CAN bus and determine whether the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

[0062] The reset sequence generation module 2023 is configured to generate a reset sequence when it is determined that the slave clock cycle corresponding to the slave clock signal matches the master clock cycle.

[0063] Optionally, combined Figure 3 As shown, the debugger 20 further includes a serial wire debugging host circuit 203. Wherein, SWD Host represents the serial wire debugging host circuit 203.

[0064] The Serial Wire Debug Port host circuit 202 includes a host encoding module 2024 .

[0065] The host encoding module 2024 is connected to the Serial Wire Debug host circuit 203, and is configured to encode the Serial Wire Debug clock and the Serial Wire Debug data in Manchester encoding based on the Serial Wire Debug protocol to obtain debugging data, and send the debugging data to the Controller Area Network bus.

[0066] The Serial Wire Debug host circuit 203 is configured to generate a Serial Wire Debug clock and a Serial Wire Debug data, and send the generated data to the host encoding module 204 .

[0067] The host decoding module 2022 is further configured to decode the data transmitted by the CAN bus in a Manchester decoding manner, obtain the Serial Wire Debug response data and send it to the host Serial Wire Debug host circuit 203 .

[0068] Based on the above chip debugging system based on the controller area network bus, combined with Figure 4 As shown, the embodiment of the present disclosure provides a chip debugging method based on a controller area network bus, comprising:

[0069] S01, the chip receives a detection sequence generated by a debugger and transmitted through a controller area network bus, and activates a serial wire debugging protocol function of the chip based on the detection sequence.

[0070] S02, after activating the serial line debugging protocol function of the chip, the chip generates a response sequence based on the detection sequence, wherein the response sequence includes a slave clock signal.

[0071] S03, the chip sends a response sequence to the controller area network bus.

[0072] S04, the chip receives a reset sequence transmitted by the controller local area network bus, and resets the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence. The reset sequence is generated after the debugger receives the response sequence and determines that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

[0073] The chip debugging method based on the controller area network bus provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, the chip is connected to the debugger through the controller area network bus. Under this hardware configuration, the chip receives the detection sequence generated by the debugger and transmitted by the controller area network bus, and activates the serial wire debugging protocol function of the chip based on the detection sequence. After the serial wire debugging protocol function is activated, the chip generates a response sequence based on the detection sequence and sends it to the debugger through the controller area network bus so that the debugger can learn its slave clock signal and then generate a reset sequence based on the matching of the slave clock cycle and the host clock cycle. After the chip sends the response sequence, the chip receives the reset sequence transmitted by the controller area network bus, and activates the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence so that the chip is in a debugging preparation state. The chip provided by the embodiment of the present disclosure utilizes the interface characteristics of the controller area network bus, and its serial wire debugging protocol function is activated and the debugging function based on the serial wire debugging protocol is reset through interaction with the debugger, so that the debugging of the automotive chip is performed in a non-unpacking manner, which reduces the difficulty of debugging the automotive chip.

[0074] Optionally, the chip activates a serial wire debug protocol function of the chip based on a detection sequence, including:

[0075] When the validity of the detection sequence is valid, the chip drives the serial wire debug port slave circuit to enable the serial wire debug port slave circuit to activate the serial wire debug protocol function.

[0076] The chip resets based on the reset sequence. The chip's debugging function based on the serial wire debug protocol includes:

[0077] In case the validity of the reset sequence is valid, the chip resets the serial wire debug port slave circuit to enable the serial wire debug port slave circuit to reset the debugging function based on the serial wire debug protocol.

[0078] In this way, the chip detects the validity of the detection sequence after receiving it. If the validity of the detection sequence is valid, it indicates that the detection sequence can be normally transmitted to the chip end through the controller LAN bus. At this time, the chip drives the serial line debug port slave circuit and enables the serial line debug port slave circuit to activate the serial line debug protocol function. The chip also detects the validity of the reset sequence after receiving it. If the validity of the reset sequence is valid, it indicates that the reset sequence can be normally transmitted to the chip end through the controller LAN bus. At this time, the chip resets the serial line debug port slave circuit and enables the serial debug port slave circuit to reset the debugging function based on the serial line debug protocol, so that the chip enters the debugging preparation state.

[0079] Optionally, the chip determines the validity of the detection sequence in the following manner:

[0080] When the detection sequence includes a zero bit of a first duration and first bit numbers of first coding units that are sequentially continuous, the chip obtains a first period difference between a period of each first coding unit and a period of a previous coding unit of each first coding unit.

[0081] When all first period differences meet the period deviation condition, the chip determines that the validity of the detection sequence is valid.

[0082] The first coding unit includes Manchester-01 or Manchester-10.

[0083] In this way, after determining that the detection sequence includes a first coding unit with a zero bit of a first duration and a first number of bits that are continuous in time sequence, the embodiment of the present disclosure obtains the first period difference between the period of each first coding unit and the period of the previous coding unit of each first coding unit. If all the first period differences meet the period deviation condition, the validity of the detection sequence is determined to be valid. The embodiment of the present disclosure can determine the validity of the detection sequence according to the sequence construction rule of the received detection sequence and the period difference of adjacent first codes, thereby ensuring the accuracy of the controller local area network bus data transmission detection.

[0084] It should be noted that all first period differences meet the period deviation condition, including: all first period differences corresponding to first coding units meet the period deviation condition. If there is a first period difference corresponding to a first coding unit that does not meet the period deviation condition, the chip determines that the validity of the detection sequence is invalid.

[0085] Optionally, the first period difference meets the period deviation condition, including: the absolute value of the first period difference is less than or equal to a period deviation threshold, wherein the period deviation threshold represents a period deviation threshold corresponding to a frequency deviation of 10%.

[0086] It can be understood that the first period difference does not meet the period deviation condition, including: the absolute value of the first period difference is greater than the period deviation threshold.

[0087] Optionally, the first duration is greater than or equal to 800 μs and less than or equal to 1000 μs. As an example, the first duration is 1000 μs. The first number of bits may be 2 n , n is an integer greater than or equal to 7 and less than or equal to 10. Preferably, n is 9.

[0088] Optionally, combined Figure 5 As shown, the chip generates a response sequence based on the detection sequence, including:

[0089] S11, the chip decodes the detection sequence in Manchester decoding mode, obtains the host clock cycle and Manchester data, and parses the Manchester data to obtain the data phase.

[0090] S12, the chip generates a slave clock reference signal, wherein the slave clock reference signal represents a clock signal of the next cycle of the slave circuit of the serial line debug port.

[0091] S13, the chip performs phase compensation processing on the slave clock reference signal according to the master clock cycle and the data phase to obtain the slave clock signal.

[0092] S14, the chip encodes the slave clock signal in Manchester encoding to generate a third encoding unit with a third number of bits.

[0093] S15, the chip constructs a response sequence based on the zero bit of the second duration and the first coding unit of the second bit number, the second coding unit of the second bit number, and the third coding unit of the third bit number.

[0094] The first coding unit is sequentially connected to the second coding unit and the third coding unit. The first coding unit is one of Manchester-01 and Manchester-10, and the second coding unit is the other of Manchester-10 and Manchester-01.

[0095] In this way, since the phase offset will occur when the decoding sequence is transmitted through the controller area network bus, in order to reduce or eliminate the phase offset, the embodiment of the present disclosure decodes the detection sequence in a Manchester decoding manner to obtain the host clock cycle and Manchester data of the debugger and parses the Manchester data to obtain the data phase, and then performs phase compensation on the slave clock reference signal according to the host clock cycle and data phase of the debugger to obtain the slave clock signal. On this basis, in order to enable the debugger end to know the slave clock signal of the chip end based on the response sequence, the embodiment of the present disclosure encodes the slave clock signal in a Manchester encoding manner to generate a third encoding unit of a third bit number and constructs a response sequence that can be transmitted through the controller area network bus based on the zero bit of the second time length and the first encoding unit of the second bit number, the second encoding unit of the second bit number, and the third encoding unit of the third bit number. At the same time, the embodiment of the present disclosure utilizes the characteristics of the controller area network bus to enable the chip to quickly identify the driver of the controller area network bus, thereby reducing the time required for the protocol communication direction conversion and improving the efficiency of automotive chip debugging.

[0096] It should be noted that the second duration is less than the first duration. Optionally, the second duration is greater than or equal to 400 μs and less than 800 μs. As an example, the second duration is 500 μs, the second number of bits is 10 bits, and the third number of bits is 12 bits. It is understandable that the second number of bits and the third number of bits can be preset according to the debugging requirements of the chip.

[0097] Combination Figure 6 As shown, the embodiment of the present disclosure also provides a chip debugging method based on a controller area network bus, comprising:

[0098] S21, the debugger generates a detection sequence.

[0099] S22, the debugger sends a detection sequence to the controller area network bus, so that the chip activates the serial line debugging protocol function based on the detection sequence.

[0100] S23, the debugger receives the response sequence transmitted by the controller area network bus, and generates a reset sequence when determining that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle. The response sequence is generated based on the detection sequence after the serial line debugging protocol function is activated on the chip, and the response sequence includes the slave clock signal.

[0101] S24, the debugger sends a reset sequence to the controller area network bus, so that the chip resets the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence.

[0102] The chip debugging method based on the controller area network bus provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, the debugger is connected to the chip through the controller area network bus. Under this hardware configuration, after the debugger generates a detection sequence, it sends the detection sequence to the controller area network bus so that the chip activates the serial wire debugging protocol function based on the received detection sequence. After that, the debugger receives the response sequence transmitted by the controller area network bus, and determines that the slave clock cycle corresponding to the slave clock signal included in the response sequence matches the host clock cycle to generate a reset sequence. Finally, the debugger sends a reset sequence to the controller area network bus so that the chip resets the debugging function based on the serial wire debugging protocol of the chip based on the received reset sequence. The debugger provided by the embodiment of the present disclosure utilizes the interface characteristics of the controller area network bus, transmits the detection sequence to the chip through the controller area network bus to activate the serial wire debugging protocol function of the chip, and then transmits the reset sequence to the chip through the controller area network bus to reset the debugging function based on the serial wire debugging protocol of the chip. The debugger provided by the embodiment of the present disclosure utilizes the interface characteristics of the controller area network bus, and debugs the automotive chip in a non-unboxing manner by interacting with the chip, thereby reducing the difficulty of debugging the automotive chip.

[0103] Optionally, the debugger generates a detection sequence, including: the debugger constructs a detection sequence based on a zero bit of a first duration and a first encoding unit of a first number of bits that are continuous in time sequence. And / or,

[0104] The debugger generates a reset sequence, including: the debugger constructs the reset sequence based on a zero bit of a first duration and a first coding unit of a second bit number that is continuous in time sequence.

[0105] The first coding unit includes Manchester-01 or Manchester-10, and the second number of bits is greater than the first number of bits.

[0106] In this way, the debugger provided by the embodiment of the present disclosure constructs a reset sequence based on a sequence construction rule in which the duration of the zero bit is the first duration and the first coding unit is continuous in time and has the second bit number, so that the chip resets the debugging function based on the serial line debugging protocol.

[0107] Optionally, the debugger determines whether the slave clock cycle corresponding to the slave clock signal matches the master clock cycle in the following manner:

[0108] The debugger calculates the second cycle difference between the slave clock cycle and the master clock cycle.

[0109] When the second cycle difference meets the cycle deviation condition, the debugger determines that the slave clock cycle matches the master clock cycle.

[0110] In the event that the second period difference does not meet the period deviation condition, the debugger determines that the slave clock period does not match the master clock period.

[0111] In this way, the embodiment of the present disclosure can determine whether the slave clock period corresponding to the slave clock signal matches the host clock period based on whether the second period difference meets the period deviation condition, thereby ensuring the accuracy and reliability of the master-slave clock signal judgment and avoiding false triggering of the chip's debugging function based on the serial line debugging protocol.

[0112] It should be noted that the specific steps for determining whether the second period difference meets the period deviation condition can refer to the steps for determining whether the first period difference meets the period deviation condition, and the embodiments of the present disclosure will not be repeated here.

[0113] Optionally, combined Figure 7 As shown, the debugger generates a reset sequence when it determines that the slave clock cycle corresponding to the slave clock signal matches the master clock cycle, including:

[0114] S31, when the slave clock cycle corresponding to the slave clock signal matches the host clock cycle, the debugger generates a success reply response sequence.

[0115] In this step, the debugger generates a success reply response sequence, including: the debugger constructs a success reply response sequence based on the zero bit of the second duration and the first coding unit of the second bit number, the second coding unit of the second bit number, and the fourth coding unit of the fourth bit number.

[0116] The first coding unit is sequentially connected to the second coding unit and the fourth coding unit. The first coding unit is one of Manchester-01 and Manchester-10, the second coding unit is the other of Manchester-10 and Manchester-01, and the fourth coding unit is one of Manchester-01 and Manchester-10.

[0117] Optionally, the fourth bit number may be 8 bits, or other values. It is understandable that the fourth bit number may be preset according to the debugging requirements of the chip.

[0118] It should be noted that the fourth encoding unit is the same as the first encoding unit. In this way, after receiving the successful reply response sequence, the chip can accurately distinguish the second encoding unit from the fourth encoding unit, thereby ensuring the accuracy of the successful reply sequence detection.

[0119] S32, the debugger sends a success reply response sequence to the controller area network bus to notify the chip that its response sequence is sent successfully.

[0120] S33, after sending a success reply response sequence to the CAN bus, the debugger generates a reset sequence.

[0121] In this way, the debugger provided by the embodiment of the present disclosure generates a successful reply response sequence when determining that the slave clock signal matches the host clock cycle, and transmits it to the chip end through the controller area network bus to notify it that the previous response sequence was sent successfully. Afterwards, the debugger generates a reset sequence for resetting the debugging function of the chip based on the serial line debugging protocol, thereby resetting the chip debugging function and performing subsequent chip debugging. At the same time, the embodiment of the present disclosure utilizes the characteristics of the controller area network bus to enable the chip to quickly identify the driver of the controller area network bus, thereby reducing the time required for the protocol communication direction conversion and improving the efficiency of automotive chip debugging.

[0122] Optionally, the debugger generates a reset sequence when determining that a slave clock cycle corresponding to the slave clock signal matches a master clock cycle, further comprising:

[0123] In the case where the slave clock cycle does not match the master clock cycle, the debugger generates a fail reply response sequence. The debugger sends a fail reply response sequence to the CAN bus to notify the chip that its response sequence transmission failed. The debugger regenerates the detection sequence and sends the detection sequence to the CAN bus.

[0124] In this way, the debugger provided by the embodiment of the present disclosure generates a failure reply response sequence when determining that the slave clock cycle does not match the host clock cycle and sends it to the chip end so that the chip can quickly know that its response sequence has failed to be sent, and regenerates a detection sequence and sends it to the chip end to reactivate the serial line debugging protocol function of the chip and reset the debugging function of the chip. In this way, the chip is controlled to quickly enter the debugging preparation state, improving the efficiency of automotive chip debugging.

[0125] Optionally, the debugger generates a failure reply response sequence, including:

[0126] The debugger constructs a response sequence based on the zero bit of the second duration, the second coding unit of the second bit number, the first coding unit of the second bit number, and the fifth coding unit of the fourth bit number.

[0127] The second coding unit is sequentially continuous with the first coding unit and the fifth coding unit, and the fifth coding unit is one of Manchester-01 and Manchester-10.

[0128] It should be noted that the fifth encoding unit is the same as the second encoding unit. In this way, the chip can accurately know whether its response sequence has occurred successfully based on the received successful reply response sequence or failed reply response sequence. At the same time, after receiving the failed reply response sequence, the chip can accurately distinguish the first encoding unit and the fifth encoding unit to ensure the accuracy of the failed response reply sequence detection.

[0129] Combination Figure 8 As shown, the embodiment of the present disclosure also provides a chip debugging method based on a controller area network bus, comprising:

[0130] S41, the debugger generates a detection sequence.

[0131] S42, the debugger sends a detection sequence to the controller area network bus, so that the chip activates the serial line debugging protocol function based on the detection sequence.

[0132] S43, the debugger receives a response sequence transmitted by the controller area network bus, and generates a reset sequence when determining that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle. The response sequence is generated based on the detection sequence after the serial line debugging protocol function is activated on the chip, and the response sequence includes the slave clock signal.

[0133] S44, the debugger sends a reset sequence to the controller area network bus, so that the chip resets the debugging function of the chip based on the serial wire debugging protocol based on the reset sequence.

[0134] S45, after the debugger sends a reset sequence to the controller area network bus, a serial line debugging clock and serial line debugging data are generated.

[0135] S46, the debugger encodes the serial line debugging clock and the serial line debugging data in Manchester encoding based on the serial line debugging protocol to obtain debugging data.

[0136] S47, the debugger sends the debugging data to the controller area network bus, so that the chip is debugged based on the debugging data.

[0137] The chip debugging method based on the controller area network bus provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, after the debugger generates a detection sequence, it sends the detection sequence to the controller area network bus so that the chip activates the serial line debugging protocol function based on the received detection sequence. After that, the debugger receives the response sequence transmitted by the controller area network bus and determines that the slave clock cycle corresponding to the slave clock signal included in the response sequence matches the host clock cycle to generate a reset sequence. Again, the debugger sends a reset sequence to the controller area network bus so that the chip resets the debugging function based on the serial line debugging protocol of the chip based on the received reset sequence. After the debugger resets the debugging function of the chip, the debugger generates a serial line debugging clock and serial line debugging data and encodes the serial line debugging clock and serial line debugging data in Manchester encoding based on the serial line debugging protocol to obtain debugging data. Finally, the debugger sends debugging data to the controller area network bus so that the chip performs chip debugging based on the debugging data. The debugger provided by the disclosed embodiment utilizes the interface characteristics of the controller area network bus, transmits a detection sequence to the chip through the controller area network bus to activate the serial line debugging protocol function of the chip, and then transmits a reset sequence to the chip through the controller area network bus to reset the chip's debugging function based on the serial line debugging protocol and obtains debugging data locally before sending it to the chip end through the controller area network bus to implement chip debugging. The disclosed embodiment debugs the automotive chip in a non-unboxing manner by interacting with the chip, reducing the difficulty of debugging the automotive chip.

[0138] In a practical application, a CAN (Controller Area Network) bus includes a CAN transmission bus and a CAN reception bus.

[0139] like Figure 2 As shown, the activation sequence detection module 1021 detects the CAN_RX port of the CAN receiving bus in the chip. When the detection sequence is received at the CAN_RX port and the validity of the detection sequence is valid, the CAN_ACTIVE signal is pulled high to activate the SWDP Target 102, thereby activating the SWD protocol function of the chip. At this time, the CAN_ACTIVE signal serves as a control signal of the CAN_TX port of the CAN transmitting bus in the chip. Among them, when the CAN_ACTIVE signal is pulled high, the SWDP Target 102 has the control function of the CAN transmitting bus.

[0140] The slave decoding module 1022 decodes the detection sequence in Manchester decoding mode, obtains the master clock signal SWD_CLK_OUT and Manchester data SWDI_Output, and sends them to the SWD Target 103 .

[0141] The SWD Target 103 parses the Manchester data SWDI_Output to obtain the data phase.

[0142] The reset sequence detection module 1025 detects the CAN_RX port of the CAN receiving bus, and when a reset sequence is received at the CAN_RX port and the validity of the reset sequence is valid, the RST_SWDP signal is pulled high to reset the SWDP Target 102, thereby resetting the SWD protocol-based debugging function of the chip.

[0143] The clock control module 1023 calculates and generates the slave clock reference signal SWD_CLK, performs phase compensation processing on the slave clock reference signal SWD_CLK according to the host clock cycle and the data phase obtained by SWDTarget103, and obtains the slave clock signal SWD_CLK. Among them, IRC_CLK is used to calculate the slave clock reference signal SWD_CLK, and IRC_CLK is a 50MHz clock.

[0144] like Figure 3 As shown, the activation sequence generation module is used to generate a detection sequence and a response sequence, and the reset sequence generation module is used to generate a reset sequence.

[0145] The SWDP Host sends a detection sequence to the chip end on the CAN bus. After activating the chip's SWD protocol function, when the SWDP Host receives the response sequence through the CAN bus and determines that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle, the reset sequence generation module generates a reset sequence and pulls up SWDO_EN, and sends a reset sequence to the CAN bus.

[0146] After pulling SWDO_EN high, the host encoding module encodes the serial wire debugging clock SWD_CLK_O and serial wire debugging data SWD_DATA_O sent by the SWD Host in Manchester encoding to obtain debugging data and sends the debugging data to the CAN sending bus in the debugger.

[0147] It should be noted that after resetting the SWDP Target, if you need to activate the SWDP Target again to activate the SWD protocol function of the chip, the debugger needs to send the detection sequence to the chip again. In addition, when the CAN_ACTIVE signal remains at a low level, the CAN device has the control function of the CAN bus. When the CAN_ACTIVE signal remains at a low level, the SWD_CLK and SWD_DATA of the SWD port are transmitted to the SWDP Target. Here, it can be ensured that the SWD protocol originally transmitted through the SWD port is not affected.

[0148] On the debugger side, when the debugger determines that the slave clock cycle corresponding to the slave clock signal does not match the host clock cycle, SWDO_EN is kept at a low level. At this time, the host decoding module decodes the data received by the CAN_RX port of the CAN receive bus according to the Manchester decoding method to obtain SWD_DATA_I and sends it to SWD_Host.

[0149] In another practical application, Fig. 9 A sequence diagram showing a detection sequence, a response sequence, a successful reply response sequence, and a reset sequence.

[0150] The SWDP Host sends a detection sequence, which is a 1000us low level and a 512-bit Manchester-10 signal that is continuous in time. After sending the 1000us low level, the SWDP Host will continue to send the Manchester-10 signal until it detects a continuous low level of 500 to 600us.

[0151] When SWDP Target detects a low level of 800 to 1000us, it detects the period of each Manchester-10 in the Manchester-10 signal. When the period difference between the Manchester-10 of the current period and the Manchester-10 of the previous period is within the period deviation threshold corresponding to the frequency deviation of 10%, it is determined that the Manchester-10 of the current period is valid. After determining that 512 valid Manchester-10s have been received, SWDP Target sends a response sequence, which is a low level of 500us, 10-bit Manchester-10, 10-bit Manchester-01 and 12-bit Manchester-10 / Manchester-01. The 12-bit Manchester-10 / Manchester-01 is used to represent the slave clock signal SWD_CLK determined by the phase compensation of the clock control module. If the Manchester-10 signal contains a signal whose period difference between a Manchester-10 of a certain period and the Manchester-10 of the previous period is outside the period deviation threshold corresponding to the frequency deviation of 10%, the SWDP Target determines that the communication does not match, does not send a response sequence, and needs to receive the detection sequence again.

[0152] When the SWDP Host receives the response sequence, it compares the slave clock cycle corresponding to the slave clock signal SWD_CLK in the response sequence with the host clock cycle SWD_CLK corresponding to the host clock signal sent by the SWD Host. If the period difference between the slave clock cycle and the host clock cycle meets the period deviation condition, a successful reply response sequence is sent; if the period difference between the slave clock cycle and the host clock cycle does not meet the period deviation condition, a failed reply response sequence is sent. Among them, the successful reply response sequence is a low level of 500us, 10 bits Manchester-10, 10 bits Manchester-01, and 8 Manchester-10s; the failed reply response sequence is a low level of 600us and 20 bits Manchester-10.

[0153] After sending the successful reply response sequence, the SWDP Host will continue to send the reset sequence. The reset sequence is a 1000us low level, 2048-bit Manchester-10 / Manchester-10 to reset the SWDP Target and notify the SWDP Target to start decoding the debug data received by the CAN bus or encoding SWD_CLK / SWD_DATA according to SWDO_EN.

[0154] In another practical application, as shown in FIG10(a), SWD_CLK and SWD_DATA are Manchester encoded to generate debug data. As shown in FIG10(b), in a single SWD_CLK cycle, SWD-1 in SWD_DATA is Manchester encoded to generate Manchester-01, and SWD-0 in SWD_DATA is Manchester encoded to generate Manchester-10.

[0155] Combination Fig.11 As shown, the embodiment of the present disclosure provides a chip debugging device 70 based on a controller area network bus, including a processor (processor) 700 and a memory (memory) 701. Optionally, the device 70 may also include a communication interface (Communication Interface) 702 and a bus 703. Among them, the processor 700, the communication interface 702, and the memory 701 can communicate with each other through the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call the logic instructions in the memory 701 to execute the chip debugging method based on the controller area network bus of the above embodiment.

[0156] In addition, the logic instructions in the memory 701 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0157] The memory 701 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 700 executes the functional application and data processing by running the program instructions / modules stored in the memory 701, that is, the chip debugging method based on the controller area network bus in the above embodiment is implemented.

[0158] The memory 701 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory and may also include a non-volatile memory.

[0159] The embodiment of the present disclosure provides a chip debugging system based on a controller area network bus, comprising the above-mentioned chip and the above-mentioned debugger. The debugger is connected to the chip via the controller area network bus.

[0160] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0161] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0162] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A chip debugging method based on a controller area network bus, characterized in that: Applied to the chip, the chip is connected to the debugger through the controller local area network bus, and the chip debugging method includes: receiving a detection sequence generated by a debugger and transmitted through a controller area network bus, and activating a serial wire debugging protocol function of the chip based on the detection sequence; After activating the serial line debugging protocol function of the chip, generating a response sequence based on the detection sequence; wherein the response sequence includes a slave clock signal; Sending a response sequence to the CAN bus; A reset sequence transmitted by a controller area network bus is received, and a debugging function based on a serial wire debugging protocol of the chip is reset based on the reset sequence; wherein the reset sequence is generated after the debugger receives a response sequence and determines that a slave clock cycle corresponding to a slave clock signal matches a host clock cycle.

2. The chip debugging method according to claim 1, characterized in that: The chip includes a serial line debug port slave circuit, and the serial line debug port slave circuit is connected to the controller area network bus; Activates the chip's Serial Wire Debug protocol functions based on the detection sequence, including: When the validity of the detection sequence is valid, driving the serial line debug port slave circuit to enable the serial line debug port slave circuit to activate the serial line debug protocol function; Debug capabilities based on the Serial Wire Debug protocol that resets the chip based on a reset sequence, including: In case the validity of the reset sequence is valid, the serial wire debug port slave circuit is reset to enable the serial wire debug port slave circuit to reset the debugging function based on the serial wire debug protocol.

3. The chip debugging method according to claim 2, characterized in that: The validity of the test sequence is determined as follows: In the case where the detection sequence includes a zero bit of a first duration and first coding units of a first number of bits that are sequentially continuous, obtaining a first period difference between a period of each first coding unit and a period of a previous coding unit of each first coding unit; When all first period differences meet the period deviation condition, determining the validity of the detection sequence is valid; The first coding unit includes Manchester-01 or Manchester-10.

4. The chip debugging method according to claim 1, characterized in that: Generate a response sequence based on the detection sequence, including: Decode the detection sequence in Manchester decoding mode to obtain the host clock cycle and Manchester data, and parse the Manchester data to obtain the data phase; Generate slave clock reference signal; According to the master clock cycle and data phase, the slave clock reference signal is subjected to phase compensation processing to obtain the slave clock signal; encoding the slave clock signal in a Manchester encoding manner to generate a third encoding unit having a third number of bits; Constructing a response sequence based on the zero bit of the second duration and the first coding unit of the second bit number, the second coding unit of the second bit number, and the third coding unit of the third bit number; The first coding unit is sequentially connected to the second coding unit and the third coding unit. The first coding unit is one of Manchester-01 and Manchester-10, and the second coding unit is the other of Manchester-10 and Manchester-01.

5. A chip debugging method based on a controller area network bus, characterized in that: Applied to debugger, chip debugging methods include: Generate a detection sequence; sending a detection sequence to the controller area network bus so that the chip activates a serial line debugging protocol function based on the detection sequence; Receiving a response sequence transmitted by a controller area network bus, and determining that a slave clock cycle corresponding to a slave clock signal matches a master clock cycle to generate a reset sequence; wherein the response sequence is generated based on a detection sequence after a serial line debugging protocol function is activated on the chip, and the response sequence includes a slave clock signal; A reset sequence is sent to the controller area network bus so that the chip resets a serial wire debugging protocol-based debugging function of the chip based on the reset sequence.

6. The chip debugging method according to claim 5, characterized in that: Generating a detection sequence includes: constructing a detection sequence based on a zero bit of a first duration and a first coding unit of a first number of bits that are continuous in time sequence; and / or, Generating a reset sequence includes: constructing a reset sequence based on a zero bit of a first duration and a first coding unit of a second number of bits that are continuous in time sequence; The first coding unit includes Manchester-01 or Manchester-10, and the second number of bits is greater than the first number of bits.

7. The chip debugging method according to claim 5, characterized in that: Determine whether the slave clock period corresponding to the slave clock signal matches the master clock period in the following manner: Calculate the second cycle difference between the slave clock cycle and the master clock cycle; When the second cycle difference meets the cycle deviation condition, determining that the slave clock cycle matches the master clock cycle; or, When the second cycle difference does not meet the cycle deviation condition, it is determined that the slave clock cycle does not match the master clock cycle.

8. The chip debugging method according to claim 5, characterized in that: A reset sequence is generated when it is determined that the slave clock period corresponding to the slave clock signal matches the master clock period, including: generating a success reply response sequence when the slave clock cycle corresponding to the slave clock signal matches the master clock cycle; Send a successful reply response sequence to the CAN bus to notify the chip that its response sequence is successfully sent; A reset sequence is generated after a successful reply response sequence is sent to the CAN bus.

9. The chip debugging method according to claim 5, characterized in that: Also includes: Generates Serial Wire Debug clock and Serial Wire Debug data after sending a reset sequence to the Controller Area Network bus; Encode the serial line debugging clock and the serial line debugging data in Manchester encoding based on the serial line debugging protocol to obtain debugging data; The debugging data is sent to the controller area network bus so that the chip can be debugged based on the debugging data.

10. A chip, characterized in that: include: A slave serial communication protocol transceiver connected to the controller area network bus and configured to receive a detection sequence transmitted by the controller area network bus; The serial wire debug port slave circuit, connected to the slave serial communication protocol transceiver, is configured as follows: Activating the serial wire debug protocol function of the chip based on the detection sequence; After activating the serial wire debug protocol function of the chip, a response sequence is generated based on the detection sequence, and the response sequence is sent to the slave serial communication protocol transceiver; A reset sequence transmitted by a controller local area network bus is received, and a debugging function based on a serial wire debugging protocol of the reset chip is reset based on the reset sequence; wherein the response sequence includes a slave clock signal, and the reset sequence is generated after the debugger receives the response sequence and determines that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle.

11. The chip according to claim 10, characterized in that: The chip also includes a serial wire debug slave circuit, and the serial wire debug port slave circuit includes: an activation sequence detection module connected to the slave serial communication protocol transceiver and configured to receive a detection sequence and drive a serial line debug port slave circuit if the validity of the detection sequence is valid; A slave decoding module is connected to the serial line debugging slave circuit and is configured to decode the detection sequence in a Manchester decoding manner to obtain a host clock cycle and Manchester data, and send the Manchester data to the serial line debugging slave circuit so that the serial line debugging slave circuit parses the Manchester data to obtain a data phase; A clock control module is connected to the serial communication protocol transceiver and the serial line debugging slave circuit respectively, and is configured to generate a slave clock reference signal, and perform phase compensation processing on the slave clock reference signal according to the host clock cycle and the data phase sent by the serial line debugging slave circuit to obtain a slave clock signal; A slave encoding module is connected to the controller area network bus and the serial line debugging slave circuit respectively, and is configured to encode the slave clock signal in a Manchester encoding manner, generate a third encoding unit of a third bit number, and construct a response sequence based on a zero bit of the second duration and the first encoding unit of the second bit number, the second encoding unit of the second bit number, and the third encoding unit of the third bit number; The reset sequence detection module is connected to the slave serial communication protocol transceiver and is configured to receive a reset sequence and determine the validity of the reset sequence and reset the debugging function of the serial line debugging port slave circuit when the reset sequence is valid.

12. A debugger, characterized in that: include: A host serial communication protocol transceiver is connected to the controller area network bus and is configured to send a detection sequence to the controller area network bus so that the chip activates a serial wire debugging protocol function based on the detection sequence; The serial wire debug port host circuit is connected to the slave serial communication protocol transceiver, and is configured to generate a detection sequence and receive a response sequence transmitted by the controller local area network bus, generate a reset sequence when determining that the slave clock cycle corresponding to the slave clock signal matches the host clock cycle, and send a reset sequence to the controller local area network bus to reset the chip based on the reset sequence and the chip's debugging function based on the serial wire debug protocol, wherein the response sequence is generated based on the detection sequence after the serial wire debug protocol function is activated by the chip, and the response sequence includes the slave clock signal.

13. The debugger according to claim 12, characterized in that: The Serial Wire Debug Port host circuitry includes: An activation sequence generation module is configured to generate a detection sequence; A host decoding module is connected to the host serial communication protocol transceiver and is configured to receive a response sequence transmitted by the controller area network bus and determine whether a slave clock cycle corresponding to the slave clock signal matches a host clock cycle; The reset sequence generation module is configured to generate a reset sequence when it is determined that a slave clock cycle corresponding to a slave clock signal matches a master clock cycle.

14. The debugger according to claim 12, wherein: The debugger also includes a serial wire debug host circuit. The serial wire debug port host circuit includes: A host encoding module is connected to the serial wire debugging host circuit and is configured to encode the serial wire debugging clock and the serial wire debugging data in a Manchester encoding manner based on the serial wire debugging protocol to obtain debugging data, and send the debugging data to the controller area network bus; The serial wire debugging host circuit is configured to generate a serial wire debugging clock and serial wire debugging data, and send the data to the host encoding module.

15. A chip debugging device based on a controller area network bus, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the chip debugging method based on the controller area network bus according to any one of claims 1 to 9 when executing the program instructions.

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