Memory management method, computing device, management device and memory management system

Abstract

The invention provides a memory management method, a computing device, a management device and a memory management system, and belongs to the field of computing devices. According to the embodiment of the invention, the LMD or the FM performs zero clearing on the first CXL memory space before the time point when the application applies for allocating the first CXL memory space, and the LMD allocates the zero-cleared first CXL memory space to the application, so that after the application applies for the first CXL memory space, the application can use the zero-cleared first CXL memory space, and the application can use the zero-cleared first CXL memory space. Therefore, the application does not need to perform zero clearing action on the first CXL memory space, so that the time overhead caused by zero clearing of the first CXL memory space is reduced.

Description

Technical Field

[0001] The present application relates to the field of memory management, and in particular to a memory management method, a computing device, a management device, and a memory management system. Background Art

[0002] Currently, the operating system kernel is responsible for managing memory. When an application needs to use a memory segment, the application sends a memory allocation request to the operating system kernel; the operating system kernel responds to the memory allocation request, allocates a memory segment for the application, and sends the address of the allocated memory segment to the application; then, the application calls the memset function to clear the obtained memory segment. Then, the application uses the cleared memory segment, and after using the memory segment, returns the memory segment to the operating system kernel.

[0003] When the above method is adopted, since the application needs to clear the memory segment, it will take too much time. Summary of the invention

[0004] The embodiments of the present application provide a memory management method, a computing device, a management device, and a memory management system, which can save the time overhead caused by clearing memory segments by applications.

[0005] In a first aspect, a memory management method is provided, which is applied to a computing device, wherein the computing device includes an LMD and a first application, and the method includes: the LMD clears a first CXL memory space to obtain the cleared first CXL memory space, where the first CXL memory space is a CXL memory space in a CXL memory pool allocated to the computing device; the first application sends a first memory allocation request to the LMD, where the first memory allocation request indicates that the CXL memory space in the CXL memory pool is allocated to the first application; in response to the first memory allocation request, the LMD allocates the cleared first CXL memory space to the first application, and sends a first memory allocation response to the first application, where the first memory allocation response includes an identifier of the cleared first CXL memory space.

[0006] Based on the method of the first aspect, since the LMD clears the first CXL memory space before the application applies for allocation of the first CXL memory space, the LMD allocates the cleared first CXL memory space to the application, so that after the application applies for the first CXL memory space, the application can use the cleared first CXL memory space. Therefore, the application does not need to perform the action of clearing the first CXL memory space, thereby reducing the time overhead caused by clearing the first CXL memory space.

[0007] In some implementations, the LMD clears the first CXL memory space, including: the LMD adds an identifier of the first CXL memory space to the first queue; the LMD obtains the identifier of the first CXL memory space from the first queue; and the LMD clears the first CXL memory space based on the identifier of the first CXL memory space.

[0008] Taking into account that it takes a long time to clear the CXL memory space, which may usually take seconds, LMD adds the identifier of the CXL memory space that needs to be cleared to the queue, thereby saving the identifier of the CXL memory space to be cleared through the queue, so that LMD can execute other tasks (such as returning a response to the application) after adding the identifier of the CXL memory space to the queue, without having to wait for the clearing to be completed before executing other tasks, thereby reducing the risk of blocking LMD's main task (the main task is, for example, LMD interacting with the application to process memory allocation requests and memory release requests sent by the application) due to clearing the CXL memory space, realizing asynchronous processing of clearing, and reducing the overall latency of the computing device in executing tasks.

[0009] In some embodiments, the computing device further includes a second application, and before the LMD obtains the identifier of the first CXL memory space from the first queue, the method further includes: the second application sends a first memory release request to the LMD, the first memory release request includes the identifier of the first CXL memory space; the LMD sends a first memory release response to the second application, the first memory release response indicates that the first CXL memory space is released successfully.

[0010] Since there is no need to wait for the completion of the clearing of the first CXL memory space before returning a response to the second application, the response can be returned directly to the second application after receiving the memory release request from the second application. Therefore, the response is returned faster and the memory release process is simpler, further saving the time overhead caused by the memory release request process for the application and reducing the risk of the second application being blocked from processing business due to waiting for a response message to the first memory release request.

[0011] In some embodiments, the LMD obtains the identifier of the first CXL memory space from the first queue, including: the LMD detects whether the first queue is empty every first time period; in response to detecting that the first queue is not empty, the LMD obtains the identifier of the first CXL memory space from the first queue.

[0012] Since LMD adopts the method of periodically clearing the CXL memory space saved in the queue, it can clear the CXL memory space as timely as possible without having to determine in real time whether there is CXL memory space to be cleared, thereby helping to reduce the CPU occupancy caused by real-time determination whether there is CXL memory space to be cleared.

[0013] In some embodiments, the LMD allocates the cleared first CXL memory space to the first application, including: the LMD queries the state of the first CXL memory space based on the identifier of the first CXL space; in response to the first CXL memory space being in a usable state, the LMD allocates the cleared first CXL memory space to the first application.

[0014] Since the CXL memory space is allocated to the first application after confirming that the CXL memory space is in a usable state and has been cleared, the risk of errors caused by different applications reading and writing data to the same CXL memory space due to allocating CXL memory space allocated to other applications other than the first application to the first application is reduced.

[0015] In some embodiments, before the LMD allocates the cleared first CXL memory space to the first application, the method further includes: the LMD adding an identifier of the first CXL memory space to the second queue; the LMD obtaining the identifier of the first CXL memory space from the second queue; and the LMD updating the state of the first CXL memory space to an available state.

[0016] Since the identifier of the CXL memory space to be updated is saved in the queue, LMD can execute other tasks after adding the identifier of the CXL memory space to be updated to the queue, without having to wait for the status update to be completed before executing other tasks. This reduces the risk of blocking LMD's main task (the main task is, for example, LMD interacting with the application to process memory allocation requests and memory release requests sent by the application) due to updating the status of the CXL memory space, realizes asynchronous processing of status updates, and reduces the overall latency of the computing device in executing tasks.

[0017] In some embodiments, the LMD obtains the identifier of the first CXL memory space from the second queue, including: the LMD detects whether the second queue is empty every second time period; in response to detecting that the second queue is not empty, the LMD obtains the identifier of the first CXL memory space from the second queue.

[0018] Since LMD adopts a method of regularly updating the status of the CXL memory space based on a queue, it can update the status of the CXL memory space as timely as possible without having to determine in real time whether there is CXL memory space to be updated, thereby helping to reduce the CPU usage caused by real-time determination whether there is CXL memory space to be updated.

[0019] In some embodiments, before the LMD updates the state of the first CXL memory space to a usable state, the method further includes: the LMD locking the state of the first CXL memory space; after the LMD updates the state of the first CXL memory space to a usable state, the method further includes: the LMD unlocking the state of the first CXL memory space.

[0020] By locking the state of the CXL memory space, it is possible to prevent multiple threads from modifying or accessing the same state at the same time, which would cause the risk of inconsistent or disordered states obtained by different threads.

[0021] In some embodiments, before the LMD clears the first CXL memory space, the method further includes: the LMD sends a second memory allocation request to the fabric management FM of the management device, the second memory allocation request indicates that the CXL memory space in the CXL memory pool is allocated to the computing device; the LMD receives a second memory allocation response from the FM, the second memory allocation response includes an identifier of the second CXL memory space in the CXL memory pool; the LMD determines the first CXL memory space from the second CXL memory space, allocates the first CXL memory space to the first application, and sends the identifier of the first CXL memory space to the first application.

[0022] Since LMD and applications allocate CXL memory space in the CXL memory pool to applications through message interaction, CXL memory space is provided to applications without going through the memory management process of the operating system. This saves the complex software stack calls caused by the operating system's memory management, and the process is relatively simple.

[0023] In some embodiments, the method further includes: in response to the first CXL memory space satisfying the return condition, the LMD sending a second memory release request to the FM, the second memory release request indicating that the first CXL memory space is returned to the CXL memory pool; the LMD deleting the identifier of the first CXL memory space from the identifiers of the CXL memory spaces managed by the LMD.

[0024] By recycling the CXL memory space that has been allocated to the computing device back to the CXL memory pool, the probability that the CXL memory space that has been allocated to the computing device is idle for a long time and other computing devices cannot obtain the CXL memory space is reduced, which facilitates multiple computing devices in a computing device cluster to share the CXL memory pool and improves the utilization rate of the CXL memory space in the CXL memory pool.

[0025] In a second aspect, a memory management method is provided, which is applied to a memory management system. The memory management system includes a management device, a computing device and a CXL memory pool. The management device includes a structure management FM. The computing device includes a local high-speed computing interconnect CXL space management process LMD and an application. The method includes: LMD sends a second memory allocation request to FM, and the second memory allocation request indicates that CXL memory space in the CXL memory pool is allocated to the computing device; FM determines a second CXL memory space from the CXL memory pool in response to the second memory allocation request, allocates the second CXL memory space to the computing device, and sends an identifier of the second CXL memory space to LMD; LMD clears a first CXL memory space in the second CXL memory space to obtain a cleared first CXL memory space; the application sends a first memory allocation request to LMD, and the first memory allocation request indicates that CXL memory space in the CXL memory pool is allocated to the application; in response to the first memory allocation request, LMD allocates the cleared first CXL memory space to the application, and sends an identifier of the cleared first CXL memory space to the application.

[0026] In a third aspect, a memory management method is provided, which is applied to a management device, the management device includes a structure management FM, the management device is connected to a computing device and a CXL memory pool respectively, the computing device includes a local high-speed computing interconnect CXL space management process LMD, and the method includes:

[0027] The FM receives an identifier of a first CXL memory space from the LMD, the first CXL memory space being a CXL memory space in the CXL memory pool allocated to the computing device;

[0028] FM clears the first CXL memory space to obtain the cleared first CXL memory space;

[0029] The FM sends the cleared identifier of the first CXL memory space to the LMD.

[0030] In some implementations, the FM clears the first CXL memory space, including:

[0031] FM adds the identifier of the first CXL memory space to the third queue;

[0032] FM obtains the identifier of the first CXL memory space from the third queue;

[0033] The FM clears the first CXL memory space based on the identifier of the first CXL memory space.

[0034] In some implementations, the FM obtains the identifier of the first CXL memory space from the third queue, including:

[0035] The FM detects whether the third queue is empty every third time period;

[0036] In response to detecting that the third queue is not empty, the FM obtains the identifier of the first CXL memory space from the third queue.

[0037] In some embodiments, the FM includes a first thread and a second thread, the first thread of the FM is used to receive the identifier of the first CXL memory space from the LMD and send the cleared identifier of the first CXL memory space to the LMD, and the second thread of the FM is used to clear the first CXL memory space.

[0038] In a fourth aspect, a memory management method is provided, which is applied to a memory management system, wherein the memory management system includes a management device, a computing device, and a CXL memory pool, wherein the management device includes a structure management FM, and the computing device includes a local high-speed computing interconnect CXL space management process LMD and a first application, wherein the method includes:

[0039] FM clears the first CXL memory space in the CXL memory pool to obtain the cleared first CXL memory space;

[0040] FM sends the cleared identifier of the first CXL memory space to LMD;

[0041] The first application sends a first memory allocation request to the LMD, where the first memory allocation request indicates allocation of CXL memory space in the CXL memory pool for the first application;

[0042] In response to the first memory allocation request, the LMD allocates the cleared first CXL memory space to the first application based on the identifier of the first CXL memory space, and sends a first memory allocation response to the first application, the first memory allocation response including the identifier of the first CXL memory space.

[0043] In a fifth aspect, a computing device is provided, the computing device comprising: an LMD and a plurality of applications,

[0044] The LMD is used to clear the first CXL memory space to obtain the cleared first CXL memory space, where the first CXL memory space is the CXL memory space allocated to the computing device in the CXL memory pool;

[0045] A first application among the multiple applications is used to send a first memory allocation request to the LMD, where the first memory allocation request indicates allocation of CXL memory space in the CXL memory pool for the first application;

[0046] The LMD is used to allocate the cleared first CXL memory space to the first application in response to the first memory allocation request, and send a first memory allocation response to the first application, where the first memory allocation response includes an identifier of the cleared first CXL memory space.

[0047] In a sixth aspect, a management device is provided, the management device comprising: a structure management FM, the FM of the management device is used to connect to the computing device and the CXL memory pool respectively, and the FM is used to execute the method of the third aspect or any one of the optional modes of the third aspect.

[0048] In the seventh aspect, a memory management system is provided, the memory management system includes a management device, a computing device and a CXL memory pool, the computing device is connected to the management device, the management device is connected to the CXL memory pool, the memory management system is used to execute the method of the second aspect, any one of the optional methods of the second aspect, the fourth aspect or any one of the optional methods of the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the architecture of a memory management system provided in an embodiment of the present application;

[0050] Figure 2 It is a schematic diagram of an internal logical architecture of an LMD provided in an embodiment of the present application;

[0051] Figure 3 It is a schematic diagram of the internal logical architecture of a FM provided in an embodiment of the present application;

[0052] Figure 4 is a flow chart of a memory management method provided by an embodiment of the present application;

[0053] Figure 5 It is a schematic diagram of an LMD managing a CXL memory space provided by an embodiment of the present application;

[0054] Figure 6 It is a schematic diagram of an LMD managing a CXL memory space provided by an embodiment of the present application;

[0055] Figure 7 It is a schematic diagram of an application applying for a first CXL memory space from a first LMD provided by an embodiment of the present application;

[0056] Figure 8 This is a flow chart of a memory asynchronous recovery method provided by an embodiment of the present application;

[0057] Fig. 9 is a flowchart of another memory management method provided by an embodiment of the present application;

[0058] Fig.10This is a schematic diagram of asynchronous memory recycling provided by an embodiment of the present application;

[0059] Fig.11 is a flowchart of another memory asynchronous recovery method provided by an embodiment of the present application;

[0060] Fig.12 This is a schematic diagram of another asynchronous memory recycling provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0062] The following is an explanation of some terminology concepts involved in the embodiments of the present application.

[0063] (1) Compute Express Link (CXL) protocol

[0064] The CXL protocol is an open industrial standard, based on the peripheral component interconnect express (PCIe) protocol, for high-bandwidth, low-latency device interconnection. The CXL protocol can be used to connect devices such as central processing units (CPUs), accelerators, memory caches, and smart network cards. The CXL protocol can be used in scenarios such as artificial intelligence (AI) and high-performance computing. CXL reuses three types of protocols based on PCIe 5.0, namely CXL.io, CXL.cache, and CXL.memory. The CXL.io protocol is used for device discovery, configuration, register access, and interrupts. The CXL.cache protocol is used for devices to access processor memory and cache memory from the processor. The CXL.memory protocol is used for the processor to access the internal memory of the device.

[0065] (2) Fabric management (FM)

[0066] FM is a software program, for example, FM is a firmware program or an application. FM communicates with a storage device, and FM communicates with a computing device. FM is used to manage the CXL memory space in the CXL memory pool. In one possible implementation, FM allocates the CXL memory space in the CXL memory pool to different computing devices for use, so that different computing devices can share the CXL memory space in the CXL memory pool. For example, if the capacity of the CXL memory space is MGB, if computing device 1 uses XGB, FM can allocate the remaining (MX)GB of CXL memory space to computing device 2. If computing device 1 is not currently using the CXL memory space, FM can allocate all CXL memory space in the CXL memory pool to computing device 2.

[0067] (3) Management device

[0068] The management device refers to a hardware device responsible for running FM. For example, the management device is a CXL switch, a CXL memory expansion card, a CXL controller, a CPU or a baseboard manager controller (BMC). This embodiment does not limit the form of the management device.

[0069] (4) Computing device

[0070] The computing device is any hardware or software that needs to use memory. The computing device can be a complete machine, for example, the computing device is a computing device, for example, the computing device is a server (such as a general server, a GPU server, a DPU server or an AI server, etc.) or a terminal. The computing device can also be a processor. For example, the computing device is a CPU or an accelerator. The accelerator is, for example, a tensor processing unit (TPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a data processing unit (DPU) or a smart network interface card (smart NIC, referred to as smart network card), etc. The computing device can also be software running on the computing device. For example, the computing device is a virtual machine or a container. In this embodiment, the computing device supports the CXL protocol, and the computing device can communicate with the storage device through the CXL protocol.

[0071] (5) Storage devices

[0072] The storage device is used to provide CXL memory space. The storage device can be a memory or a hard disk. The memory can be either a random access memory or a read only memory (ROM). For example, the random access memory is a dynamic random access memory (DRAM) or a storage class memory (SCM). DRAM is a semiconductor memory, and like most random access memories (RAM), it is a volatile memory device. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard disks, but has a slower access speed than DRAM and is cheaper than DRAM. The memory can also include other random access memories, such as static random access memory (SRAM). Read only memory is, for example, a programmable read only memory (PROM) or an erasable programmable read only memory (EPROM). Exemplarily, the storage device is a dual in-line memory module or a dual in-line memory module (DIMM) memory stick. For example, the storage device is a module composed of DRAM. Exemplarily, the storage device is a memory expansion card. Exemplarily, the storage device is a memory disk with a PCIe interface. Alternatively, the storage device is a hard disk. For example, the storage device is a solid state drive (SSD) or a hard disk drive (HDD).

[0073] (6) Local CXL Space Management Daemon (LMD)

[0074] LMD is a user-mode program. LMD runs on a computing device. LMD is used to manage CXL memory space allocated to the computing device in the CXL memory pool. For example, LMD is used to allocate CXL memory space to applications running in the computing device. LMD is, for example, a process. LMD includes at least one thread.

[0075] (7)CXL Memory Pool

[0076] CXL memory pool refers to a memory pool implemented based on the CXL protocol. CXL memory pool is used to manage and allocate CXL memory space. A CXL memory pool includes CXL memory space from multiple storage devices.

[0077] (8)CXL Memory Space

[0078] The CXL memory space may also be referred to as a CXL memory segment or a CXL memory block. The CXL memory space is, for example, a memory space with continuous physical addresses, or the CXL memory space includes a plurality of memory spaces with discontinuous physical addresses.

[0079] (9) Clear

[0080] Clearing the CXL memory space means setting the value of each bit in the CXL memory space to 0. 0 usually represents a null value or a value in an undefined state in a computer. The CXL memory space after clearing can be understood as an empty and clean memory space. There is no dirty data in the CXL memory space after clearing. Since the CXL memory space is cleared to zero, dirty data is prevented from interfering with the business processing logic of the application. Dirty data refers to data originally stored in the CXL memory space. For example, the first application 111 includes APP 1 and APP 2. The LMD first allocates a CXL memory space to APP 1. During the process of APP 1 using the CXL memory space, APP 1 stores some data in the CXL memory space, for example, APP 1 stores variables, caches, or intermediate calculation results in the CXL memory space. When APP 1 no longer needs to use the CXL memory space, APP 1 sends a first memory release request to the LMD to request the release of the CXL memory space. After LMD clears the CXL memory space, it allocates the cleared CXL memory space to APP 2, thereby preventing the dirty data stored in the CXL memory space of APP 1 from interfering with the business processing logic of APP 2.

[0081] (10) Logical Device (LD)

[0082] LD is a basic unit for managing memory divided from the memory pool. In a possible implementation, FM 210 divides the CXL memory pool into one or more LDs, and FM 210 manages the LDs. Figure 1 As shown, FM 210 divides the CXL memory pool into LD1, LD2, LD3, ..., LD9. Optionally, the capacity of one LD is 16G, for example, Figure 1As shown, LD1 occupies space from 0 to 16G in the CXL memory pool, and LD1 occupies space from 16G to 32G in the CXL memory pool. Optionally, the CXL memory segment uses LD as the basic unit. Of course, the CXL memory segment can also use blocks, pages or other units.

[0083] (11) Identification of CXL memory space

[0084] The identifier of the CXL memory space is used to identify the corresponding CXL memory space. For example, the identifier of the CXL memory space includes the address of the CXL memory space. The address of the CXL memory space is used to indicate the location of the CXL memory space in the storage device. For example, the address of the CXL memory space includes the starting address and offset of the CXL memory space. The starting address indicates the starting position of the CXL memory space. The offset indicates the distance of the CXL memory space relative to the starting address. For example, if the starting address of a CXL memory space is 0x1000 and the offset is 2, it can be determined that the CXL memory space is located at the position corresponding to the memory address 0x1002. For another example, the address of the CXL memory space includes the starting address and the ending address of the CXL memory space. For another example, the identifier of the CXL memory space includes the capacity of the CXL memory space. The capacity of the CXL memory space is, for example, 256MB, 512MB, or 1GB. For another example, the identifier of the CXL memory space includes the identifier of the storage device where the CXL memory space is located. For example, the identifier of the CXL memory space includes the universally unique identifier (UUID) of the storage device where the CXL memory space is located. The UUID is a 128-bit value, usually represented in the form of 32 hexadecimal digits, and the UUID of the storage device is used to identify the storage device on which the CXL memory space is located.

[0085] (12) Status of CXL memory space

[0086] The states of CXL memory space include available state, allocated state, and released state.

[0087] The allocated state means that the CXL memory space is already allocated to the application. After the LMD allocates the CXL memory space to the application, it updates the state of the CXL memory space to the allocated state.

[0088] The usable state means that the CXL memory space is in a state that can be used by an application. After clearing the CXL memory space, the LMD can update the state of the cleared CXL memory space to the usable state.

[0089] The released state refers to the state in which the CXL memory space is released by the application request. The LMD may set the state of the CXL memory space to the released state after receiving the first memory release request from the application. The CXL memory space in the released state may not be cleared to zero. The LMD may clear the CXL memory space in the released state and then update the state of the CXL memory space from the released state to the usable state.

[0090] In a possible implementation, LMD allocates memory based on the state of CXL memory space. For example, if LMD receives a memory request from an application, LMD can query the state of CXL memory space allocated to the computing device; when a CXL memory space is in a usable state, LMD can allocate the CXL memory space to the application; when a CXL memory space is in an allocated state, LMD will not allocate the CXL memory space to the application, thereby avoiding allocating the memory space allocated to one application to other applications again, causing conflicts between different applications occupying the same CXL memory space; when the CXL memory space is in a released state, LMD will not allocate the CXL memory space to the application, thereby avoiding allocating the uncleared CXL memory space to the application, causing old data to interfere with the processing logic of the application.

[0091] The following is an example of an application scenario of the embodiment of the present application.

[0092] The embodiment of the present application is applied to the scenario of managing CXL memory space in a CXL memory pool. The first CXL memory space is cleared by LMD or FM before the application applies for allocation of the first CXL memory space, and the LMD or FM allocates the cleared first CXL memory space to the application, so that after the application applies for the first CXL memory space, it can use the cleared first CXL memory space. Therefore, the application does not need to execute the action of clearing the first CXL memory space, thereby reducing the time overhead caused by clearing the first CXL memory space.

[0093] The following is an example of a system architecture suitable for this application scenario.

[0094] Please refer to the attached Figure 1 , attached Figure 1 1 is a schematic diagram of the architecture of a memory management system 10 provided in an embodiment of the present application. Figure 1 The illustrated memory management system 10 includes a computing device cluster 110 , a management device 200 , and a storage system 300 .

[0095] The computing device cluster 110 is used to provide computing power. The computing device cluster 110 can use the CXL memory provided by the storage system 300 to process business. The computing device cluster 110 includes one or more computing devices. The computing devices support the CXL protocol. Figure 1 In the example, the computing device cluster 110 includes a first computing device 110 and a second computing device 120. The computing device cluster 110 is in communication connection with the management device 200.

[0096] The management device 200 is used to manage the CXL memory pool 340 provided by the storage system 300. The management device 200 includes FM 210, and the management device 200 implements the function of managing the CXL memory space by running FM 210. Alternatively, FM 210 can also run on a computing device. Optionally, FM 210 is used to divide the CXL memory pool 340 into multiple LDs and manage the LDs. The management device 200 is in communication connection with the storage system 300 (or the CXL memory pool 340).

[0097] The storage system 300 is used to provide a CXL memory pool 340. The CXL memory pool 340 includes a CXL memory space. Optionally, the CXL memory space uses LD as a basic unit. The storage system 300 includes one or more storage devices. Figure 1 In the description, a storage system 300 including a first storage device 310, a second storage device 320 and a third storage device 330 is taken as an example.

[0098] The computing device includes one or more application programs (applications), LMDs and one or more interfaces. The interface connection management device 200. The LMD is used to apply for CXL memory space from the FM 210 and manage the CXL memory space.

[0099] For example, please refer to the attached Figure 1 , the first computing device 110 includes a first application 111, a first LMD 112, and a first interface 113. Optionally, the first computing device 110 also includes a second application 114. The second computing device 120 includes a third application 121, a second LMD 122, and a second interface 123. The first interface 113 of the first computing device 110 is connected to the third interface 220 in the management device 200. The second interface 123 of the second computing device 120 is connected to the fourth interface 230 in the management device 200. The fifth interface 240 in the management device 200 is connected to the storage system 300.

[0100] The number of computing devices in the computing device cluster 110 may be more or less. For example, there may be only one computing device, or there may be dozens or hundreds of computing devices, or a greater number. This embodiment does not limit the number of computing devices.

[0101] Figure 2 1 is a schematic diagram of an internal logical architecture of the first LMD 112 provided in an embodiment of the present application. The first LMD 112 includes a first message communication module 1121 , a first inspection module 1122 and a memory metadata management module 1123 .

[0102] The first message communication module 1121 is used to communicate with other components other than the first LMD 112 in a message manner.

[0103] The first message communication module 1121 is used to perform message interaction with the first application 111 deployed on the first computing device 110. The first message communication module 1121 includes a CXL memory space application interface and a CXL memory space release interface. When the first application 111 calls the CXL memory space application interface to send a first memory allocation request, the first message communication module 1121 receives and processes the first memory allocation request. When the first application 111 calls the CXL memory space release interface to send a first memory release request, the first message communication module 1121 receives and processes the first memory release request.

[0104] Optionally, the first message communication module 1121 is also used for cross-device communication. For example, the first message communication module 1121 is used for message interaction with the FM 210 in the management device 200. For example, the first message communication module 1121 is used to send a second memory allocation request and a second memory release request to the FM 210 and receive a second memory allocation response or a second memory release response from the FM 210.

[0105] The first inspection module 112 is used to periodically detect whether there is a first CXL memory space that is requested to be released by the first application 111. If the first inspection module 112 detects that the first CXL memory space is requested to be released by the first application 111, in the case of the first embodiment, the first inspection module 1122 clears the first CXL memory space. In the case of the second embodiment, the first inspection module 1122 sends the identifier of the first CXL memory space to the FM 210.

[0106] The memory metadata management module 1123 is used to manage metadata of the first CXL memory space. The metadata of the CXL memory space includes the state of the CXL memory space and information of the LD corresponding to the CXL memory space.

[0107] The first message communication module 1121, the first inspection module 1122, and the memory metadata management module 1123 may be software virtual modules. For example, the first message communication module 1121, the first inspection module 1122, and the memory metadata management module 1123 include program codes running on the first computing device 110. For example, the memory in the first computing device 110 stores executable program codes, and the processor in the first computing device 110 executes the executable program codes to respectively implement the functions of the first message communication module 1121, the first inspection module 1122, and the memory metadata management module 1123.

[0108] Figure 3 2 is a schematic diagram of a logical architecture of an FM 210 provided in an embodiment of the present application. The FM 210 includes a second message communication module 2101 and a second inspection module 2102. The second message communication module 2101 is used to perform message interaction with the first LMD 112. The second inspection module 2102 is used to perform inspection tasks. For example, in the case of the second embodiment, the second inspection module 2102 is used to periodically detect whether there is an identifier of the first CXL memory space sent by the first LMD 112. If it is detected that there is an identifier of the first CXL memory space sent by the first LMD 112, the second inspection module 2102 clears the first CXL memory space.

[0109] The second message communication module 2101 and the second inspection module 2102 may be software virtual modules. For example, the second message communication module 2101 and the second inspection module 2102 include program codes running on the management device 200. For example, the memory in the management device 200 stores executable program codes, and the processor in the management device 200 executes the executable program codes to respectively implement the functions of the second message communication module 2101 and the second inspection module 2102.

[0110] In some implementations of the present application, the LMD in the computing device is responsible for clearing the CXL memory space for the application in the computing device, which is illustrated in Example 1 below. In other implementations of the present application, the FM is responsible for clearing the CXL memory space allocated to the application in the computing device, which is illustrated in Example 2 below. Regardless of whether the LMD or the FM is responsible for clearing, since the CXL memory space obtained by the application is the CXL memory space after clearing, the time overhead caused by the application clearing the CXL memory space can be saved, and the embodiments of the present application do not limit the execution subject responsible for clearing the CXL memory space.

[0111] Example 1

[0112] Attached Figure 4is a flow chart of a memory management method provided by an embodiment of the present application. In a possible implementation, embodiment 1 is applied to the attached Figure 1 The memory management system 10 is shown. For example, in Embodiment 1, Figure 1 The computing device cluster 110, the management device 200 and the storage system 300 are executed interactively.

[0113] Embodiment 1 involves FM 210 allocating CXL memory space to LMD and LMD allocating CXL memory space to application. In order to distinguish the description of FM 210 allocating CXL memory space to LMD and LMD allocating CXL memory space to application, “first CXL memory space” is used to describe the CXL memory space allocated by LMD to application, and “second CXL memory space” is used to describe the CXL memory space allocated by FM 210 to computing device. The second CXL memory space includes the first CXL memory space. It can also be understood that the first CXL memory space is a subset of the second CXL memory space. For example, FM 210 allocates a CXL memory space with a capacity of 32 GB to the computing device, and the LMD running in the computing device further allocates 10 GB of CXL memory space from the 32 GB of CXL memory space to the application running in the computing device. In this example, the 32 GB of CXL memory space is a specific example of the second CXL memory space, and the 10 GB of CXL memory space is a specific example of the first CXL memory space.

[0114] Embodiment 1 involves the process of memory allocation request and memory allocation response interaction between LMD and application, and also involves the process of memory allocation request and memory allocation response interaction between LMD and FM 210. In order to distinguish the memory allocation request describing the interaction between LMD and application and the memory allocation request describing the interaction between LMD and FM 210, the memory allocation request describing the interaction between LMD and FM 210 is described by “second memory allocation request”, and the memory allocation request describing the interaction between LMD and application is described by “first memory allocation request”. In order to distinguish the memory allocation response describing the interaction between LMD and application and the memory allocation response describing the interaction between LMD and FM210, the memory allocation response describing the interaction between LMD and FM 210 is described by “second memory allocation response”, and the memory allocation response describing the interaction between LMD and application is described by “first memory allocation response”. Memory allocation request may also be referred to as memory application request.

[0115] Embodiment 1 involves the process of memory release request and memory release response interacting between LMD and application, and also involves the process of memory release request and memory release response interacting between LMD and FM 210. In order to distinguish the memory release request interacting between LMD and application and the memory release request interacting between LMD and FM 210, the memory release request interacting between LMD and FM 210 is described by “second memory release request”, and the memory release request interacting between LMD and application is described by “first memory release request”. In order to distinguish the memory release response interacting between LMD and application and the memory release response interacting between LMD and FM210, the memory release response interacting between LMD and FM 210 is described by “second memory release response”, and the memory release response interacting between LMD and application is described by “first memory release response”.

[0116] Optionally, the memory allocation request interacting between the LMD and the application includes a configuration capacity, and the memory allocation request interacting between the LMD and the FM 210 also includes a configuration capacity. The configuration capacities carried by different memory allocation requests may be different. In order to distinguish and describe the configuration capacities carried by different memory allocation requests, the "first configuration capacity" is used below to describe the configuration capacity included in the first memory allocation request, and the "second configuration capacity" is used to describe the configuration capacity included in the second memory allocation request. For example, the second configuration capacity is greater than or equal to the first configuration capacity. For the meaning and function of the first configuration capacity and the second configuration capacity, please refer to the description of the corresponding steps in Example 1.

[0117] Embodiment 1 relates to a process in which an LMD interacts with an application to perform memory allocation and a process in which an LMD interacts with an application to perform memory release. In order to distinguish the description, a "first application" is used to describe an application that interacts with an LMD in a memory allocation process, and a "second application" is used to describe an application that interacts with an LMD in a memory release process. The first application and the second application are deployed on the same computing device. The first application and the second application are optionally different applications. For example, by executing embodiment 1, the LMD clears a CXL memory space requested to be released by an application and allocates it to another application, thereby supporting the application to obtain the cleared CXL memory space and realizing that multiple applications share the CXL memory space. The first application and the second application are optionally the same application. For example, when an application requests to release the CXL memory space, the LMD clears the CXL memory space. Subsequently, when the application requests the LMD to allocate the CXL memory space again, the LMD can allocate the cleared CXL memory space to the application again, thereby realizing allocation of the CXL memory space according to the needs of the application.

[0118] S234 , the first LMD 112 in the first computing device 110 clears the first CXL memory space to obtain a cleared first CXL memory space.

[0119] Regarding the method of clearing the first CXL memory space, optionally, the first LMD 112 calls a memset function to clear the first CXL memory space. Alternatively, the first LMD 112 loops through each byte in the first CXL memory space and sets the value of each byte in the first CXL memory space to zero. Alternatively, the first LMD 112 calls a specific hardware instruction (such as a repstos instruction) to clear the first CXL memory space.

[0120] Because the first LMD 112 clears the first CXL memory space before receiving the first memory application request from the first application 111, the first LMD 112 can allocate the cleared first CXL memory space to the first application 111 after receiving the first memory application request from the first application 111. Then, after the first application 111 applies for the first CXL memory space, the first application 111 does not need to clear the applied first CXL memory space, but can directly use the cleared first CXL memory space, thereby eliminating the first application 111 from calling the memset function to clear the first CXL memory space, saving the time overhead of the first application 111 due to the execution of the clearing operation. Moreover, since the first LMD 112 is a user-mode program, the first LMD 112 manages the first CXL memory space, so that when the first application 111 applies for the first CXL memory space, it does not need to go through the layers of complex memory management calls of the operating system, thereby reducing the software stack overhead and simplifying the process. Based on this, the first LMD 112 provides efficient and reliable services of applying for CXL memory and releasing CXL memory for applications of the first computing device 110 .

[0121] In a possible implementation, S234 includes S234a to S234c.

[0122] S234a: The first LMD 112 adds the identifier of the first CXL memory space to the first queue.

[0123] The first queue is used to store the identifier of the CXL memory space to be cleared. Optionally, the first queue is used to store the identifier of the CXL memory space that the application requests to release. In a possible implementation, the first LMD 112 adds the identifier of the first CXL memory space to the end of the first queue. Considering that it takes a long time to clear the CXL memory space, which may usually take seconds, the identifier of the CXL memory space to be cleared is stored in the queue, so that the first LMD 112 can perform other tasks (such as returning a response to the application) after adding the identifier of the CXL memory space to be cleared to the queue, without having to wait for the clearing to be completed before performing other tasks, thereby reducing the risk of blocking the main task of the first LMD 112 (the main task is, for example, the first LMD 112 interacting with the application to process the memory allocation request and memory release request sent by the application) caused by clearing the CXL memory space, realizing asynchronous processing of clearing, and reducing the overall delay of the first computing device 110 in executing tasks.

[0124] Optionally, the first queue is a first-in-first-out queue. The identifiers of the CXL memory spaces in the first queue are arranged in order from earliest to latest according to the time points at which they are requested to be released. In other words, the earlier a CXL memory space is requested to be released by an application, the closer the identifier of the CXL memory space is to the head of the queue in the first queue. For example, the first LMD 112 obtains the identifier of the CXL memory space at the head of the first queue to obtain the identifier of the first CXL memory space, and the first LMD 112 clears the first CXL memory space corresponding to the identifier of the first CXL memory space. In addition, in a possible implementation, after the first LMD 112 clears the first CXL memory space, the first LMD 112 deletes the identifier of the first CXL memory space from the first queue, so that the identifier of the next CXL memory space after the first CXL memory space in the first queue is again at the head of the queue. By using a first-in-first-out queue to store the identifier of the CXL memory space to be cleared, the CXL memory space released by the application request first can be cleared first, and then the CXL memory space released by the application request first can be reclaimed first, so that the CXL memory space released by the application request first can be used again as soon as possible.

[0125] S234b: The first LMD 112 obtains the identifier of the first CXL memory space from the first queue.

[0126] In a possible implementation, when the identifier of the first CXL memory space is at the head of the first queue, the first LMD 112 obtains the identifier of the first CXL memory space from the first queue, and clears the first CXL memory space corresponding to the identifier of the first CXL memory space.

[0127] S234c: The first LMD 112 determines the first CXL memory space based on the identifier of the first CXL memory space. The first LMD 112 clears the first CXL memory space.

[0128] In addition, in a possible implementation, after the first LMD 112 clears the first CXL memory space, the first LMD 112 deletes the identifier of the first CXL memory space from the first queue, so that the identifier of the next CXL memory space after the identifier of the first CXL memory space in the first queue is placed at the head of the queue, thereby achieving orderliness of the first queue and facilitating clearing the next CXL memory space.

[0129] In a possible implementation, the first LMD 112 detects whether the first queue is empty every first time period; in response to detecting that the first queue is not empty and the identifier of the first CXL memory space is at the head of the first queue, the first LMD 112 obtains the identifier of the first CXL memory space from the first queue, and clears the first CXL memory space based on the identifier of the first CXL memory space.

[0130] Since the first LMD 112 uses the method of periodically clearing the CXL memory space stored in the queue, it is possible to clear the CXL memory space as timely as possible without having to determine in real time whether there is a CXL memory space to be cleared, thereby helping to reduce the CPU occupancy rate caused by the real-time determination of whether there is a CXL memory space to be cleared. The length of the first time period can be set according to demand. For example, the length of the first time period is 5 seconds.

[0131] Optionally, the first LMD 112 performs S234 by executing a first inspection task, which includes detecting whether the first queue is empty at every first time period, and clearing the CXL memory space corresponding to the identifier of the CXL memory space at the head of the first queue if the first queue is not empty.

[0132] Optionally, the first inspection task is executed in a threaded manner. For example, the first LMD 112 includes a first thread and a second thread. The first thread is used to execute the first inspection task. The second thread is used to perform message interaction with the application. For example, the second thread is used to allocate the first CXL memory space to the application and release the first CXL memory space previously allocated to the application. The first thread and the second thread are, for example, two independent threads. Since the first CXL memory space is cleared by an independent thread, the first LMD 112 can perform the action of clearing the first CXL memory space and the action of performing message interaction with the application in parallel through multiple threads.

[0133] For example, while the first thread clears the first CXL memory space, the second thread receives and processes the memory allocation request and memory allocation response from the application, and allocates other CXL memory spaces other than the first CXL memory space to the application. Based on this, the first LMD 112 implements clearing the first CXL memory space in the background in a multi-threaded manner, reduces the risk that clearing the first CXL memory space affects the efficiency of message interaction between the first LMD 112 and the application, and improves the overall efficiency of the first LMD 112 in clearing and interacting with the application.

[0134] Optionally, the first inspection task is a background task of the first LMD 112. The foreground task of the first LMD 112 is, for example, allocating a first CXL memory space and releasing the first CXL memory space.

[0135] For example, as attached Figure 5 As shown in (a), in the process of executing the first inspection task, in response to the identifier of CXL memory space 3 in the first queue being at the head of the first queue, the first inspection module 1122 in the first LMD 112 executes S234b to obtain (pop) the identifier of CXL memory space 3 from the first queue. The first inspection module 1122 in the first LMD 112 executes S234c to clear CXL memory space 3. The first inspection module 1122 in the first LMD 112 deletes the identifier of CXL memory space 3 from the first queue, so that the identifier of CXL memory space 6 moves to the head of the first queue, and the identifier of CXL memory space 9 moves to the second position in the first queue.

[0136] For example, as attached Figure 5 As shown in (b), in the process of executing the first inspection task, in response to the identifier of CXL memory space 6 being at the head of the first queue, the first inspection module 1122 in the first LMD 112 executes S234b to obtain (pop) the identifier of CXL memory space 6 from the first queue, and executes S234c to clear CXL memory space 6. The first inspection module 1122 in the first LMD 112 deletes the identifier of CXL memory space 6 from the first queue, so that the identifier of CXL memory space 9 moves to the head of the first queue.

[0137] For example, as attached Figure 5As shown in (c) of FIG. 1 , during the process of executing the first inspection task, the first inspection module 1122 in the first LMD 112, in response to the identifier of the CXL memory space 9 in the first queue being at the head of the queue, executes S234b to obtain (pop) the identifier of the CXL memory space 9 from the first queue, and executes S234c to clear the CXL memory space 9. The first inspection module 1122 in the first LMD 112 deletes the identifier of the CXL memory space 9 from the first queue, so that the first queue is empty, as shown in FIG. Figure 5 As shown in the first queue in (d).

[0138] S244 : The first application in the first computing device 110 generates a first memory allocation request. The first application sends the first memory allocation request to the first LMD 112 in the first computing device 110 .

[0139] The first memory allocation request indicates that a CXL memory space in a CXL memory pool is allocated to the first application. Optionally, the first memory allocation request is a message having an encapsulation format specified by the CXL protocol. By sending the first memory allocation request to the first LMD 112, the first application is equivalent to notifying the first LMD 112 that the first application needs to obtain CXL memory space, thereby automatically triggering the first LMD 112 to perform a subsequent memory allocation process. In a possible implementation, the first memory allocation request is a message having an encapsulation format specified by the CXL protocol.

[0140] In a possible implementation, the first LMD 112 includes a memory allocation interface. The memory allocation interface is used to request allocation of CXL memory space. When the first application needs CXL memory space, the first application can call the memory allocation interface provided by the first LMD 112 and send a first memory application request to the first LMD 112.

[0141] In a possible implementation, the first memory allocation request includes a first configuration capacity. The first configuration capacity is equivalent to the required capacity of the application. The first configuration capacity indicates the capacity of the CXL memory space that the application applies to obtain from the CXL memory pool. The first configuration capacity can also be understood as the capacity of the memory space that FM 210 needs to allocate to the application. For example, the first application determines the first configuration capacity based on business needs, and the first application writes the first configuration capacity to the first memory allocation request. Since the first memory allocation request carries the first configuration capacity, it is convenient for FM 210 to know how much CXL memory space needs to be allocated to the first application.

[0142] In some possible implementations, the first LMD 112 provides a CXL memory space application interface. The CXL memory space application interface is used to apply for the first CXL memory space. The CXL memory space application interface is, for example, an SDK interface. The first application 111 calls the CXL memory space application interface to send a first memory application request to the first LMD 112.

[0143] S245 , the first LMD 112 receives the first memory allocation request, and in response to the first memory allocation request, the first LMD 112 allocates the cleared first CXL memory space to the first application.

[0144] In a possible implementation of allocating the first CXL memory space, the first LMD 112 queries the state of the first CXL memory space based on the identifier of the first CXL memory space; in response to the first CXL memory space being in a usable state, the first LMD 112 allocates the first CXL memory space after being cleared to the first application. Since the CXL memory space is allocated to the first application after confirming that the CXL memory space is in a usable state and has been cleared, the first application does not need to clear the CXL memory space, thereby reducing the delay caused by the first application clearing the CXL memory space after obtaining the CXL memory space, and also reducing the risk of errors caused by different applications reading and writing data to the same CXL memory space due to allocating the CXL memory space allocated to other applications other than the first application to the first application.

[0145] In a possible implementation of allocating the first CXL memory space, the first LMD 112 parses the first memory allocation request and obtains the first configuration capacity carried in the first memory allocation request. The first LMD 112 determines the first CXL memory space from the second CXL memory space based on the first configuration capacity carried in the first memory allocation request, and the capacity of the first CXL memory space is greater than or equal to the first configuration capacity. By allocating the first CXL memory space based on the first configuration capacity, it is helpful that the allocated CXL memory space can meet the application's demand for the capacity of the CXL memory space.

[0146] Exemplarily, the first LMD 112 queries the state of the first CXL memory space based on the identifier of the first CXL memory space; in response to the first CXL memory space being in a usable state and the capacity of the first CXL memory space being greater than or equal to the first configured capacity, the first LMD 112 allocates the first CXL memory space after being cleared to the first application. By allocating the CXL memory space in consideration of both capacity and state, the allocated CXL memory space can meet the application's demand for the capacity of the CXL memory space, and also reduces the risk of errors caused by different applications reading and writing data to the same CXL memory space when the CXL memory space allocated to other applications other than the first application is allocated to the first application.

[0147] Optionally, after the first LMD 112 allocates the cleared first CXL memory space to the first application, the first LMD 112 establishes a first mapping relationship. The first mapping relationship includes an identifier of the first CXL memory space and an identifier of the first application. The first mapping relationship may also be referred to as a binding relationship between the first CXL memory space and the first application. The first LMD 112 identifies that the first CXL memory space has been allocated to the first application by establishing the first mapping relationship.

[0148] In a possible implementation, after the first LMD 112 allocates the first CXL memory space to the first application, the first LMD 112 updates the state of the first CXL memory space to an allocated state, and the allocated state indicates that the first CXL memory space has been allocated to the first application. Therefore, when allocating memory subsequently, the first CXL memory space will not be allocated to other applications, thereby reducing the probability of conflicts caused by allocating the same CXL memory space to two applications at the same time.

[0149] In a possible implementation, the first LMD 112 locks the state of the first CXL memory space before updating the state of the first CXL memory space; after the first LMD 112 updates the state of the first CXL memory space to the allocated state, the first LMD 112 unlocks the state of the first CXL memory space. The first LMD 112 locks the state of the CXL memory space and updates the state of the CXL memory space while the state of the CXL memory space is locked, thereby reducing the risk of inconsistency in the states of the CXL memory space modified or accessed by different threads, which may cause errors.

[0150] S246: The first LMD sends a first memory allocation response to the first application.

[0151] The first memory allocation response includes the first CXL memory space identifier after being cleared. After the first application receives the first memory allocation response, the first application can obtain the first CXL memory space identifier from the first memory allocation response, and the first application can access the first CXL memory space based on the first CXL memory space identifier to read and write data to the first CXL memory space.

[0152] The method provided in this embodiment improves the timing of clearing the CXL memory space. The CXL memory space is cleared in advance before being allocated to the application, and the cleared CXL memory space is allocated to the application. This makes it unnecessary for the application to clear the CXL memory space after obtaining the CXL memory space, thereby greatly reducing time overhead.

[0153] In addition, since the first LMD 112 and the application allocate CXL memory space through message interaction, there is no need to go through the layers of complicated memory management of the operating system, thereby reducing software stack overhead, simplifying the process and improving flexibility.

[0154] In addition, the first LMD 112 clears and resets the CXL memory space for applications located in the same first computing device 110 as the first LMD 112, thereby saving the network communication delay caused by the first computing device 110 communicating with the FM210 in the management device through the network, shortening the memory recovery time and improving the efficiency of memory recovery.

[0155] Optionally, in Embodiment 1, after the first LMD 112 executes S234 , the first LMD 112 further executes the following S237 .

[0156] S237 , the first LMD 112 updates the cleared state of the first CXL memory space to a usable state.

[0157] Updating the cleared state of the first CXL memory space is equivalent to indicating that the first CXL memory space can be allocated to the application, so that the first LMD 112 can allocate the first CXL memory space to the first application when executing the memory allocation step in S244 .

[0158] Optionally, S237 includes S237a to S237b.

[0159] S237a: The first LMD 112 adds the identifier of the first CXL memory space to the second queue.

[0160] S237b, the first LMD 112 obtains the identifier of the first CXL memory space from the second queue. The first LMD 112 determines the state of the first CXL memory space based on the identifier of the first CXL memory space; the first LMD 112 updates the state of the first CXL memory space to a usable state. For example, the first LMD 112 updates the state of the first CXL memory space from a released state to a usable state.

[0161] The second queue is used to store the identifier of the CXL memory space whose state is to be updated. For example, the second queue is used to store the identifier of the CXL memory space after being cleared. Considering that the action of updating the state of the CXL memory space usually involves locking and unlocking and is therefore time-consuming, since the identifier of the CXL memory space whose state is to be updated is stored in the queue, the first LMD 112 can perform other tasks after adding the identifier of the CXL memory space whose state needs to be updated to the queue, without having to wait for the state update to be completed before performing other tasks, thereby reducing the risk of blocking the main task of the first LMD 112 (the main task is, for example, the first LMD 112 interacting with the application to process the memory allocation request and memory release request sent by the application) caused by updating the state of the CXL memory space, realizing asynchronous processing of the state update, and reducing the overall delay of the first computing device 110 in executing tasks.

[0162] Optionally, the second queue is a first-in-first-out queue. The identifiers of the CXL memory spaces in the second queue are arranged in order from earliest to latest according to the time points at which they are cleared. In other words, the earlier a CXL memory space is cleared, the closer the identifier of the CXL memory space is to the head of the queue in the second queue. For example, after the first LMD 112 clears the first CXL memory space, the first LMD 112 adds the identifier of the first CXL memory space to the tail of the second queue. When the identifier of the first CXL memory space is at the head of the second queue, the first LMD 112 obtains the identifier of the first CXL memory space from the second queue. The first LMD 112 updates the state of the first CXL memory space to an available state based on the identifier of the first CXL memory space. In addition, after the first LMD 112 clears the first CXL memory space, the first LMD 112 deletes the identifier of the first CXL memory space from the second queue, so that the identifier of the next CXL memory space after the first CXL memory space in the second queue is again at the head of the queue.

[0163] By using a first-in-first-out queue to save and obtain the identifier of the CXL memory space to be updated, the state of the CXL memory space that is cleared first can be updated to a usable state first, so that the CXL memory space that is cleared first can be allocated to the application as soon as possible.

[0164] In a possible implementation, the first LMD 112 detects whether the second queue is empty every second time period; in response to detecting that the second queue is not empty and the identifier of the first CXL memory space is at the head of the second queue, the first LMD 112 obtains the identifier of the first CXL memory space from the second queue, and clears the first CXL memory space based on the identifier of the first CXL memory space. Since the first LMD 112 adopts a method of regularly updating the state of the CXL memory space based on the queue, it is possible to update the state of the CXL memory space as timely as possible without having to determine in real time whether there is a CXL memory space to be updated, thereby helping to reduce the CPU occupancy caused by the real-time determination of whether there is a CXL memory space to be updated. The length of the second time period can be set according to demand. For example, the length of the second time period is 5 seconds.

[0165] Optionally, the first LMD 112 performs S237 by executing a second inspection task including detecting whether the second queue is empty at every second time period, and updating the state of the CXL memory space corresponding to the identifier of the CXL memory space at the head of the second queue to a usable state if the second queue is not empty.

[0166] Optionally, the second inspection task is executed in a threaded manner. For example, the first LMD 112 includes a third thread. The third thread is used to execute the second inspection task. The third thread and the second thread are, for example, two independent threads. Since the state of the first CXL memory space is updated through an independent thread, the first LMD 112 can execute the action of updating the state of the first CXL memory space and the action of performing message interaction with the application in parallel through multiple threads.

[0167] For example, while the third thread updates the state of the first CXL memory space, the second thread receives and processes the memory allocation request and memory allocation response from the application, and allocates other CXL memory spaces other than the first CXL memory space to the application. Based on this, the first LMD 112 implements the use of a multi-threaded method to update the state of the first CXL memory space in the background, reduces the risk that the update of the first CXL memory space and the locking and unlocking process executed for updating the first CXL memory space affect the efficiency of message interaction between the first LMD 112 and the application, and improves the overall efficiency of the first LMD 112 updating the first CXL memory space and interacting with the application.

[0168] In a possible implementation, before the first LMD 112 updates the state of the first CXL memory space, the first LMD 112 locks the state of the first CXL memory space; after the first LMD 112 updates the state of the first CXL memory space to a usable state, the first LMD 112 unlocks the state of the first CXL memory space. For example, the first LMD 112 locks the state of the CXL memory space using a mutual exclusion lock mechanism. For example, before the first LMD 112 updates the state of the first CXL memory space, the first LMD 112 locks the state of the first CXL memory space, so that the state of the first CXL memory space is in a locked state. If the state of the first CXL memory space is locked successfully, the first LMD 112 can access the state of the first CXL memory space. The first LMD 112 can update the state of the CXL memory space to a usable state during the period when the state of the first CXL memory space is locked. If a second thread other than the first LMD 112 needs to access the state of the first CXL memory space, the second thread will be blocked and the second thread will wait for unlocking. When the first LMD 112 finishes updating the state of the first CXL memory space, the first LMD 112 unlocks the state of the first CXL memory space. After the state of the first CXL memory space is unlocked, the second thread can access the state of the first CXL memory space.

[0169] By locking the state of the CXL memory space, it is possible to avoid the risk of multiple threads modifying or accessing the same state at the same time, which may cause inconsistent states or disordered states obtained by different threads. For example, if the first thread included in the first LMD 112 is updating the state of the CXL memory space from the released state to the usable state, and the second thread included in the first LMD 112 is querying the CXL memory space in the usable state in order to allocate the CXL memory space in the usable state to the application, then the state read by the second thread may have been modified, resulting in inconsistent states. The first LMD 112 locks the state of the CXL memory space and updates the state of the CXL memory space while the state of the CXL memory space is in the locked state, thereby reducing the risk of inconsistent states of the CXL memory space modified or accessed by different threads, which may cause errors.

[0170] In a possible implementation, the process of updating the state of the CXL memory space and the business process (allocating the CXL memory space and releasing the CXL memory space) share a lock. For example, the first LMD 112 initializes the lock. When the first thread included in the first LMD 112 requests to acquire the lock, if the second thread does not hold the lock, the first thread included in the first LMD 112 successfully acquires the lock, and the first thread can lock the state of the CXL memory space so as to update the state of the CXL memory space when the CXL memory space is in a locked state. On the contrary, if the second thread already holds the lock, the first thread will be blocked and the first thread needs to wait for the lock to be released.

[0171] For example, as attached Figure 5 As shown in (a) of FIG. 2 , during the process of executing S237b, after the first LMD 112 obtains (pops) the identifier of the CXL memory space 3 from the second queue, the first LMD 112 requests to obtain the lock. The first LMD 112 locks the state of the CXL memory space 3. During the state locking of the CXL memory space 3, the first LMD 112 updates the state of the CXL memory space 3 to the usable state, so that the usable CXL memory space includes the CXL memory space 3.

[0172] For example, as attached Figure 5 As shown in (b), during the process of executing S237b, after the first LMD 112 obtains (pops) the identifier of the CXL memory space 6 from the second queue, the first LMD 112 requests to obtain the lock. The first LMD 112 locks the state of the CXL memory space 6. During the period of locking the state of the CXL memory space 6, the first LMD 112 updates the state of the CXL memory space 6 to a usable state, so that the usable CXL memory space includes the CXL memory space 3 and the CXL memory space 6.

[0173] For example, as attached Figure 5 As shown in (c) in FIG. 2 , during the process of executing S237b, the first LMD 112 obtains (pops) the identifier of the CXL memory space 9 from the second queue. The first LMD 112 requests to obtain the lock. The first LMD 112 locks the state of the CXL memory space 9. During the period of locking the state of the CXL memory space 9, the first LMD 112 updates the state of the CXL memory space 9 to a usable state, so that the usable CXL memory space includes the CXL memory space 3, the CXL memory space 6, and the CXL memory space 9.

[0174] Optionally, the identifier of the first CXL memory space stored in the second queue comes from the first queue. For example, the first LMD 112 obtains the identifier of the first CXL memory space from the first queue; the first LMD 112 clears the first CXL memory space and saves the identifier of the first CXL memory space in the second queue, which is equivalent to moving the identifier of the first CXL memory space from the first queue to the second queue as the first CXL memory space is cleared, thereby indicating that the first CXL memory space has been cleared.

[0175] For example, as attached Figure 5 As shown in (a) of FIG. 1 , as the CXL memory space 3 is cleared, the first LMD 112 moves the identifier of the CXL memory space 3 from the first queue to the second queue. Figure 5 As shown in (b) of FIG. 1 , as the CXL memory space 6 is cleared, the first LMD 112 moves the identifier of the CXL memory space 6 from the first queue to the second queue. Figure 5 As shown in (c) in FIG. 1 , as the CXL memory space 9 is cleared, the first LMD 112 moves the identifier of the CXL memory space 9 from the first queue to the second queue.

[0176] Optionally, the first queue and the second queue are created by the first computing device 110. For example, the first computing device 110 creates two queues based on a basic data structure in C++ as the first queue and the second queue. By creating the first queue and the second queue during initialization, the first queue and the second queue are conveniently used later.

[0177] Optionally, the capacity of the first queue and the capacity of the second queue are both 1024. The capacity of a queue refers to the maximum number of elements that a queue can store. In other words, the first queue and the second queue can store the identifiers of 1024 CXL memory spaces. Of course, the capacity of the first queue and the capacity of the second queue can also be replaced by other values, for example, the capacity of the first queue and the capacity of the second queue are 512 or 2048.

[0178] Optionally, before executing S237, the first LMD 112 detects whether the first LMD 112 is in an idle state. When the first LMD 112 detects that the first LMD 112 is in an idle state, S237 is executed. When the first LMD 112 detects that the first LMD 112 is in a non-idle state, other tasks other than S237 are executed, such as clearing the CXL memory space requested to be released by the application. Since the first LMD 112 is in a non-idle state, the first LMD 112 is likely to be performing an action of allocating memory or releasing memory, and the action of allocating memory or releasing memory may optionally include the operation of acquiring a lock, locking, and unlocking, and the process of updating the state of the CXL memory space in S237 may also optionally include the operation of acquiring a lock, locking, and unlocking. By executing S237 when the first LMD 112 is in an idle state, the risk of lock competition between allocating memory or releasing memory and S237 is reduced, and the probability of S237 blocking the allocation of memory or releasing memory is reduced.

[0179] Optionally, Example 1 also includes the following S242.

[0180] S242, the terminal sends a service processing request to the first computing device 110.

[0181] For example, the first application deployed by the first computing device 110 is a server application, and the terminal deploys a client application corresponding to the server application. The user triggers an operation on the client application. The terminal generates a business processing request in response to the operation triggered on the client application and sends the business processing request to the first computing device 110. The first application in the first computing device 110 receives the business processing request and executes S244 in response to the business processing request.

[0182] Optionally, Embodiment 1 also includes the following S230 and S232.

[0183] S230 , the second application in the first computing device 110 generates a first memory release request, and the second application sends the first memory release request to the first LMD 112 in the first computing device 110 .

[0184] The first memory release request indicates to release the first CXL memory space. For example, the first memory release request includes an identifier of the first CXL memory space. Optionally, the first memory release request is a message having an encapsulation format specified by the CXL protocol. In an exemplary scenario, the first LMD 112 originally allocates the first CXL memory space to the second application. After the second application finishes using the first CXL memory space, the second application executes S230, thereby triggering a process of reclaiming the first CXL memory space.

[0185] For example, please refer to the attached Figure 4 , Figure 4 APP 1, APP 2 and APP 3 are all specific examples of the second application. After APP 1 finishes using CXL memory space 3, APP 1 sends a first memory release request to the first message communication module 1121 in the first LMD 112, and the first memory release request sent by APP 1 includes the identifier of CXL memory space 3. For another example, after APP 2 finishes using the first CXL memory space 6, APP 2 sends a first memory release request to the first message communication module 1121 in the first LMD 112. The first memory release request sent by APP 2 includes the identifier of CXL memory space 6. For another example, after APP 3 finishes using the first CXL memory space 9, APP 3 sends a first memory release request to the first message communication module 1121 in the first LMD 112, and the first memory release request sent by APP 3 includes the identifier of CXL memory space 9.

[0186] S232: The first LMD 112 receives a first memory release request, generates a first memory release response, and sends the first memory release response to the second application.

[0187] The first memory release response indicates that the first CXL memory space is released successfully. Optionally, the first memory release response is a message having an encapsulation format specified by the CXL protocol.

[0188] The first LMD 112 sends the first memory release response to the second application, which is equivalent to notifying the second application that the first CXL memory space has been released successfully. Since there is no need to wait for the completion of clearing the first CXL memory space before returning a response to the second application, the first LMD 112 can directly return a response to the second application after receiving the memory release request from the second application. Therefore, the response is returned faster, the memory release process is simpler, and the time overhead caused by the memory release request process to the application is further saved, reducing the risk of the second application being blocked from processing business due to waiting for a response message to the first memory release request.

[0189] In some possible implementations, the first LMD 112 provides a CXL memory space release interface. The CXL memory space release interface is used to release the first CXL memory space. The CXL memory space release interface may be a software development kit (SDK) interface. When the first application 111 finishes using the first CXL memory space, the first application 111 calls the CXL memory space release interface to send a first memory release request to the first LMD 112.

[0190] Regarding the relationship between S234, S230, and S232, optionally, the first CXL memory space targeted in S234 is determined based on S230, and S234 is used to clear the CXL memory space requested to be released by the second application in S230 and reallocate it to the first application. Exemplarily, during the process of executing S232, the first LMD 112 obtains the identifier of the first CXL memory space from the first memory release response, and the first LMD 112 determines that the first CXL memory space is the CXL memory space to be cleared based on the identifier of the first CXL memory space, and thus executes S234 on the first CXL memory space. Alternatively, the first CXL memory space targeted in S234 is determined based on other methods other than S230. For example, the first LMD 112 uses the CXL memory space allocated by the FM 210 to the first computing device 110 as the first CXL memory space to execute S234.

[0191] This embodiment does not limit the time sequence of S232 and S234a. The first LMD 112 may execute S232 first and then S234a, or may execute S234a first and then S232.

[0192] Take the example of executing S234a first and then executing S232. Figure 6 , Figure 6APP 1, APP 2 and APP 3 are all specific examples of the second application. APP 1, APP 2 and APP 3 initiate a first memory release request to the first LMD 112 in sequence. After the first LMD 112 receives the first memory release requests from APP 1, APP 2 and APP 3 respectively, the first LMD 112 executes S234a to add the identifier of the CXL memory space 3 requested to be released by APP 1 to the first queue, and then the first LMD 112 executes S232 to send a first memory release response to APP 1, thereby notifying APP 1 that the CXL memory space 3 has been successfully released. After the first LMD 112 executes S234a to add the identifier of the CXL memory space 6 requested to be released by APP 2 to the first queue, the first LMD 112 executes S232 to send a first memory release response to APP 2, thereby notifying APP 2 that the CXL memory space 6 has been successfully released. After the first LMD 112 executes S234a to add the identifier of the CXL memory space 9 requested to be released by the APP 3 to the first queue, the first LMD 112 executes S232 to send a first memory release response to the APP 3 to notify the APP 3 that the CXL memory space 9 has been released successfully. The first queue sequentially stores the identifier of the CXL memory space 3, the identifier of the CXL memory space 6, and the identifier of the CXL memory space 9. The identifier of the CXL memory space 3 is at the head of the first queue, the identifier of the CXL memory space 6 is at the second position in the first queue, and the identifier of the CXL memory space 9 is at the third position in the first queue.

[0193] Optionally, when the first LMD 112 processes the first memory release request sent by the first application 111, the first LMD 112 will also continuously add the identifier of the first CXL memory space requested to be released by the first application 111 to the first queue. At this time, when the first application 111 sends the first memory application request to the first LMD 112 again, the first LMD 112 directly selects the first CXL memory space from the CXL memory space in the usable state and allocates the first CXL memory space to the first application 111 for use. Since the first CXL memory space obtained by the first application 111 is cleared by the first LMD 112, the first application 111 does not need to perform the clearing operation, thereby eliminating the time overhead caused by the clearing operation.

[0194] After the first LMD 112 adds the identifier of the CXL memory space requested to be released by the application to the queue, it can return the first memory release response to the application without waiting for the CXL memory space to be cleared and the status update of the CXL memory space to be completed before sending the memory release response to the application, thereby realizing asynchronous recovery of the CXL memory space, reducing the risk of blocking the application operation due to the long time taken for clearing and status update when returning a response to the application after executing clearing and status update, speeding up the speed of returning a response to the application, and improving the efficiency of the communication and interaction between the first LMD 112 and the application. In addition, since it does not need to go through the memory management process of the operating system, it saves the complex software stack calls caused by the memory management of the operating system, and the process is relatively simple.

[0195] In addition, compared to the method in which the application interacts with FM 210 in the management device through the network to achieve memory recovery, since memory recovery is achieved through interaction between the application and LMD in the same computing device, the memory recovery process can be implemented through inter-process communication, thereby reducing the network communication overhead and communication delay caused to the computing device and the management device by cross-device communication through the network to achieve memory recovery, and further improving the efficiency of memory recovery.

[0196] In addition, distributing the memory recycling tasks applied in each computing device to the first LMD local to each computing device can reduce the burden on FM 210. The LMD of each computing device independently performs memory recycling and does not need to frequently communicate with FM 210, which can reduce the burden on FM 210 and improve overall efficiency and scalability.

[0197] The following uses S201 to S203 and S220 to S222 to illustrate the process of allocating CXL memory space from the perspective of the interaction between the LMD, the application and the FM 210. Optionally, the first CXL memory space requested to be released by the second application in S230 to S232 is allocated to the second application by the first LMD 112 by executing S220 to S222.

[0198] S201: The first LMD 112 generates a second memory allocation request, and the first LMD 112 sends the second memory allocation request to the FM 210 in the management device.

[0199] The second memory allocation request indicates that a CXL memory space in the CXL memory pool is allocated to the first computing device 110. The first LMD 112 sends the second memory allocation request to the FM 210, thereby notifying the FM 210 that the first computing device 110 needs to obtain memory, thereby triggering the FM 210 to perform a memory allocation process. The second memory allocation request may be a message in an encapsulation format specified by the CXL protocol.

[0200] In a possible implementation, the second memory allocation request includes a second configuration capacity. The second configuration capacity may also be referred to as the required capacity of the first computing device 110. The second configuration capacity indicates the capacity of the memory space that the first computing device 110 needs to obtain from the CXL memory pool. The second configuration capacity may also be understood as the capacity of the memory space that the FM 210 needs to allocate to the first computing device 110. For example, the first LMD 112 determines the second configuration capacity based on the required capacity of the CXL memory space of each application in the first computing device 110. The second configuration capacity is greater than or equal to the sum of the required capacities of each application in the first computing device 110. The first LMD 112 writes the second configuration capacity into the second memory allocation request. Since the second memory allocation request carries the second configuration capacity, it is convenient for the FM 210 to know how much CXL memory space needs to be allocated to the first computing device 110, which helps the capacity of the CXL memory space allocated by the FM 210 to meet the overall requirements of each application in the first computing device 110.

[0201] In a possible implementation, the second memory allocation request includes the identifier of the first computing device 110. For example, the first LMD 112 determines the identifier of the first computing device 110 where the first LMD 112 is located, and the first LMD 112 writes the identifier of the first computing device 110 into the second memory allocation request. Since the second memory allocation request includes the identifier of the first computing device 110, it is convenient for the FM 210 to know which first computing device 110 the CXL memory space is allocated to, so as to subsequently record the correspondence between the identifier of the first computing device 110 and the identifier of the CXL memory space based on the identifier of the first computing device 110. The identifier of the first computing device 110 is, for example, the IP address of the first computing device 110.

[0202] S202 : The FM 210 receives a second memory allocation request. In response to the second memory allocation request, the FM 210 determines a second CXL memory space from the CXL memory pool, and allocates the second CXL memory space to the first computing device 110 .

[0203] In some embodiments of determining the second CXL memory space, the FM 210 obtains the identifier of the first computing device 110 and the second configured capacity carried in the second memory allocation request. The FM 210 determines the second CXL memory space from the CXL memory pool based on the second configured capacity and the state of the CXL memory space in the CXL memory pool. For example, the FM 210 determines a CXL memory space in the CXL memory pool that is in an available state and has a capacity greater than or equal to the second configured capacity, to obtain the second CXL memory space.

[0204] Optionally, after FM 210 allocates the second CXL memory space to the first computing device 110, FM 210 establishes a second mapping relationship. The second mapping relationship includes an identifier of the second CXL memory space and an identifier of the first computing device 110. For example, the second mapping relationship includes an ID of the LD corresponding to the second CXL memory space and an IP address of the first computing device 110. The second mapping relationship may also be referred to as a binding relationship between the second CXL memory space and the first computing device 110. The second mapping relationship is used to identify that the second CXL memory space has been allocated to the first computing device 110. Then, when the second computing device 120 subsequently initiates a second memory allocation request to FM 210, FM 210 will not allocate the second CXL memory space to the second computing device 120 based on the second mapping relationship, thereby reducing the risk of allocating the same CXL memory space to two computing devices, resulting in a read / write conflict between the two computing devices on the same CXL memory space.

[0205] S203 , the FM 210 sends a second memory allocation response to the first LMD 112 .

[0206] In one possible implementation, the second memory allocation response includes an identifier of the CXL memory space. For example, the second memory allocation response includes a starting address and an offset of the CXL memory space. For another example, the second memory allocation response includes a UUID of the LD corresponding to the CXL memory space. For example, FM 210 writes the identifier of the allocated CXL memory space into the second memory allocation response, so that the second memory allocation response includes the identifier of the CXL memory space. FM 210 sends the identifier of the CXL memory space to the first LMD 112, so that the first LMD 112 can know which CXL memory space in the CXL memory pool is allocated to the first computing device 110, so that the first LMD 112 can perform further memory allocation based on the CXL memory space allocated to the first computing device 110.

[0207] The first LMD 112 receives the second memory allocation response. In a possible implementation, the first LMD 112 obtains the identifier of the second CXL memory space carried in the second memory allocation response. The first LMD 112 records the identifier of the second CXL memory space. For example, the identifier of the second CXL memory space includes the address and capacity of the second CXL memory space. The first LMD 112 records the address of the second CXL memory space so that the application accesses the second CXL memory space based on the second CXL memory space, and the first LMD 112 records the capacity of the second CXL memory space so that the CXL memory space is allocated to the application in combination with the capacity.

[0208] Optionally, the first LMD 112 maps the CXL memory space to a / dev / dax0.x file. The first LMD 112 may record the identifier of the CXL memory space.

[0209] After applying for the second CXL memory space, the first LMD 112 completes the initialization process, and the first LMD 112 can provide memory allocation services to the application, and the first LMD 112 can wait for the first memory allocation request from the application. The application can apply for the first CXL memory space from the first LMD 112 by sending the first memory allocation request to the first LMD 112.

[0210] Optionally, the first LMD 112 searches locally whether the second CXL memory space has been mapped to the / dev / dax0.x file based on the UUID of the second CXL memory space. If the second CXL memory space is not mapped to the / dev / dax0.x file, the first LMD 112 maps the second CXL memory space to the / dev / dax0.x file, so that the application can access the file through the mmap (Memory Map) function, thereby achieving memory access. The / dev / dax0.x file is a file representing a storage device. " / dev" is one of the directories used to represent device files under the Linux system. "dax" represents a direct access external memory device. "0.x" represents the number of the device, where "x" can be a number used to distinguish different direct access external memory devices. For example, the / dev / dax0.x file is / dev / dax0.0 or / dev / dax1.0, etc. The / dev / dax0.x file can be used to map the direct access external memory to the virtual address space of the application, so that the application can directly access the persistent memory area. Applications can use the mmap (Memory Map) function to map the / dev / dax0.x file to the application's address space, so that they can access this persistent memory like accessing ordinary memory, thus achieving memory access. mmap is a system call used in Unix, Linux, and other Unix-like systems. mmap is used to map a part of a file or device to the virtual address space of a process. By mapping the second CXL memory space to the / dev / dax0.x file, applications can use file read and write operations to apply for, release, and access the second CXL memory space, thereby simplifying the application and release process and improving efficiency.

[0211] S220 : The second application generates a first memory allocation request, and sends the first memory allocation request to the first LMD 112 .

[0212] For example, please refer to the attached Figure 7 , attached Figure 7FIG. 1 is a schematic diagram of an application applying for a first CXL memory space from a first LMD 112 according to an embodiment of the present application. Figure 7 APP 1, APP 2, and APP 3 are specific examples of the first application or the second application. APP 1 sends a first memory allocation request to the first LMD 112. The first memory allocation request includes 256MB, which is a specific example of the first configuration capacity. The first allocation request sent by APP 1 indicates that APP 1 applies for a CXL memory space with a capacity of 256MB. APP 2 sends a first memory allocation request to the first LMD 112. The first memory allocation request includes 512MB, which is a specific example of the first configuration capacity. The first allocation request sent by APP 2 indicates that APP 2 applies for a CXL memory space with a capacity of 512MB. APP 3 sends a first memory allocation request to the first LMD 112. The first memory allocation request includes 1GB, which is a specific example of the first configuration capacity. The first memory allocation request sent by APP 3 indicates that APP3 applies for a CXL memory space with a capacity of 1GB.

[0213] S221 : In response to the first memory allocation request, the first LMD 112 determines a first CXL memory space from the second CXL memory space, and allocates the first CXL memory space to the second application.

[0214] S222: The first LMD 112 sends a first memory allocation response to the second application.

[0215] For implementation details of S220, refer to S244. For implementation details of S221, refer to S245.

[0216] S220 to S222 above illustrate an example of the process of the first LMD 112 allocating CXL memory space to the application. Optionally, the CXL memory space allocated by the first LMD 112 to the application in S220 to S222 above is derived from the CXL memory space allocated by the FM 210 to the first LMD 112. The following example illustrates the process of the CXL memory space allocated by the FM 210 to the first LMD 112 from the perspective of the interaction between the FM 210 and the first LMD 112.

[0217] Optionally, Embodiment 1 also includes the following S261 to S263.

[0218] S261 , in response to the first CXL memory space satisfying the return condition, the first LMD 112 sends a second memory release request to the FM 210 .

[0219] The second memory release request indicates to return the first CXL memory space to the CXL memory pool. For example, the second memory release request includes an identifier of the first CXL memory space.

[0220] The return condition is used to trigger the return of the CXL memory space to the CXL memory pool. For example, the return condition is that the time period during which the first CXL memory space is not occupied exceeds a threshold. For another example, the return condition is that the time period during which the first CXL memory space is in an idle state exceeds a threshold.

[0221] S262 : The FM 210 deletes the mapping relationship between the first CXL memory space and the first computing device 110 in response to the second memory release request.

[0222] The effect of deleting the mapping relationship between the first CXL memory space and the first computing device 110 is equivalent to unbinding the first CXL memory space from the first computing device 110, so that from the perspective of the FM 210, the first CXL memory space is in an allocatable state. For example, after S262, if the second computing device 120 requests the FM 210 to allocate the CXL memory space, the FM 210 can allocate the first CXL memory space to the second computing device 120.

[0223] S263 : The first LMD 112 deletes the identifier of the first CXL memory space from the identifiers of the CXL memory spaces managed by the first LMD 112 .

[0224] The first LMD 112 deleting the identifier of the first CXL memory space is equivalent to indicating that the first computing device 110 no longer uses the first CXL memory space. Optionally, when the first computing device 110 needs to use the first CXL memory space again, the first LMD 112 may initiate a memory application request to the FM 210 again.

[0225] Through S261 to S263, the CXL memory space that has been allocated to the computing device is recycled back to the CXL memory pool, reducing the probability that the CXL memory space that has been allocated to the computing device is idle for a long time, resulting in other computing devices being unable to obtain the CXL memory space. This facilitates multiple computing devices in a computing device cluster to share the CXL memory pool, thereby improving the utilization rate of the CXL memory space in the CXL memory pool.

[0226] Reference Figure 8 , attached Figure 8 is a flowchart of a memory asynchronous recovery method provided by this embodiment, Figure 8 The memory asynchronous recycling method shown includes steps S510 to S560. Figure 8 The asynchronous memory recovery method shown is attached Figure 4 The memory management method shown is a further refinement of S234 and S237.

[0227] In step S510, the first LMD 112 determines whether the second queue is empty. When the second queue is not empty, the first LMD 112 executes step S520. When the second queue is empty, the first LMD 112 executes step S530. Since the second queue is not empty, it indicates that there is a first CXL memory space that has been cleared but the state has not been updated. The first LMD 112 can execute subsequent steps to update the state of the first CXL memory space to a usable state, so that the first CXL memory space can be allocated to the application that needs memory as soon as possible.

[0228] In step S520, the first LMD 112 determines whether the first LMD 112 is in an idle state; when the first LMD 112 is not in an idle state, the first LMD 112 executes step S530. When the first LMD 112 is in an idle state, the first LMD 112 executes step S540.

[0229] In step S530, the first LMD 112 determines whether the first queue is empty. When the first queue is empty, the first LMD 112 executes step S560. When the first queue is not empty, the first LMD 112 executes step S550.

[0230] In step S540, the first LMD 112 obtains the cleared identifier of the first CXL memory space from the second queue. The first LMD 112 updates the state of the first CXL memory space. The first LMD 112 updates the state of the first CXL memory space from the released state to the usable state. The first LMD 112 may return to step S510.

[0231] Memory recycling is achieved by updating the state of the cleared first CXL memory space from the released state to the usable state. Memory recycling refers to changing the unused memory to the usable state for subsequent allocation and use, so that other applications or other first computing devices 110 can reuse the memory.

[0232] Step S550, the first LMD 112 obtains the identifier of the first CXL memory space in the released state from the first queue; the first LMD 112 clears the first CXL memory space corresponding to the identifier of the first CXL memory space; the first LMD 112 adds the cleared identifier of the first CXL memory space to the second queue, so that the second queue is not empty, and returns to step S510.

[0233] Step S560: The first LMD 112 waits for a time period. When the waiting time reaches the time period, the process returns to step S510. The length of the time period can be preset according to the requirements. For example, the length of the time period is 5 seconds.

[0234] By waiting for a time period and then returning to step S510, the execution frequency of clearing the memory can be reduced, thereby reducing the occupation of processing resources.

[0235] In the memory management method provided in the above embodiment 1, the process of clearing the CXL memory space by the LMD is described. The process of clearing the CXL memory space by the FM 210 is described in the following embodiment 2. For the sake of simplicity, the following embodiment 2 focuses on the differences from embodiment 1. For the parts of embodiment 2 that are the same or similar to embodiment 1, please refer to embodiment 1.

[0236] Example 2

[0237] Attached Fig. 9 is a flowchart of another memory management method provided by an embodiment of the present application, Fig. 9 The memory management method shown replaces S234 in Embodiment 1 with S234'. In addition, Embodiment 2 also includes the following S251 to S252.

[0238] S251 : The first LMD 112 sends an identifier of the first CXL memory space to the FM 210 .

[0239] Regarding the manner in which the first LMD 112 determines the first CXL memory space, in a possible implementation, the first LMD 112 uses the CXL memory space requested to be released by the application as the first CXL memory space. For example, after the first LMD 112 receives the first memory release request of the application, the first LMD 112 obtains the identifier of the first CXL memory space carried in the first memory release request.

[0240] Optionally, the first LMD 112 sends the identifier of the first CXL memory space to the FM 210 in a message. For example, the first LMD 112 generates and sends a memory clear request to the FM 210, and the memory clear request is used to instruct to clear the first CXL memory space. The memory clear request carries the identifier of the first CXL memory space. Optionally, the memory clear request also includes an operator indicating to perform a clear operation.

[0241] S252: The FM 210 in the management device receives an identifier of the first CXL memory space.

[0242] Optionally, FM 210 obtains the identifier of the first CXL memory space and the operator carried in the memory clear request, determines the first CXL memory space based on the identifier of the first CXL memory space, and performs S234' on the first CXL memory space based on the operator indicating the clear operation.

[0243] S234', FM 210 clears the first CXL memory space to obtain a cleared first CXL memory space.

[0244] The main difference between S234' in Embodiment 2 and S234 in Embodiment 1 is the different execution subjects. In S234', the execution subject of clearing the parent first CXL memory space is replaced by FM 210. The technical details of clearing can be referred to S234 in Embodiment 1.

[0245] Optionally, Embodiment 2 also includes S253 to S254.

[0246] S253 , FM 210 adds (pushes) the identifier of the first CXL memory space to the third queue.

[0247] The third queue is used to store the identifier of the CXL memory space to be cleared. The difference between the third queue and the first queue is that the third queue can be stored in the memory space of the management device, while the first queue can be stored in the memory space of the computing device. Optionally, the third queue is created by FM 210 when it is powered on and initialized. Considering that it takes a long time to clear the CXL memory space, which usually takes seconds, since the identifier of the CXL memory space to be cleared is stored in the queue, FM 210 can perform other tasks (such as allocating CXL memory space to the computing device) after adding the identifier of the CXL memory space to be cleared to the queue, without having to wait for the clearing to be completed before performing other tasks, thereby reducing the risk of blocking the main task of FM 210 (the main task is, for example, FM 210 interacting with the computing device to allocate CXL memory space) caused by clearing the CXL memory space, realizing asynchronous processing of clearing, and reducing the overall delay of the management device in executing tasks.

[0248] Optionally, the third queue is a first-in-first-out queue. For example, after receiving the identifier of the first CXL memory space, FM 210 adds the identifier of the first CXL memory space to the tail of the third queue. Based on this, the identifiers of the CXL memory spaces in the third queue are arranged in order from early to late according to the time point when they are requested to be released. In other words, the earlier the identifier of a CXL memory space is sent to FM 210 by LMD, the closer the position of the identifier of the CXL memory space in the third queue is to the head of the queue.

[0249] For example, as attached Fig.10As shown in (a), after FM 210 receives the identifier of CXL memory space 3, the identifier of CXL memory space 6 and the identifier of CXL memory space 9 in sequence, FM 210 adds (pushes) the identifier of CXL memory space 3, the identifier of CXL memory space 6 and the identifier of CXL memory space 9 to the third queue in sequence, so that the identifier of CXL memory space 3 is at the head of the third queue, the identifier of CXL memory space 6 is at the second position in the third queue, and the identifier of CXL memory space 9 is at the third position in the third queue.

[0250] S254 , FM 210 obtains the identifier of the first CXL memory space from the third queue.

[0251] FM 210 obtains the identifier of the first CXL memory space from the third queue; FM 210 determines the first CXL memory space based on the identifier of the first CXL memory space. FM 210 clears the first CXL memory space. In a possible implementation, after FM 210 clears the first CXL memory space, FM 210 deletes the identifier of the first CXL memory space from the third queue.

[0252] Optionally, the third queue is a first-in-first-out queue. When the identifier of the first CXL memory space is at the head of the third queue, FM 210 obtains the identifier of the first CXL memory space from the third queue, and FM 210 clears the first CXL memory space corresponding to the identifier of the first CXL memory space. After FM 210 clears the first CXL memory space, FM 210 deletes the identifier of the first CXL memory space from the third queue, so that the identifier of the next CXL memory space after the first CXL memory space in the third queue is re-arranged at the head of the queue. By using a first-in-first-out queue to store the identifier of the CXL memory space to be cleared, the CXL memory space corresponding to the identifier sent first by the LMD can be cleared first, and then the CXL memory space released first by the application request can be recovered first, so that the CXL memory space released first by the application request can be used again as soon as possible.

[0253] In one possible implementation, FM 210 detects whether the third queue is empty every third time period; in response to detecting that the third queue is not empty and the identifier of the first CXL memory space is at the head of the third queue, FM 210 obtains the identifier of the first CXL memory space from the third queue, and clears the first CXL memory space based on the identifier of the first CXL memory space.

[0254] Since FM 210 uses the method of periodically clearing the CXL memory space stored in the queue, it is possible to clear the CXL memory space as timely as possible without having to determine in real time whether there is CXL memory space to be cleared, thereby helping to reduce the CPU occupancy rate caused by the real-time determination of whether there is CXL memory space to be cleared. The length of the third time period can be set according to demand. For example, the length of the third time period is 5 seconds.

[0255] Optionally, FM 210 performs S234' by executing a third inspection task, which includes detecting whether the third queue is empty every third time period, and clearing the CXL memory space corresponding to the identifier of the CXL memory space at the head of the third queue if the third queue is not empty.

[0256] Optionally, FM 210 uses a multi-threaded approach to parallelly execute the action of clearing the first CXL memory space and the action of interacting with the computing device through messages. For example, in a possible implementation, FM 210 includes a first thread and a second thread. The first thread of FM 210 is used to interact with the LMD in the computing device through messages. The second thread of FM 210 is used to clear the CXL memory space. For example, the second thread of FM 210 is used to execute the third inspection task. For example, FM 210 executes S252 and S255 through the first thread. FM 210 executes S234' through the second thread. The first thread and the second thread are, for example, two independent threads. Considering that clearing the CXL memory space takes a relatively long time, by having different threads respectively execute the actions of clearing the CXL memory space and interacting with the computing device through messages, the risk of the clearing action blocking the FM 210 from interacting with the computing device through messages is further reduced, and parallel execution of clearing the CXL memory space and interacting with the computing device through messages can be achieved.

[0257] For example, as attached Fig.10As shown in (a), in the process of executing the third inspection task, in response to the identifier of CXL memory space 3 in the third queue being at the head of the third queue, FM 210 obtains (pops) the identifier of CXL memory space 3 from the third queue. FM 210 clears CXL memory space 3. FM 210 deletes the identifier of CXL memory space 3 from the third queue, so that the identifier of CXL memory space 6 moves to the head of the third queue, and the identifier of CXL memory space 9 moves to the second position in the third queue. Thereafter, in response to the identifier of CXL memory space 6 in the third queue being at the head of the third queue, FM 210 obtains (pops) the identifier of CXL memory space 6 from the third queue. FM 210 clears CXL memory space 6. FM 210 deletes the identifier of CXL memory space 6 from the third queue, so that the identifier of CXL memory space 9 moves to the head of the third queue. Afterwards, in response to the identifier of CXL memory space 9 being at the head of the third queue, FM 210 pops the identifier of CXL memory space 9 from the third queue. FM 210 clears CXL memory space 9. FM 210 deletes the identifier of CXL memory space 9 from the third queue, making the third queue empty.

[0258] For example, while the first thread clears the first CXL memory space, the second thread receives and processes the memory allocation request and memory allocation response from the LMD in the computing device, and the second thread allocates the second CXL memory space to the computing device. Based on this, the FM 210 implements clearing the first CXL memory space in the background in a multi-threaded manner, reduces the risk that clearing the first CXL memory space affects the efficiency of message interaction between the FM 210 and the LMD in the computing device, and improves the overall efficiency of the FM 210 in clearing and interacting with the LMD in the computing device.

[0259] Optionally, the third patrol task is a background task of FM 210. For example, the foreground task of FM 210 is to interact with the computing device to allocate the second CXL memory space for the computing device and release the second CXL memory space. By executing the third patrol task in the background, FM 210 further reduces the impact of clearing the CXL memory space on the communication efficiency of FM 210 performing message interaction with the computing device in the foreground.

[0260] Optionally, Embodiment 2 also includes S255 to S256.

[0261] S255 , the FM 210 sends the cleared identifier of the first CXL memory space to the first LMD 112 .

[0262] Optionally, FM 210 sends the identifier of the first CXL memory space to FM 210 in a message. For example, FM 210 generates and sends a memory clear response to first LMD 112. The memory clear response is used to indicate that the first CXL memory space has been cleared. The memory clear response carries the identifier of the first CXL memory space.

[0263] S256 , the first LMD 112 receives the cleared identifier of the first CXL memory space from the FM 210 .

[0264] Based on the received identifier of the first CXL memory space, the first LMD 112 can know that the first CXL memory space has been cleared, and then the first LMD 112 can execute S237 to update the state of the first CXL memory space to a usable state. The process of the first LMD 112 updating the state of the first CXL memory space can refer to the first embodiment.

[0265] Optionally, Example 2 also includes S242 to S246, S261 to S263, S220 to S222 and S201 to S203, and specific details can be referred to Example 1.

[0266] Reference Fig.11 , attached Fig.11 is a flowchart of a memory asynchronous recovery method provided by this embodiment, Fig.11 The method shown includes steps S610 to S660. Fig.11 The memory asynchronous recycling method shown is a further refinement of the process executed by the LMD side in the memory asynchronous recycling process in Example 2. Steps S610 to S660 show that the LMD executes S251 and S237 in Example 2 in a patrol manner.

[0267] In step S610, the first LMD 112 determines whether the second queue is empty. When the second queue is not empty, the first LMD 112 executes step S620. When the second queue is empty, the first LMD 112 executes step S630.

[0268] In step S620, the first LMD 112 determines whether the first LMD 112 is in an idle state; when the first LMD 112 is not in an idle state, the first LMD 112 executes step S630. When the first LMD 112 is in an idle state, the first LMD 112 executes step S640.

[0269] In step S630, the first LMD 112 determines whether the first queue is empty. When the first queue is empty, the first LMD 112 executes step S660. When the first queue is not empty, the first LMD 112 executes step S650.

[0270] In step S640, the first LMD 112 obtains a cleared identifier of the first CXL memory space from the second queue. The first LMD 112 updates the state of the first CXL memory space. The first LMD 112 updates the state of the first CXL memory space from the released state to the usable state. The first LMD 112 may return to step S610.

[0271] Step S650 : The first LMD 112 obtains the identifier of the first CXL memory space in the first queue that is in the released state; the first LMD 112 sends the identifier of the first CXL memory space to the FM 210 , and the process returns to step S610 .

[0272] In step S660, the first LMD 112 waits for a time period. When the waiting time reaches the time period, the process returns to step S610. The length of the time period can be preset. For example, the length of the time period is 5 seconds.

[0273] Based on the attached Fig.11 In the asynchronous memory recovery method shown, before allocating the first CXL memory space to the application, the first LMD 112 sends the identifier of the first CXL memory space to the FM 210 so that the FM 210 clears the first CXL memory space, so that the first CXL memory space obtained by the application is the CXL memory space after clearing, so the application does not need to perform the clearing operation, which greatly reduces the time overhead. In addition, the LMD is responsible for managing the memory, so there is no need to go through the memory management process of the operating system kernel, thereby avoiding the complex software stack call caused by the operating system managing the memory, which is more flexible and simpler.

[0274] Reference Fig.12 , attached Fig.12 is a flowchart of a memory asynchronous recovery method provided by this embodiment, Fig.12 The method shown includes steps S710 to S750. Fig.12 The memory asynchronous recycling method shown is a further refinement of the process executed by FM 210 in the memory asynchronous recycling process of embodiment 2. Steps S710 to S750 show that FM 210 executes S253, S254, S234' and S255 in embodiment 2 in a patrol manner.

[0275] In step S710, FM 210 determines whether the third queue is empty. When the third queue is not empty, FM 210 executes step S720. When the third queue is empty, FM 210 executes step S730.

[0276] In step S720, FM 210 determines whether FM 210 is in an idle state; when FM 210 is not in an idle state, FM 210 executes step S750. When FM 210 is in an idle state, FM 210 executes step S730.

[0277] In step S730, FM 210 obtains an identifier of a first CXL memory space from the third queue, and FM 210 clears the first CXL memory space corresponding to the identifier of the first CXL memory space.

[0278] In step S740 , the FM 210 sends the cleared identifier of the first CXL memory space to the first LMD 112 .

[0279] In step S750, FM 210 waits for a time period, and when the waiting time reaches the time period, it returns to step S710.

[0280] Based on the attached Fig.12 In the method shown, the FM 210 clears the first CXL memory space before allocating it to the application, so that the first CXL memory space obtained by the application is the cleared CXL memory space. Therefore, the application does not need to perform a clearing operation, which greatly reduces time overhead.

[0281] Attached Fig.10 is a schematic diagram of a process flow of asynchronous memory recycling provided by an embodiment of the present application, and Fig.10 The process of asynchronous memory recycling is further explained by the interaction between LMD and FM 210. Fig.10 It includes the following S810 to S850.

[0282] S810: The first application 111 sends a first memory release request to the first LMD 112. The first message communication module 1121 in the first LMD 112 receives the first memory release request from the first application 111. The first message communication module 1121 in the first LMD 112 obtains the identifier of the first CXL memory space carried in the first memory release request. The first message communication module 1121 in the first LMD 112 adds the identifier of the first CXL memory space to the first queue. Fig.10 As shown, the first message communication module 1121 adds the identifier of CXL memory space 3, the identifier of CXL memory space 6 and the identifier of CXL memory space 9 to the first queue in sequence, so that the identifier of CXL memory space 3 is at the head of the first queue, the identifier of CXL memory space 6 is at the second position in the first queue, and the identifier of CXL memory space 9 is at the third position in the first queue.

[0283] S820, the first inspection module 1122 in the first LMD 112 detects that the first queue is not empty. The first inspection module 1122 in the first LMD 112 obtains the identifier of the first CXL memory space in the released state from the first queue. The first inspection module 1122 in the first LMD 112 sends the identifier of the first CXL memory space in the released state to the first message communication module 1121 in the first LMD 112. The first message communication module 1121 in the first LMD 112 sends the identifier of the first CXL memory space that needs to be asynchronously cleared (the first CXL memory space in the released state) to the second message communication module 2101 in the FM 210.

[0284] For example, as attached Fig.10 As shown, the first inspection module 1122 sequentially obtains (pops) the identifier of CXL memory space 3, the identifier of CXL memory space 6, and the identifier of CXL memory space 9 from the first queue. The first message communication module 1121 sequentially sends the identifier of CXL memory space 3, the identifier of CXL memory space 6, and the identifier of CXL memory space 9 to the second message communication module 2101 in FM 210.

[0285] S830: The second message communication module 2101 in the FM 210 receives the identifier of the asynchronously cleared first CXL memory space from the first LMD 112. The second message communication module 2101 in the FM 210 adds the identifier of the first CXL memory space to the third queue.

[0286] For example, as attached Fig.10 As shown, the second message communication module 2101 in FM 210 sequentially adds (pushes) the identifier of CXL memory space 3, the identifier of CXL memory space 6 and the identifier of CXL memory space 9 to the third queue, so that the identifier of CXL memory space 3 is at the head of the third queue, the identifier of CXL memory space 6 is at the second position in the third queue, and the identifier of CXL memory space 9 is at the third position in the third queue.

[0287] S840, the second inspection module 2102 in the FM 210 detects that the third queue is not empty. The second inspection module 2102 in the FM 210 obtains an identifier of a first CXL memory space from the third queue. The second inspection module 2102 in the FM 210 clears the first CXL memory space corresponding to the identifier of the first CXL memory space. The second inspection module 2102 in the FM 210 sends the cleared identifier of the first CXL memory space to the first LMD 112.

[0288] S850: The first message communication module 1121 of the first LMD 112 receives the cleared identifier of the first CXL memory space sent by the FM 210, and the first message communication module 1121 of the first LMD 112 adds the cleared identifier of the first CXL memory space to the second queue.

[0289] Attached Fig.10 The subsequent process of S850 in the embodiment is Figure 8 The subsequent process of S510 in the embodiment is consistent.

[0290] Based on the attached Fig.10 In the method shown, the FM 210 clears the CXL memory space before allocating the CXL memory space to the application, so that the CXL memory space obtained by the application is the cleared CXL memory space. Therefore, the application does not need to perform the clearing operation, which greatly reduces the time overhead.

[0291] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0292] A refers to B, which means that A is the same as B or A is a simple variant of B.

[0293] In the embodiments of the present application, unless otherwise specified, “at least one” means one or more, and “plurality” means two or more.

[0294] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in accordance with the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. Available media can be magnetic media, (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state hard disk Solid State Disk (SSD)), etc.

[0295] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, characterized in that: Applied to a computing device, the computing device includes a space management process LMD and a first application, the method includes: The LMD clears the first CXL memory space to obtain a cleared first CXL memory space, where the first CXL memory space is a CXL memory space in a CXL memory pool allocated to the computing device; The first application sends a first memory allocation request to the LMD, where the first memory allocation request indicates allocating CXL memory space in the CXL memory pool for the first application; In response to the first memory allocation request, the LMD allocates the cleared first CXL memory space to the first application, and sends a first memory allocation response to the first application, where the first memory allocation response includes an identifier of the cleared first CXL memory space.

2. The method according to claim 1, characterized in that The LMD clears the first CXL memory space, including: The LMD adds the identifier of the first CXL memory space to the first queue; The LMD obtains the identifier of the first CXL memory space from the first queue; The LMD clears the first CXL memory space based on the identifier of the first CXL memory space.

3. The method according to claim 2, characterized in that The computing device further includes a second application. Before the LMD obtains the identifier of the first CXL memory space from the first queue, the method further includes: The second application sends a first memory release request to the LMD, where the first memory release request includes an identifier of the first CXL memory space; The LMD sends a first memory release response to the second application, where the first memory release response indicates that the first CXL memory space is released successfully.

4. The method according to claim 2 or 3, characterized in that: The LMD obtains the identifier of the first CXL memory space from the first queue, including: The LMD detects whether the first queue is empty every first time period; In response to detecting that the first queue is not empty, the LMD obtains the identifier of the first CXL memory space from the first queue.

5. The method according to claim 1, characterized in that The LMD allocating the cleared first CXL memory space to the first application includes: The LMD queries, based on the identifier of the first CXL space, a state of the first CXL memory space; In response to the first CXL memory space being in an available state, the LMD allocates the cleared first CXL memory space to the first application.

6. The method according to claim 5, characterized in that Before the LMD allocates the cleared first CXL memory space to the first application, the method further includes: The LMD adds the identifier of the first CXL memory space to the second queue; The LMD obtains the identifier of the first CXL memory space from the second queue; The LMD updates the state of the first CXL memory space to a usable state.

7. The method according to claim 6, characterized in that The LMD obtains the identifier of the first CXL memory space from the second queue, including: The LMD detects whether the second queue is empty every second time period; In response to detecting that the second queue is not empty, the LMD obtains the identifier of the first CXL memory space from the second queue.

8. The method according to claim 6, characterized in that Before the LMD updates the state of the first CXL memory space to a usable state, the method further includes: The LMD locks the state of the first CXL memory space; After the LMD updates the state of the first CXL memory space to a usable state, the method further includes: The LMD unlocks the state of the first CXL memory space.

9. The method according to claim 1, characterized in that: Before the LMD clears the first CXL memory space, the method further includes: The LMD sends a second memory allocation request to the fabric management FM of the management device, wherein the second memory allocation request indicates allocating a CXL memory space in the CXL memory pool to the computing device; The LMD receives a second memory allocation response from the FM, the second memory allocation response including an identifier of a second CXL memory space in the CXL memory pool; The LMD determines the first CXL memory space from the second CXL memory space, allocates the first CXL memory space to the first application, and sends an identifier of the first CXL memory space to the first application.

10. The method according to claim 1, characterized in that The method further comprises: In response to the first CXL memory space satisfying a return condition, the LMD sending a second memory release request to the FM, wherein the second memory release request indicates returning the first CXL memory space to the CXL memory pool; The LMD deletes the identifier of the first CXL memory space from identifiers of CXL memory spaces managed by the LMD.

11. A memory management method, characterized in that: Applied to a memory management system, the memory management system includes a management device, a computing device and a CXL memory pool, the management device includes a structure management FM, the computing device includes a space management process LMD and an application, the method includes: The LMD sends a second memory allocation request to the FM, wherein the second memory allocation request indicates allocating a CXL memory space in the CXL memory pool to the computing device; In response to the second memory allocation request, the FM determines a second CXL memory space from the CXL memory pool, allocates the second CXL memory space to the computing device, and sends an identifier of the second CXL memory space to the LMD; The LMD clears the first CXL memory space in the second CXL memory space to obtain the cleared first CXL memory space; The application sends a first memory allocation request to the LMD, where the first memory allocation request indicates allocation of CXL memory space in the CXL memory pool for the application; In response to the first memory allocation request, the LMD allocates the cleared first CXL memory space to the application, and sends an identifier of the cleared first CXL memory space to the application.

12. A memory management method, characterized in that: Applied to a management device, the management device includes a structure management FM, the management device is connected to a computing device and a CXL memory pool respectively, the computing device includes a space management process LMD, the method includes: The FM receives an identifier of a first CXL memory space from the LMD, the first CXL memory space being a CXL memory space in the CXL memory pool allocated to the computing device; The FM clears the first CXL memory space to obtain the cleared first CXL memory space; The FM sends the cleared identifier of the first CXL memory space to the LMD.

13. The method according to claim 12, characterized in that The FM clears the first CXL memory space, including: The FM adds the identifier of the first CXL memory space to a third queue; The FM obtains the identifier of the first CXL memory space from the third queue; The FM clears the first CXL memory space based on the identifier of the first CXL memory space.

14. The method according to claim 13, characterized in that The FM obtains the identifier of the first CXL memory space from the third queue, including: The FM detects whether the third queue is empty every third time period; In response to detecting that the third queue is not empty, the FM obtains the identifier of the first CXL memory space from the third queue.

15. The method according to any one of claims 12 to 14, characterized in that The FM includes a first thread and a second thread. The first thread of the FM is used to receive an identifier of a first CXL memory space from the LMD and send a cleared identifier of the first CXL memory space to the LMD. The second thread of the FM is used to clear the first CXL memory space.

16. A memory management method, characterized in that: Applied to a memory management system, the memory management system includes a management device, a computing device and a CXL memory pool, the management device includes a structure management FM, the computing device includes a space management process LMD and a first application, the method includes: The FM clears the first CXL memory space in the CXL memory pool to obtain the cleared first CXL memory space; The FM sends the cleared identifier of the first CXL memory space to the LMD; The first application sends a first memory allocation request to the LMD, where the first memory allocation request indicates allocating CXL memory space in the CXL memory pool for the first application; In response to the first memory allocation request, the LMD allocates the cleared first CXL memory space to the first application based on the identifier of the first CXL memory space, and sends a first memory allocation response to the first application, where the first memory allocation response includes the identifier of the first CXL memory space.

17. A computing device, characterized in that: The computing device includes: an LMD and a plurality of applications, The LMD is used to clear the first CXL memory space to obtain the cleared first CXL memory space, where the first CXL memory space is the CXL memory space in the CXL memory pool allocated to the computing device; A first application among the multiple applications is used to send a first memory allocation request to the LMD, where the first memory allocation request indicates allocation of CXL memory space in the CXL memory pool for the first application; The LMD is configured to allocate the cleared first CXL memory space to the first application in response to the first memory allocation request, and send a first memory allocation response to the first application, where the first memory allocation response includes an identifier of the cleared first CXL memory space.

18. A management device, characterized in that: The management device comprises: a structure management FM, wherein the FM of the management device is used to connect with a computing device and a CXL memory pool respectively, and the FM is used to execute the method according to any one of claims 12-15.

19. A memory management system, characterized in that: The memory management system comprises a management device, a computing device and a CXL memory pool, the computing device is connected to the management device, the management device is connected to the CXL memory pool, and the memory management system is used to execute the method according to claim 11 or 16.

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