Method and apparatus for implementing clock stretching based on integrated circuit bus IIC

Abstract

The application provides a clock stretching implementation method and device based on an integrated circuit bus IIC. The application adds a clock stretching indication signal line between an IIC master device and a control device in a communication control system. The IIC master device sends a first notification to the control device through the clock stretching indication signal line to start clock stretching, so that the control device maintains a low voltage state of a slave device SCL pin, and suspends data transmission. In the case where a second notification sent by the IIC master device to the control device through the clock stretching indication signal line is not received to cancel the clock stretching, even if a specified period of an SCL clock cycle ends, the slave device SCL pin connected to the slave device SCL is not in a high resistance state as in the conventional IIC data transmission mechanism, but is maintained in a low voltage state until the second notification is received, breaking the limitation of the current data transmission mechanism and realizing the clock stretching mechanism triggered by the IIC master device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a clock stretching implementation method and device based on an integrated circuit bus IIC. BACKGROUND

[0002] Clock stretching is an important mechanism in the IIC (Inter-Integrated Circuit) communication protocol, which means that the IIC master device or the IIC slave device suspends data transmission by keeping the SCL signal line at a low level until the SCL (Serial Clock Line) is converted from a low level to a high level to resume data transmission. For example, during data transmission between the IIC master device and the IIC slave device, the IIC master device receives a task with higher priority, at this time, the IIC master device can control the SCL pin connected with the IIC slave device to be low, so that the SCL signal line is maintained at a low level, to preferentially process the task with higher priority. After completing the task with higher priority, the IIC master device can control the SCL pin connected with the IIC slave device to be in a high impedance state, to resume data transmission with the IIC slave device.

[0003] In actual application, in order to be able to more flexibly apply the IIC bus, the IIC master device is usually communicated with the IIC slave device through a control device. In the case that the SCL between the IIC master device and the IIC slave device is not directly connected, the clock stretching mechanism in the IIC communication protocol cannot be implemented. SUMMARY

[0004] Therefore, the present application provides a communication control system, method and device based on an integrated circuit bus IIC, to implement the clock stretching mechanism in the IIC communication protocol in the case that the SCL between the IIC master device and the IIC slave device is not directly connected through the control device.

[0005] The technical scheme provided by the present application is as follows:

[0006] According to the embodiment of the first aspect of the present application, a clock stretching implementation method based on an integrated circuit bus IIC is provided, which is applied to an IIC master device in a communication control system; the communication control system further includes an IIC slave device connected with the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock stretching indication signal line is further connected between the IIC master device and the control device; the method comprises the following steps:

[0007] If it is determined to start the clock stretching, a first notification is sent to the control device through the clock stretching indication signal line, so that the control device maintains the pin connected to the slave SCL at low level based on the first notification; wherein when the control device receives a falling edge of the SCL clock signal, the control device controls the pin connected to the slave SCL to be at low level and controls the pin connected to the master SCL to be at low level;

[0008] If it is determined to cancel the clock stretching, a second notification is sent to the control device through the clock stretching indication signal line, so that the control device controls the pin connected to the slave SCL to be in high impedance state based on the second notification.

[0009] Optionally, the control device comprises a slave SCL control component; the slave SCL control component is configured to control the state of the pin connected to the slave SCL of the control device.

[0010] The IIC master is connected to the slave SCL control component through the clock stretching indication signal line.

[0011] Optionally, the pin connected to the master SCL of the IIC master is in high impedance state after the IIC master determines to cancel the clock stretching.

[0012] Optionally, the first notification is sent in a specified period of an SCL clock period after sending the falling edge of the SCL clock signal, and the SCL clock period is a set time length based on the falling edge of the SCL clock signal.

[0013] Optionally, the SCL clock period comprises an SCL low period and an SCL high period, the SCL high period comprises a data transmission period, and the specified period comprises:

[0014] the SCL low period and the SCL high period except the data transmission period.

[0015] According to the embodiments of the second aspect of the present application, a clock stretching implementation method based on an integrated circuit bus IIC is provided, which is applied to a control device in a communication control system; the communication control system further comprises an IIC master and an IIC slave connected to the IIC master, the control device is connected between the IIC master and the IIC slave, and a clock stretching indication signal line is further connected between the control device and the IIC master; the method comprises:

[0016] If the first notification sent by the IIC master device is received through the clock extension indication signal line between the IIC master device and the control device, the pin of the control device connected with the slave SCL is maintained in a low state based on the first notification; wherein, when the control device receives a falling edge of the SCL clock signal, the control device controls the pin connected with the slave SCL to be in a low state and controls the pin connected with the master SCL to be in a low state;

[0017] If the second notification sent by the IIC master device is received through the clock extension indication signal line between the IIC master device and the control device, the pin of the control device connected with the slave SCL is controlled to be in a high impedance state based on the second notification;

[0018] If it is detected that the level of the slave SCL is converted from low to high, the pin of the control device connected with the master SCL is controlled to be in a high impedance state.

[0019] Optionally, the control device comprises a slave SCL control component; the slave SCL control component is configured to control the state of the pin of the control device connected with the slave SCL.

[0020] The slave SCL control component is connected with the IIC master device through the clock extension indication signal line.

[0021] Optionally, the first notification is sent in a specified period of a SCL clock cycle after a falling edge of the SCL clock signal sent by the IIC master device; the SCL clock cycle is a SCL clock cycle starting from a recently received falling edge of the SCL clock signal sent by the master SCL.

[0022] Optionally, the SCL clock cycle comprises a SCL low period and a SCL high period, the SCL high period comprises a data transmission period, and the specified period comprises:

[0023] the SCL low period and the SCL high period except the data transmission period.

[0024] Optionally, the first notification is sent in a SCL low period of a SCL clock cycle after a falling edge of the SCL clock signal sent by the IIC master device, and the method further comprises:

[0025] If the second notification sent by the IIC master through the clock extension indication signal line is received, it is checked whether the current time is the time before the end of the SCL low period in the SCL clock cycle; if yes, the SCL clock cycle is ended, and if no, the operation of controlling the pin connected with the slave SCL on the control device to be in the high resistance state based on the second notification is continuously performed.

[0026] Optionally, the first notification is sent in the SCL low period of the SCL clock cycle after the SCL clock signal falling edge sent by the IIC master, and the method further comprises:

[0027] If the second notification sent by the IIC master through the clock extension indication signal line is not received at the end of the SCL low period in the SCL clock cycle, the pin connected with the slave SCL on the control device is continuously maintained in the low state.

[0028] Optionally, the first notification is sent in the SCL high period of the SCL clock cycle except the data transmission period after the SCL clock signal falling edge sent by the IIC master, and the method further comprises:

[0029] The SCL clock cycle is ended, a new SCL clock cycle is started, if the second notification sent by the IIC master through the clock extension indication signal line is received, it is checked whether the current time is the time before the end of the SCL low period in the new SCL clock cycle; if yes, the new SCL clock cycle is ended, and if no, the operation of controlling the pin connected with the slave SCL on the control device to be in the high resistance state based on the second notification is continuously performed; the pin connected with the master SCL on the IIC master is in the low state after the IIC master determines to start the clock extension.

[0030] Optionally, the first notification is sent in the SCL high period of the SCL clock cycle except the data transmission period after the SCL clock signal falling edge sent by the IIC master, and the method further comprises:

[0031] The SCL clock cycle is ended, a new SCL clock cycle is started, if the second notification sent by the IIC master through the clock extension indication signal line is not received at the end of the SCL low period in the new SCL clock cycle, the pin connected with the slave SCL on the control device is continuously maintained in the low state; the pin connected with the master SCL on the IIC master is in the low state after the IIC master determines to start the clock extension.

[0032] According to an embodiment of the third aspect of the present application, an IIC clock stretching implementation device based on an integrated circuit bus (IIC) is provided, which is applied to an IIC master in a communication control system; the communication control system further comprises an IIC slave connected with the IIC master, and a control device connected between the IIC master and the IIC slave, and a clock stretching indication signal line is further connected between the IIC master and the control device; the device comprises:

[0033] an opening unit, configured to, if it is determined to open the clock stretching, send a first notification to the control device through the clock stretching indication signal line, so that the control device maintains a pin connected with the slave SCL on the control device in a low state based on the first notification; wherein, when the control device receives a falling edge of an SCL clock signal, the control device controls the pin connected with the slave SCL on the control device to be in a low state and controls a pin connected with the master SCL on the control device to be in a low state;

[0034] a canceling unit, configured to, if it is determined to cancel the clock stretching, send a second notification to the control device through the clock stretching indication signal line, so that the control device controls a pin connected with the slave SCL on the control device to be in a high-impedance state based on the second notification.

[0035] According to an embodiment of the fourth aspect of the present application, an IIC clock stretching implementation device based on an integrated circuit bus (IIC) is provided, which is applied to a control device in a communication control system; the communication control system further comprises an IIC master and an IIC slave connected with the IIC master, and the control device is connected between the IIC master and the IIC slave, and a clock stretching indication signal line is further connected between the control device and the IIC master; the device comprises:

[0036] a maintaining unit, configured to, if a first notification sent by the IIC master is received through the clock stretching indication signal line between the IIC master and the control device, maintain a pin connected with the slave SCL on the control device in a low state based on the first notification; wherein, when the control device receives a falling edge of an SCL clock signal, the control device controls the pin connected with the slave SCL on the control device to be in a low state and controls a pin connected with the master SCL on the control device to be in a low state;

[0037] The control unit is configured to control the pin connected to the slave SCL on the control device to be in a high-impedance state based on a second notification sent by the IIC master if the second notification is received through the clock stretching indication signal line between the IIC master and the control device; and control the pin connected to the master SCL on the control device to be in a high-impedance state if it is detected that the level of the slave SCL changes from low to high.

[0038] According to the embodiment of the fifth aspect of the present application, an IIC master is provided, which is an IIC master in a communication control system; the communication control system further includes an IIC slave connected to the IIC master, and a control device connected between the IIC master and the IIC slave, and a clock stretching indication signal line is further connected between the IIC master and the control device; the IIC master is configured to perform the method according to the first aspect.

[0039] According to the embodiment of the sixth aspect of the present application, a control device is provided, which is a control device in a communication control system; the communication control system further includes an IIC master and an IIC slave connected to the IIC master; the control device is connected between the IIC master and the IIC slave, and a clock stretching indication signal line is further connected between the IIC master and the control device; the control device includes:

[0040] a frequency counter, which is in communication connection with the slave SCL control module, and is configured to count at a preset frequency and trigger the slave SCL control module to control the pin connected to the slave SCL on the control device to be in a high-impedance state when counting to the end of a specified period;

[0041] a slave SCL control module, which is in communication connection with the frequency counter and the master-slave SCL control module, and is connected to the IIC slave through the slave SCL and connected to the IIC master through the clock stretching indication signal line; the slave SCL control module is configured to control the state of the pin connected to the slave SCL on the control device according to signals sent by the master-slave SCL control module, the frequency counter and the clock stretching indication signal line;

[0042] a first edge detection module, which is connected to the IIC master through the master SCL and in communication connection with the master-slave SCL control module; the first edge detection module is configured to detect the level change of the master SCL;

[0043] The master-slave SCL control module is connected in communication with the first edge detection module, the slave device SCL control module and the second edge detection module, and is connected with the IIC master device through the master device SCL, and the master-slave SCL control module is configured to control the state of the pin connected with the master device SCL on the control device according to the detection results of the first edge detection module and the second edge detection module, and control the slave device SCL control module, so that the slave device SCL control module controls the state of the pin connected with the slave device SCL on the control device.

[0044] The second edge detection module is connected with the IIC slave device through the slave device SCL, and is connected in communication with the master-slave SCL control module, and the second edge detection module is configured to detect the level conversion of the slave device SCL.

[0045] From the above technical solutions, it can be seen that the present application adds a clock extension indication signal line between the IIC master device and the control device in the communication control system. When the IIC master device determines to start clock extension, it sends a first notification to the control device through the clock extension indication signal line, so that the control device maintains the slave device SCL pin connected with the slave device SCL on the control device in a low state based on the first notification. In the case where no clock extension invalidation indication signal is received, even if the specified period of the SCL clock cycle ends, the slave device SCL pin connected with the slave device SCL will not be controlled to be in a high resistance state as in the conventional data transmission mechanism, but will always be maintained in a low state. The slave device SCL pin connected with the slave device SCL on the control device is in a low state to suspend data transmission, breaking the limitation of the current IIC data transmission mechanism. Until the master device sends a second notification to the control device through the clock extension indication signal line to cancel the clock extension, the slave device SCL pin connected with the slave device SCL is controlled to be in a high resistance state, and the data transmission is restored. In the case where there is no direct connection between the SCL of the IIC master device and the IIC slave device, the clock extension mechanism in the IIC communication protocol is realized. BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0047] Figure 1 The communication control system structure schematic diagram provided for the embodiment of the present application;

[0048] Figure 2 The flow chart of a clock extension implementation method based on an integrated circuit bus IIC provided for the embodiment of the present application;

[0049] Figure 3Another flow chart of a clock stretching implementation method based on an integrated circuit bus IIC provided in an embodiment of the present application;

[0050] Figure 4 A specific module schematic diagram of a communication control system provided in an embodiment of the present application;

[0051] Figure 5 A specific structure schematic diagram of a communication control system of a multi-IIC host provided in an embodiment of the present application;

[0052] Figure 6 Another specific module schematic diagram of a communication control system provided in an embodiment of the present application;

[0053] Figure 7 A structure schematic diagram of a clock stretching implementation device based on an integrated circuit bus IIC provided in an embodiment of the present application;

[0054] Figure 8 Another structure schematic diagram of a clock stretching implementation device based on an integrated circuit bus IIC provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the technical solution provided in the embodiments of the present application better understood by those skilled in the art, and make the above-mentioned purposes, features and advantages of the embodiments of the present application more apparent and easy to understand, the technical solution in the embodiments of the present application is further described in detail below with reference to the drawings.

[0056] First, the communication control system applied in the embodiments of the present application is described in combination with Figure 1 The communication control system applied in the embodiments of the present application is described in combination with

[0057] Please refer to Figure 1 , Figure 1 A structure schematic diagram of a communication control system provided in an embodiment of the present application.

[0058] As shown in Figure 1 , the communication control system includes an integrated circuit bus (IIC: Inter-Integrated Circuit) master device, an IIC slave device connected with the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock stretching indication signal line is further connected between the IIC master device and the control device.

[0059] In the embodiment, the IIC master device and the control device are connected through a master device serial clock line (SCL ：and a clock extension indication signal line; the IIC slave device is connected with the control device through the slave device SCL; the IIC master device is connected with the IIC slave device through a serial data line (SDA: Serial Data Line).

[0060] In the embodiment, the control device can be a complex programmable logic device (CPLD: Complex Programmable Logic Device) or a field-programmable gate array (FPGA: Field-Programmable Gate Array), which is not limited in the application.

[0061] As an embodiment, the control device comprises a control component for controlling the slave device SCL; the control component is used for controlling the state of the slave device SCL pin;

[0062] The IIC master device is connected with the control component through the clock extension indication signal line.

[0063] Based on the above control communication control system, the application provides a clock extension implementation method based on an integrated circuit bus IIC, to realize the clock extension of the host.

[0064] Please refer to Figure 2 , Figure 2 The clock extension implementation method based on the integrated circuit bus IIC provided in the embodiment of the application is shown in a flowchart.

[0065] As Figure 2 shown, the method is applied to an IIC master device in a communication control system, and the method can comprise the following steps:

[0066] In step 201, if it is determined to start the clock extension, a first notification is sent to the control device through a clock extension indication signal line, so that the control device maintains the pin connected with the slave device SCL on the control device in a low voltage state based on the first notification.

[0067] In the embodiment, when the control device receives the falling edge of the SCL clock signal, the pin connected with the slave device SCL on the control device is controlled to be in a low voltage state, and the pin connected with the master device SCL on the control device is controlled to be in a low voltage state.

[0068] In the embodiment, the SCL clock signal comprises a low voltage signal and a high voltage signal, the conversion from high voltage to low voltage is called the falling edge of the clock signal, the conversion from low voltage to high voltage is called the rising edge of the clock signal, and the SCL clock period is a set time length based on the falling edge of the SCL clock signal, and one SCL clock period is used for the transmission of 1-bit data.

[0069] In the embodiment, one SCL clock cycle includes an SCL low period and an SCL high period, the data on the serial data line SDA changes in the SCL low period, and the data is read starting from the rising edge of the clock signal, i.e., the rising edge generated when the SCL low period is converted into the SCL high period. The period in which the data reading process belongs to can be recorded as a data transmission period, and the data transmission period is part of the SCL high period.

[0070] As an embodiment, one SCL clock cycle can include a first half low period and a second half high period, and the application does not limit this.

[0071] The falling edge of the SCL clock signal can be the falling edge caused by the SCL low period in a normal SCL clock cycle, or the falling edge caused by the control device controlling the pin connected to the SCL of the slave device to be in a low state based on the first notification. The two cases will be described in detail in the following embodiments, and will not be described here.

[0072] As an embodiment, the first notification is sent in a specified period of the SCL clock cycle after the falling edge of the SCL clock signal. The specified period can include the SCL low period and the SCL high period except the data transmission period.

[0073] For the two different periods of sending the first notification, the two cases will be described in detail in the following embodiments, and will not be described here.

[0074] In step 202, if it is determined to cancel the clock extension, a second notification is sent to the control device through the clock extension indication signal line, so that the control device controls the pin connected to the SCL of the slave device on the control device to be in a high impedance state based on the second notification.

[0075] In the embodiment, before receiving the second notification, the control device will always maintain the pin connected to the SCL of the slave device on the control device to be in a low state. Since no rising edge and falling edge are generated, the communication between the IIC master device and the IIC slave device is suspended.

[0076] In the case where the IIC master device determines to cancel the clock extension, the second notification for indicating the cancellation of the clock extension can be sent through the clock extension indication signal line. After receiving the second notification, the control device can control the pin connected to the SCL of the slave device on the control device to be in a high impedance state. At this time, the slave device SCL is converted from low to high, a rising edge is generated, the data on the SDA line is read, and the communication between the IIC master device and the IIC slave device is restored.

[0077] As an embodiment, the pin connected with the master SCL on the IIC master is in high impedance state after the IIC master determines to cancel the clock stretching.

[0078] At the same time when the IIC master determines to cancel the clock stretching, the pin connected with the master SCL on the IIC master can be controlled to be in high impedance state to wait for the start of the next SCL clock cycle.

[0079] The specific process of the master starting the clock stretching will be described in detail in the specific embodiments below, and will not be repeated here.

[0080] Thus, the description of the flow of Figure 2 is ended.

[0081] Please refer to Figure 3 , Figure 3 Another flow chart of an implementation method of clock stretching based on an integrated circuit bus IIC provided by the embodiments of the present application.

[0082] As shown in Figure 3 , the method is applied to a control device in a communication control system, and the method can include the following steps:

[0083] Step 301, if a first notification sent by an IIC master is received through a clock stretching indication signal line between the control device and the IIC master, then based on the first notification, the pin connected with a slave SCL on the control device is maintained in a low voltage state.

[0084] Among them, when the control device receives a falling edge of the SCL clock signal, the pin connected with the slave SCL on the control device is controlled to be in a low voltage state, and the pin connected with the master SCL on the control device is controlled to be in a low voltage state.

[0085] Step 302, if a second notification sent by the IIC master is received through the clock stretching indication signal line between the control device and the IIC master, then based on the second notification, the pin connected with the slave SCL on the control device is controlled to be in a high impedance state.

[0086] Step 303, if it is detected that the level of the slave SCL is converted from low voltage to high voltage, then the pin connected with the master SCL on the control device is controlled to be in a high impedance state.

[0087] It is easy to understand that Figure 3 the method in is a method described with the control device as the execution subject, and the overall flow is similar to that of Figure 2 .

[0088] In the embodiment, the first notification is sent in a specified period of a SCL clock cycle after the SCL clock signal falling edge sent by the IIC master device; the SCL clock cycle is one SCL clock cycle starting from the SCL clock signal falling edge of the latest received master device SCL sending.

[0089] The SCL clock cycle includes an SCL low period and an SCL high period, the SCL high period includes a data transmission period, and the specified period can include:

[0090] the SCL low period and the SCL high period except the data transmission period.

[0091] In the embodiment, the sending time of the first notification can include the SCL low period and the SCL high period except the data transmission period.

[0092] As an embodiment, the first notification is sent in the SCL low period of a SCL clock cycle after the SCL clock signal falling edge sent by the IIC master device, and the method proposed in the embodiment can further include:

[0093] If the second notification sent by the IIC master device through the clock extension indication signal line is received, it is checked whether the current time is a time before the end of the SCL low period in the SCL clock cycle; if yes, the SCL clock cycle is ended, and if no, the operation of controlling the pin connected to the slave SCL on the control device to be in a high resistance state based on the second notification is continued.

[0094] If the second notification sent by the IIC master device through the clock extension indication signal line is not received at the end of the SCL low period in the SCL clock cycle, the pin connected to the slave SCL on the control device is continued to be maintained in a low state.

[0095] In the embodiment, in the SCL low period, the SDA line has completed the level conversion, and the level of the SDA line is converted to the level signal required for transmission in the current SCL clock cycle. When the next rising edge appears, the level signal on the SDA line can be transmitted.

[0096] If the second notification is received before the end of the SCL low period in the SCL clock cycle, it indicates that the clock extension has been cancelled before the end of the SCL low period. Since the master SCL and the slave SCL are both in a low state in the conventional signal transmission mechanism in the SCL low period, this case is equivalent to not performing clock extension. At this time, the data transmission can be normally performed according to the flow of the conventional mechanism, and the record of the length of the current clock cycle is ended.

[0097] If the second notification is not received before the end of the SCL low period in the SCL clock cycle, it indicates that the clock stretching is still continuing at the end of the SCL low period, and if the conventional mechanism is followed, the pin connected to the slave SCL on the control device needs to be adjusted to a high-impedance state according to the rising edge generated to perform data transmission. However, since the clock stretching is still continuing in the scheme proposed in the embodiment, the pin connected to the slave SCL on the control device is maintained in a low state to suspend the communication between the IIC master and the IIC slave, that is, to suspend the transmission of the level signal in the current SCL clock cycle, until the second notification sent by the IIC master through the clock stretching indication signal line is received, and then the pin connected to the slave SCL on the control device is controlled to a high-impedance state to restore the communication between the IIC master and the IIC slave and complete the transmission of the level signal in the current SCL clock cycle.

[0098] It can be seen that the method proposed in the embodiment breaks the limitation of the conventional IIC transmission mechanism. At the end of the SCL low period, the pin connected to the slave SCL on the control device is not directly adjusted to a high-impedance state according to the conventional transmission mechanism to perform data transmission according to the rising edge generated, but is controlled to a high-impedance state to restore the communication between the IIC master and the IIC slave and complete the transmission of the level signal in the current SCL clock cycle only when the second notification is received, so that the IIC master can also initiate clock stretching.

[0099] In the embodiment, the first notification is sent in the SCL low period of the SCL clock cycle after the IIC master sends the SCL clock signal falling edge. The IIC master starts clock stretching to suspend the transmission of the level signal in the current SCL clock cycle, and after the clock stretching is cancelled, the transmission of the level signal in the current SCL clock cycle is restored and completed.

[0100] As an embodiment, the first notification is sent in the SCL high period of the SCL clock cycle after the IIC master sends the SCL clock signal falling edge, except for the data transmission period. The method proposed in the embodiment can further include:

[0101] The SCL clock cycle is ended, a new SCL clock cycle is started, and if the second notification sent by the IIC master through the clock stretching indication signal line is received, it is checked whether the current time is before the end of the SCL low period in the new SCL clock cycle; if yes, the new SCL clock cycle is ended, and if no, the operation of controlling the pin connected to the slave SCL on the control device to a high-impedance state based on the second notification is continued; the pin connected to the master SCL on the IIC master is in a low state after the IIC master determines to start clock stretching.

[0102] If the second notification sent by the IIC master through the clock extension indication signal line is not received at the end of the SCL low period in the new SCL clock cycle, the pin of the control device connected to the SCL of the slave device is continuously maintained in the low state.

[0103] In the embodiment, the first notification is sent in the SCL high period of the SCL clock cycle after the SCL clock signal falling edge is sent by the IIC master, that is, the clock extension is started in the case that the data transmission of the current SCL clock cycle has been completed.

[0104] Since the clock extension is started in the SCL high period, after the clock extension is started, the IIC master controls the pin of the IIC master connected to the SCL of the master device to be in the low state, and the control device controls the pin of the control device connected to the SCL of the slave device to be in the low state, at this time, the SCL of the master device and the SCL of the slave device are both converted from the high state to the low state, the SCL of the master device appears a falling edge, and enters the next SCL clock cycle (marked as a new SCL clock cycle), when the control device detects the SCL clock signal falling edge, the pin of the control device connected to the SCL of the slave device is controlled to be in the low state, and the pin of the control device connected to the SCL of the master device is controlled to be in the low state.

[0105] If the second notification is received before the end of the SCL low period in the new SCL clock cycle, it indicates that the clock extension has been cancelled before the end of the SCL low period, since in the SCL low period, the SCL of the master device and the SCL of the slave device are both in the low state in the conventional signal transmission mechanism, in this case, it is equivalent to not performing the clock extension, at this time, the transmission of the level signal in the new SCL clock cycle can be normally performed according to the flow of the conventional mechanism, and the recording of the length of the current clock cycle is ended.

[0106] If the second notification is not received before the end of the SCL low period in the new SCL clock cycle, it indicates that the clock extension is still continuing at the end of the SCL low period, at this time, if the conventional mechanism is followed, the pin of the control device connected to the SCL of the slave device needs to be adjusted to the high impedance state, and the data transmission is performed according to the rising edge generated, but since the clock extension is still continuing in the scheme proposed in the embodiment, the pin of the control device connected to the SCL of the slave device is continuously maintained in the low state, so as to suspend the communication between the IIC master and the IIC slave, that is, to suspend the transmission of the level signal in the new SCL clock cycle, until the second notification sent by the IIC master through the clock extension indication signal line is received, and then the SCL of the slave device connected to the SCL of the slave device is controlled to be in the high impedance state, so as to restore the communication between the IIC master and the IIC slave, and complete the transmission of the level signal in the new SCL clock cycle.

[0107] Similarly, the method proposed in the embodiment breaks the limitation of the conventional IIC transmission mechanism. At the end of the SCL low period, instead of directly adjusting the pin connected to the slave SCL on the control device to a high-impedance state according to the conventional transmission mechanism, the level signal transmission is performed according to the generated rising edge, and the slave SCL pin connected to the slave SCL on the control device is controlled to a high-impedance state only after receiving the second notification to restore the communication between the IIC master and the IIC slave, so that the IIC master can also initiate the clock extension.

[0108] In the embodiment, when the first notification is sent in the SCL high period of the SCL clock cycle after the SCL clock signal falling edge sent by the IIC master, the IIC master starts the clock extension, the data transmission in the new SCL clock cycle (i.e., the next SCL clock cycle after the SCL clock cycle after the SCL clock signal falling edge sent by the IIC master) is paused, and after the clock extension is cancelled, the data transmission in the new SCL clock cycle is resumed and completed.

[0109] The specific process of starting the clock extension by the master will be described in detail in the specific embodiments below, and will not be described here again.

[0110] So far, the description of the process in the Figure 3 embodiment ends.

[0111] The present application adds a clock extension indication signal line between the IIC master and the control device in the communication control system. When the IIC master determines to start the clock extension, the IIC master sends the first notification to the control device through the clock extension indication signal line, so that the control device maintains the slave SCL pin connected to the slave SCL on the control device in a low state based on the first notification. In the absence of the clock extension invalidation indication signal, even if the specified period of the SCL clock cycle ends, the slave SCL pin connected to the slave SCL on the control device will not be controlled to a high-impedance state as in the conventional data transmission mechanism, but will always be maintained in a low state to pause the data transmission, breaking the limitation of the current IIC data transmission mechanism. Until the IIC master sends the second notification to the control device through the clock extension indication signal line to cancel the clock extension, the slave SCL pin connected to the slave SCL on the control device is controlled to a high-impedance state to restore the data transmission, so as to realize the clock extension mechanism in the IIC communication protocol in the absence of a direct connection between the IIC master and the IIC slave.

[0112] The application further provides an IIC master device, which is an IIC master device in a communication control system; the communication control system further comprises an IIC slave device connected with the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is further connected between the IIC master device and the control device. The IIC master device is configured to execute the method in the above Figure 2

[0113] The application further provides a control device, which is a control device in a communication control system; the communication control system further comprises an IIC master device and an IIC slave device connected with the IIC master device, and the control device is connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is further connected between the IIC master device and the control device.

[0114] Specifically, the control device can comprise:

[0115] a frequency counter, which is in communication connection with the slave SCL control module, and is configured to count at a preset frequency and trigger the slave SCL control module to control the pin connected with the slave SCL on the control device to be in a high-impedance state when counting to the end of a specified period;

[0116] a slave SCL control module, which is in communication connection with the frequency counter and the master-slave SCL control module, is connected with the IIC slave device through the slave SCL, and is connected with the IIC master device through the clock extension indication signal line, and is configured to control the state of the pin connected with the slave SCL on the control device according to the signals sent by the master-slave SCL control module, the frequency counter and the clock extension indication signal line;

[0117] a first edge detection module, which is connected with the IIC master device through the master SCL and is in communication connection with the master-slave SCL control module, and is configured to detect the level transition of the master SCL;

[0118] a master-slave SCL control module, which is in communication connection with the first edge detection module, the slave SCL control module and the second edge detection module, is connected with the IIC master device through the master SCL, and is configured to control the state of the pin connected with the master SCL on the control device according to the detection results of the first edge detection module and the second edge detection module, and control the slave SCL control module so as to control the state of the pin connected with the slave SCL on the control device by the slave SCL control module;

[0119] a second edge detection module, which is connected with the IIC slave device through the slave SCL and is in communication connection with the master-slave SCL control module, and is configured to detect the level transition of the slave SCL.​

[0120] The cooperation between the modules in the control device will be described in detail in the specific embodiments below, and thus will not be described here again.

[0121] The IIC-based communication control system and method proposed in the present application will be described below through several specific embodiments.

[0122] Embodiment 1

[0123] Please refer to Figure 4 , Figure 4 The specific structure diagram of an IIC communication control system provided by the embodiment of the present application.

[0124] As shown in Figure 4 , the system includes an IIC master device, a control device, and two IIC slave devices.

[0125] Specifically, the control device can include:

[0126] A frequency counter, which is in communication connection with the slave SCL control module, is used to count at a preset frequency and trigger the slave SCL control module to control the pin connected to the slave SCL on the control device to be in a high-impedance state when counting to the end of a specified period.

[0127] The slave SCL control module, which is in communication connection with the frequency counter, the master-slave SCL control module, is connected to the IIC slave device through the slave SCL and connected to the IIC master device through the clock extension indication signal line, and is used to control the state of the pin connected to the slave SCL on the control device according to the signals sent by the master-slave SCL control module, the frequency counter, and the clock extension indication signal line.

[0128] A first edge detection module, which is connected to the IIC master device through the master SCL and in communication connection with the master-slave SCL control module, is used to detect the level transition of the master SCL.

[0129] The master-slave SCL control module, which is in communication connection with the first edge detection module, the slave SCL control module, and the second edge detection module, is connected to the IIC master device through the master SCL, and is used to control the state of the pin connected to the master SCL on the control device according to the detection results of the first edge detection module and the second edge detection module, and control the slave SCL control module so that the slave SCL control module controls the state of the pin connected to the slave SCL on the control device.

[0130] The second edge detection module is connected with the IIC slave device through the slave SCL and is in communication connection with the master-slave SCL control module, and is used for detecting the level conversion of the slave SCL.

[0131] The SCL gate is connected with each IIC slave device through the slave SCL, and is in communication connection with the slave SCL control module and the second edge detection module, and is used for determining the IIC slave device which needs to communicate according to the instruction of the IIC master device.

[0132] The IIC communication control method proposed in the present application is described below based on the above IIC communication control system.

[0133] Before describing the process of starting the clock extension function of the IIC host, the level conversion mechanism in the IIC communication control system is first introduced.

[0134] In the embodiment, the master SCL refers to the serial clock line between the IIC host and the control device, and the level thereof is controlled by the master device and the control device. When the pin of the master SCL is controlled to be in a low level state by either the master device or the control device (denoted as pulling down the master SCL), the level of the master SCL is low. When the pin of the master SCL is controlled to be in a high impedance state by both the master device and the control device (denoted as releasing the master SCL), the level of the master SCL is high.

[0135] Similarly, the slave SCL refers to the serial clock line between the IIC slave and the control device, and the level thereof is controlled by the slave device and the control device. When the pin of the slave SCL is controlled to be in a low level state by either the slave device or the control device (denoted as pulling down the slave SCL), the level of the slave SCL is low. When the pin of the slave SCL is controlled to be in a high impedance state by both the slave device and the control device (denoted as releasing the slave SCL), the level of the slave SCL is high.

[0136] It should be noted that the IIC system performs level signal transmission once in a cycle of the SCL signal. Taking the case of a cycle of the SCL signal including a low level in the first 1 / 2 cycle and a high level in the second 1 / 2 cycle as an example, the data on the SDA changes during the low level in the first 1 / 2 cycle of the SCL, and is read starting from the rising edge generated by the conversion of the low level to the high level, i.e., during the high level in the second 1 / 2 cycle.

[0137] The method of starting the clock extension function of the ICC host is described below taking the scene of the IIC communication control system performing the IIC task of multi-byte reading and writing as an example.

[0138] In the embodiment, the host side clock stretching function is started when the SCL low period in any SCL clock cycle included in the SCL clock signal, that is, the clock stretching function is started in the first half of any SCL clock cycle in the current scenario.

[0139] Taking the IIC task of reading and writing multiple bytes as an example, 8 bytes of data are read and written, and 1 bit of data is read in each SCL clock cycle during the reading of the data of any byte, for example, the second byte.

[0140] Taking the reading of the third bit of the second byte in the current SCL clock cycle as an example, when the SCL clock cycle corresponding to the third bit starts, the master device is controlled to be at a low level at the pin connected to the master device SCL on the master device according to the SCL clock signal, and a falling edge of the master device SCL appears.

[0141] When the control device detects that the master device SCL has a falling edge through the first edge detection module, the master-slave SCL control module is instructed to control the pin connected to the master device SCL on the control device to be at a low level, and the master-slave SCL control module controls the slave device SCL control module to control the pin connected to the slave device SCL on the control device to be at a low level. (At this time, the master device SCL is at a low level state pulled down by the master device and the control device simultaneously, and the slave device SCL is at a low level state pulled down by the control device)

[0142] In the first half of the SCL clock cycle for transmitting the third bit, the master device SCL is at a low level state pulled down by the master device and the control device simultaneously, and the slave device SCL is at a low level state pulled down by the control device.

[0143] If there is a higher priority task of the IIC master device to be processed in the first half of the SCL clock cycle for transmitting the third bit, the clock stretching can be started actively, a first notification is sent to the control device through the clock stretching indication signal line, and the pin connected to the slave device SCL on the control device is maintained at a low level. At this time, the clock stretching needs to be cancelled by the IIC master device, and the communication between the master device and the slave device is suspended. (At this time, the master device SCL is at a low level state pulled down by the master device and the control device simultaneously, and the slave device SCL is at a low level state pulled down by the control device)

[0144] The IIC frequency counter starts counting at the beginning of the SCL clock cycle corresponding to the 3rd bit. When the host finishes processing the task of higher priority, the clock stretching can be cancelled, and a second notification is sent to the control device through the clock stretching indication signal line. When the slave SCL control module receives the second notification sent by the IIC master through the clock stretching indication signal line, it is detected whether the IIC frequency counter counts to 1 / 2 of the SCL clock cycle. If not, it indicates that the clock stretching has ended in the SCL low period (the first 1 / 2 period) of the SCL clock cycle. At this time, the transmission of the 3rd bit data can be performed according to the normal IIC transmission mechanism, and the counting of the IIC frequency counter can be stopped.

[0145] If the IIC frequency counter has counted more than 1 / 2 of the SCL clock cycle, it indicates that the master device is still in the clock stretching state, i.e. the pin connected to the master SCL on the control device is in low state. At this time, the master device cancels the clock stretching, controls the pin connected to the master SCL on the control device to be in high impedance state, and controls the pin connected to the slave SCL on the control device to be in high impedance state through the slave SCL control module. At this time, the slave SCL is converted from low to high, and a rising edge of the clock signal is generated. The slave receives or sends the 3rd bit data through SDA according to the rising edge, and the communication between the master and the slave is restored. (At this time, the master SCL is in low state pulled down by the controlled device, and the slave SCL is in high state released by the controlled device and the slave)

[0146] When the control device detects the rising edge of the slave SCL through the second edge detection module, it instructs the master and slave SCL control modules to control the pin connected to the master SCL on the control device to be in high impedance state. (At this time, the master SCL is released by the controlled device and the host, and is converted from low to high. The slave SCL remains in high state)

[0147] At this time, the clock stretching initiated by the host ends, the slave completes the reading of the current 3rd bit data, and the master SCL and the slave SCL return to high state. The reading of the 4th bit data will continue.

[0148] At this time, the description of embodiment 1 ends.

[0149] Embodiment 2

[0150] In this embodiment, the IIC communication control method proposed in the present application is described based on the IIC communication control system shown in Figure 4

[0151] ​In the embodiment, the host side clock stretching function is enabled in the SCL high period other than the data transmission period of the SCL clock cycle, and in the current scenario, it means that the clock stretching function is enabled in the latter 1 / 2 period of any SCL clock cycle other than the data transmission period in the process of reading or writing a certain byte.

[0152] Still taking the IIC task of reading and writing multiple bytes as an example, in the process of reading the data of the second byte, 1-bit data is read in each SCL clock cycle.

[0153] Taking the reading of the third bit of the second byte in the current SCL clock cycle as an example, in the SCL clock cycle corresponding to the third bit, after the transmission of the third bit of data is completed in the latter 1 / 2 period, the master SCL and the slave SCL are both in the high state.

[0154] If there is a higher priority task to be processed after the transmission of the third bit of data is completed in the latter 1 / 2 period, the clock stretching can be actively enabled, the pin connected to the master SCL on the IIC master is controlled to be in the low state, the current SCL clock cycle is ended, a new SCL clock cycle (the SCL clock cycle corresponding to the transmission of the fourth bit of data) is started, the IIC frequency counter starts timing, and the first notification is sent to the control device through the clock stretching indication signal line, the pin connected to the slave SCL on the control device is controlled to be in the low state, and at this time, the clock stretching needs to be cancelled by the IIC master, and the communication between the master and the slave is suspended. (At this time, the master SCL is pulled low by the master, and the state is changed from the high state to the low state, generating a falling edge, and the slave SCL is pulled low by the control device, and the state is changed from the high state to the low state)

[0155] When the control device detects the falling edge of the host SCL through the first edge detection module, the pin connected to the slave SCL on the control device is controlled to be in the low state, and the pin connected to the master SCL on the control device is controlled to be in the low state. (At this time, the master SCL is pulled low by the master and the control device, and is in the low state; the slave SCL is pulled low by the control device, and is in the low state)

[0156] The IIC frequency counter starts counting at the beginning of the new SCL clock cycle corresponding to the 4th bit, and when the host finishes processing the higher priority task, the clock stretching can be cancelled, a second notification is sent to the control device through the clock stretching indication signal line, and when the slave SCL control module receives the second notification sent by the IIC master through the clock stretching indication signal line, it is detected whether the IIC frequency counter has counted to 1 / 2 of the new SCL clock cycle, if not, it indicates that the clock stretching has ended within the SCL low period (the first 1 / 2 period) of the new SCL clock cycle, at this time, only the transmission of the 3rd bit data according to the normal IIC transmission mechanism can be carried out, and the counting of the IIC frequency counter can be stopped.

[0157] If the IIC frequency counter has counted more than 1 / 2 of the new SCL clock cycle, it indicates that the master device is still in the process of starting clock stretching, that is, the pin connected to the master SCL on the control device is in a low state, at this time, the master device cancels the clock stretching, controls the pin connected to the master SCL on the control device to be in a high impedance state, and controls the pin connected to the slave SCL on the control device to be in a high impedance state through the slave SCL control module, at this time, the slave SCL is converted from a low level to a high level, a clock signal rising edge is generated, and the slave receives or sends the 4th bit data according to the rising edge, and the communication between the master and the slave is restored. (At this time, the master SCL is in a low state pulled down by the controlled device, and the slave SCL is in a high state released by the controlled device and the slave)

[0158] When the control device detects that the slave SCL rising edge appears through the second edge detection module, it instructs the master and slave SCL control module to control the pin connected to the master SCL on the control device to be in a high impedance state. (At this time, the master SCL is released by the controlled device and the host, and is converted from a low state to a high state, and the slave SCL remains in a high state)

[0159] At this time, the clock stretching initiated by the host ends, the slave completes the reading of the current 4th bit data, and the master SCL and the slave SCL return to a high state, and the reading of the 5th bit data continues.

[0160] At this time, the description of embodiment 2 ends.

[0161] Embodiment 3

[0162] Please refer to Figure 5 , Figure 5 The specific structure diagram of an IIC communication control system provided by the embodiment of the application.

[0163] As Figure 5As shown, the system includes two IIC master devices, a control device, and two IIC slave devices.

[0164] In this embodiment, if the IIC master device 1 starts clock extension, the data transmission with the IIC slave device 1 is suspended. During this process, since the slave SCL of the IIC slave device 1 has been occupied by the IIC master device 1, the IIC master device 2 cannot perform data transmission with the IIC slave device 1.

[0165] If the IIC master device 2 needs to perform data transmission with the IIC slave device 1, after the IIC master device 1 ends clock extension and releases the occupation of the IIC slave device 1, the IIC master device 2 can perform data transmission with the IIC slave device 1.

[0166] Thus far, the description of embodiment 3 ends.

[0167] Embodiment 4

[0168] Please refer to Figure 6 , Figure 6 Another specific structure diagram of a communication control system provided by the embodiment of the present application.

[0169] In the above embodiment 1, since the SDA signal line is level sampling rather than edge sampling, the SDA signal line can be directly connected to each host without the control device, thus saving the resources of the control device.

[0170] In this embodiment, as shown in Figure 6 , a structure is provided in which the SDA signal line also passes through the control device. An SDA direction indication signal line needs to be added in the control device to indicate the start of the corresponding transmission path according to the direction of data transmission.

[0171] Meanwhile, in the case where multiple IIC slave devices exist, an SDA gate can be added in the control device to determine the IIC slave device that needs to perform communication according to the instruction of the IIC master device.

[0172] Thus far, the description of embodiment 4 ends.

[0173] Please refer to Figure 7 , Figure 7 is a structure diagram of a clock extension implementation device based on an integrated circuit bus IIC, which is applied to an IIC master device in a communication control system. The communication control system further includes an IIC slave device connected with the IIC master device, and a control device connected between the IIC master device and the IIC slave device. A clock extension indication signal line is further connected between the IIC master device and the control device. As shown in Figure 7As shown, the apparatus can include an opening unit 701 and a canceling unit 702. Specifically, the apparatus includes:

[0174] The opening unit 701 is configured to, if it is determined to open the clock stretching, send a first notification to the control device through the clock stretching indication signal line, so that the control device maintains the pin connected to the slave device SCL on the control device in a low state based on the first notification; wherein when the control device receives a falling edge of the SCL clock signal, the control device controls the pin connected to the slave device SCL on the control device to be in a low state and controls the pin connected to the master device SCL on the control device to be in a low state.

[0175] The canceling unit 702 is configured to, if it is determined to cancel the clock stretching, send a second notification to the control device through the clock stretching indication signal line, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0176] Optionally, the control device includes a slave device SCL control component; the slave device SCL control component is configured to control the state of the pin connected to the slave device SCL on the control device.

[0177] The IIC master device is connected to the slave device SCL control component through the clock stretching indication signal line.

[0178] Optionally, the pin connected to the master device SCL on the IIC master device is in a high impedance state after the IIC master device determines to cancel the clock stretching.

[0179] Optionally, the first notification is sent in a specified period of an SCL clock period after the falling edge of the SCL clock signal is sent, and the SCL clock period is a set time length based on the falling edge of the SCL clock signal.

[0180] Optionally, the SCL clock period includes an SCL low period and an SCL high period, the SCL high period includes a data transmission period, and the specified period includes:

[0181] the SCL low period and the SCL high period except the data transmission period.

[0182] Thus far, the description of the structure diagram of the clock stretching implementation apparatus based on the integrated circuit bus IIC in Figure 7 is ended.

[0183] Please refer to Figure 8 , Figure 8A target detection model training device structure diagram is proposed in an embodiment of the present application. The device is applied to a control device in a communication control system. The communication control system further includes an IIC master device and an IIC slave device connected with the IIC master device. The control device is connected between the IIC master device and the IIC slave device. A clock extension indication signal line is further connected between the control device and the IIC master device. As shown in Figure 8 , the device can include a maintaining unit 801 and a control unit 802. Specifically, the device includes:

[0184] The maintaining unit 801 is configured to, if a first notification sent by the IIC master device is received through the clock extension indication signal line between the control device and the IIC master device, maintain a pin connected with the slave device SCL on the control device in a low voltage state based on the first notification. When the control device receives a falling edge of an SCL clock signal, the control device controls the pin connected with the slave device SCL on the control device to be in a low voltage state and controls a pin connected with the master device SCL on the control device to be in a low voltage state.

[0185] The control unit 802 is configured to, if a second notification sent by the IIC master device is received through the clock extension indication signal line between the control device and the IIC master device, control the pin connected with the slave device SCL on the control device to be in a high resistance state based on the second notification. If it is detected that the level of the slave device SCL is converted from a low voltage to a high voltage, the control unit 802 controls the pin connected with the master device SCL on the control device to be in a high resistance state.

[0186] Optionally, the control device includes a slave device SCL control component. The slave device SCL control component is configured to control the state of the pin connected with the slave device SCL on the control device.

[0187] The slave device SCL control component is connected with the IIC master device through the clock extension indication signal line.

[0188] Optionally, the first notification is sent in a specified period of an SCL clock period after a falling edge of an SCL clock signal sent by the IIC master device. The SCL clock period is one SCL clock period starting from a falling edge of an SCL clock signal sent by the master device SCL and received most recently.

[0189] Optionally, the SCL clock period includes an SCL low voltage period and an SCL high voltage period. The SCL high voltage period includes a data transmission period. The specified period includes:

[0190] The SCL low voltage period and the SCL high voltage period except the data transmission period.

[0191] Optionally, the first notification is sent in a SCL low period of a SCL clock cycle after a falling edge of a SCL clock signal sent by the IIC master device, and the control unit 802 is further configured to:

[0192] If the second notification sent by the IIC master device through the clock stretching indication signal line is received, it is checked whether the current time is a time before the end of a SCL low period in a SCL clock cycle; if yes, the SCL clock cycle is ended, and if no, the operation of controlling the pin connected to the SCL of the slave device on the control device to be in a high impedance state based on the second notification is continuously performed.

[0193] Optionally, the first notification is sent in a SCL low period of a SCL clock cycle after a falling edge of a SCL clock signal sent by the IIC master device, and the control unit 802 is further configured to:

[0194] If the second notification sent by the IIC master device through the clock stretching indication signal line is not received at the end of the SCL low period in the SCL clock cycle, the pin connected to the SCL of the slave device on the control device is continuously maintained in a low state.

[0195] Optionally, the first notification is sent in a SCL high period of a SCL clock cycle except a data transmission period after a falling edge of a SCL clock signal sent by the IIC master device, and the control unit 802 is further configured to:

[0196] The SCL clock cycle is ended, a new SCL clock cycle is started, if the second notification sent by the IIC master device through the clock stretching indication signal line is received, it is checked whether the current time is a time before the end of a SCL low period in the new SCL clock cycle; if yes, the new SCL clock cycle is ended, and if no, the operation of controlling the pin connected to the SCL of the slave device on the control device to be in a high impedance state based on the second notification is continuously performed; the pin connected to the SCL of the master device on the IIC master device is in a low state after the IIC master device determines to start clock stretching.

[0197] Optionally, the first notification is sent in a SCL high period of a SCL clock cycle except a data transmission period after a falling edge of a SCL clock signal sent by the IIC master device, and the control unit 802 is further configured to:

[0198] The SCL clock cycle is ended, a new SCL clock cycle is started, if the second notification sent by the IIC master device through the clock stretching indication signal line is not received at the end of the SCL low period in the new SCL clock cycle, the pin connected to the SCL of the slave device on the control device is continuously maintained in a low state; the pin connected to the SCL of the master device on the IIC master device is in a low state after the IIC master device determines to start clock stretching.

[0199] Thus far, the description of the structure diagram of the another target detection model training device in the middle has been completed. Figure 8 Thus far, the description of the structure diagram of the another target detection model training device in the middle has been completed.

[0200] The above merely provides a preferred embodiment of the present application, but not for limiting the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for implementing clock stretching based on an integrated circuit bus (IIC), characterized in that, The method is applied to an IIC master device in a communication control system; the communication control system further comprises an IIC slave device connected with the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is further connected between the IIC master device and the control device; the method comprises: If it is determined to start clock extension, a first notification is sent to the control device through the clock extension indication signal line, so that the control device maintains a pin connected with the slave device SCL on the control device in a low state based on the first notification; wherein when the control device receives a falling edge of an SCL clock signal, the control device controls the pin connected with the slave device SCL on the control device to be in a low state and controls a pin connected with the master device SCL on the control device to be in a low state; If it is determined to cancel clock extension, a second notification is sent to the control device through the clock extension indication signal line, so that the control device controls the pin connected with the slave device SCL on the control device to be in a high-impedance state based on the second notification.

2. The method of claim 1, wherein, The control device comprises a slave device SCL control component; the slave device SCL control component is used to control the state of the pin connected with the slave device SCL on the control device; The IIC master device is connected with the slave device SCL control component through the clock extension indication signal line.

3. The method of claim 1, wherein, The pin connected with the master device SCL on the IIC master device is in a high-impedance state after the IIC master device determines to cancel clock extension.

4. The method of claim 1, wherein, The first notification is sent in a specified period of an SCL clock period after sending a falling edge of an SCL clock signal, and the SCL clock period is a set time length based on the falling edge of the SCL clock signal.

5. The method of claim 4, wherein, The SCL clock period comprises an SCL low period and an SCL high period, and the SCL high period comprises a data transmission period, and the specified period comprises: The SCL low period and the SCL high period except the data transmission period.

6. A method for implementing clock stretching based on an integrated circuit bus (IIC), characterized by, The method is applied to a control device in a communication control system; the communication control system further comprises an IIC master device and an IIC slave device connected with the IIC master device, and the control device is connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is further connected between the control device and the IIC master device; the method comprises: If a first notification sent by the IIC master device is received through the clock extension indication signal line between the control device and the IIC master device, the pin connected with the slave device SCL on the control device is maintained in a low state based on the first notification; wherein when the control device receives a falling edge of an SCL clock signal, the control device controls the pin connected with the slave device SCL on the control device to be in a low state and controls a pin connected with the master device SCL on the control device to be in a low state; If a second notification sent by the IIC master is received through the clock extension indication signal line between the control device and the IIC master, the pin of the control device connected to the slave SCL is controlled to be in a high-impedance state based on the second notification; If it is detected that the level of the slave SCL changes from low to high, the pin of the control device connected to the master SCL is controlled to be in a high-impedance state.

7. The method of claim 6, wherein, The control device comprises a slave SCL control component, which is configured to control the state of the pin of the control device connected to the slave SCL. The slave SCL control component is connected to the IIC master through the clock extension indication signal line.

8. The method of claim 6, wherein, The first notification is sent in a specified period of an SCL clock cycle after a falling edge of an SCL clock signal sent by the IIC master; the SCL clock cycle is one SCL clock cycle starting from a most recently received falling edge of an SCL clock signal sent by the master SCL.

9. The method of claim 8, wherein, The SCL clock cycle comprises an SCL low period and an SCL high period, the SCL high period comprises a data transmission period, and the specified period comprises: The SCL low period and the SCL high period except the data transmission period.

10. The method of claim 9, wherein, The first notification is sent in an SCL low period of an SCL clock cycle after a falling edge of an SCL clock signal sent by the IIC master, and the method further comprises: If a second notification sent by the IIC master through the clock extension indication signal line is received, it is checked whether the current time is a time before the end of the SCL low period in the SCL clock cycle; if yes, the SCL clock cycle is ended, and if no, the operation of controlling the pin of the control device connected to the slave SCL to be in a high-impedance state based on the second notification is continued.

11. The method of claim 9, wherein, The first notification is sent in an SCL low period of an SCL clock cycle after a falling edge of an SCL clock signal sent by the IIC master, and the method further comprises: If a second notification sent by the IIC master through the clock extension indication signal line is not received at the end of the SCL low period in the SCL clock cycle, the pin of the control device connected to the slave SCL is continued to be maintained in a low state.

12. The method of claim 9, wherein, The first notification is sent in an SCL high period except a data transmission period of an SCL clock cycle after a falling edge of an SCL clock signal sent by the IIC master, and the method further comprises: If the second notification sent by the IIC master through the clock extension indication signal line is received, it is checked whether the current time is the time before the end of the SCL low period in the new SCL clock cycle; if yes, the new SCL clock cycle is ended, and if no, the operation of controlling the pin connected to the slave SCL on the control device to be in the high-impedance state based on the second notification is continuously performed.

13. The method of claim 9, wherein, The first notification is sent in the SCL high period of the SCL clock cycle except the data transmission period after the SCL clock signal falling edge is sent by the IIC master, and the method further comprises: If the second notification sent by the IIC master through the clock extension indication signal line is not received at the end of the SCL low period in the new SCL clock cycle, the pin connected to the slave SCL on the control device is continuously maintained in the low state; the pin connected to the master SCL on the IIC master is in the low state after the IIC master determines to open the clock extension.

14. An apparatus for clock stretching implementation based on an integrated circuit bus (IIC), characterized by, The device is applied to an IIC master in a communication control system; the communication control system further comprises an IIC slave connected to the IIC master, and a control device connected between the IIC master and the IIC slave, and a clock extension indication signal line is further connected between the IIC master and the control device; the device comprises: An opening unit is configured to send a first notification to the control device through the clock extension indication signal line if it is determined to open the clock extension, so that the control device maintains the pin connected to the slave SCL on the control device in the low state based on the first notification; when the control device receives an SCL clock signal falling edge, the pin connected to the slave SCL on the control device is controlled to be in the low state, and the pin connected to the master SCL on the control device is controlled to be in the low state; A canceling unit is configured to send a second notification to the control device through the clock extension indication signal line if it is determined to cancel the clock extension, so that the control device controls the pin connected to the slave SCL on the control device to be in the high-impedance state based on the second notification.

15. An apparatus for clock stretching implementation based on an integrated circuit bus (IIC), characterized in that, The device is applied to a control device in a communication control system; the communication control system further comprises an IIC master and an IIC slave connected to the IIC master, and the control device is connected between the IIC master and the IIC slave, and a clock extension indication signal line is further connected between the control device and the IIC master; the device comprises: An opening unit is configured to send a first notification to the control device through the clock extension indication signal line if it is determined to open the clock extension, so that the control device maintains the pin connected to the slave SCL on the control device in the low state based on the first notification; when the control device receives an SCL clock signal falling edge, the pin connected to the slave SCL on the control device is controlled to be in the low state, and the pin connected to the master SCL on the control device is controlled to be in the low state; The maintaining unit is used for maintaining the pin connected with the slave SCL on the control device in a low voltage state based on the first notification if the first notification sent by the IIC master is received through the clock extension indication signal line between the IIC master and the control device; wherein the control device controls the pin connected with the slave SCL on the control device to be in a low voltage state and controls the pin connected with the master SCL on the control device to be in a low voltage state when the falling edge of the SCL clock signal is received; The control unit is used for controlling the pin connected with the slave SCL on the control device to be in a high resistance state based on the second notification if the second notification sent by the IIC master is received through the clock extension indication signal line between the IIC master and the control device; and controlling the pin connected with the master SCL on the control device to be in a high resistance state if it is detected that the level of the slave SCL is converted from a low voltage to a high voltage.

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