Real-time data interaction system and method of full-connection network

Abstract

The invention discloses a real-time data interaction system and method for a full-connection network, and the system is characterized in that a main communication link and a standby communication link are arranged between any two CPU board cards in the full-connection network, and an output CPU board card transmits to-be-transmitted data from the main communication link and the standby communication link at the same time; the third-party CPU board card located on the standby communication link receives the data sent by the output CPU board card and forwards the data; the input CPU board card receives data sent by the output CPU board card from the main communication link, and receives data sent by the output CPU board card and forwarded by the third-party CPU board card from the standby communication link; and when the input CPU board card fails to receive the data of the main communication link, receiving the data sent by the output CPU board card from the standby communication link. According to the invention, communication fault tolerance of real-time data interaction between any two CPU board cards on a full-connection network can be realized, and the reliability and stability of real-time data interaction between the CPU board cards are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electric power secondary equipment, and in particular relates to a real-time data interaction system and method for a fully connected network. Background Art

[0002] Power secondary protection and control equipment is an important part of the power system, responsible for status monitoring and protection control of the primary equipment of the power system. With the continuous advancement of the construction of new power systems, core power secondary protection and control equipment needs to adapt to new fault characteristics and meet the rapid control requirements of a high proportion of power electronic equipment in the power grid. The increase in algorithm complexity and rapid control response require stronger computing resources. The system hardware generally uses extended computing CPU boards to achieve flexible expansion of computing resources, and uses a fully connected network to achieve non-blocking communication between computing CPU boards. The protection and control business algorithm program can be split and deployed on multiple computing CPU boards. Each board completes single-board calculations in parallel, and realizes coordinated control of the entire equipment system through real-time interactive data communication over a fully connected network.

[0003] Considering that the power secondary protection and control equipment is subject to interference from harsh operating environments such as complex external electromagnetic environments and extreme climates on the internal CPU operation and backplane high-speed signal transmission of the equipment, errors may occur in the data interaction communication messages between the computing CPUs, resulting in communication abnormalities on certain channels on the fully connected network, affecting the collaborative control process of the business algorithm, and in extreme cases may cause the control and protection functions of the primary equipment to fail.

[0004] To solve the above problems, one of the existing solutions is to add redundant links physically and design dual-network redundancy for the communication links between any two CPU boards that need data interaction. The redundant network forms generally include point-to-point dual networks and hand-in-hand bracelet networks. The sending and receiving CPU boards send and receive messages from the main network and the redundant network at the same time, so that after one network is interrupted, the other network can continue to be used for communication. Another solution is to add communication message confirmation and retransmission processing to the sending and receiving control process. For example, after the output CPU board sends data, it must wait for the receiving CPU board to respond and confirm. After receiving the message, the input CPU board replies to the sending CPU board with a confirmation message; if the output CPU board judges that it has not received the reply confirmation message within the timeout period, the output CPU board immediately resends the message.

[0005] CN104283658 discloses a dual-network redundancy implementation method based on a PRP parallel redundant protection device, and proposes to implement dual-network redundancy and redundant processing methods at the data link layer. This disclosed solution is mainly aimed at external communication of the device. For the data communication between boards inside the protection device, if a dual-network redundancy design is also adopted, the number of high-speed communication interfaces of the single-board CPU will double. When the number of boards in the device is large, the CPU hardware resources may not be able to meet the demand, and a CPU with more high-speed communication interface resources must be used, which greatly increases the system hardware cost; if the CPU hardware resources remain unchanged, the number of the system's maximum scalable computing nodes needs to be reduced, significantly reducing the system's comprehensive computing power.

[0006] CN112202690 discloses a high-speed bus network based on switching and ring network redundancy. The bus network requires the adjacent nodes of the system to be connected hand in hand, and the head and tail nodes are connected to form a ring network. In the inter-board bus network inside the device in the disclosed scheme, the communication between non-adjacent nodes in the ring network structure must be forwarded through the intermediate node, which increases the fixed delay, and the fixed delay increases exponentially with the increase in the number of intermediate nodes. When the number of CPU boards in the device is large, the delay of calculating the real-time data interaction between the CPU boards is greatly increased, which cannot meet the system requirements of fast collaborative control between the boards inside the device.

[0007] For the solution of adding communication message confirmation and retransmission processing to the sending and receiving control process, if a permanent failure or interference occurs in the transmission link, resulting in two consecutive link communication message errors, the real-time data interaction between the two CPU boards will be permanently interrupted and cannot be restored, or at least the collaborative control data of one control response cycle will be lost; on the other hand, the timeout waiting time setting of the output CPU board must be at least greater than the round-trip transmission delay of a single message on the link, and considering the transmission delay of a timeout retransmission message, the maximum link transmission delay of a data interaction is at least greater than 3 times the single message transmission delay; the increase in the inherent transmission delay of data interaction will cause the system control response cycle to become longer, which may not meet the real-time requirements of data interaction for fast control protection equipment in low-latency scenarios. Summary of the invention

[0008] Purpose of the invention: The purpose of the present invention is to provide a real-time data interaction system and method for a fully connected network to solve one or more problems existing in the prior art.

[0009] Technical solution: A real-time data interaction system of a fully connected network of the present invention comprises a fully connected network with point-to-point cross-connection, any two nodes on the fully connected network are directly connected through a link, and any two nodes are indirectly connected through at least one third-party node, and each node in the fully connected network corresponds to a CPU board;

[0010] There is a main communication link and a backup communication link between any two CPU boards. The main communication link is a direct connection communication link between the two data exchange CPU boards, and the backup communication link is a communication link between the two data exchange CPU boards that is connected through a single forwarding of a third-party CPU board.

[0011] The output CPU board sends the data to be sent from the main communication link and the backup communication link at the same time. After the third-party CPU board on the backup communication link receives the data sent by the output CPU board, it forwards the data from the backup communication link; the input CPU board receives the data sent by the output CPU board from the main communication link, and at the same time receives the data sent by the output CPU board forwarded by the third-party CPU board from the backup communication link; when the input CPU board fails to receive the data from the main communication link, it receives the data sent by the output CPU board from the backup communication link.

[0012] Furthermore, the CPU board is a single-core or multi-core processor.

[0013] Based on the same inventive concept, the real-time data interaction method of the real-time data interaction system of the present invention comprises: designating a CPU board card to concurrently serve as a system management configuration node;

[0014] The system management configuration node obtains the output-input mapping relationship of data interaction between any two CPU boards according to the specified data arrangement order based on all CPU board configuration information stored thereon, and generates a data sending relationship table of the output CPU board and a data receiving relationship table of the input CPU board according to the output and input CPU boards of the data interaction between the two boards, and sends them to the output and input CPU boards respectively;

[0015] The system management configuration node determines the main communication link between any two CPU boards according to the output-input mapping relationship of data interaction between any two CPU boards, and further determines the backup communication link between the two CPU boards according to the configuration information of all CPU boards through the static network topology algorithm; the system management configuration node sends the main and backup communication link information to the corresponding output and input CPU boards respectively, and also sends it to the corresponding third-party CPU boards;

[0016] The data interaction output CPU board, input CPU board and third-party CPU board are all processed through automatic port detection to determine the mapping relationship between each network port sequence of this board and the board address;

[0017] The output CPU board composes the data to be sent into a message according to the data sending relationship table, and sends the message from the two corresponding network ports of the input CPU board of the main communication link and the input CPU board of the backup communication link according to the mapping relationship between the network port sequence number and the board address; the third-party CPU board on the backup communication link receives the message from the corresponding network port of the output CPU board according to the mapping relationship between the network port sequence number and the board address, and forwards the message from the corresponding network port of the input CPU board;

[0018] The input CPU board receives messages from the corresponding two network ports of the main communication link output CPU board and the backup communication link third-party CPU board according to the data reception relationship table and the mapping relationship between the communication network port serial number and the board address; the input CPU board first determines whether the main communication link message is received and verifies it; if it is received and the verification is correct, the main communication link is used to receive data; if the main communication link message is not received or the message verification is wrong, the backup communication link reception message is verified, if it is received and the verification is correct, the backup communication link is used to receive data; if the verification of both the main and backup communication link messages fails, the system is locked and alarmed, and the operation is exited, prompting manual disposal.

[0019] Furthermore, all CPU board configuration information includes the number of boards and the communication board address of each board.

[0020] Furthermore, the data transmission relationship table of the output CPU board includes the source address of the transmitted data and the offset in the message, and the corresponding input CPU board address.

[0021] Furthermore, the data receiving relationship table of the input CPU board includes the target address of the received data and the offset in the message, and the corresponding output CPU board address.

[0022] Furthermore, the system management configuration node sends the data sending relationship table, the input CPU board address, and the third-party CPU board address to the output CPU board; the system management configuration node sends the data receiving relationship table, the output CPU board address, and the third-party CPU board address to the input CPU board; the system management configuration node sends the output CPU board address and the input CPU board address to the third-party CPU board on the backup communication link.

[0023] Further, the static network topology algorithm includes: the system management configuration node takes each data transmission relationship table of each output CPU board in the fully connected network as a unit, and calculates the backup communication link between two output and input CPU boards corresponding to the data transmission relationship table one by one;

[0024] For any two data-interacting output and input CPU boards, the output and input board addresses of the main communication link select the larger board address number, add 1 to the larger address number, and then take the modulus according to the total number of CPU boards in the system to determine whether the remainder is equal to the smaller board address; if not, the third-party CPU board address is the remainder; if equal, the third-party CPU board address is the remainder plus 1; thereby determining the backup communication link between the output and input CPU boards;

[0025] According to the same method, the backup communication link between the output CPU board and other input CPU boards is determined.

[0026] Furthermore, the automatic port detection process includes: each CPU board sends a broadcast handshake request message to each connection network port between the board and the fully connected network, and after the board on the opposite side of the network port receives the broadcast handshake request message, it replies with a handshake response message; each CPU board can confirm the address of the board on the opposite side of each network port through the interactive process of sending handshake requests and receiving handshake response messages, that is, confirm the mapping relationship between the network port sequence and the board address for communication between the board and other CPU boards on the fully connected network.

[0027] Furthermore, based on the mapping relationship between the network port sequence number and the board address, when the output CPU board sends a message, the sending network port sequence number of this board can be determined according to the receiving message board address; when the input CPU board receives a message, the receiving network port sequence number of this board can be determined according to the sending message board address.

[0028] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0029] To solve the problem that the power secondary protection control equipment is interfered by the external complex electromagnetic operating environment, and a single communication link between multiple CPU boards fails, affecting the system collaborative control process, and then causing the failure of the core business functions of the equipment. The present invention realizes real-time data interaction between multiple CPU boards through a fully connected network. In the device initialization stage, the static network topology algorithm is used to automatically determine the main and backup communication links between all CPU boards that require data interaction in the system; in the device operation stage, the sending and receiving boards of the data interaction simultaneously send and receive messages through the main and backup communication links; if a permanent failure occurs in the main communication link, the receiving end will identify and seamlessly switch to the backup communication link, thereby realizing communication fault tolerance for real-time data interaction between any two CPU boards on the fully connected network. This solution has the following advantages:

[0030] 1) Using the backup link of the fully connected network to achieve hot redundancy of the primary and backup link data communication between any two CPU boards, it neither increases the system hardware cost nor affects the expansion capability of the system computing CPU resources;

[0031] 2) The third-party node (transit node) on the backup communication link between any two CPU boards is determined by a static network topology algorithm, and is forwarded only once by the third-party node. This not only avoids the uncertainty of the transmission link caused by the dynamic topology, but also ensures the controllability of the overall transmission delay (fixed maximum 2 times the single message transmission delay), ensuring the real-time nature of data interaction;

[0032] 3) The primary and standby communication links are calculated using a static network topology algorithm, which not only ensures the balanced distribution of data traffic on each physical link on the network, but also does not depend on the number of fully connected network CPU boards, and supports flexible expansion of system computing resources (CPU boards);

[0033] 4) The data exchange messages between the two CPU boards are sent and received in a point-to-point port manner, which avoids the surge in the total data traffic of the system on the fully connected network caused by the output CPU board broadcasting to all external ports of the board, and reduces the processor time consumption of the CPU message sending and receiving links; on the other hand, the sending and receiving boards use automatic port detection processing to achieve the decoupling of the software transceiver control processing and the physical port connection sequence between the CPU boards.

[0034] In summary, the present invention can effectively improve the reliability and stability of real-time data interaction between multiple CPU plug-ins in a fully connected network inside the power secondary protection control equipment, and reduce the situation in which a single fault causes functional failure during the operation of the equipment project and requires shutdown for maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a real-time data interaction system of a fully connected network in an embodiment of the present invention;

[0036] Figure 2 is a flow chart of a static network topology algorithm in an embodiment of the present invention;

[0037] Figure 3 It is a schematic diagram of sending and receiving messages between the primary and standby links in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described below in conjunction with the accompanying drawings.

[0039] Example 1

[0040] Embodiment 1 provides a real-time data interaction system of a fully connected network, including a fully connected network with point-to-point cross-connections, wherein any two nodes on the fully connected network are directly connected through a link, and any two nodes are indirectly connected through at least one third-party node, and each node in the fully connected network corresponds to a CPU board.

[0041] There is a main communication link and a backup communication link between any two CPU boards. The main communication link is a direct connection communication link between the two data exchange CPU boards, and the backup communication link is a communication link between the two data exchange CPU boards connected through a single forwarding of a third-party CPU board.

[0042] The output CPU board sends the data to be sent from the main communication link and the backup communication link at the same time. After the third-party CPU board on the backup communication link receives the data sent by the output CPU board, it immediately forwards the data from the backup communication link; the input CPU board receives the data sent by the output CPU board from the main communication link, and at the same time receives the data sent by the output CPU board forwarded by the third-party CPU board from the backup communication link; when the main communication link fails and the input CPU board fails to receive the data from the main communication link, it receives the data sent by the output CPU board from the backup communication link.

[0043] The CPU board can be a single-core processor or a multi-core processor, supporting the deployment of business logic programs. The real-time data interaction between any two CPU boards adopts point-to-point message sending and receiving communication mode. The business logic programs on any two CPU boards in the fully connected network realize message communication through custom format messages. The link transmission delay of the message from the sending CPU board to the receiving CPU board is controllable and cannot exceed the maximum allowable delay of the collaborative computing of the business logic program.

[0044] Figure 1 A real-time data interaction system consisting of four CPU boards is exemplified in the figure. It is easy to understand for those skilled in the art that the real-time data interaction system can also be composed of more CPU boards.

[0045] Example 2

[0046] Embodiment 2 provides a real-time data interaction method of a real-time data interaction system of a fully connected network, comprising:

[0047] (1) Allocation of output-input mapping relationships corresponding to data interaction between any two CPU boards

[0048] A CPU card on the fully connected network is designated to serve as a system management configuration node. The local flash of the system management configuration node stores all CPU card configuration information (signal input and output link relationship configuration information between all CPU cards), including the number of cards and the communication card address of each card.

[0049] The system management configuration node obtains the output-input mapping relationship of the data interaction between any two CPU boards according to the configuration information and the specified data arrangement order, and further generates the data sending relationship table of the output CPU board and the data receiving relationship table of the input CPU board according to the output and input CPU boards of the data interaction between the two boards, and sends them to the output and input CPU boards respectively; wherein the data sending relationship table of the output CPU board includes the source address of the sent data and the offset in the message, and the corresponding input CPU board address; the data receiving relationship table of the input CPU board includes the target address of the received data and the offset in the message, and the corresponding output CPU board address.

[0050] (2) Automatic network static topology processing determines the primary and standby communication links between any two CPU boards

[0051] The system management configuration node determines the main communication link between the two CPU boards, that is, the direct connection channel between the two CPU boards, according to the output-input mapping relationship of the data interaction between any two CPU boards; further, according to the configuration information of all CPU boards, the backup communication link between the two CPU boards is determined through the static network topology algorithm during the power-on initialization phase, that is, the two CPU boards can communicate through a single forwarding of a third-party CPU board.

[0052] The system management configuration node sends the information of the main and backup communication links between the two data interaction CPU boards to the output CPU board and the input CPU board of the data interaction, and sends it to the third-party CPU board on the backup communication link. Specifically, the system management configuration node sends the data sending relationship table, the input CPU board address (the input board address of the main communication link), and the third-party CPU board address (the board address of the backup communication link) to the output CPU board; the system management configuration node sends the data receiving relationship table, the output CPU board address (the output board address of the main communication link), and the third-party CPU board address (the board address of the backup communication link) to the input CPU board; the system management configuration node sends the output CPU board address and the input CPU board address of the main communication link to the third-party CPU board on the backup communication link.

[0053] Combination Figure 2 , the above static network topology algorithm includes:

[0054] The system management configuration node takes each data transmission relationship table of each output CPU board in the fully connected network as a unit, and calculates the backup communication link between two output and input CPU boards corresponding to the data transmission relationship table one by one;

[0055] For any two data-interacting output and input CPU boards, the output and input board addresses of the main communication link select the larger board address number, add 1 to the larger address number, and then take the modulus according to the total number of CPU boards in the system to determine whether the remainder is equal to the smaller board address; if not, the third-party CPU board address is the remainder; if equal, the third-party CPU board address is the remainder plus 1; thereby determining the backup communication link between the output and input CPU boards;

[0056] According to the same method, the backup communication link between the output CPU board and other input CPU boards is determined.

[0057] (3) Each CPU board automatically detects the port to determine the mapping relationship between the network port number and the board address

[0058] Each CPU board (including the system management configuration node itself) is also responsible for automatically detecting and processing the mapping relationship between the network port sequence and the board address for communication between the board and other CPU boards on the fully connected network. Based on the mapping relationship between the network port sequence and the board address, when the CPU board sends a message, the network port sequence number of the board can be determined according to the board address of the receiving message, and when the CPU board receives a message, the network port sequence number of the board can be determined according to the board address of the sending message.

[0059] Specifically, each CPU board sends a broadcast handshake request message to each network port connected to the fully connected network during the power-on initialization phase. After receiving the broadcast handshake request message, the board on the opposite side of the network port replies with a handshake response message. Through the above-mentioned interactive process of sending handshake requests and receiving handshake response messages, each CPU board can confirm the address of the board on the opposite side of each network port, that is, confirm the mapping relationship between the network port sequence and the board address for communication between this board and other CPU boards on the fully connected network.

[0060] (4) Run the primary and backup link message sending and receiving processing

[0061] When the system is running, the output CPU board composes the data to be sent into a message according to the data sending relationship table, and sends the message from the two corresponding network ports of the input CPU board of the main communication link and the input CPU board of the backup communication link according to the mapping relationship between the network port sequence number and the board address; the third-party CPU board on the backup communication link receives the message from the corresponding network port of the output CPU board of the main communication link according to the mapping relationship between the network port sequence number and the board address, and forwards the message directly from the corresponding network port of the input CPU board of the main communication link;

[0062] The input CPU board receives messages from the corresponding two network ports of the main communication link output CPU board and the backup communication link third-party CPU board according to the data reception relationship table and the mapping relationship between the communication network port sequence number and the board address; the input CPU board first determines whether the main communication link message is received and verifies it; if it is received and the verification is correct, the main communication link is used to receive data, and the main communication link received data is parsed to provide protection control business logic program use; if the main communication link message is not received or the message verification error is incorrect, the main link may fail, and the backup communication link received message is immediately verified. If it is received and the verification is correct, the backup communication link is used to receive data, and the backup communication link received data is parsed to provide protection control business logic program use; if the main and backup communication link messages fail to verify, multiple communication channel failures may occur simultaneously in the fully connected network, and the system is immediately locked and alarmed, exiting operation, prompting manual disposal.

[0063] Example 3

[0064] Embodiment 3 Figure 1 Taking the real-time data interaction system of the fully connected network shown as an example, the real-time data interaction method described in Example 2 is exemplarily described.

[0065] Specify CPU board 1 as the system management configuration node.

[0066] In the first step of the initial power-on phase, CPU board 1 completes the allocation of the output-input mapping relationship of data interaction between each CPU board on the fully connected network. Take the configuration information of the signal unidirectional input-output link relationship between CPU board 2 and CPU board 1, CPU board 3, and CPU board 4 as an example, that is, CPU board 2->CPU board 1, CPU board 2->CPU board 3, CPU board 2->CPU board 4; the system management configuration node organizes and generates the data sending relationship table of CPU board 2 and the data receiving relationship table of CPU board 1 / 3 / 4, as shown in Table 1.

[0067] Table 1 Data sending and receiving relationship table

[0068]

[0069] In the second step of the initialization power-on phase, CPU board 1 sends the above-organized data sending and receiving relationship tables to each CPU board, that is, sends 3 data sending relationship tables to CPU board 2, and sends 1 data receiving relationship table to CPU boards 1 / 3 / 4 respectively.

[0070] In the third step of the initial power-on phase, CPU board 1 completes the automatic network static topology processing of the primary and backup communication links between each CPU board on the fully connected network, that is, the system management configuration node determines the primary communication link between the two CPU boards according to the output-input mapping relationship of the data interaction between any two CPU boards, that is, the direct connection channel between the two CPU boards; further, according to the configuration information of all CPU boards, the backup communication link between the two CPU boards is determined by the static network topology algorithm in the power-on initialization phase, that is, the two CPU boards can communicate through a single forwarding of a third-party CPU board.

[0071] Combination Figure 2 , static network topology algorithm process:

[0072] Step 1: The management configuration node takes each data transmission relationship table of each output CPU board in the fully connected network as a unit, and calculates the communication main and backup links between the two output and input CPU boards corresponding to the data transmission relationship table one by one;

[0073] Step 2: According to the data transmission relationship table information of CPU board 2 obtained in Table 1, taking CPU board 2 transmission relationship table 1 as an example, confirm that the output board of the main communication link is board 2, and the input board is 1;

[0074] Step 3: Since the address 2 of the output board is the larger one, calculate 2+1=3, 3%4=3;

[0075] Step 4: determine that the calculation result 3 of step 3 is not equal to the smaller board address 1, so the standby link transfer CPU board address of CPU board 2 sending relationship table 1 (CPU board 2->CPU board 1) is 3;

[0076] Step 5: According to steps 2 to 4, confirm in sequence that the standby link transfer CPU board address of CPU board 2 sending relationship table 2 (CPU board 2->CPU board 3) is 4, and the standby link transfer CPU board address of CPU board 2 sending relationship table 3 (CPU board 2->CPU board 4) is 1;

[0077] Through the above automatic static network topology processing, the master-slave communication link information between CPU board 2 and other CPU boards is obtained, as shown in Table 2.

[0078] Table 2 Primary and standby communication link information table

[0079]

[0080] In the fourth step of the initialization power-on phase, CPU board 1 sends the above-mentioned main and backup link information to the corresponding output and input CPU boards. Taking the sending relationship table 1 of CPU board 2 as an example, its main link information (input board address is 1) and backup link information (transit node board address is 3) are sent to the output CPU board 2; the main link information (output board address is 2) and backup link information (transit node board address is 3) of the corresponding receiving relationship table (receiving relationship table 1 of CPU board 1) are sent to the input CPU board 1; at the same time, the source output board address (CPU board 2) and destination input board address (CPU board 1) of the backup link are sent to the transit node board (CPU board 3).

[0081] In the fifth step of the initialization power-on phase, CPU board 1 / 2 / 3 / 4 completes the automatic detection and processing of the mapping relationship between the network port serial number and the board address for communicating with other boards on the fully connected network, and obtains the mapping relationship between the network port serial number of each board and the address of the opposite board.

[0082] Taking CPU board 2 as an example, the specific detection process is as follows:

[0083] Step 1: CPU board 2 sends handshake request messages to network ports 1 / 2 / 3 respectively, and the target board address is broadcast;

[0084] Step 2: CPU board 1 / 3 / 4 receives the handshake request message from CPU board 2, and sends the handshake response message back from the receiving network port point-to-point. The handshake response message contains the address information of the CPU board from which the message was sent (i.e., CPU board 1 / 3 / 4).

[0085] Step 3: CPU board 2 receives the handshake response messages from CPU board 1 / 3 / 4 from the 1st / 2nd / 3rd network ports respectively, confirming the address mapping relationship between the 1st / 2nd / 3rd network ports of this board and the opposite board, that is, the 1st network port is connected to CPU board 1; the 2nd network port is connected to CPU board 3; and the 3rd network port is connected to CPU board 4.

[0086] In the sixth step of the initialization power-on phase, CPU board 1 / 2 / 3 / 4 combines the above-mentioned communication primary and backup link information and the mapping relationship between the network port serial number and the address of the opposite side board card to obtain the sending and receiving network port serial numbers corresponding to the communication primary and backup link information; taking CPU board 2 as an example, as shown in Table 3 and Table 4.

[0087] Table 3. The sequence table of the sending network ports of the primary and standby communication links

[0088]

[0089] Table 4. Main and standby communication link receiving network port sequence table

[0090]

[0091] When the system is put into operation, the management configuration node (CPU board 1) in the system outputs the real-time data interaction rhythm control signal to each board in the fully connected network through the backplane. Other CPU boards 2 / 3 / 4 input signals through the backplane, and through the CPU interrupt IO method, trigger the real-time data interaction task to be scheduled and executed with a fixed configuration period. At the same time, CPU board 1 also inputs this signal to trigger the scheduling of the real-time data interaction task of this board. Through the above design, all CPU boards in the system can send and receive inter-board communication data in a synchronized hard-real interrupt task according to a fixed period.

[0092] Take the real-time data interaction of CPU board 2->CPU board 1 as an example. Figure 3 shown.

[0093] Step 1: CPU board 2 performs data transmission processing at the end of T1 interrupt task execution. According to the transmission data relationship table 1 in Table 3 and the corresponding primary and standby communication link transmission network port sequence number, the data to be sent to CPU board 1 by this interruption is sent out from the primary link network port 1 and the standby link network port 3 respectively;

[0094] Step 2: CPU board 3 polls network port 1 at the end of T1 interrupt task execution to query and receive the backup link message from CPU board 2->CPU board 1; after receiving the message, it forwards the backup link message from network port number 2 to CPU board 1;

[0095] Step 3: CPU board 1 first polls network port 3 to query and receive the main link message sent by CPU board 2 at the head of T2 interrupt task execution. If the message is received and the verification message passes, the message is parsed and the data is provided to the upper-layer business logic for use; if the message is not received or the message is received but the verification fails due to the main link failure of CPU board 2->CPU board 1, CPU board 1 continues to poll network port 2 to query and receive the backup link message forwarded by CPU board 3. If the message is received and the verification message passes, the message is parsed and the data is provided to the upper-layer business logic for use;

[0096] Through the above method, link hot standby redundant communication can be achieved between any other two nodes in the fully connected network. When a permanent failure occurs in the main link, the nodes can seamlessly switch to the backup link for communication without data loss at the receiving end, thus achieving fault tolerance of real-time data interaction in the fully connected network.

Claims

1. A real-time data interaction system for a fully connected network, characterized in that: A fully connected network including point-to-point cross-connections, where any two nodes on the fully connected network are directly connected through a link, and any two nodes are indirectly connected through at least one third-party node, and each node in the fully connected network corresponds to a CPU board; There is a main communication link and a backup communication link between any two CPU boards. The main communication link is a direct connection communication link between the two data exchange CPU boards, and the backup communication link is a communication link between the two data exchange CPU boards that is connected through a single forwarding of a third-party CPU board. The output CPU board sends the data to be sent from the main communication link and the backup communication link at the same time. After the third-party CPU board located on the backup communication link receives the data sent by the output CPU board, it forwards the data from the backup communication link. The input CPU board receives data sent by the output CPU board from the main communication link, and at the same time receives data sent by the output CPU board forwarded by the third-party CPU board from the backup communication link; when the input CPU board fails to receive data from the main communication link, it receives data sent by the output CPU board from the backup communication link.

2. The real-time data interaction system according to claim 1, characterized in that: The CPU board is a single-core or multi-core processor.

3. A real-time data interaction method of the real-time data interaction system according to claim 1, characterized in that: include: Designate a CPU board to serve as the system management configuration node; The system management configuration node obtains the output-input mapping relationship of data interaction between any two CPU boards according to the specified data arrangement order based on all CPU board configuration information stored thereon, and generates a data sending relationship table of the output CPU board and a data receiving relationship table of the input CPU board according to the output and input CPU boards of the data interaction between the two boards, and sends them to the output and input CPU boards respectively; The system management configuration node determines the main communication link between any two CPU boards according to the output-input mapping relationship of data interaction between any two CPU boards, and further determines the backup communication link between the two CPU boards according to the configuration information of all CPU boards through the static network topology algorithm; the system management configuration node sends the main and backup communication link information to the corresponding output and input CPU boards respectively, and also sends it to the corresponding third-party CPU boards; The data interaction output CPU board, input CPU board and third-party CPU board are all processed through automatic port detection to determine the mapping relationship between each network port sequence of this board and the board address; The output CPU board composes the data to be sent into a message according to the data sending relationship table, and sends the message from the two corresponding network ports of the input CPU board of the main communication link and the input CPU board of the backup communication link according to the mapping relationship between the network port sequence number and the board address; the third-party CPU board on the backup communication link receives the message from the corresponding network port of the output CPU board according to the mapping relationship between the network port sequence number and the board address, and forwards the message from the corresponding network port of the input CPU board; The input CPU board receives messages from the corresponding two network ports of the main communication link output CPU board and the backup communication link third-party CPU board according to the data receiving relationship table and the mapping relationship between the communication network port sequence number and the board address; The input CPU board first determines whether the main communication link message is received and verifies it; If received and verified correctly, the data is received using the main communication link; If no message from the main communication link is received or the message verification is incorrect, the message received on the backup communication link will be verified. If it is received and the verification is correct, the backup communication link will be used to receive data. If both the main and backup communication link messages fail to be verified, the system will be locked and alarmed, exiting operation and prompting manual handling.

4. The real-time data interaction method according to claim 3, characterized in that: All CPU board configuration information includes the number of boards and the communication board address of each board.

5. The real-time data interaction method according to claim 3, characterized in that: The data transmission relationship table of the output CPU board includes the source address of the transmitted data and the offset in the message, as well as the corresponding input CPU board address.

6. The real-time data interaction method according to claim 3, characterized in that: The data receiving relation table of the input CPU board includes the target address of the received data and the offset in the message, and the corresponding output CPU board address.

7. The real-time data interaction method according to claim 3, characterized in that: The system management configuration node sends the data sending relationship table, the input CPU board address, and the third-party CPU board address to the output CPU board; the system management configuration node sends the data receiving relationship table, the output CPU board address, and the third-party CPU board address to the input CPU board; the system management configuration node sends the output CPU board address and the input CPU board address to the third-party CPU board on the backup communication link.

8. The real-time data interaction method according to claim 3, characterized in that: The static network topology algorithm includes: the system management configuration node takes each data transmission relationship table of each output CPU board in the fully connected network as a unit, and calculates the backup communication link between two output and input CPU boards corresponding to the data transmission relationship table one by one; For any two data-interacting output and input CPU boards, the output and input board addresses of the main communication link select the larger board address number, add 1 to the larger address number, and then take the modulus according to the total number of CPU boards in the system to determine whether the remainder is equal to the smaller board address; if not, the third-party CPU board address is the remainder; if equal, the third-party CPU board address is the remainder plus 1; thereby determining the backup communication link between the output and input CPU boards; According to the same method, the backup communication link between the output CPU board and other input CPU boards is determined.

9. The real-time data interaction method according to claim 3, characterized in that: The automatic port detection process includes: each CPU board sends a broadcast handshake request message to each network port connected to the board and the fully connected network, and the board on the opposite side of the network port replies with a handshake response message after receiving the broadcast handshake request message; each CPU board can confirm the address of the board on the opposite side of each network port through the interactive process of sending handshake requests and receiving handshake response messages, that is, confirm the mapping relationship between the network port sequence port and the board address for communication between the board and other CPU boards on the fully connected network.

10. The real-time data interaction method according to claim 9, characterized in that: Based on the mapping relationship between the network port sequence number and the board address, when the output CPU board sends a message, the sending network port sequence number of this board can be determined according to the receiving message board address; when the input CPU board receives a message, the receiving network port sequence number of this board can be determined according to the sending message board address.

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