Master-slave all-in-one machine based on I2C communication protocol on SoC

Abstract

The invention discloses a master-slave all-in-one machine based on an I2C (Inter-Integrated Circuit) communication protocol on an SoC (System on Chip), and an all-in-one machine module can be integrated on the SoC and comprises an I2C host module, an I2C slave module, a state machine module and an FIFO (First In First Out) module. The system can be flexibly configured as a host or a slave through an APB bus, is suitable for different application scenes and system requirements, supports multiple communication modes (standard, high-speed and fast modes), and can be compatible with multiple devices. Through the optimized state machine design and the FIFO data buffering mechanism, efficient data transmission can be achieved, data loss and delay are reduced, and the overall communication performance is improved. When the slave is used as a reading source, an intelligent waiting mechanism is adopted, the transaction of the host can be automatically suspended when the data is not ready, the validity and integrity of the data are ensured, and thus the communication error rate is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a master-slave integrated machine module based on an I2C communication protocol implemented on a system-level chip. Background Art

[0002] In modern electronic devices, the I2C communication protocol is widely used for data transmission and control between different devices. The I2C module implements serial data transmission through the data line (SDA) and the clock line (SCL). This communication method is suitable for short-distance, low-speed data transmission scenarios, such as communication between SoC and peripheral devices such as sensors and memory. During data transmission, the I2C module converts the data from parallel format to serial format for transmission, and converts the serial data back to parallel format when receiving. SoC can control external devices through the I2C module. For example, it can read sensor data, configure memory parameters, control the switch of LEDs, etc. The I2C protocol supports the connection of multiple hosts (Master) and multiple slaves (Slave), so the SoC can control multiple slave devices as a host, or it can be controlled by other hosts as a slave.

[0003] The use of I2C module greatly simplifies the circuit design. Since only two lines (SDA and SCL) are needed to realize communication and control between multiple devices, a large number of pin resources can be saved and the circuit complexity can be reduced. The I2C module adopts low-power design during data transmission and is suitable for application scenarios with high power requirements. By optimizing the communication protocol and circuit design, the power consumption during I2C communication can be reduced.

[0004] Since the I2C module supports multiple transmission rates and communication modes (such as standard mode, fast mode, and high-speed mode, etc.), it can be flexibly configured according to the needs of specific application scenarios. In addition, the I2C module also supports advanced functions such as interrupt mode and DMA (Direct Memory Access), which further enhances the flexibility and performance of the system. The I2C module has good compatibility and can connect to many different types of peripheral devices. These devices may use different technical standards and voltage levels, but they can all communicate and be controlled through the I2C module.

[0005] Existing I2C modules usually only support the connection between a single master device and multiple slave devices, and have certain limitations in long-distance communication, power consumption management, timing and signal integrity.

[0006] Foreign countries started research on I2C modules earlier and the technology is relatively mature, but domestic research in this field still needs to be strengthened. The shortcomings of existing technologies mainly include:

[0007] Communication distance limitation: Signal attenuation and noise interference will affect data accuracy during long-distance transmission of I2C communication.

[0008] Single-master device limitation: The I2C protocol does not support communication between multiple master devices, which limits its application in complex networks.

[0009] Power consumption issue: The power consumption of existing I2C modules still needs to be further optimized to meet the needs of mobile devices and IoT technology.

[0010] Signal integrity challenges: In high-speed I2C communications, timing and signal integrity issues can cause communication errors.

[0011] Insufficient module integration and compatibility: With the development of SoC technology, the requirements for the integration and compatibility of I2C modules are increasing, but the existing modules are still insufficient in this regard. Summary of the invention

[0012] The purpose of the present invention is to provide a master-slave integrated machine module based on the I2C communication protocol on a SoC, which can overcome the shortcomings of the prior art and improve the flexibility and reliability of I2C communication. The module can realize two-way communication on the SoC and support multiple configuration modes.

[0013] The technical solution adopted to solve the above technical problems is: a master-slave integrated machine based on the I2C communication protocol on a SoC, wherein the integrated machine module can be integrated on a system-on-chip (SoC), and the module includes:

[0014] I2C master module, used to initiate communication, control SCL and SDA buses, send and receive data;

[0015] I2C slave module, used to respond to the host's request, send and receive data;

[0016] The state machine module is used to manage the state transition of I2C communication, including the processing of start bit, stop bit, address bit, data bit and response bit;

[0017] FIFO module, used to store sent and received data, supports continuous frame processing.

[0018] Furthermore, the integrated module is configured as a host or a slave through an APB bus, supports high speed (Hs) and fast / standard (F / S) modes, and has a configurable divider.

[0019] Furthermore, the states defined by the state machine module include IDLE, READ_START, WRITE_START, ADDRESS, READ_DATA, WRITE_DATA, REPEAT_START and STOP.

[0020] Furthermore, the FIFO module has a depth of 16×8 bits, supporting data processing of consecutive frames.

[0021] Furthermore, the integrated machine module has an intelligent waiting mechanism. When the slave serves as a reading source, if the data is not ready, it notifies the host to suspend the transaction by pulling down the SCL signal.

[0022] Furthermore, the all-in-one module is designed with error handling logic, which can deal with abnormal situations during the communication process and generate an interrupt signal to notify the SoC to process the I2C communication event.

[0023] Furthermore, the all-in-one module supports multiple transmission rates and communication modes, and can be flexibly configured according to the requirements of specific application scenarios.

[0024] Furthermore, the register configuration options of the integrated module include registers selected as a host or a slave, a control register, an address register, a data register and a timing parameter register.

[0025] Furthermore, the register configuration options include:

[0026] IIC_choose register is used to select master or slave mode;

[0027] The IIC_ctrl register is used to control the start, stop and interrupt enable of I2C communication;

[0028] IIC_address register, used to configure the slave address;

[0029] IIC_txfifo and IIC_rxfifo registers are used to send and receive data.

[0030] Furthermore, the all-in-one module can perform bidirectional communication with external devices through an APB interface, and supports the connection of multiple hosts and multiple slaves.

[0031] The beneficial effects of the present invention are as follows:

[0032] The present invention can be flexibly configured as a host or a slave through the APB bus, adapting to different application scenarios and system requirements, supporting multiple communication modes (standard, high-speed, fast mode), making it compatible with a variety of devices.

[0033] Through the optimized state machine design and FIFO data buffer mechanism, the present invention can achieve efficient data transmission, reduce data loss and delay, and improve overall communication performance. When the slave is used as the reading source, an intelligent waiting mechanism is adopted to automatically suspend the host's transaction when the data is not ready, ensuring the validity and integrity of the data, thereby reducing the communication error rate.

[0034] The present invention has designed a sound error handling logic, which can actively detect and handle abnormal situations in the communication process, such as timeouts, data errors, etc., and generate interrupt signals in time to notify the SoC to perform corresponding processing, thereby improving the stability and reliability of the system. Through reasonable design and control strategies, the module has excellent power consumption performance in standby and working states, and is suitable for mobile devices and Internet of Things applications, meeting the demand for low power consumption.

[0035] In addition, the present invention integrates the master-slave all-in-one function into the SoC, reduces the number and complexity of external devices, reduces the design cost and volume of the system, and improves the integration and reliability of the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a design structure diagram of the present invention;

[0037] Figure 2 It is a state machine diagram when the present invention is used as a master host;

[0038] Figure 3 It is a state machine diagram of the present invention when it acts as a slave machine;

[0039] Figure 4 It is a read and write timing diagram of the module of the present invention;

[0040] Figure 5 It is a timing diagram of handshake signals of the present invention;

[0041] Figure 6 It is a timing diagram of the feedback handshake signal of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] In this embodiment, a master-slave integrated machine based on an I2C communication protocol on a SoC, the integrated machine module can be integrated on a system-on-chip (SoC), and the module includes:

[0044] I2C master module, used to initiate communication, control SCL and SDA buses, send and receive data;

[0045] I2C slave module, used to respond to the host's request, send and receive data;

[0046] The state machine module is used to manage the state transition of I2C communication, including the processing of start bit, stop bit, address bit, data bit and response bit;

[0047] FIFO module, used to store sent and received data, supports continuous frame processing.

[0048] In a preferred embodiment, the integrated machine module is configured as a host or a slave through the APB bus, supports high speed (Hs) and fast / standard (F / S) modes, and has a configurable divider.

[0049] In a preferred embodiment, the states defined by the state machine module include IDLE, READ_START, WRITE_START, ADDRESS, READ_DATA, WRITE_DATA, REPEAT_START and STOP.

[0050] In a preferred embodiment, the FIFO module has a depth of 16×8 bits, supporting data processing of consecutive frames.

[0051] In a preferred embodiment, the integrated machine module has an intelligent waiting mechanism. When the slave acts as a reading source, if the data is not ready, it notifies the host to suspend the transaction by pulling down the SCL signal.

[0052] In a preferred embodiment, the all-in-one module is designed with error handling logic, which can deal with abnormal situations during the communication process and generate an interrupt signal to notify the SoC to process the I2C communication event.

[0053] In a preferred embodiment, the all-in-one module supports multiple transmission rates and communication modes, and can be flexibly configured according to the requirements of specific application scenarios.

[0054] In a preferred embodiment, the register configuration options of the integrated module include registers selected as a host or a slave, a control register, an address register, a data register, and a timing parameter register.

[0055] In a preferred embodiment, the register configuration options include:

[0056] IIC_choose register is used to select master or slave mode;

[0057] The IIC_ctrl register is used to control the start, stop and interrupt enable of I2C communication;

[0058] IIC_address register, used to configure the slave address;

[0059] IIC_txfifo and IIC_rxfifo registers are used to send and receive data.

[0060] In a preferred embodiment, the integrated machine module can perform bidirectional communication with external devices through an APB interface, and supports the connection of multiple hosts and multiple slaves.

[0061] The specific working process of the present invention is as follows:

[0062] Whenever you use the master-slave module, you must first configure the two-choice selector through the apb interface to make the module choose between master mode and slave mode. When the master mode is selected, if you want to use interrupts, you need to enable the required interrupts in the register at address 04H. By default, interrupts are all shielded. When writing data, you must first write the slave address and the data to be sent into the txfifo register. When reading data, the data is also read from the rxfifo. If necessary, you can also configure the setup time and hold time of the SCL data line.

[0063] Refer to the instruction manual Figure 4 Read and write timing diagram.

[0064] Writing data process:

[0065] 1. The host sends an I2C bus start signal;

[0066] 2. The host sends the I2C slave address and write mode (W / R=0) signal, and waits for a response signal from the slave;

[0067] 3. After receiving the ACK response signal, the host sends an 8-bit register address and waits for a response signal from the slave;

[0068] 4. Execute step 3 three more times to complete the 32-bit register address sending;

[0069] 5. After receiving the ACK response signal, the host sends an 8-bit data (dummy) and waits for a response signal from the slave;

[0070] 6. After receiving the ACK response signal, the host sends an 8-bit data and waits for a response signal from the slave;

[0071] 7. Perform step 6 three more times to complete the 32-bit data transmission;

[0072] 8. After the host receives the ACK response signal, it sends the I2C bus end signal to stop;

[0073] 9. When the slave receives a data, it will generate AXI master write timing;

[0074] 10. If the previous data AXI master is not completed, the I2C slave will return NACK in step 2 of the next write to notify the host to rewrite.

[0075] Reading data process:

[0076] 1. The host sends an I2C bus start signal;

[0077] 2. The host sends the I2C slave address and write mode (W / R=0) signal, and waits for a response signal from the slave;

[0078] 3. After receiving the ACK response signal, the host sends an 8-bit register address (MSB) and waits for a response signal from the slave;

[0079] 4. Execute step 3 three more times to complete the 32-bit register address sending;

[0080] 5. After receiving the ACK response signal, the host resends the I2C bus start signal;

[0081] 6. At this time, an AXI master read is generated and data is filled into the tx buffer;

[0082] 7. The host sends the I2C slave address and read mode (W / R=1) signal, and waits for a response signal from the slave;

[0083] 8. After the slave returns the ACK response signal, it returns a byte of status data and waits for a response signal from the host;

[0084] 9. After receiving the ACK response signal, the slave returns a byte of valid data and waits for a response signal from the host;

[0085] 10. Execute step 9 three more times to complete the 32-bit data return;

[0086] 11. After the host sends the NACK signal, it sends the I2C bus end signal.

[0087] Note: The lowest bit of the status data indicates that the data is valid, otherwise the returned data is invalid. If the read data is invalid, it is recommended that the host read until the data is valid to form a closed loop. Otherwise, the next read of other addresses will return the last valid data. When the host returns NACK, the read sequence needs to be resent.

[0088] Read status handshake mechanism (handshake signal timing diagram as shown Figure 5 (shown)

[0089] A complete i2c master read will only generate one axi bus read request until the i2c slave returns valid read data (during which there may be multiple i2c master read sequences); the next i2c master read will generate a new axi bus read request.

[0090] Read valid status return mechanism: After each complete i2c read, the first read restart will generate a read data request (rdata_updata_req), axi rvalid is high to clear the read data request, and generate a read data updated signal (rdata_update). When the second to last data in the read data feedback state is detected, determine whether the current data is ready. If it is ready, set the rdata_ready signal. When the first to last data in the read data feedback state is detected, determine whether sda is high and then clear the rdata_ready signal.

[0091] Write feedback handshake mechanism (feedback handshake signal timing diagram as shown Figure 6 (shown)

[0092] Each time the fourth valid data is written, a wdata_ready valid signal is generated, which is not cleared until axibvalid is high. This signal is used as a basis for determining whether to return NACK in the ACK phase after the device address is sent. It can be seen that if wdata_ready is always in a valid state, the ACK in the device address phase will always return NACK, and the I2C protocol will always be blocked.

[0093] The present invention selects to be a master or a slave through register configuration, and the configurable registers are shown in Table 1 below:

[0094]

[0095]

[0096] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A master-slave integrated machine based on I2C communication protocol on SoC, characterized by: The all-in-one module includes: I2C master module, used to initiate communication, control SCL and SDA buses, send and receive data; I2C slave module, used to respond to the host's request, send and receive data; The state machine module is used to manage the state transition of I2C communication, including the processing of start bit, stop bit, address bit, data bit and response bit; FIFO module, used to store sent and received data, supports continuous frame processing.

2. The master-slave integrated machine based on the I2C communication protocol according to claim 1, characterized in that: The all-in-one module is configured as a host or a slave through the APB bus, supports high speed (Hs) and fast / standard (F / S) modes, and has a configurable divider.

3. The master-slave integrated machine based on the I2C communication protocol according to claim 1, characterized in that: The states defined by the state machine module include IDLE, READ_START, WRITE_START, ADDRESS, READ_DATA, WRITE_DATA, REPEAT_START and STOP.

4. The master-slave integrated machine based on the I2C communication protocol according to claim 1, characterized in that: The FIFO module has a depth of 16×8 bits and supports data processing of consecutive frames.

5. The master-slave integrated machine based on the I2C communication protocol according to claim 1, characterized in that: The integrated machine module has an intelligent waiting mechanism. When the slave is used as a reading source, if the data is not ready, it notifies the host to suspend the transaction by pulling down the SCL signal.

6. The master-slave integrated machine based on the I2C communication protocol according to any one of claims 1 to 5, characterized in that: The all-in-one module is designed with error handling logic, which can deal with abnormal situations during the communication process and generate an interrupt signal to notify the SoC to process the I2C communication event.

7. The master-slave integrated machine based on the I2C communication protocol according to any one of claims 1 to 6, characterized in that: The all-in-one module supports multiple transmission rates and communication modes, and can be flexibly configured according to the needs of specific application scenarios.

8. The master-slave integrated machine based on the I2C communication protocol according to any one of claims 1 to 7, characterized in that: The register configuration options of the integrated module include registers selected as a host or a slave, a control register, an address register, a data register and a timing parameter register.

9. The master-slave integrated machine based on the I2C communication protocol according to claim 8, characterized in that: The register configuration options include: IIC_choose register is used to select master or slave mode; The IIC_ctrl register is used to control the start, stop and interrupt enable of I2C communication; IIC_address register, used to configure the slave address; IIC_txfifo and IIC_rxfifo registers are used to send and receive data.

10. The master-slave integrated machine based on the I2C communication protocol according to any one of claims 1 to 9, characterized in that: The all-in-one module can perform bidirectional communication with external devices through the APB interface and supports the connection of multiple hosts and multiple slaves.

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