FPGA single event upset detection system and method

Abstract

The invention discloses an FPGA single event upset detection system and method, and relates to the field of FPGA testing, and the system comprises an upper computer, a test bottom plate and a test daughter board. The test daughter board comprises an FPGA to be tested; the test base plate configures an original code stream file sent by the upper computer to the to-be-tested FPGA, gradually increases the same fluence to perform single-particle irradiation tests of multiple test periods on the to-be-tested FPGA, and reads back the read-back code stream file of each test period; and the upper computer compares the read-back code stream file of the current test period with the read-back code stream file of the previous test period, determines the occurrence position of single event upset in the current test period, and accumulates the single event upset number of each occurrence position to obtain the total single event upset number under the total fluence of the current test period. The problems that the single event upset occurrence position cannot be detected and the situation that single event upset of the same circuit unit is carried out for multiple times cannot be detected are solved.

Description

Technical Field

[0001] The present application relates to the field of field programmable gate array (FPGA) testing, and in particular to an FPGA single particle upset detection system and method. Background Art

[0002] With the development of integrated circuit technology, the application of FPGA in the aerospace field has put forward higher requirements for reliability. Therefore, reliability has gradually become an important issue that needs to be considered as important as performance when designing FPGA. Especially in the space environment, FPGA is easily affected by single particle effects, which can cause the contents of the logic cells in the FPGA to flip and lock, resulting in FPGA failure. Before designing a fault-tolerant FPGA, it is necessary to conduct an in-depth single particle effect sensitivity analysis, especially the behavioral characteristics of the FPGA when a single particle effect occurs. The detection of single particle flip is an important technology for FPGA reliability assessment, so the research and design of single particle flip detection tools are of great significance.

[0003] The related single-particle upset detection method is to read back the configuration file from the FPGA and compare it with the original configuration file, and transmit the error number to the host computer through the serial port for analysis. The main disadvantages of this method are: in the single-particle upset test, only the number of upsets can be obtained, and the specific location of the upset cannot be known, making it difficult to perform targeted single-particle reinforcement on the FPGA; at the same time, the single-particle upset of each circuit unit can only be recorded once at most, and the situation where the same circuit unit flips more than twice cannot be recorded, resulting in the most sensitive area of ​​single-particle upsets being ignored during radiation reinforcement. Summary of the invention

[0004] The purpose of the present application is to provide an FPGA single particle upset detection system and method, which solves the problem of being unable to detect the location where the single particle upset occurs and being unable to detect multiple single particle upsets in the same circuit unit.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides an FPGA single-particle upset detection system, the FPGA single-particle upset detection system comprising: a host computer, a test baseboard and a test subboard; the test subboard comprises: an FPGA to be tested; the host computer is connected to the test baseboard; the test baseboard is connected to the FPGA to be tested;

[0007] The host computer is used for:

[0008] Sending the original code stream file to the test baseboard;

[0009] The test base plate is used for:

[0010] Configuring the original code stream file on the FPGA to be tested;

[0011] Under the single particle upset test, the code stream file of the FPGA to be tested is read back in each test cycle to obtain the read-back code stream file of each test cycle; the single particle upset test is a test for single particle irradiation of the FPGA to be tested by increasing the same injection amount from the first test cycle to the last test cycle; the total injection amount of the last test cycle reaches the rated total injection amount;

[0012] Send the readback code stream file of each test cycle to the host computer;

[0013] The host computer is also used for:

[0014] The readback code stream file of the current test cycle is compared with the readback code stream file of the previous test cycle to determine the occurrence position of the single-particle upset in the current test cycle, and the number of single-particle upsets at each occurrence position is accumulated to obtain the total number of single-particle upsets under the total injection of the current test cycle.

[0015] Optionally, in the single particle upset test, in terms of reading back the code stream file of the FPGA to be tested in each test cycle to obtain the read-back code stream file of each test cycle, the test baseboard is specifically used for:

[0016] Under the single-particle upset test, for any test cycle, a triple-modular redundant structure is used to read back the triple-modular redundant code stream of the current test cycle; the triple-modular redundant code stream includes: a first code stream file, a second code stream file, and a third code stream file of the FPGA to be tested;

[0017] According to the triple-modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

[0018] Optionally, the test base plate is also used for:

[0019] In the single-particle upset test, for any test cycle, the source determiner is used to determine the number of single-particle transients based on the triple-modular redundant code stream of the current test cycle.

[0020] Optionally, the test baseboard includes: a processing FPGA and a memory; the processing FPGA is connected to the host computer, the memory and the FPGA to be tested respectively;

[0021] The processing FPGA is used to:

[0022] Sending the original code stream file to the memory;

[0023] The memory is used for:

[0024] caching the original code stream file;

[0025] The processing FPGA is also used for:

[0026] Configuring the original code stream file cached in the memory onto the FPGA to be tested;

[0027] Under the single particle upset test, read back the bit stream file of the FPGA to be tested in each test cycle to obtain the read-back bit stream file of each test cycle;

[0028] The memory is also used for:

[0029] Cache the readback code stream file of each test cycle;

[0030] The processing FPGA is also used for:

[0031] The read-back code stream file of each test cycle cached in the memory is sent to the host computer.

[0032] Optionally, the processing FPGA includes: a data control module, an Ethernet interface and a SelectMap interface;

[0033] The data control module is connected to the memory; the data control module is connected to the host computer via the Ethernet interface; the data control module is connected to the FPGA to be tested via the SelectMap interface;

[0034] The Ethernet interface is used for:

[0035] Sending the original code stream file to the data control module;

[0036] The data control module is used for:

[0037] Sending the original code stream file to the memory;

[0038] The original code stream file cached in the memory is configured to the FPGA to be tested through the SelectMap interface;

[0039] Under the single particle upset test, the code stream file of the FPGA to be tested is read back through the SelectMap interface in each test cycle to obtain the read-back code stream file of each test cycle;

[0040] The read-back code stream file of each test cycle cached in the memory is sent to the host computer through the Ethernet interface.

[0041] Optionally, the processing FPGA further comprises: a serial port;

[0042] The data control module is connected to the host computer via the serial port;

[0043] The serial port is used to send control instructions to the host computer; the control instructions include: code stream input instructions, code stream configuration instructions, code stream read back instructions and memory read instructions;

[0044] The host computer is used for:

[0045] When receiving the code stream input instruction, controlling the Ethernet interface to send the original code stream file to the data control module and cache it in the memory;

[0046] When the bitstream configuration instruction is received, the original bitstream file cached in the memory is controlled to be configured on the FPGA to be tested through the SelectMap interface;

[0047] When the code stream readback instruction is received, the SelectMap interface is controlled to read back the code stream file of the FPGA to be tested in the current test cycle, obtain the readback code stream file of the current test cycle, and cache it in the memory;

[0048] When the memory read instruction is received, the Ethernet interface is controlled to obtain the readback code stream file of the current test cycle cached in the memory.

[0049] Optionally, the source determiner is an AND gate.

[0050] In a second aspect, the present application provides an FPGA single particle upset detection method, which is used in the above-mentioned FPGA single particle upset detection system, and the FPGA single particle upset detection method includes:

[0051] Get the original code stream file;

[0052] Configuring the original code stream file on the FPGA to be tested;

[0053] Under the single particle upset test, the code stream file of the FPGA to be tested is read back in each test cycle to obtain the read-back code stream file of each test cycle; the single particle upset test is a test for single particle irradiation of the FPGA to be tested by increasing the same injection amount from the first test cycle to the last test cycle; the total injection amount of the last test cycle reaches the rated total injection amount;

[0054] Send the readback code stream file of each test cycle to the host computer;

[0055] The host computer compares the readback code stream file of the current test cycle with the readback code stream file of the previous test cycle, determines the occurrence position of the single particle upset in the current test cycle, and accumulates the number of single particle upsets at each occurrence position to obtain the total number of single particle upsets under the total injection amount of the current test cycle.

[0056] Optionally, in a single particle upset test, reading back the bitstream file of the FPGA to be tested in each test cycle to obtain the readback bitstream file of each test cycle specifically includes:

[0057] Under the single-particle upset test, for any test cycle, a triple-modular redundant structure is used to read back the triple-modular redundant code stream of the current test cycle; the triple-modular redundant code stream includes: a first code stream file, a second code stream file, and a third code stream file of the FPGA to be tested;

[0058] According to the triple-modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

[0059] Optionally, after obtaining the triple-mode redundant code stream of the current test cycle, the FPGA single-event upset detection method further includes:

[0060] According to the triple-modular redundant code stream of the current test cycle, a source determiner is used to determine the number of single-particle transients.

[0061] According to the specific embodiments provided in this application, this application has the following technical effects:

[0062] The present application provides a FPGA single-particle upset detection system and method, the system comprising: a host computer, a test baseboard and a test subboard; the test subboard comprises: an FPGA to be tested; the test baseboard adopts an incremental detection method to read back the readback code stream file of each test cycle, and the host computer compares the readback code stream file of the current test cycle with the readback code stream file of the previous test cycle, so as to not only determine the occurrence position of the single-particle upset in the current test cycle, but also obtain the total number of single-particle upsets under the total injection amount of the current test cycle, thereby solving the problem that the occurrence position of the single-particle upset cannot be detected and the situation that the single-particle upset of the same circuit unit cannot be detected multiple times. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1This is a structural schematic diagram of an FPGA single-particle upset detection system in an embodiment of the present application;

[0065] Figure 2 A schematic diagram of a triple-module redundancy structure provided in one embodiment of the present application;

[0066] Figure 3 A schematic diagram of a flow chart of an FPGA single-particle upset detection method provided in another embodiment of the present application. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0068] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0069] See also Figure 1 The embodiment of the present application provides an FPGA single-particle upset detection system, including: a host computer, a test baseboard and a test sub-board; the test sub-board includes: an FPGA to be tested; the host computer is connected to the test baseboard; the test baseboard is connected to the FPGA to be tested.

[0070] The host computer is used to send the original code stream file to the test baseboard, wherein the original code stream file is an FPGA configuration file in a binary file format.

[0071] The test baseboard is used to configure the original code stream file to the FPGA to be tested. Under the single-particle flip test, the code stream file of the FPGA to be tested is read back in each test cycle to obtain the read-back code stream file of each test cycle; the single-particle flip test is a test for single-particle irradiation of the FPGA to be tested by gradually increasing the same injection amount from the first test cycle to the last test cycle. The read-back code stream file of each test cycle is sent to the host computer. Among them, the total injection amount of the first test cycle is the initial total injection amount, and the total injection amount of the last test cycle reaches the rated total injection amount. The injection amount increased each time is the same, and the total injection amount each time increases cumulatively from the initial total injection amount until the rated total injection amount is reached. For example, the rated total injection amount is 10 7 In the single-particle upset test, the readback code stream file obtained immediately after configuration is the readback code stream file of the first test cycle, and then the total injection amount is increased by 10% (i.e. 10 6particles) until the total injection reaches the rated total injection 10 7 Among them, readback means that the FPGA to be tested sends its own configuration file to the receiving end of the test baseboard.

[0072] The host computer is also used to compare the readback code stream file of the current test cycle with the readback code stream file of the previous test cycle, determine the occurrence position of the single particle upset in the current test cycle, and accumulate the number of single particle upsets at each occurrence position to obtain the total number of single particle upsets under the total injection of the current test cycle. The host computer can be a computer that sends operation commands to the test baseboard and performs post-analysis on the data.

[0073] In this embodiment, the host computer is placed in the test monitoring room for test setting, test process control and test result processing; the test base plate and the test sub-board are placed in the irradiation test room.

[0074] This embodiment sends the complete readback code stream file to the host computer to obtain the occurrence positions of all single-particle upsets, thereby solving the problem that the single-particle upset test cannot obtain the precise occurrence position; an incremental detection method is adopted, and the readback code stream file of each test cycle is compared with the readback code stream file of the previous test cycle, rather than compared with the original code stream file, thereby solving the problem that the single-particle upset of the same circuit unit can only be detected once, that is, it is possible to detect multiple single-particle upsets of the same circuit unit.

[0075] In an exemplary embodiment, in terms of reading back the code stream file of the FPGA to be tested in each test cycle under a single-particle flip test to obtain the read-back code stream file for each test cycle, the test baseboard is specifically used for: under a single-particle flip test, for any test cycle, using a triple-modular redundancy (TMR) structure to read back the triple-modular redundant code stream of the current test cycle; the triple-modular redundant code stream includes: the first code stream file, the second code stream file and the third code stream file of the FPGA to be tested. Based on the triple-modular redundant code stream of the current test cycle, a majority voter is used to determine the read-back code stream file for the current test cycle. The schematic diagram of the triple-modular redundant structure is shown in FIG. Figure 2 shown.

[0076] Among them, triple-mode redundancy is a common single-particle effect mitigation method. Using three identical redundant computing paths, all redundant units should have the same output when there is no fault. The output of each redundant unit is compared with the other redundant units through the majority voter. If the output of one redundant unit is inconsistent with the other two redundant units, the majority voter will still produce the correct output.

[0077] In an exemplary embodiment, due to the related FPGA single-particle upset detection method, the periodic code stream readback is performed in an irradiated environment, and it is impossible to confirm whether the error in the readback code stream is caused by the single-particle upset of the device or the single-particle transient during the code stream reading process. Therefore, please refer to Figure 2 The test baseboard in this embodiment is also used for: in a single-particle upset test, for any test cycle, according to the triple-modular redundant code stream of the current test cycle, using a source determiner to determine the number of single-particle transients. The source determiner may be an AND gate.

[0078] This embodiment separates the errors introduced by dynamic readback in the single particle test, and further improves the accuracy of the single particle test by comparing the redundant data (i.e., the triple-modular redundant code stream). At the same time, by comparing the results of each path in the triple-modular redundant code stream, the single particle transient phenomenon in the readback process can be analyzed.

[0079] In an exemplary embodiment, see Figure 1 The test baseboard includes: a processing FPGA and a memory; the processing FPGA is connected to the host computer, the memory and the FPGA to be tested respectively.

[0080] The processing FPGA is used to send the original code stream file to the memory.

[0081] The memory is used to cache the original code stream file.

[0082] The processing FPGA is also used to: configure the original code stream file cached in the memory to the FPGA to be tested. Under the single particle upset test, read back the code stream file of the FPGA to be tested in each test cycle to obtain the read-back code stream file of each test cycle.

[0083] The memory is also used to cache the read-back code stream file of each test cycle.

[0084] The processing FPGA is also used to send the read-back code stream file of each test cycle cached in the memory to the host computer.

[0085] In this embodiment, the memory may be a double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR).

[0086] In an exemplary embodiment, due to the insufficient transmission rate of the serial port, it takes more than one minute to configure and read back a large-scale FPGA, and the real-time and accuracy of the detection results cannot be guaranteed. Figure 1In this embodiment, the processing FPGA includes: a data control module, an Ethernet interface, and a SelectMap interface. The data control module is connected to the memory; the data control module is connected to the host computer through the Ethernet interface; the data control module is connected to the FPGA to be tested through the SelectMap interface. Among them, the SelectMap interface is an interface inherent to the FPGA that is configured through input and output pins.

[0087] The Ethernet interface is used to send the original code stream file to the data control module.

[0088] The data control module is used to: send the original code stream file to the memory. Configure the original code stream file cached in the memory to the FPGA to be tested through the SelectMap interface. Under the single particle flip test, read back the code stream file of the FPGA to be tested in each test cycle through the SelectMap interface to obtain the read-back code stream file for each test cycle. Send the read-back code stream file of each test cycle cached in the memory to the host computer through the Ethernet interface.

[0089] In this embodiment, before the single-particle upset test, the data control module sends the initial code stream file received by the Ethernet interface to the memory, and then reads the stored initial code stream file from the memory and sends it to the SelectMap interface for configuration; during the single-particle upset test, the data control module regularly moves the code stream file read back from the FPGA to be tested input by the SelectMap interface to the memory, and then reads the stored read-back code stream file from the D memory and sends it to the Ethernet interface, and then the host computer compares it with the read-back code stream file of the previous test cycle to calculate the precise occurrence position of the single-particle upset in each test cycle. In this embodiment, the use of the Ethernet interface to transmit the code stream file can greatly reduce the time required for transmission, provide a hardware foundation for redundant data transmission, and improve the real-time and accuracy of single-particle upset detection.

[0090] In an exemplary embodiment, see Figure 1 , the processing FPGA also includes: a serial port; the data control module is connected to the host computer through the serial port.

[0091] The serial port is used to send control instructions to the host computer; the control instructions include: code stream input instructions, code stream configuration instructions, code stream read back instructions and memory read instructions.

[0092] The host computer is used to: when receiving the code stream input instruction, control the Ethernet interface to send the original code stream file to the data control module and cache it in the memory. When receiving the code stream configuration instruction, control the original code stream file cached in the memory to be configured on the FPGA to be tested through the SelectMap interface. When receiving the code stream readback instruction, control the SelectMap interface to read back the code stream file of the FPGA to be tested in the current test cycle, obtain the readback code stream file of the current test cycle, and cache it in the memory. When receiving the memory read instruction, control the Ethernet interface to obtain the readback code stream file of the current test cycle cached in the memory.

[0093] In this embodiment, the host computer and the test baseboard transmit data through the serial port and the Ethernet interface, and the test baseboard and the test daughter board transmit data through the FPGA mezzanine card (FPGA Mezzanine Card, FMC) interface.

[0094] In practical applications, a specific implementation process of the FPGA single-particle upset detection system of the above embodiment of the present application can be described as follows: (1) The host computer sends the original code stream file to the cache on the memory through the Ethernet interface; (2) The original code stream file cached in step (1) is configured on the FPGA to be tested through the SelectMap interface; (3) The single-particle irradiation source is turned on, the FPGA to be tested is subjected to single-particle irradiation, and the single-particle upset test is started; (4) Wait for a predetermined time, and use a triple-mode redundant structure to periodically read back the three-way code stream file (i.e., triple-mode redundant code stream) of the FPGA to be tested from the SelectMap interface to the cache on the memory; (5) The host computer receives the triple-mode redundant code stream cached in step (4); (6) Compare the triple-mode redundant code stream in step (4) to analyze the single-particle transient error in the path , record the number of dynamic readback single-particle transients, and calculate the readback code stream file through the majority voter and cache it in the memory, and the readback code stream file is sent from the memory to the host computer via Ethernet; (7) The host computer compares the readback code stream file of the current test cycle in step (6) with the readback code stream file of the previous test cycle bit by bit to obtain the occurrence position of the single-particle flip in this test cycle, where, if the current test cycle is the first test cycle, the readback code stream file of the current test cycle is compared with the original code stream file to obtain the occurrence position of the single-particle flip in this test cycle; (8) The number of single-particle flips at each position is accumulated to obtain the total number of single-particle flips under the total injection of the current test cycle; (9) Steps (4) to (8) are repeated until the total injection of single-particle irradiation reaches the rated total injection.

[0095] The above embodiments of the present application provide a system that realizes incremental detection of FPGA single-particle flips and transients in order to obtain the precise location of FPGA single-particle flips, detect multiple flips of single particles, distinguish the error sources of single-particle effects, and improve the real-time and accuracy of single-particle flip detection. The system can locate the specific location of FPGA single-particle flips, detect flips of more than 2 times in the same circuit unit, distinguish between static single-particle flips of devices and dynamic single-particle transients of code stream readback, and greatly shorten the time consumed by data transmission, completing the accurate detection of FPGA single-particle flips.

[0096] Another embodiment of the present application further provides an FPGA single particle upset detection method, which is used in the above-mentioned FPGA single particle upset detection system.

[0097] See also Figure 3 , the FPGA single-particle upset detection method comprises:

[0098] Step 301: Obtain the original code stream file.

[0099] Step 302: configure the original code stream file to the FPGA to be tested.

[0100] Step 303: Under the single-particle upset test, read back the bitstream file of the FPGA to be tested in each test cycle to obtain the readback bitstream file of each test cycle.

[0101] The single particle upset test is a test in which the FPGA to be tested is subjected to single particle irradiation by successively increasing the same injection amount from the first test cycle to the last test cycle; the total injection amount of the last test cycle reaches the rated total injection amount.

[0102] Step 304: Send the readback code stream file of each test cycle to the host computer.

[0103] Step 305: The host computer compares the readback code stream file of the current test cycle with the readback code stream file of the previous test cycle, determines the occurrence position of the single particle upset in the current test cycle, and accumulates the number of single particle upsets at each occurrence position to obtain the total number of single particle upsets under the total injection of the current test cycle.

[0104] In an exemplary embodiment, step 303 specifically includes: in a single event upset test, for any test cycle, using a triple modular redundancy structure to read back the triple modular redundancy code stream of the current test cycle.

[0105] The triple-module redundant code stream includes: a first code stream file, a second code stream file and a third code stream file of the FPGA to be tested.

[0106] According to the triple-modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

[0107] In an exemplary embodiment, after obtaining the triple-modular redundant code stream of the current test cycle, the FPGA single-particle upset detection method further includes: determining the number of single-particle transients using a source determiner based on the triple-modular redundant code stream of the current test cycle.

[0108] In order to solve the problems that the precise position of FPGA single particle upset cannot be obtained, the same circuit unit can detect at most one single particle upset, the source of single particle error is unknown, and the single particle upset detection lacks real-time and accuracy, the embodiment of the present application proposes an FPGA single particle upset detection method. The detection method can be described in detail as follows:

[0109] (1) Send a code stream input command through the serial port, and use the Ethernet interface to send the original code stream file to the memory for storage; (2) Send a code stream configuration command through the serial port, and configure the original code stream file in the memory to the FPGA to be tested through the SelectMap interface; (3) Establish a single-particle flip count counter for each bit of the code stream file on the host computer, and set the initial value to 0; (4) Turn on the single-particle irradiation source to perform single-particle irradiation on the FPGA to be tested; (5) Send a triple-mode redundant code stream readback command through the serial port at regular intervals (for example, every 1 second), and read the code stream file of the FPGA to be tested after irradiation back to the memory through the SelectMap interface for storage; (6) Send a memory read command through the serial port, and use the Ethernet interface to obtain the data stored in step (5) in the memory. ; (7) read back the triple-mode redundant code stream using the triple-mode redundant structure, use the majority voter to compare the triple-mode redundant code stream, and calculate and record the number of single-particle transients on the three paths through the AND gate, and use the result of the majority voter as the read-back code stream file; (8) compare the read-back code stream file of the current test cycle in step (7) with the read-back code stream file of the previous test cycle bit by bit, mark all different bits, which are the locations where the single-particle flip occurs in this test cycle; (9) accumulate the single-particle flip number counter established in step (3), add 1 to the counters of all single-particle flip positions in step (8), and keep the counters of the other positions unchanged; (10) repeat steps (5) to (9) until the total injection reaches the rated value. (11) query the circuit unit number in the FPGA to be tested corresponding to the bit of the single-particle flip number counter that is not 0 according to the inherent format of the code stream file, and determine the exact location where the flip occurs in the FPGA to be tested.

[0110] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. An FPGA single-event upset detection system, characterized in that: The FPGA single-particle upset detection system comprises: a host computer, a test baseboard and a test subboard; the test subboard comprises: an FPGA to be tested; the host computer is connected to the test baseboard; the test baseboard is connected to the FPGA to be tested; The host computer is used for: Sending the original code stream file to the test baseboard; The test base plate is used for: Configuring the original code stream file on the FPGA to be tested; Under the single particle upset test, the code stream file of the FPGA to be tested is read back in each test cycle to obtain the read-back code stream file of each test cycle; the single particle upset test is a test for single particle irradiation of the FPGA to be tested by increasing the same injection amount from the first test cycle to the last test cycle; the total injection amount of the last test cycle reaches the rated total injection amount; Send the readback code stream file of each test cycle to the host computer; The host computer is also used for: The readback code stream file of the current test cycle is compared with the readback code stream file of the previous test cycle to determine the occurrence position of the single-particle upset in the current test cycle, and the number of single-particle upsets at each occurrence position is accumulated to obtain the total number of single-particle upsets under the total injection of the current test cycle.

2. The FPGA single event upset detection system according to claim 1, characterized in that: In terms of reading back the code stream file of the FPGA to be tested in each test cycle under the single particle upset test to obtain the read-back code stream file of each test cycle, the test baseboard is specifically used for: Under the single-particle upset test, for any test cycle, a triple-modular redundant structure is used to read back the triple-modular redundant code stream of the current test cycle; the triple-modular redundant code stream includes: a first code stream file, a second code stream file, and a third code stream file of the FPGA to be tested; According to the triple-modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

3. The FPGA single event upset detection system according to claim 2, characterized in that: The test base plate is also used for: In the single-particle upset test, for any test cycle, the source determiner is used to determine the number of single-particle transients based on the triple-modular redundant code stream of the current test cycle.

4. The FPGA single event upset detection system according to claim 1, characterized in that: The test baseboard includes: a processing FPGA and a memory; the processing FPGA is connected to the host computer, the memory and the FPGA to be tested respectively; The processing FPGA is used to: Sending the original code stream file to the memory; The memory is used for: caching the original code stream file; The processing FPGA is also used for: Configuring the original code stream file cached in the memory onto the FPGA to be tested; Under the single particle upset test, read back the bit stream file of the FPGA to be tested in each test cycle to obtain the read-back bit stream file of each test cycle; The memory is also used for: Cache the readback code stream file of each test cycle; The processing FPGA is also used for: The read-back code stream file of each test cycle cached in the memory is sent to the host computer.

5. The FPGA single event upset detection system according to claim 4, characterized in that: The processing FPGA includes: a data control module, an Ethernet interface and a SelectMap interface; The data control module is connected to the memory; the data control module is connected to the host computer via the Ethernet interface; the data control module is connected to the FPGA to be tested via the SelectMap interface; The Ethernet interface is used for: Sending the original code stream file to the data control module; The data control module is used for: Sending the original code stream file to the memory; The original code stream file cached in the memory is configured to the FPGA to be tested through the SelectMap interface; Under the single particle upset test, the code stream file of the FPGA to be tested is read back through the SelectMap interface in each test cycle to obtain the read-back code stream file of each test cycle; The read-back code stream file of each test cycle cached in the memory is sent to the host computer through the Ethernet interface.

6. The FPGA single event upset detection system according to claim 5, characterized in that: The processing FPGA also includes: a serial port; The data control module is connected to the host computer via the serial port; The serial port is used to send control instructions to the host computer; the control instructions include: code stream input instructions, code stream configuration instructions, code stream read back instructions and memory read instructions; The host computer is used for: When receiving the code stream input instruction, controlling the Ethernet interface to send the original code stream file to the data control module and cache it in the memory; When the bitstream configuration instruction is received, the original bitstream file cached in the memory is controlled to be configured on the FPGA to be tested through the SelectMap interface; When the code stream readback instruction is received, the SelectMap interface is controlled to read back the code stream file of the FPGA to be tested in the current test cycle, obtain the readback code stream file of the current test cycle, and cache it in the memory; When the memory read instruction is received, the Ethernet interface is controlled to obtain the readback code stream file of the current test cycle cached in the memory.

7. The FPGA single event upset detection system according to claim 3, characterized in that: The source determiner is an AND gate.

8. A FPGA single-particle upset detection method, characterized in that: The FPGA single particle upset detection method is used in the FPGA single particle upset detection system according to any one of claims 1 to 7, and the FPGA single particle upset detection method comprises: Get the original code stream file; Configuring the original code stream file on the FPGA to be tested; Under the single particle upset test, the code stream file of the FPGA to be tested is read back in each test cycle to obtain the read-back code stream file of each test cycle; the single particle upset test is a test for single particle irradiation of the FPGA to be tested by increasing the same injection amount from the first test cycle to the last test cycle; the total injection amount of the last test cycle reaches the rated total injection amount; Send the readback code stream file of each test cycle to the host computer; The host computer compares the readback code stream file of the current test cycle with the readback code stream file of the previous test cycle, determines the occurrence position of the single particle upset in the current test cycle, and accumulates the number of single particle upsets at each occurrence position to obtain the total number of single particle upsets under the total injection amount of the current test cycle.

9. The FPGA single event upset detection method according to claim 8, characterized in that: Under the single-particle upset test, the code stream file of the FPGA to be tested is read back in each test cycle to obtain the read-back code stream file of each test cycle, specifically including: Under the single-particle upset test, for any test cycle, a triple-modular redundant structure is used to read back the triple-modular redundant code stream of the current test cycle; the triple-modular redundant code stream includes: a first code stream file, a second code stream file, and a third code stream file of the FPGA to be tested; According to the triple-modular redundant code stream of the current test cycle, a majority voter is used to determine the readback code stream file of the current test cycle.

10. The FPGA single event upset detection method according to claim 9, characterized in that: After obtaining the triple-mode redundant code stream of the current test cycle, the FPGA single-particle upset detection method further includes: According to the triple-modular redundant code stream of the current test cycle, a source determiner is used to determine the number of single-particle transients.

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