A real-time simulation method and system for large-scale cascaded H-bridges with full detail modeling
By equivalently dividing the circuit topology of a large cascaded H-bridge system into a main system and a subsystem, and using controlled voltage sources, current sources, and circuit breaker bypass switches for control, a full physical I/O interaction hardware-in-the-loop test of the large cascaded H-bridge system was realized. This solved the problem of limited topology size and I/O channels in the existing technology and met the needs of user-defined topology design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MODELINGTECH ENERGY TECHNOLOGY CO LTD
- Filing Date
- 2024-12-20
- Publication Date
- 2026-05-26
AI Technical Summary
Existing single simulators support a limited topology size and physical I/O channels, making it impossible to achieve full physical I/O interaction hardware-in-the-loop testing of large cascaded H-bridge systems.
The circuit topology of a large cascaded H-bridge system is equivalently divided into a main system circuit topology and several subsystem circuit topologies. Equivalent substitution is achieved using controlled voltage sources and controlled current sources. The operating status of each cascaded H-bridge branch is controlled by circuit breakers and bypass switches. Full physical I/O interaction is achieved using fiber optic communication and physical I/O.
We have achieved full physical I/O interaction hardware-in-the-loop testing of large-scale cascaded H-bridge systems, accurately simulating various operating conditions and meeting the user's custom topology design requirements.
Smart Images
Figure CN119830836B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of real-time simulation technology for power converters, and in particular to a real-time simulation method and system for large-scale cascaded H-bridge applications with full detail modeling. Background Technology
[0002] Cascaded topology converters are a new type of high-voltage, high-power converter with advantages such as high transmission power, high system efficiency, and good waveform quality. They are widely used in high-voltage direct current transmission, new energy power generation, reactive power compensation, and high-voltage frequency converters. Large cascaded H-bridge systems, such as chained SVG, high-voltage direct-connected energy storage, MMC, and high-voltage frequency converters, generally have a large number of switching elements and high power. Building a physical platform for testing is costly, time-consuming, dangerous, and difficult to reproduce operating conditions. Therefore, semi-physical simulation platforms are usually used for testing and verification in cascaded topology applications. However, traditional stand-alone real-time simulators are limited by FPGA simulation resources, which restrict the number of system topologies they can support. Furthermore, the physical I / O interfaces of a single device are limited, making it impossible to achieve hardware-in-the-loop testing of large cascaded topology systems with full physical I / O interaction with the controller. While using commercially available dedicated cascaded topology modeling and fiber optic communication solutions can achieve cascaded topology system simulation with a single device, it still cannot fully meet the full physical I / O testing needs of industrial users. Moreover, the system topology is relatively fixed and singular, making it impossible to achieve user-customized topology design. Summary of the Invention
[0003] The purpose of this invention is to overcome the limitations of existing single simulators in terms of topology size and physical I / O channels, and to provide a real-time simulation method and system for large-scale cascaded H-bridge applications with full detail modeling.
[0004] The objective of this invention can be achieved through the following technical solutions:
[0005] As a first aspect of the present invention, a real-time simulation method for a large-scale cascaded H-bridge application is provided, the method comprising the following steps:
[0006] The circuit topology of a large cascaded H-bridge system is equivalently divided into a main system circuit topology and several subsystem circuit topologies. The main system circuit topology is a power grid system, and the subsystem circuit topology is a cascaded H-bridge system.
[0007] The equivalently segmented circuit is replaced by controlled voltage sources and controlled current sources. In the main system circuit, multiple controlled voltage sources are used to replace the topology of each subsystem circuit respectively; in the subsystem circuit, controlled current sources are used to replace the main system circuit.
[0008] The branch current of the controlled voltage source in the main system circuit is measured and fed into the controlled current source input in the corresponding subsystem circuit; the voltage across the controlled current source is measured and fed into the corresponding controlled voltage source input in the main system circuit.
[0009] Each controlled voltage source branch in the main system equivalent circuit is equipped with a circuit breaker, and a bypass switch is connected in parallel across the controlled current source in each subsystem circuit.
[0010] A circuit breaker state logic determination module is constructed. Based on the PWM signal, branch voltage, branch current and submodule capacitor voltage of the equivalent circuit of the cascaded H-bridge in each subsystem, the current working state of each cascaded H-bridge branch is determined. The circuit breaker in the main system circuit and the bypass switch in each subsystem circuit are controlled to turn on and off according to the different working states.
[0011] The equivalent partitioned main system circuit topology and several subsystem circuit topologies are loaded into each simulator, and the circuit breaker state logic determination module is loaded into the simulator. The simulators interact with each other through optical fiber communication, and the simulators interact with the controller through physical I / O, realizing the hardware-in-the-loop simulation of the full physical I / O of the large cascaded H-bridge system.
[0012] As a preferred technical solution, the circuit topology of the large-scale cascaded H-bridge system is divided according to the specific number of cascades in the cascaded H-bridge system and the topology size and number of IO channels supported by the single-machine simulator: for the actual number of cascades in the system is n, the maximum scale of cascades supported by the single-machine simulator is m, and the system topology is divided into at least n / m equivalent circuits. If n / m is not an integer, it is rounded up.
[0013] As a preferred technical solution, the equivalent division is to divide each phase of the large-scale cascaded H-bridge system circuit topology into a separate subsystem cascaded H-bridge equivalent circuit or into multiple subsystem cascaded H-bridge equivalent circuits.
[0014] As a preferred technical solution, the switching states of the bypass switches in the cascaded H-bridge equivalent circuit of the main system circuit topology circuit breaker and the corresponding subsystem are opposite, that is, when the main circuit circuit breaker is turned on, the bypass switch in the corresponding cascaded H-bridge equivalent circuit is turned off; when the main circuit circuit breaker is turned off, the bypass switch in the cascaded H-bridge equivalent circuit of the corresponding subsystem is turned on.
[0015] As a preferred technical solution, the circuit breaker status determination module determines the current working status of each cascaded H-bridge branch as follows:
[0016] The circuit breaker status logic determination module detects whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit of each subsystem. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in uncontrolled rectification or high impedance state, and proceeds to the next step of judgment.
[0017] If no PWM signal is detected, the circuit breaker status logic determination module will check whether the current of the cascaded H-bridge branch crosses zero. If it does not cross zero, it will determine that the cascaded H-bridge branch is in an uncontrolled rectification state; if it crosses zero, it will need to proceed to the next step of judgment.
[0018] If the circuit breaker state logic determination module detects that the current of the cascaded H-bridge branch is zero, it will disconnect the circuit breaker in the control main circuit and compare the sum of the branch voltage and the capacitor voltage of the cascaded H-bridge equivalent circuit. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in a high-impedance state.
[0019] As a preferred technical solution, the control of the main system circuit circuit breaker and the bypass switch in each subsystem circuit according to different operating states is as follows:
[0020] When the circuit breaker status logic determination module determines that the cascaded H-bridge branch is in PWM working state, it controls the circuit breaker of the equivalent circuit of the main system to be turned on, and the bypass switch of the equivalent circuit of the cascaded H-bridge in the corresponding subsystem level is turned off, and the system is in normal working mode.
[0021] When the circuit breaker status logic determines that the branch is in an uncontrolled rectification state, the circuit breaker of the main system equivalent circuit remains on, the bypass switch of the cascaded H-bridge equivalent circuit in the corresponding subsystem is turned off, and the system is in an uncontrolled rectification mode.
[0022] When the circuit breaker status logic determination module determines that the branch is in a high-resistance state, it controls the circuit breaker of the equivalent circuit of the main system to turn off, and the bypass switch of the equivalent H-bridge in the corresponding subsystem level is turned on, short-circuiting the equivalent controlled current source.
[0023] As a preferred technical solution, the equivalent partitioned main system circuit topology and several subsystem circuit topologies are respectively loaded into the FPGA of each simulator, and the circuit breaker state logic determination module is loaded into the simulator CPU.
[0024] The FPGA uploads branch voltage, submodule capacitor voltage and branch current data to the CPU. The logic control program in the CPU sends control instructions for each circuit breaker and bypass switch to the FPGA topology circuit breaker and bypass switch of each simulator.
[0025] The simulators communicate with each other via fiber optic communication; clock synchronization lines are connected between the simulators to synchronize clock signals between different devices.
[0026] As a second aspect of the present invention, a real-time simulation system for large-scale cascaded H-bridge applications is provided, characterized in that the system includes multiple simulators;
[0027] The FPGA of the simulator is loaded with an equivalent circuit topology of a segmented large cascaded H-bridge system. In the main system circuit, multiple controlled voltage sources are used to equivalently replace the topology of each subsystem circuit. In the subsystem circuit, controlled current sources are used to equivalently replace the main system circuit. The branch current of the controlled voltage source in the main system circuit is measured and fed to the controlled current source input in the corresponding subsystem circuit. The voltage across the controlled current source is measured and fed to the corresponding controlled voltage source input in the main system circuit.
[0028] The CPU of the simulator is loaded with a circuit breaker status logic determination module. Based on the PWM signal, branch voltage, branch current and sub-module capacitor voltage of the cascaded H-bridge equivalent circuit in each subsystem, the module determines the current working state of each cascaded H-bridge branch and controls the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit to turn on and off according to the different working states.
[0029] The simulators communicate with each other via fiber optic communication and are synchronized via a clock synchronization line. The simulators and the controller communicate with each other via physical I / O, enabling hardware-in-the-loop simulation of the full physical I / O of a large cascaded H-bridge system.
[0030] As a preferred technical solution, the circuit topology of the large-scale cascaded H-bridge system is divided according to the specific number of cascades in the cascaded H-bridge system and the topology size and number of IO channels supported by the single-machine simulator: for the actual number of cascades in the system is n, the maximum scale of cascades supported by the single-machine simulator is m, and the system topology is divided into at least n / m equivalent circuits. If n / m is not an integer, it is rounded up.
[0031] As a preferred technical solution, the circuit breaker status logic determination module is specifically as follows:
[0032] The system checks whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit in each subsystem circuit. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in PWM operation mode. If no PWM signal is detected, it indicates that the cascaded H-bridge is in uncontrolled rectification or high impedance mode, and the next step is to be determined.
[0033] If no PWM signal is detected, the circuit breaker status logic determination module will check whether the current of the cascaded H-bridge branch crosses zero. If it does not cross zero, it will determine that the cascaded H-bridge branch is in an uncontrolled rectification state; if it crosses zero, it will proceed to the next step of judgment.
[0034] If the logic determination module detects that the current of the cascaded H-bridge branch is zero, and the circuit breaker of the main circuit is opened, the sum of the branch voltage and the capacitor voltage of the equivalent circuit of the cascaded H-bridge is compared. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, the cascaded H-bridge branch is determined to be in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, the cascaded H-bridge branch is determined to be in a high-impedance state.
[0035] When the circuit breaker status logic determination module determines that the branch is in PWM working state, it controls the main circuit circuit breaker to turn on, and the corresponding cascaded H-bridge equivalent circuit bypass switch to turn off, and the system is in normal working mode.
[0036] When the circuit breaker status logic determines that the branch is in an uncontrolled rectification state, the main circuit circuit breaker remains on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in an uncontrolled rectification mode.
[0037] When the circuit breaker status logic determination module determines that the branch is in a high-resistance state, it controls the main circuit circuit breaker to turn off, and the corresponding cascaded H-bridge equivalent circuit bypass switch is turned on, short-circuiting the equivalent controlled current source.
[0038] Compared with the prior art, the present invention has the following beneficial effects:
[0039] This invention adds circuit breakers to the segmented main system circuit topology and connects bypass switches in parallel with current sources in the equivalent circuits of the remaining cascaded H-bridges. Based on the PWM signal, branch voltage, branch current, and submodule voltage in the circuit, the current operating state of each cascaded H-bridge branch is determined, and the main circuit circuit breaker is turned off and the corresponding bypass switches in the equivalent circuits of the cascaded H-bridges are turned on, thereby achieving accurate simulation of various system operating conditions; and enabling hardware-in-the-loop testing of the controller with full physical I / O interaction for large-scale cascaded H-bridge applications with fully detailed modeling. Attached Figure Description
[0040] Figure 1 Flowchart of the real-time simulation method for the application of large-scale cascaded H-bridges with full detail modeling for this invention;
[0041] Figure 2 This is a schematic diagram of the overall equivalent segmentation of the SVG system of the present invention.
[0042] Figure 3 Logic block diagram of the circuit breaker status determination module of this invention
[0043] Figure 4 This is a schematic diagram of the equivalent segmentation device of the SVG system in one embodiment of the present invention.
[0044] Figure 5The waveform diagrams are real-time simulation results of a 40-level SVG system in one embodiment of the present invention, showing a) grid-side voltage, b) grid-side current, and c) cascaded H-bridge capacitor voltage. Detailed Implementation
[0045] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.
[0046] Example 1
[0047] This invention addresses the limitations of existing single-unit simulators in supporting limited topology size and I / O channels by proposing a parallel simulation method for multi-level systems. This invention enables hardware-in-the-loop testing of controllers with full physical I / O interaction in large-scale cascaded H-bridge applications with fully detailed modeling. Figure 1 As shown, the real-time simulation method for large-scale cascaded H-bridges with full detail modeling proposed in this invention includes the following steps:
[0048] Step 1: Based on the scale of the cascaded H-bridge system, the entire system circuit topology is equivalently divided into a main system circuit topology and several subsystem circuit topologies. The main system circuit topology is defined as the power grid system, and the subsystem circuit topology is defined as the cascaded H-bridge system.
[0049] In step 1: the circuit topology of the large cascaded H-bridge system is divided according to the specific number of cascades in the system and the topology size and number of I / O channels supported by the single-machine simulator; if the actual number of cascades in the system is n and the maximum cascade scale supported by the single-machine simulator is m, then the system topology needs to be divided into at least n / m (rounded up if not an integer) equivalent circuits.
[0050] As one of the segmentation methods, such as Figure 2 The diagram shows the circuit partitioning of a 24-level SVG system. It uses a fully detailed model of a 24-level SVG three-phase system with a total of 72 cascaded H-bridge sub-modules. A single simulator cannot support this scale of topology due to resource limitations. The system is then divided into equivalent partitions, with each phase as a separate subsystem cascaded H-bridge equivalent circuit. Each subsystem equivalent circuit contains 24 cascaded H-bridges.
[0051] Step 2: Use controlled voltage and current sources to perform equivalent substitution on the equivalently partitioned circuit. In the main system circuit, replace the subsystem circuit topology with a controlled voltage source and measure the branch current of the controlled voltage source as feedback; in the subsystem circuit, replace the main system circuit with a controlled current source and measure the voltage across it as feedback; for example... Figure 2As shown, ammeters are added at the three-phase controlled voltage sources A, B, and C in the main system circuit topology to measure their branch currents, and voltmeters are connected in parallel at the controlled current sources in each subsystem circuit topology to measure their voltages.
[0052] Step 3: Measure the current in the controlled voltage source branch and supply it to the controlled current source input in the corresponding subsystem circuit; measure the voltage across the controlled current source and supply it to the corresponding controlled voltage source input in the main system circuit.
[0053] Step 3 includes the following steps:
[0054] Step 3a: Measure the current in the controlled voltage source branch in the main system circuit topology, and measure the voltage across the controlled current source in the subsystem circuit topology;
[0055] Step 3b: As Figure 2 As shown, the measured controlled voltage source branch current is transmitted through optical fiber to the controlled current source input in the corresponding A, B, and C three-phase subsystem circuits; the measured voltage across the controlled current source is transmitted through optical fiber to the controlled voltage source input in the main system circuit topology.
[0056] Step 4: Add a circuit breaker to each phase branch in the main system circuit, and connect a bypass switch in parallel across the controlled current source in each subsystem circuit;
[0057] In step 4: such as Figure 2 As shown, a circuit breaker is added to the split main system circuit topology, and a bypass switch is connected in parallel with the current source in the remaining cascaded H-bridge equivalent circuits. The switching states of the circuit breaker and the corresponding cascaded H-bridge equivalent circuit in the main system circuit topology are opposite. That is, when the circuit breaker of the branch in the main circuit is turned on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off; when the circuit breaker of the branch in the main circuit is turned off, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned on.
[0058] Step 5: Acquire the PWM signal and branch voltage V in the acquisition circuit. bran h, branch current I branc h, submodule voltage, design circuit breaker status logic determination module;
[0059] like Figure 3 As shown, step 5 specifically includes the following steps:
[0060] Step 5a: The logic determination module detects whether there is a PWM signal in the equivalent circuit branch of each cascaded H-bridge. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in uncontrolled rectification or high impedance state, and the next step of judgment is required.
[0061] Step 5b: If no PWM signal is detected, the logic control program will check whether the current of the cascaded H-bridge branch crosses zero. If it does not cross zero, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if it crosses zero, the next step of judgment is required.
[0062] Step 5c: If the logic determination module detects that the current of the cascaded H-bridge branch is zero, after the main circuit circuit breaker is opened, the sum of the branch voltage and the capacitor voltage of the cascaded H-bridge equivalent circuit will be compared. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in a high-impedance state.
[0063] Step 6: Determine the current working status of each cascaded H-bridge branch based on the output of the circuit breaker status logic determination module, and control the circuit breakers in the main system circuit and the bypass switches in each subsystem circuit to turn on and off according to the different working statuses.
[0064] like Figure 3 As shown, when the circuit breaker status logic determination module determines that the branch is in PWM working state, it controls the main circuit circuit breaker to turn on, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit turns off, and the system is in normal working mode.
[0065] When the circuit breaker status logic determines that the branch is in an uncontrolled rectification state, the main circuit circuit breaker remains on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in an uncontrolled rectification mode.
[0066] When the circuit breaker state logic determination module determines that the branch is in a high-resistance state, it controls the main circuit circuit breaker to turn off, and the corresponding cascaded H-bridge equivalent circuit bypass switch is turned on, short-circuiting the equivalent controlled current source. This avoids the continuous rise of the branch capacitor voltage caused by the branch current not being zero due to the simulation not being ideal.
[0067] Step 7: Load the equivalent partitioned main system circuit topology and several subsystem circuit topologies into the FPGA of each simulator, load the circuit breaker state logic determination module into the simulator CPU, and exchange data between the simulators through optical fiber communication and ensure the synchronous operation of multiple simulators through clock synchronization lines.
[0068] Step 7 includes the following steps:
[0069] Step 7a: As Figure 4 As shown, the segmented equivalent circuit topologies are loaded into the FPGA of each simulator, and the logic control program is loaded into the simulator CPU.
[0070] Step 7b: The FPGA will convert the branch voltage V branc h, Submodule capacitor voltage Vcap and branch current I branc Data such as h is uploaded to the CPU, and the logic control program in the CPU sends the control instructions of each circuit breaker and bypass switch to the FPGA topology circuit breaker and bypass switch of each simulator.
[0071] Step 7c: Each simulator is connected via a fiber optic interface. Fiber optic communication is used to transmit data between different devices in parallel simulation. Clock synchronization lines are connected between each simulator. The function of the clock synchronization lines is to synchronize the clock signals between different devices to ensure that different devices run in parallel within a unified clock cycle.
[0072] Step 8: Each simulator and controller interacts with each other via physical I / O to achieve hardware-in-the-loop simulation of the full physical I / O of a large-scale cascaded H-bridge system with full detail modeling.
[0073] Example 2
[0074] This embodiment provides a specific implementation example of using the above method for real-time SVG simulation, taking a 40-level SVG system as an example to verify its performance. Simulation model parameters: three-phase grid voltage is 35kV, grid frequency is 50Hz, SVG system level is 40, grid-side inductance parameter is 9mH, capacitance parameter is 7000uF, and rated voltage is 800V.
[0075] The hardware-in-the-loop testing method for controllers with full physical I / O interaction in a large-scale cascaded H-bridge application using the fully detailed modeling method provided by this invention divides the original SVG system into three equivalent circuits according to the equivalent partitioning method provided by this invention, and loads them into three simulators respectively. The main system simulator and the other subsystem simulators transmit data through optical fiber and synchronize through a clock synchronization line. The SVG controller interfaces with the real-time simulator, and the SVG controller and the real-time simulation device provided by this invention exchange data information through physical I / O, thereby realizing the hardware-in-the-loop testing of the fully detailed modeled SVG system with full physical I / O interaction.
[0076] Figure 5 It contains three sub-images. Figure 5 (a) Figure 5 (b) Figure 5 (c) The waveforms of the simulation results, namely the grid-side voltage, grid-side current, and cascaded H-bridge capacitor voltage, are sampled by the simulator's host computer. Figure 5 It can be seen that this simulation method can realize hardware-in-the-loop testing with full physical I / O interaction with the controller; the simulator can accurately simulate system voltage and current, and the voltage and current waveform quality is good. At the same time, it can accurately simulate the ripple size and equalization effect of sub-module voltage. Therefore, the hardware-in-the-loop testing method of controller hardware-in-the-loop interaction with full physical I / O interaction using a large cascaded H-bridge application with full detail modeling will produce more accurate results.
[0077] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.
Claims
1. A real-time simulation method for large-scale cascaded H-bridges with fully detailed modeling, characterized in that, The method steps include: The circuit topology of a large cascaded H-bridge system is equivalently divided into a main system circuit topology and several subsystem circuit topologies. The main system circuit topology is a power grid system, and the subsystem circuit topology is a cascaded H-bridge system. The equivalently segmented circuit is replaced by controlled voltage sources and controlled current sources. In the main system circuit, multiple controlled voltage sources are used to replace the topology of each subsystem circuit respectively; in the subsystem circuit, controlled current sources are used to replace the main system circuit. The branch current of the controlled voltage source in the main system circuit is measured and fed into the controlled current source input in the corresponding subsystem circuit; the voltage across the controlled current source is measured and fed into the corresponding controlled voltage source input in the main system circuit. Each controlled voltage source branch in the main system equivalent circuit is equipped with a circuit breaker, and a bypass switch is connected in parallel across the controlled current source in each subsystem circuit. A circuit breaker status logic determination module is constructed. Based on the PWM signal, branch voltage, branch current, and submodule capacitor voltage of the equivalent circuit of the cascaded H-bridge in each subsystem, it determines the current operating status of each cascaded H-bridge branch and controls the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit to turn on and off according to the different operating statuses, as detailed below: When the circuit breaker status logic determination module determines that the cascaded H-bridge branch is in PWM working state, it controls the circuit breaker of the equivalent circuit of the main system to be turned on, and the bypass switch of the equivalent circuit of the cascaded H-bridge in the corresponding subsystem is turned off, and the system is in normal working mode. When the circuit breaker status logic determines that the branch is in an uncontrolled rectification state, the circuit breaker of the main system equivalent circuit remains on, the bypass switch of the cascaded H-bridge equivalent circuit in the corresponding subsystem is turned off, and the system is in an uncontrolled rectification mode. When the circuit breaker status logic determination module determines that the branch is in a high-resistance state, it controls the circuit breaker of the equivalent circuit of the main system to turn off, and the bypass switch of the equivalent circuit of the cascaded H-bridge in the corresponding subsystem is turned on, short-circuiting the equivalent controlled current source. The equivalent partitioned main system circuit topology and several subsystem circuit topologies are loaded into each simulator, and the circuit breaker state logic determination module is loaded into the simulator. The simulators interact with each other through optical fiber communication, and the simulators interact with the controller through physical I / O, realizing the hardware-in-the-loop simulation of the full physical I / O of the large cascaded H-bridge system.
2. The real-time simulation method for large-scale cascaded H-bridges with full detail modeling as described in claim 1, characterized in that, The circuit topology of the large-scale cascaded H-bridge system is divided according to the specific number of cascaded H-bridges and the topology size and number of I / O channels supported by the single-machine simulator: for the actual number of cascaded H-bridges in the system... n Level, the maximum scale of simulation cascading supported by a single-machine simulator is [number missing]. m Level, at least divide the system topology into n / m An equivalent circuit, if n / m If the result is not an integer, round it up.
3. The real-time simulation method for large-scale cascaded H-bridges with full detail modeling as described in claim 2, characterized in that, The equivalent partitioning refers to dividing each phase of a large-scale cascaded H-bridge system circuit topology into a separate subsystem cascaded H-bridge equivalent circuit or into multiple subsystem cascaded H-bridge equivalent circuits.
4. The real-time simulation method for large-scale cascaded H-bridges with full detail modeling as described in claim 1, characterized in that, The switching states of the bypass switches in the equivalent circuits of the main system circuit topology circuit breaker and the corresponding cascaded H-bridge circuits of the subsystems are opposite, that is, when the main circuit circuit breaker is turned on, the bypass switches in the equivalent circuits of the corresponding cascaded H-bridges are turned off. When the main circuit interrupter is turned off, the bypass switch in the cascaded H-bridge equivalent circuit of the corresponding subsystem is turned on.
5. The real-time simulation method for large-scale cascaded H-bridges with full detail modeling as described in claim 1, characterized in that, The specific implementation of the circuit breaker status determination module for judging the current working status of each cascaded H-bridge branch is as follows: The circuit breaker status logic determination module detects whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit of each subsystem. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in uncontrolled rectification or high impedance state, and proceeds to the next step of judgment. If no PWM signal is detected, the circuit breaker status logic determination module will check whether the current of the cascaded H-bridge branch crosses zero. If it does not cross zero, it will determine that the cascaded H-bridge branch is in an uncontrolled rectification state; if it crosses zero, it will need to proceed to the next step of judgment. If the circuit breaker state logic determination module detects that the current of the cascaded H-bridge branch is zero, it will disconnect the circuit breaker in the control main circuit and compare the sum of the branch voltage and the capacitor voltage of the cascaded H-bridge equivalent circuit. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in a high-impedance state.
6. The real-time simulation method for large-scale cascaded H-bridges with full detail modeling according to claim 1, characterized in that, The equivalent partitioned main system circuit topology and several subsystem circuit topologies are respectively loaded into the FPGA of each simulator, and the circuit breaker state logic determination module is loaded into the simulator CPU. The FPGA uploads branch voltage, submodule capacitor voltage and branch current data to the CPU. The logic control program in the CPU sends control instructions for each circuit breaker and bypass switch to the FPGA topology circuit breaker and bypass switch of each simulator. The simulators exchange data via fiber optic communication. Clock synchronization lines are connected between each simulator to synchronize clock signals between different devices.
7. A real-time simulation system for a large-scale cascaded H-bridge application with fully detailed modeling, characterized in that, The system performs a real-time simulation method for large-scale cascaded H-bridge applications with full detail modeling as described in any one of claims 1-6, including multiple simulators; The FPGA of the simulator is loaded with an equivalent circuit topology of a segmented large cascaded H-bridge system. In the main system circuit, multiple controlled voltage sources are used to equivalently replace the topology of each subsystem circuit. In the subsystem circuit, controlled current sources are used to equivalently replace the main system circuit. The branch current of the controlled voltage source in the main system circuit is measured and fed to the controlled current source input in the corresponding subsystem circuit. The voltage across the controlled current source is measured and fed to the corresponding controlled voltage source input in the main system circuit. The CPU of the simulator is loaded with a circuit breaker status logic determination module. Based on the PWM signal, branch voltage, branch current and sub-module capacitor voltage of the cascaded H-bridge equivalent circuit in each subsystem, the module determines the current working state of each cascaded H-bridge branch and controls the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit to turn on and off according to the different working states. The simulators communicate with each other via fiber optic communication and are synchronized via a clock synchronization line. The simulators and the controller communicate with each other via physical I / O, enabling hardware-in-the-loop simulation of the full physical I / O of a large cascaded H-bridge system.
8. A real-time simulation system for large-scale cascaded H-bridge applications with fully detailed modeling as described in claim 7, characterized in that, The circuit topology of the large-scale cascaded H-bridge system is divided according to the specific number of cascaded H-bridges and the topology size and number of I / O channels supported by the single-machine simulator: for the actual number of cascaded H-bridges in the system... n Level, the maximum scale of simulation cascading supported by a single-machine simulator is [number missing]. m Level, at least divide the system topology into n / m An equivalent circuit, if n / m If the result is not an integer, round it up.
9. A real-time simulation system for large-scale cascaded H-bridge applications with fully detailed modeling as described in claim 7, characterized in that, The circuit breaker status logic determination module is implemented as follows: The system checks whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit in each subsystem circuit. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in PWM operation mode. If no PWM signal is detected, it indicates that the cascaded H-bridge is in uncontrolled rectification or high impedance mode, and the next step is to be determined. If no PWM signal is detected, the circuit breaker state logic determination module will detect whether the current of the cascaded H-bridge branch crosses zero. If it does not cross zero, it will determine that the cascaded H-bridge branch is in an uncontrollable rectification state. If the value crosses zero, proceed to the next step of the judgment; If the logic determination module detects that the current of the cascaded H-bridge branch is zero, and the circuit breaker of the main circuit is opened, the sum of the branch voltage and the capacitor voltage of the equivalent circuit of the cascaded H-bridge is compared. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, the cascaded H-bridge branch is determined to be in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, the cascaded H-bridge branch is determined to be in a high-impedance state. When the circuit breaker status logic determination module determines that the branch is in PWM working state, it controls the main circuit circuit breaker to turn on, and the corresponding cascaded H-bridge equivalent circuit bypass switch to turn off, and the system is in normal working mode. When the circuit breaker status logic determines that the branch is in an uncontrolled rectification state, the main circuit circuit breaker remains on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in an uncontrolled rectification mode. When the circuit breaker status logic determination module determines that the branch is in a high-resistance state, it controls the main circuit circuit breaker to turn off, and the corresponding cascaded H-bridge equivalent circuit bypass switch is turned on, short-circuiting the equivalent controlled current source.