Layout design method based on high-speed IP internal reference wiring

Abstract

The invention discloses a layout design method based on high-speed IP internal reference wiring, and relates to the technical field of integrated circuits. The method comprises the following steps: acquiring a resistance requirement of circuit design and a distance requirement between a reference module at the top layer of an IP and a module in the IP; obtaining a shielding degree requirement of the shielding wire according to the reference wire requirement; selecting a metal level, a metal width and a metal distance; selecting a shielding layer and performing noise shielding; connecting the shielding wire to a substrate of a reference module to complete a reference wire design; and calculating the resistance of the reference wire, comparing the resistance with the resistance requirement of the circuit design, and updating the resistance requirement of the circuit design based on a comparison result. According to the invention, shielding optimization and integration are carried out on the reference wiring, so that various noises can be efficiently shielded, the resistance can be quickly calculated, the wiring width or the module position can be adjusted in cooperation with a circuit, the layout estimation can be quickly carried out in cooperation with the IP layout, and the layout iteration is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a reference routing layout design method based on a high-speed IP. Background Art

[0002] In the existing reference signal lines (reference routing), solving the noise shielding problem is crucial. Usually, the routing will add shielding lines on the same layer on both sides of the metal routing on the same layer, or increase the distance from the noise routing, but will ignore the noise introduced by the upper and lower environments of the routing, as well as the influence of the noise introduced by the substrate in the high-speed IP. In the high-speed IP, there are many high-speed devices in the CLK signal routing (clock signal routing), and the bias voltage / current or reference voltage reference signal of the reference module will be provided to each high-speed module. In this way, the above-mentioned reference routing can easily introduce the noise of the CLK signal routing. Since it is inside the high-speed module, the substrate noise cannot be ignored. Even if a higher level of metal is used, substrate noise will be introduced, resulting in inaccurate reference current or voltage of other modules, causing design failure. Secondly, the parasitic resistance of the reference signal line cannot be ignored. Usually, the circuit design will estimate the resistance range of the routing. When it exceeds a certain range, it will cause the reference to deviate too much; when the layout is laid out, the resistance can be estimated at the same time to avoid later layout iterations, which will cause layout changes in severe cases.

[0003] As the frequency of high-speed IPs continues to increase, the shielding of reference modules and reference traces becomes more and more stringent when the process nodes are smaller. In order to ensure that the reference traces connected from the reference modules to the inside of each high-speed IP are not affected by high-speed signals and noisy substrates, conventional shielding and distance between noise traces can no longer meet design requirements. At small process nodes, the metal thickness is getting smaller and smaller, and coupling capacitance is more likely to exist between different layers; the resistance of metal blocks is getting larger and larger, which will cause excessive deviation from the reference to the module in some designs, causing design mismatch. Therefore, it is necessary to optimize the reference traces to address this phenomenon. Summary of the invention

[0004] The purpose of the present invention is to provide a reference routing layout design method based on high-speed IP. By shielding optimization and integration of reference routing, various noises can be efficiently shielded, resistance can be quickly calculated, and routing width or module position can be adjusted in coordination with the circuit. At the same time, layout estimation can be quickly performed in coordination with the IP layout to reduce layout iterations.

[0005] The present invention can be achieved through the following technical solutions: In a first aspect, an embodiment of the present application provides a method for designing a reference routing layout based on a high-speed IP, comprising the following steps: Get the resistance requirements for the circuit design; Get the distance requirement between the reference module at the top level of the IP and the module inside the IP; Obtain the shielding degree requirements for shielded routing based on the reference routing requirements; Selecting metal layers, metal widths, and metal distances according to the resistance requirements and the distance requirements; Selecting a shielding layer according to the shielding degree requirement and performing noise shielding; Connecting the shield trace to the substrate of the reference module to complete the reference trace design based on the selected shield layer and the selected metal level, metal width, and metal distance; The resistance of the reference trace is calculated based on the selected metal level, metal width and metal distance, and compared with the resistance requirement of the circuit design, and the resistance requirement of the circuit design is updated based on the comparison result.

[0006] Preferably, the noise shielding comprises: adding shielding traces to the upper metal layer and the lower metal layer of the reference trace while adding shielding traces on the left and right sides.

[0007] Preferably, the adding of shielding routing to the upper metal layer and the lower metal layer of the reference routing is specifically: adding upper and lower metal layers based on a preset DRC, and the upper and lower metal layers are added in a slot manner.

[0008] Preferably, the slot method is specifically: setting gaps or holes in the upper and lower metal layers.

[0009] Preferably, obtaining the shielding degree requirement of the shielded routing according to the reference routing requirement is specifically: Requirement 1: The shielding metal must have low resistance; Requirement 2: The shielding metal is required to be connected to the ground of the reference module.

[0010] Preferably, the noise shielding further comprises: selecting the metal layer to be a network structure to form a metal network.

[0011] Preferably, the metal network exists at the starting node of the routing, so as to facilitate directly connecting the shielding metal to the ground of the reference module in the layout design.

[0012] In the second aspect, the embodiment of the present application provides a resistance calculation method based on the reference routing layout design in the high-speed IP, which is applied to the reference routing layout design method as described above, and the resistance of the reference routing is calculated based on the selected metal level, metal width and metal distance, specifically: The calculation of the reference trace resistance is directly integrated into PCELL to directly obtain the reference trace resistance when adjusting the width, length and metal layer of the reference trace.

[0013] The beneficial effects of the present invention are as follows: the present invention performs shielding optimization and integration on the reference routing, which can not only effectively shield various noises, but also quickly calculate the resistance, cooperate with the circuit to adjust the routing width or the module position, and quickly cooperate with the IP layout to perform layout estimation, thereby reducing layout iterations. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0015] Figure 1 A flowchart of the steps of a method for designing a reference routing layout based on a high-speed IP provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0017] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to any or all possible combinations of one or more associated listed items.

[0018] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0019] Example 1 See also Figure 1 The present application embodiment provides a method for designing a reference routing layout based on a high-speed IP, comprising the following steps: Get the resistance requirements for the circuit design; Get the distance requirement between the reference module at the top level of the IP and the module inside the IP; Obtain the shielding degree requirements for shielded routing based on the reference routing requirements; Selecting metal layers, metal widths, and metal distances according to the resistance requirements and the distance requirements; Selecting a shielding layer according to the shielding degree requirement and performing noise shielding; Connecting the shield trace to the substrate of the reference module to complete the reference trace design based on the selected shield layer and the selected metal level, metal width, and metal distance; The resistance of the reference trace is calculated based on the selected metal level, metal width and metal distance, and compared with the resistance requirement of the circuit design, and the resistance requirement of the circuit design is updated based on the comparison result.

[0020] Specifically, the purpose of this application is to provide a design method based on the reference current and voltage routing layout in a high-speed IP, and to calculate the resistance of the corresponding routing at the same time, which specifically includes the following contents: first, respectively obtain the resistance requirements of the circuit design and the distance requirements between the top-level reference module of the IP and the internal module of the IP; then obtain the shielding degree requirements of the shielding routing according to the reference routing requirements; then select the metal level, metal width and metal distance according to the resistance requirements and the distance requirements; then select the shielding layer according to the shielding degree requirements; furthermore, based on the selected shielding layer and the selected metal level, metal width and metal distance, connect the shielding routing to the top-level reference module substrate of the IP to complete the reference routing design; finally, based on the selected metal level, metal width and metal distance, calculate the resistance of the reference routing, and compare it with the resistance requirements of the circuit design, and update the resistance requirements of the circuit design based on the comparison results. This application optimizes and integrates the shielding of the reference routing, which can not only efficiently shield various noises, but also quickly calculate the resistance, cooperate with the circuit to adjust the routing width or module position, and quickly cooperate with the IP layout to perform layout estimation, reducing layout iterations.

[0021] This application scheme mainly integrates the reference routing layout into a PCELL (Parameterized Cell), selects the metal level, metal width, and metal distance according to the distance requirements between the IP top-level modules and the resistance requirements of the circuit design, so as to calculate whether the corresponding resistance meets the circuit design requirements; the strictness of the shielding routing is selected by compromising the reference routing requirements, and finally the routing is completed.

[0022] The above scheme of the present application includes the selection of metal level of routing; the selection of metal width, metal distance and number of metal strips of routing; the selection of shielding line of routing; the automatic processing of the maximum and minimum width of metal level routing through level selection; the DRC (Design Rule Check) is ensured by adjusting the routing width and routing distance; the noise caused by high-speed signals is shielded by selecting shielding line to ensure the cleanness of reference routing; the resistance of routing is calculated by metal level and metal width, including the resistance of the maximum process angle (max), typical process angle (typical) and minimum process angle (minimum) under the three process corners (corner) of the process. The addition of shielding line greatly improves the quality of reference routing, ensuring that there is no noise introduced by other signals from reference routing to each module in high-speed IP, which causes excessive reference deviation.

[0023] It should be noted that the above-mentioned PCELL (Parameterized Cell) is a semiconductor design unit that can be designed through parameterization. It is a standard unit that can be flexibly configured and reused in integrated circuit design. Through parameterized design, the size, layout, electrical characteristics, etc. of the components can be flexibly adjusted to meet different design requirements, which not only improves design efficiency and reusability, but also reduces the occurrence of human errors.

[0024] The above-mentioned DRC is an important step in integrated circuit (IC) design, which is mainly used to verify whether the design meets the physical and electrical rules in the manufacturing process. It ensures that the layout of the chip meets the process requirements and avoids irreparable defects or failures in the manufacturing process. The core functions of DRC include: Verify the physical rules of the design: Each manufacturing process has specific rules that define the minimum size, spacing, alignment requirements, etc. that should be followed at each level and between components during design. DRC is used to detect whether the design complies with these process restrictions.

[0025] Avoid manufacturing defects: Design rule checking helps prevent problems in the circuit such as too small wire spacing, too wide wires, misaligned layers, etc., which can cause shorts, opens, failures or other problems during the manufacturing process.

[0026] Improve production yield: Following design rules ensures the reliability of the circuit, thereby improving the yield of the chip and reducing the possibility of rework and manufacturing defects.

[0027] DRC usually checks the following categories of rules: Minimum Width: The width of each trace and other structure must not be less than a specific value to ensure that structural damage does not occur during the manufacturing process.

[0028] Minimum Spacing: Sufficient spacing must be maintained between components, traces, and metal layers to avoid short circuits and signal interference.

[0029] Via and contact rules: Check whether the size, spacing, etc. of vias and contact holes meet the manufacturing process requirements.

[0030] Layer Alignment: Check whether the alignment between different layers (such as metal layer, active layer, substrate layer, etc.) is correct to avoid functional failure caused by layer misalignment.

[0031] Overlap and connection rules of metal layers: Check whether the connection between metal wires is reasonable to avoid electrical short circuits or signal distortion due to incorrect connection.

[0032] Electrical rules: In addition to physical rules, DRC may also include electrical rule checks, such as checking the connection between power and ground, continuity of signal paths, etc.

[0033] In addition, it should be noted that in integrated circuit design and manufacturing, the process corner refers to the performance changes of circuit components under different process conditions. In order to ensure that the circuit can work properly under different working environments and manufacturing variations, the impact of different process corners needs to be considered during design. The process corners usually include the maximum process corner (Max), the typical process corner (Typical) and the minimum process corner (Min), which represent the possible range of changes in the electrical characteristics of the components (such as resistance, capacitance, current, etc.) during the manufacturing process. The resistance changes under different process corners reflect the impact of factors such as process, temperature, voltage and manufacturing errors on component performance.

[0034] In an embodiment provided in the present application, the noise shielding includes: adding shielding traces to the upper metal layer and the lower metal layer of the reference trace while adding shielding traces on the left and right sides.

[0035] In an embodiment provided in the present application, the adding of shielding routing to the upper metal layer and the lower metal layer of the reference routing is specifically: adding upper and lower metal layers based on a preset DRC, and the upper and lower metal layers are added in a slot manner.

[0036] In an embodiment provided in the present application, the slot method is specifically: setting gaps or holes in the upper and lower metal layers.

[0037] Specifically, as the frequency of IP design continues to increase, in order to ensure that the routing provided by the reference module to each high-speed module is not affected by the high-speed clock (clock, clk), it is necessary to shield the routing from noise. The impact of noise is essentially that there is parasitic capacitance (parasitic capacitance) between the reference routing and the noise signal. Only by cutting off the parasitic capacitance between the two can the impact of noise be avoided. Therefore, this application has done the following processing on noise shielding: The first method: while adding shielding lines on the left and right sides, add shielding lines to the upper and lower metal layers of the reference line: due to the continuous reduction of process nodes, the line width and line shape requirements of metal lines are more stringent, and certain rules are required when adding upper and lower metal (that is, DRC, design rule check). When there are many reference lines, putting them in parallel will make the width of the entire line much larger than the maximum line width of the shielding line. At this time, the upper and lower layers are added in the form of slots to avoid DRC caused by excessive metal line width. In this embodiment, after taking into account the DRCs that the metal meets, the space of PCELL is adjusted to avoid the DRC of the slot area being too small, so that the line can be adjusted quickly.

[0038] It should be noted that in circuit design, parasitic C (parasitic capacitance) refers to the natural capacitance effect due to the relative position and electric field between different conductors in the circuit. This capacitance is usually accidental and unintentional, and they are not explicitly designed in the circuit design, but are caused by factors such as wiring, interlayer dielectrics, conductor size and relative position. There is a parasitic capacitance between the reference trace and the noise trace due to their proximity. This parasitic capacitance will cause the noise signal to enter the reference trace through capacitive coupling, causing signal interference or noise. The impact of parasitic capacitance is particularly prominent in high-speed signal transmission, because as the frequency increases, the coupling effect of capacitance becomes more significant.

[0039] In an embodiment provided in the present application, obtaining the shielding degree requirement of the shielded routing according to the reference routing requirement is specifically: Requirement 1: The shielding metal must have low resistance; Requirement 2: The shielding metal must be connected to the ground of the reference module.

[0040] In an embodiment provided in the present application, the noise shielding further includes: selecting the metal layer to be a network structure to form a metal network.

[0041] In an embodiment provided in the present application, the metal network exists at the starting node of the routing, which facilitates directly connecting the shielding metal to the ground of the reference module in the layout design.

[0042] Specifically, the reference routing must not only shield the clock noise, but also consider the noise brought by the p+ substrate of the wafer. In high-speed IP, the p+ substrate is a very dirty noise source. If the reference routing is shielded by such a dirty substrate, it will cause jitter of the reference routing. Usually, the reference routing shielding line has the following requirements: (1) The shielding metal resistance is required to be low. When the resistance of the shielding routing is too high, the noise of the surrounding environment cannot be quickly conducted away through the shielding metal in time, and the shielding effect will be greatly reduced; (2) The shielding metal is connected to a clean ground, usually connected to the ground of the reference module. The shielding metal layer in this embodiment adopts a network structure, which greatly reduces the parasitic resistance of the shielding metal. The metal network exists directly from the starting node of the routing, which is convenient for directly connecting to the ground of the reference module in the layout design.

[0043] It should be noted that the above-mentioned Wafer is a single crystal silicon wafer that serves as the basis for chip production during the semiconductor manufacturing process. The wafer has a series of hierarchical structures during the manufacturing process, such as an oxide layer, a metallization layer, and semiconductor doping, etc. Different layers will affect the transmission of electrical signals, noise coupling, and other electrical characteristics. P+ substrate refers to a silicon substrate doped with a high concentration of P-type dopants in a semiconductor wafer. P-type silicon is usually doped with elements such as boron (B) to make it appear as a "missing" electron, that is, to produce "holes", while P+ is a case where the doping concentration in P-type silicon is particularly high. In short, the P+ substrate is a P-type silicon substrate with a very high doping concentration, which usually has strong conductivity. As the base layer of the chip, the P+ substrate usually serves as the ground wire of the circuit. However, the P+ substrate itself is conductive and may bring noise through capacitive coupling and other means, affecting the surrounding signal lines, especially high-frequency signals such as clock signals. Therefore, in order to reduce the interference of the P+ substrate noise to the circuit in this embodiment, shielding, isolation, and reasonable wiring measures need to be taken during design to ensure the signal integrity and performance of the circuit.

[0044] In an embodiment provided in the present application, the resistance of the reference trace is calculated based on the selected metal level, metal width and metal distance, specifically: the calculation of the reference trace resistance is directly integrated on PCELL.

[0045] Specifically, in high-speed IP, the reference routing resistance is also very important. When the resistance is too large and exceeds the circuit design margin, there will be deviations after the reference to the module, causing errors in the module function (mapping relationship). The present invention directly integrates the calculation of resistance on PCELL. When adjusting the line width, line length and metal level, the resistance of the routing can be directly known, which greatly facilitates layout and wiring and improves the efficiency of layout drawing.

[0046] It should be noted that circuit design margin (also called design margin) refers to the safety or tolerance range reserved for various possible changes, errors, disturbances and uncertainties in circuit design. The purpose of margin is to ensure that the circuit can work stably and reliably under various conditions (such as voltage, current, temperature, component errors, etc.) to avoid circuit failure or malfunction due to parameter deviation, external environment changes or inconsistent component performance.

[0047] On the other hand, this application conducts experiments based on the above scheme and content. By comparing the parasitic results extracted after testing the circuit and layout, it is obvious from the extraction results that the coupling of A net (a node in the metal network) is almost all interfered by the shielding, and is almost unaffected by external environmental noise and substrate coupling. As long as the shielding is clean enough, it is easy to meet the design requirements. The parasitics of the substrate to the reference routing also account for a large proportion, so the substrate noise in the high-speed IP cannot be ignored.

[0048] In summary, this application mainly includes the following beneficial effects: (1) Resolve the impact of noise introduced by the surrounding environment on the reference routing.

[0049] (2) Quickly calculate the required length and width of the reference routing to reduce layout iterations.

[0050] (3) Quickly complete the connection and layout of the reference routing layout and estimate the area.

[0051] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0052] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for designing a reference routing layout based on a high-speed IP, characterized in that: The steps include: Get the resistance requirements for the circuit design; Get the distance requirement between the reference module at the top level of the IP and the module inside the IP; Obtain the shielding degree requirements for shielded routing based on the reference routing requirements; Selecting metal layers, metal widths, and metal distances according to the resistance requirements and the distance requirements; Selecting a shielding layer according to the shielding degree requirement and performing noise shielding; Connecting the shield trace to the substrate of the reference module to complete the reference trace design based on the selected shield layer and the selected metal level, metal width, and metal distance; Calculate the resistance of the reference trace based on the selected metal level, metal width and metal distance, compare it with the resistance requirement of the circuit design, and update the resistance requirement of the circuit design based on the comparison result; Wherein, the noise shielding comprises: While adding shielding lines on the left and right sides, shielding lines are added to the upper metal layer and the lower metal layer of the reference line, and the metal layer is selected as a network structure to form a metal network.

2. A method for designing a layout based on a high-speed IP internal reference routing according to claim 1, characterized in that: The adding of shielding routing to the upper metal layer and the lower metal layer of the reference routing is specifically: adding the upper and lower metal layers based on the preset DRC, and the upper and lower metal layers are added in the form of slots.

3. A method for designing a layout based on a high-speed IP internal reference routing according to claim 2, characterized in that: The slot method is specifically: setting gaps or holes in the upper and lower metal layers.

4. The method for designing a layout based on a high-speed IP internal reference routing according to claim 1, characterized in that: The shielding degree requirements of the shielded routing are obtained according to the reference routing requirements, specifically: Requirement 1: The shielding metal must have low resistance; Requirement 2: The shielding metal is required to be connected to the ground of the reference module.

5. The method for designing a layout based on a high-speed IP internal reference routing according to claim 1, characterized in that: The metal network exists at the starting node of the routing, which facilitates directly connecting the shielding metal to the ground of the reference module in the layout design.

6. A resistance calculation method based on reference routing layout design in a high-speed IP, applied to the reference routing layout design method according to any one of claims 1 to 5, characterized in that: The resistance of the reference trace is calculated based on the selected metal level, metal width, and metal distance, specifically: The calculation of the reference trace resistance is directly integrated into PCELL to directly obtain the reference trace resistance when adjusting the width, length and metal layer of the reference trace.

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