Pixel driving circuit and display panel

Abstract

The invention provides a pixel driving circuit and a display panel, and the pixel driving circuit comprises a driving unit which is used for driving a light-emitting element to emit light; the first switch unit is used for receiving a data signal; the second switch unit is used for controlling threshold voltage compensation; a first storage unit connected between the fourth node and the second node; the time sequence control circuit is used for respectively controlling the on and off of the first switch unit and the second switch unit so as to separate the data signal writing time from the compensation time, and controlling the Vth compensation time to be greater than the one-line scanning time; and in the light emitting stage, pulse type resetting is carried out on the source electrode potential of the driving unit by outputting a pulse signal. According to the pixel driving circuit provided by the invention, the technical problem that high and low refresh rates are difficult to be compatible in the prior art is effectively solved, the targets of high-quality display under the high refresh rate and low-power-consumption and flicker-free display under the low refresh rate are achieved, and the performance of display equipment and the user experience are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of display panel circuits, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] With the rapid development of display technology, people have higher and higher requirements for display devices, especially in the fields of mobile devices, virtual reality (VR) / augmented reality (AR) devices and high-definition televisions, which pose higher challenges to the performance of display screens. Among them, refresh rate is one of the important indicators to measure the performance of display screens.

[0003] High refresh rates can provide smoother display effects, reduce motion blur, and improve user experience, especially in scenes such as games and fast-motion video playback. In addition, high refresh rates can also help reduce eye fatigue and protect eyesight. However, traditional pixel drive circuits face some technical difficulties at high refresh rates. As the scanning time of each row of pixels is shortened, the time used for threshold voltage (Vth) compensation is also reduced accordingly, resulting in insufficient Vth compensation, which causes problems such as uneven display and brightness deviation, seriously affecting display quality. On the other hand, although low refresh rates can significantly reduce display power consumption and extend the battery life of the device, at low refresh rates, the threshold voltage drift and hysteresis effect of the driver transistor (Driver TFT) become more obvious, resulting in unstable OLED light emission, and the human eye can perceive obvious screen flicker, reducing viewing comfort.

[0004] Currently, most display devices on the market use a fixed refresh rate or a few fixed refresh rates, such as 60Hz, 90Hz, 120Hz, etc. This single or several refresh rate mode cannot meet the needs of users in different application scenarios. For example, when browsing static web pages or reading e-books, a high refresh rate is unnecessary and will increase power consumption; while when playing games or watching high-speed motion videos, a low refresh rate will cause the picture to freeze and blur.

[0005] Therefore, how to design a pixel driving circuit that is compatible with high and low refresh rates so that it can provide high-quality image display at a high refresh rate and effectively reduce power consumption and reduce screen flicker at a low refresh rate has become a technical problem that needs to be urgently solved in the current display technology field.

[0006] It should be noted that the information claimed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In view of this, the present invention provides a pixel driving circuit and a display panel, which can perform sufficient Vth compensation at a high refresh rate to improve display uniformity and picture quality; and can effectively suppress the hysteresis effect of the driving transistor at a low refresh rate to reduce screen flicker and enhance the viewing experience.

[0008] An aspect of an embodiment of the present invention provides a pixel driving circuit, including: A driving unit, used for driving the light-emitting element to emit light; A first switch unit, configured to receive a data signal from a data input terminal and transmit the data signal to a fourth node; A second switch unit, used for controlling threshold voltage compensation and transmitting the compensated voltage to a second node; a first storage unit connected between the fourth node and the second node; The timing control circuit is used to output control signals to the first control signal terminal, the second control signal terminal, the third control signal terminal and the fourth control signal terminal respectively to control the on and off of the first switch unit and the second switch unit, thereby separating the data signal writing time from the threshold voltage compensation time, and controlling the on time of the second switch unit so that the threshold voltage compensation time is greater than a row scanning time; and in the light-emitting stage, by outputting a pulse signal to the third control signal terminal, the driving unit is pulse-reset.

[0009] In some optional embodiments, the first switch unit includes a first transistor, a gate of the first transistor is connected to the first control signal terminal, a first electrode of the first transistor is connected to the data input terminal, and a second electrode of the first transistor is connected to the fourth node.

[0010] In some optional embodiments, the second switch unit includes a third transistor, a gate of the third transistor is connected to the second control signal terminal, a first electrode of the third transistor is connected to the third node, and a second electrode of the third transistor is connected to the second node.

[0011] In some optional embodiments, a third switching unit is further included, the third switching unit includes a sixth transistor, the sixth transistor is a dual-gate thin film transistor, a gate of which is connected to the fourth control signal terminal, a first electrode of the sixth transistor is connected to the first reference voltage input terminal, and a second electrode of the sixth transistor is connected to the second node.

[0012] In some optional embodiments, a third storage unit is further included. The third storage unit is connected between the midpoint of the double-gate thin film transistor of the sixth transistor and the gate of the sixth transistor to stabilize the potential of the second node.

[0013] In some optional embodiments, it also includes: a fourth switch unit connected between the second reference voltage input terminal and the fifth node; The fifth switch unit is connected between the driving unit and the third reference voltage input terminal; the timing control circuit controls the on and off of the fourth switch unit and the fifth switch unit respectively through the third control signal terminal to achieve pulse reset of the driving unit.

[0014] In some optional embodiments, the fourth switch unit includes a seventh transistor, the gate of the seventh transistor is connected to the third control signal terminal, the first electrode of the seventh transistor is connected to the second reference voltage input terminal, and the second electrode of the seventh transistor is connected to the fifth node; the fifth switch unit includes an eighth transistor, the gate of the eighth transistor is connected to the third control signal terminal, the first electrode of the eighth transistor is connected to the third reference voltage input terminal, and the second electrode of the eighth transistor is connected to the first node.

[0015] In some optional embodiments, at least the transistor in the first switch unit and the transistor in the second switch unit are dual-gate thin film transistors.

[0016] In some optional embodiments, the light emitting element is an organic light emitting diode.

[0017] Another aspect of an embodiment of the present invention provides a display panel, comprising the above-mentioned pixel driving circuit.

[0018] The pixel driving circuit and display panel of the present invention respectively control the on and off of the first switch unit and the second switch unit through the timing control circuit, and completely separate the data signal writing time and the threshold voltage compensation time, so that the threshold voltage compensation process is no longer limited to the scanning time of each row of pixels, so that sufficient threshold voltage compensation can be performed at a high refresh rate, effectively improving the uniformity of the display screen, and eliminating problems such as brightness deviation and afterimage. By accurately controlling the on time of the second switch unit, the present invention ensures that the threshold voltage compensation time can be greater than a row of scanning time, which further enhances the effect of threshold voltage compensation, and can ensure the accuracy of threshold voltage compensation even at a high refresh rate, thereby significantly improving the display quality at a high refresh rate. In the light-emitting stage, the present invention outputs a pulse signal to the third control signal terminal through the timing control circuit, controls the on and off of at least two switch units connected to the driving unit, and realizes a pulse reset of the driving unit potential. This multiple reset effectively suppresses the hysteresis effect of the driving transistor, reduces the instability of OLED light emission, thereby significantly reducing screen flickering at a low refresh rate and improving viewing comfort.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0021] Figure 1 is a circuit connection diagram of a pixel driving circuit according to an embodiment of the present invention; Figure 2 This is a waveform diagram of an internal compensation pixel driving circuit in operation according to an embodiment of the present invention.

[0022] Among them, T1-first transistor, T2-second transistor, T3-third transistor, T4-fourth transistor, T5-fifth transistor, T6-sixth transistor, T7-seventh transistor, T8-eighth transistor, T9-ninth transistor, T10-tenth transistor, N1-first node, N2-second node, N3-third node, N4-fourth node, N5-fifth node, C1-first capacitor, C2-second capacitor, C3-third capacitor, SN_T1-first control signal terminal, SN_T3-second control signal terminal, SN+1-third control signal terminal, SN-1-fourth control signal terminal, Data-data input terminal, ELVDD-first power supply terminal, ELVSS-second power supply terminal, Vint1-first reference voltage input terminal, Vint2-second reference voltage input terminal, Vint3-third reference voltage input terminal, Vint4-fourth reference voltage input terminal, EM-enable signal input terminal. DETAILED DESCRIPTION

[0023] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0024] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application.However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, modules, devices, steps etc. can be adopted.In other cases, known modules, methods, devices, realizations, steps or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0025] In OLED displays, the brightness of a pixel is determined by the current flowing through the organic light-emitting diode (OLED) controlled by the driver transistor (Driver TFT). Due to the inherent process deviation of TFT devices, the threshold voltage (Vth) of the driver transistor of different pixels is different, resulting in different currents flowing through the OLED even if the same gate voltage is applied, causing uneven display brightness. Threshold voltage compensation technology aims to eliminate or reduce the impact of this Vth difference on the display effect. Its basic principle is to detect or compensate the Vth of the driver transistor through a specific circuit structure and driving timing to ensure the consistency of the brightness of each pixel. In addition, the data writing process is the process of converting the digital signal representing the pixel brightness into an analog voltage signal and writing it into the pixel capacitor. The rate and accuracy of this process directly affect the refresh rate and display quality of the display. On the other hand, the hysteresis effect of the driver transistor, that is, the phenomenon that the output current cannot reach the steady-state value instantaneously after the gate voltage changes, is particularly significant at low refresh rates, which will cause unstable OLED light emission and produce flicker that can be perceived by the human eye. Pulse drive technology drives OLED light emission by applying high voltage pulses in a short period of time and uses the visual persistence effect of the human eye to reduce flicker at low refresh rates while reducing average power consumption. The present invention aims at the problem that the traditional row-by-row Vth compensation method has insufficient compensation time at high refresh rates, and the flickering caused by the hysteresis effect of the driving transistor at low refresh rates. The present invention uses a timing control circuit to accurately control the on and off of the switch unit, realizes the separation of data writing and Vth compensation process, and makes the Vth compensation time greater than a row scanning time, thereby ensuring the adequacy of Vth compensation at high refresh rates. At the same time, by applying multiple pulse signals to the source of the driving unit during the light-emitting stage, the hysteresis effect of the driving transistor is effectively suppressed, and the screen flickering at low refresh rates is reduced, thereby achieving good compatibility between high and low refresh rates.

[0026] like Figure 1 As shown, one aspect of an embodiment of the present invention provides a pixel driving circuit, including: The driving unit is used to drive the light emitting element to emit light. A thin film transistor (TFT) is usually used as a driving transistor to control the current flowing through the OLED, thereby controlling the light emitting brightness of the OLED. In the embodiment of the present invention, the driving unit is preferably a thin film transistor, more preferably a P-type thin film transistor TFT, such as Figure 1The second transistor T2 in the embodiment is a PMOS TFT. The gate of the second transistor T2 receives a voltage signal from the second node N2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. The current between the source and drain of the second transistor T2 is controlled by the gate voltage, thereby driving the OLED to emit light. In other embodiments, the second transistor T2 may also adopt other circuit structures or devices with similar driving functions.

[0027] The first switch unit is used to receive the data signal of the data input terminal Data and transmit it to the fourth node N4. In the embodiment of the present invention, the first switch unit is preferably a thin film transistor, and more preferably a P-type thin film transistor, such as a PMOS TFT. The control end of the first switch unit is connected to the first control signal terminal SN_T1, the input end is connected to the data input terminal Data, and the output end is connected to the fourth node N4. When the first control signal terminal SN_T1 is at a valid level, such as a low level, the first switch unit is turned on and the data signal is transmitted to the fourth node N4; when the first control signal terminal SN_T1 is at an invalid level, such as a high level, the first switch unit is turned off to prevent the data signal from being transmitted. In other embodiments, the first switch unit may also adopt other circuit structures or devices with switching functions, such as transmission gates.

[0028] The second switch unit is used to control the threshold voltage compensation and transmit the compensated voltage to the second node N2. In an embodiment of the present invention, the second switch unit is preferably a thin film transistor, more preferably a P-type thin film transistor, such as a PMOS TFT. The control end of the second switch unit is connected to the second control signal terminal SN_T3, the input end is connected to the third node N3, and the output end is connected to the second node N2. By controlling the level of the second control signal terminal SN_T3, the conduction and shutdown of the second switch unit can be controlled, thereby controlling the Vth compensation process. In other embodiments, the second switch unit can also adopt other circuit structures or devices with switching functions.

[0029] The first storage unit is connected between the fourth node N4 and the second node N2. The function of the first storage unit is to keep the voltage of the second node stable during the data writing stage and the light emitting stage, so as to ensure the normal operation of the driving transistor. In an embodiment of the present invention, the first storage unit is preferably a capacitor. In some embodiments, the first storage unit includes a first capacitor C1, which is connected between the fourth node N4 and the second node N2, and is used to store the charge written to the fourth node N4 during the data writing stage, and affects the potential of the second node N2 through the capacitive coupling effect, thereby controlling the gate voltage of the second transistor T2. Specifically, when the data signal is written to the fourth node N4 through the first switch unit, the potential of the fourth node N4 changes. Since the voltage across the first capacitor C1 cannot change suddenly, the potential of the second node N2 will also change accordingly, and the magnitude of the change depends on the capacitance value of the first capacitor C1 and the capacitance values ​​of other related capacitors. This capacitive coupling effect enables the data signal to be effectively transmitted to the gate of the second transistor T2, thereby controlling the luminous brightness of the OLED. In addition, in the light-emitting stage, the first capacitor C1 also plays a role in maintaining the potential of the second node N2 stable, preventing the gate voltage of the second transistor T2 from fluctuating due to factors such as leakage, thereby affecting the light-emitting stability of the OLED.

[0030] In some optional embodiments, the pixel driving circuit further includes a second capacitor C2, which is connected between the first power supply terminal ELVDD and the fourth node N4, and is used to stabilize the potential of the fourth node N4 in the Vth compensation stage, and assist the first capacitor C1 in maintaining the potential stability of the fourth node N4 in the data writing stage. Specifically, in the Vth compensation stage, by controlling the relevant switch unit, the potential of the fourth node N4 can be precharged to a specific voltage value, and the second capacitor C2 can store the charge corresponding to the voltage, and play a role in maintaining the stability of the potential of the fourth node N4 in the subsequent data writing stage and the light emitting stage, reducing the influence of interference or leakage of other circuit elements on the potential of the fourth node N4, thereby improving the accuracy of data writing and Vth compensation.

[0031] The timing control circuit is used to output control signals to the first control signal terminal SN_T1, the second control signal terminal SN_T3, the third control signal terminal SN+1 and the fourth control signal terminal SN-1, respectively, to control the on and off of the first switch unit and the second switch unit, so as to separate the data signal writing time from the threshold voltage compensation time, and control the on time of the second switch unit so that the compensation time of the threshold voltage Vth is greater than the line scanning time; and in the light-emitting stage, by outputting a pulse signal to the third control signal terminal SN+1, the potential of the driving unit is reset in a pulsed manner. Specifically, the timing control circuit generates a specific timing signal so that the first switch unit and the second switch unit are turned on or off respectively in different time periods, thereby realizing the time-sharing of data writing and Vth compensation. In addition, the timing control circuit controls the on time of the second switch unit so that the Vth compensation time can exceed the line scanning time to ensure that Vth is fully compensated. In addition, in the light-emitting stage, the timing control circuit outputs a pulse signal through the third control signal terminal SN+1 to control the on and off of at least two switch units connected to the first electrode of the second transistor T2, thereby realizing a pulse reset of the potential of the first electrode of the second transistor T2 to reduce the hysteresis effect of the driving transistor. The specific implementation of the timing control circuit can adopt various known timing control circuit structures, such as a shift register, a logic gate circuit, etc.

[0032] In some embodiments, the first switch unit includes a first transistor T1, the gate of the first transistor T1 is connected to the first control signal terminal SN_T1, the first electrode of the first transistor T1 is connected to the data input terminal Data, and the second electrode of the first transistor T1 is connected to the fourth node N4. Specifically, in this embodiment, the first switch unit uses a thin film transistor to realize the transmission control of the data signal. The first control signal terminal SN_T1 signal is used to control the on and off of the first transistor T1. When the first control signal terminal SN_T1 is a valid level, such as a low level, the first transistor T1 is turned on; when the first control signal terminal SN_T1 is an invalid level, such as a high level, the first transistor T1 is turned off. By controlling the level change of the first control signal terminal SN_T1, the writing timing of the data signal can be accurately controlled. The data input terminal Data is used to provide a data signal to be written into the pixel, and the data signal is usually an analog voltage signal, which represents the brightness information of the pixel. The first electrode of the first transistor T1, such as the source, is connected to the data input terminal Data so that the data signal is transmitted when the first transistor T1 is turned on. The second electrode of the first transistor T1, such as the drain, is connected to the fourth node N4. When the first transistor T1 is turned on, the data signal is transmitted from the data input terminal Data to the fourth node N4 through the first transistor T1, thereby completing the data writing process. In other embodiments, the first switch unit also includes a ninth transistor T9, the gate of the ninth transistor T9 is connected to the second control signal terminal SN_T3, the first electrode of the ninth transistor T9 is connected to the fourth reference voltage input terminal Vint4, and the second electrode of the ninth transistor T9 is connected to the fourth node N4. The ninth transistor T9 is used in this embodiment to reset the fourth node N4 in the threshold voltage (Vth) compensation stage. Specifically, in the Vth compensation stage, the second control signal terminal SN_T3 outputs a valid level, such as a low level, so that the ninth transistor T9 is turned on, and the potential of the fourth node N4 is pulled to the potential of the fourth reference voltage input terminal Vint4. In this way, the potential of the fourth node N4 can be initialized to a known state before Vth compensation is performed, thereby ensuring the accuracy of Vth compensation. In other stages, such as the data writing stage and the light emitting stage, the second control signal terminal SN_T3 outputs an invalid level, such as a high level, so that the ninth transistor T9 is turned off to avoid affecting the data writing and light emitting process. The ninth transistor T9 is preferably a thin film transistor TFT, and more preferably a P-type metal oxide semiconductor thin film transistor PMOS TFT.

[0033] By adopting the above implementation, the first control signal terminal SN_T1 is used to control the on and off of the first transistor T1, so as to accurately control the writing timing of the data signal, and cooperate with the timing control circuit to achieve the separation of the data signal writing time and the threshold voltage compensation time, which lays the foundation for the subsequent Vth compensation and driving the OLED to emit light. It should be pointed out that in this embodiment, Figure 1 The use of PMOS TFT as the first switch unit is only a preferred implementation and is not a limitation of the present invention. Any circuit structure or device that can realize data signal transmission control and can cooperate with the timing control circuit to realize the technical solution of separating the data signal writing time and the threshold voltage compensation time should fall within the protection scope of the present invention.

[0034] In some embodiments, the second switch unit includes a third transistor T3, the gate of the third transistor T3 is connected to the second control signal terminal SN_T3, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the second node N2. In an embodiment of the present invention, the second control signal terminal SN_T3 signal is used to control the on and off of the third transistor T3. When the second control signal terminal SN_T3 is a valid level, such as a low level, the third transistor T3 is turned on; when the second control signal terminal SN_T3 is an invalid level, such as a high level, the third transistor T3 is turned off. By controlling the level change of the second control signal terminal SN_T3, the start and end time of Vth compensation can be accurately controlled. Combined with the timing control circuit, the Vth compensation time can be greater than a row scan time. The third node N3 is connected to the second electrode of the second transistor T2. The second node N2 is connected to the gate of the second transistor T2. When the third transistor T3 is turned on, the voltage after Vth compensation is transmitted from the third node N3 to the second node N2 through the third transistor T3, thereby adjusting the gate voltage of the second transistor T2 to compensate for its threshold voltage drift. In other embodiments, the second switch unit further includes a tenth transistor T10, which is connected between the first power supply terminal ELVDD and the first node N1 and is controlled by the second control signal terminal SN_T3 signal. In this embodiment, the tenth transistor T10 is used to provide a compensation voltage, such as the potential of the first power supply terminal ELVDD, to the first node N1 during the threshold voltage (Vth) compensation stage. Specifically, during the Vth compensation stage, the second control signal terminal SN_T3 outputs an effective level, such as a low level, so that the third transistor T3 and the tenth transistor T10 are turned on at the same time. The conduction of the tenth transistor T10 applies the voltage of the first power supply terminal ELVDD to the first node N1. Combined with the connection relationship and timing control of the circuit, this helps to establish an appropriate voltage difference between the gate and source of the second transistor T2, that is, between the second node N2 and the third node N3 during the Vth compensation stage, thereby realizing Vth compensation. By controlling the effective level duration of the second control signal terminal SN_T3, the time length of Vth compensation can be controlled, thereby realizing that the Vth compensation time is greater than a row scanning time. In other stages, such as the data writing stage and the light emitting stage, the second control signal terminal SN_T3 outputs an invalid level, such as a high level, so that the tenth transistor T10 is turned off to avoid affecting the data writing and light emitting process. The tenth transistor T10 is preferably a thin film transistor TFT, and more preferably a P-type metal oxide semiconductor thin film transistor PMOS TFT.

[0035] By adopting the above-mentioned implementation mode, the second control signal terminal SN_T3 is used to control the conduction and shutdown of the third transistor T3, and in combination with other related circuits and timing control, Vth compensation can be effectively realized, and the time of Vth compensation can be accurately controlled to be greater than a line scanning time, thereby ensuring the adequacy of Vth compensation at a high refresh rate and significantly improving the uniformity of the display screen. It should be pointed out that the use of PMOS TFT as the second switching unit in this embodiment is only a preferred implementation mode and is not a limitation of the present invention. Any circuit structure or device that can realize Vth compensation control and voltage transmission, and can cooperate with the timing control circuit to realize a technical solution of Vth compensation time greater than a line scanning time, should fall within the protection scope of the present invention.

[0036] In some embodiments, the pixel driving circuit further includes a third switch unit, the third switch unit includes a sixth transistor T6, the sixth transistor T6 is a double-gate thin film transistor, the gate of which is connected to the fourth control signal terminal SN-1, the first electrode of the sixth transistor T6 is connected to the first reference voltage input terminal Vint1, and the second electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 adopts a double-gate thin film transistor (Double-Gate TFT) structure. Compared with the traditional single-gate TFT, the double-gate TFT has better switching characteristics, lower leakage current and higher stability. In the embodiment of the present invention, the use of a double-gate TFT as the sixth transistor T6 can more effectively control its conduction and shutdown, and reduce its influence on other circuit elements, especially in the Vth compensation and reset stage, it can better stabilize the potential of the second node N2 and improve the accuracy of compensation and reset. The signal of the fourth control signal terminal SN-1 is used to control the conduction and shutdown of the sixth transistor T6. When the fourth control signal terminal SN-1 is a valid level, such as a low level, the sixth transistor T6 is turned on; when the fourth control signal terminal SN-1 is an invalid level, such as a high level, the sixth transistor T6 is turned off. By controlling the level change of the fourth control signal terminal SN-1, the working state of the sixth transistor T6 can be controlled. Combined with the timing control circuit, the sixth transistor T6 can be turned on in a specific time period to stabilize the potential of the second node N2. The first reference voltage input terminal Vint1 provides a stable reference voltage for assisting in stabilizing the potential of the second node N2. When the sixth transistor T6 is turned on, the voltage of the first reference voltage input terminal Vint1 affects the potential of the second node N2, reducing the influence of noise and interference on the potential of the second node N2. In other embodiments, the third switch unit can also be implemented by other circuit structures or devices with similar functions.

[0037] By adopting the above-mentioned implementation mode, using a dual-gate TFT as the sixth transistor T6, and using the fourth control signal terminal SN-1 to control it, the potential of the second node N2 can be more effectively stabilized, and the influence of noise and interference on the potential of the second node N2 can be reduced, thereby improving the accuracy of Vth compensation and reset, and ultimately helping to improve the quality of the display image. The use of dual-gate TFTs also enhances the stability of the circuit and improves the reliability of the device. It should be pointed out that in this embodiment, the use of a dual-gate PMOS TFT as the sixth transistor T6 of the third switch unit is only a preferred implementation mode and is not a limitation of the present invention. Any circuit structure or device that can achieve the stabilization of the potential of the second node N2 and can cooperate with the timing control circuit to realize the relevant functions should fall within the protection scope of the present invention.

[0038] In some embodiments, the pixel driving circuit also includes a third storage unit, which is connected between the midpoint of the dual-gate thin-film transistor of the sixth transistor T6 and the gate of the sixth transistor T6, and is used to stabilize the potential of the second node N2. In an embodiment of the present invention, in order to further improve the stability of the potential of the second node N2, the third storage unit also includes a third capacitor C3. The dual-gate TFT has two gates, which can be used in parallel or controlled separately. When the midpoint between the two gates of the dual-gate TFT has a certain parasitic capacitance due to its special structure. After connecting the additional capacitor, namely the third capacitor C3, it is equivalent to increasing the parasitic capacitance to form a capacitive voltage divider network. This capacitive voltage divider network can effectively filter out high-frequency noise and interference, and reduce the potential fluctuation of the second node N2 caused by factors such as switching actions or leakage of other circuit elements. When the two gates are used in parallel, such as Figure 1 As shown, there is a midpoint between the two gates, and the midpoint usually has a certain capacitance effect. The third capacitor C3 is not directly connected between the N2 node and the gate of the sixth transistor T6, but is connected between the double-gate midpoint of the sixth transistor T6 and the gate of the sixth transistor T6. This connection method utilizes the inherent capacitance characteristics of the double-gate TFT, and combines the additional third capacitor C3 to form a more effective capacitor network, thereby more effectively stabilizing the potential of the second node N2. The role of the third capacitor C3 is to stabilize the potential of the second node N2 in different working stages, such as the Vth compensation stage, the data writing stage, and the light-emitting stage, and reduce the impact of noise and interference on the potential of the second node N2. Since the second node N2 is directly connected to the gate of the second transistor T2, the stability of the second node N2 potential directly affects the working state of the second transistor T2, thereby affecting the luminous brightness of the OLED.

[0039] By adopting the above-mentioned embodiment, the third capacitor C3 connected between the midpoint and the gate of the dual-gate TFT can be used to more effectively stabilize the potential of the second node N2, reduce noise and interference, improve the accuracy of Vth compensation, and ultimately improve the quality of the display image. In particular, when the driving transistor works for a long time or works at a high ambient temperature, the stabilizing effect of the third storage unit is more obvious, and it can effectively prevent the display image from flickering or uneven brightness. It should be pointed out that in this embodiment, the use of the capacitor connected between the midpoint and the gate of the dual-gate TFT, that is, the third capacitor C3, to stabilize the potential of the second node N2 is only a preferred embodiment and is not a limitation of the present invention. Any circuit structure or device that can effectively stabilize the potential of the second node N2 should fall within the scope of protection of the present invention.

[0040] In some embodiments, in order to reduce the hysteresis effect of the driving unit at a low refresh rate, thereby reducing screen flicker, the pixel driving circuit further includes: The fourth switch unit is connected between the second reference voltage input terminal Vint2 and the fifth node N5. In the embodiment of the present invention, the fourth switch unit is used to pull the potential of the fifth node N5, ie, the first electrode of the OLED, to the potential of the second reference voltage input terminal Vint2 during the reset phase.

[0041] The fifth switch unit is connected between the driving unit and the third reference voltage input terminal Vint3. The timing control circuit controls the on and off of the fourth switch unit and the fifth switch unit through the third control signal terminal SN+1 to achieve pulse reset of the driving unit. Due to the hysteresis effect of the second transistor T2, its output current will show different characteristics due to different historical states when the same gate voltage is applied. In an embodiment of the present invention, the fifth switch unit is used to pull the potential of the first pole of the driving unit to the potential of the third reference voltage input terminal Vint3 during the reset stage. During the light-emitting stage, that is, during the light-emitting period of the OLED, the timing control circuit outputs a series of pulse signals through the third control signal terminal SN+1. By reasonably setting the values ​​of the second reference voltage input terminal Vint2 and the third reference voltage input terminal Vint3, the VGS change of the second transistor T2 during the reset period can be effectively controlled, thereby achieving the best reset effect, and then the hysteresis effect of the second transistor T2 can be effectively suppressed, and the instability of the OLED light emission can be reduced, thereby reducing the screen flicker.

[0042] By adopting the above implementation, the fourth switch unit and the fifth switch unit are controlled by the timing control circuit, so as to realize the pulse reset of the potential of the first electrode of the driving unit, which can effectively suppress the hysteresis effect of the second transistor T2, significantly reduce the screen flicker at a low refresh rate, and improve the viewing comfort. In addition, by adjusting the frequency and amplitude of the pulse, it can be optimized according to different display requirements to further improve the display performance.

[0043] In some embodiments, the pixel driving circuit further includes: the fourth switch unit includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third control signal terminal SN+1, the first electrode of the seventh transistor T7 is connected to the second reference voltage input terminal Vint2, and the second electrode of the seventh transistor T7 is connected to the fifth node N5. In the embodiment of the present invention, the seventh transistor T7 is preferably a thin film transistor TFT, and more preferably a P-type metal oxide semiconductor thin film transistor PMOS TFT. When the third control signal terminal SN+1 is at an effective level, such as a low level, the seventh transistor T7 is turned on, and the potential of the fifth node N5, i.e., the second electrode of the second transistor T2, is pulled to Vint2 to achieve reset.

[0044] The fifth switch unit includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the third control signal terminal SN+1, the first electrode of the eighth transistor T8 is connected to the third reference voltage input terminal Vint3, and the second electrode of the eighth transistor T8 is connected to the first node N1, i.e., the first electrode of the driving unit. In the embodiment of the present invention, the eighth transistor T8 is preferably a PMOS TFT. When the third control signal terminal SN+1 is at an effective level, such as a low level, the eighth transistor T8 is turned on, and the potential of the first node N1 is pulled to the potential of the third reference voltage input terminal Vint3. It should be pointed out that since the second electrode of the eighth transistor T8 is connected to the first node N1, i.e., the first electrode of the second transistor T2, the conduction of the eighth transistor T8 actually indirectly affects the change of its potential by affecting the potential of the first electrode of the driving unit. Combined with the action of the seventh transistor T7, the seventh transistor T7 pulls the potential of the fifth node N5 to the potential of the second reference voltage input terminal Vint2, and the eighth transistor T8 pulls the potential of the first node N1 to the potential of the third reference voltage input terminal Vint3. By the pulse change of the signal at the third control signal terminal SN+1, the conduction and cutoff of the seventh transistor T7 and the eighth transistor T8 are controlled simultaneously, so as to realize the pulse reset of the driving unit, namely the second transistor T2.

[0045] In some embodiments, at least the transistor in the first switch unit and the transistor in the second switch unit are double-gate thin film transistors. Compared with single-gate TFT, double-gate TFT has smaller leakage current and higher stability. The two gates of double-gate TFT can more effectively control the formation and conduction of the channel, thereby reducing leakage current and improving the switching speed and stability of the device. The first switch unit is used to control the writing of data signals, and its performance directly affects the accuracy and speed of data writing. Using double-gate TFT as the transistor in the first switch unit can effectively reduce leakage current and improve switching speed, thereby improving the accuracy of data writing. The second switch unit is used to control Vth compensation, and its performance directly affects the accuracy of Vth compensation. Using double-gate TFT as the transistor in the second switch unit can also effectively reduce leakage current and improve switching speed, thereby improving the accuracy of Vth compensation. Specifically, in the embodiment of the present invention, in order to further improve the performance and stability of the circuit, especially to better stabilize the potential of the second node N2 and the fourth node N4, and improve hysteresis and leakage, at least the transistors in the first switch unit and the second switch unit adopt a double-gate thin film transistor (Double-Gate TFT) structure. Preferably, the thin film transistor TFT connected to the second node N2 and the fourth node N4, that is, the first transistor T1, the third transistor T3 and the ninth transistor T9 are all dual-gate TFTs. Compared with the single-gate TFT, the dual-gate TFT has a smaller leakage current and can reduce charge leakage, thereby better maintaining the voltage stability of the node.

[0046] By adopting the above-mentioned implementation mode, using a dual-gate TFT to replace part or all of the thin-film transistor TFTs connected to the second node N2 and the fourth node N4 can more effectively stabilize the potential of the second node N2 and the fourth node N4, reduce leakage and hysteresis effects, thereby improving the screen flicker perceived by the human eye, especially at low refresh rates. The effect is more obvious. This allows the pixel driving circuit of the present invention to support a lower refresh rate display, such as a display of 30Hz or even lower than 30Hz, thereby further reducing the display power consumption while ensuring the display quality. It should be pointed out that in this embodiment, replacing the transistors in at least the first switch unit and the second switch unit with dual-gate TFTs, and preferably replacing all the TFTs connected to the second node N2 and the fourth node N4 with dual-gate TFTs is only a preferred implementation mode and is not a limitation of the present invention. Any circuit structure or device that can effectively reduce leakage current, improve node potential stability, and thus improve display effects should fall within the scope of protection of the present invention.

[0047] In some embodiments, the thin film transistor TFT connected to the first capacitor C1 and the second capacitor C2 is not limited to a P-type TFT or an N-type TFT. Specifically, the thin film transistor TFT connected to the first capacitor C1 and the second capacitor C2, such as the first transistor T1, the third transistor T3, the sixth transistor T6, and the ninth transistor T9, can use a P-type TFT, that is, a PMOS TFT, as a transistor in the switch unit. Preferably, if the thin film transistor TFT connected to the first capacitor C1 and the second capacitor C2 is an N-type TFT. The leakage current of the transistor is one of the important factors affecting the performance of the circuit. The leakage current will cause the leakage of the charge, thereby affecting the stability and power consumption of the circuit. In the pixel driving circuit, the leakage current will cause the charge stored on the capacitor to decrease, thereby affecting the display brightness. Especially at low refresh rates, due to the long refresh cycle, the influence of the leakage current is more obvious. Using a transistor with a lower leakage current characteristic can effectively slow down the charge leakage and improve the display effect. Then the refresh rate can be further reduced by about 1Hz. N-type TFT may have a lower leakage current characteristic under certain process conditions, such as using an oxide semiconductor material (such as IGZO). Lower leakage current means that the charge stored in the first capacitor C1 and the second capacitor C2 leaks more slowly, so that the potential of the node can be kept stable for a longer time, which is suitable for application scenarios with extremely low refresh rates.

[0048] In some embodiments, the light-emitting element is an organic light-emitting diode (OLED). OLED is composed of multiple layers of organic thin films and is connected between the cathode and the anode. Specifically, in this embodiment, the pixel driving circuit is used to drive the organic light-emitting diode (OLED) to emit light. OLED is a current-driven light-emitting device, and its luminous brightness is proportional to the magnitude of the current flowing through it. Under the action of the electric field, electrons and holes are injected into the organic layer from the cathode and the anode respectively, and recombine in the light-emitting layer to generate photons and emit light. OLED has the advantages of self-luminescence, wide viewing angle, high contrast, fast response speed, and low power consumption, so it has been widely used in the display field. In the present invention, OLED is connected between the fifth node N5 and the second power supply terminal ELVSS, and the current flowing through it is controlled by the driving unit to control its luminous brightness. It should be pointed out that the use of OLED as a light-emitting element in this embodiment is only a preferred embodiment and is not a limitation of the present invention. Any element that can be driven to emit light by current and can be used in conjunction with the pixel driving circuit of the present invention should fall within the scope of protection of the present invention.

[0049] Based on the same inventive concept, another aspect of the embodiment of the present invention further provides a display panel, including the above-mentioned pixel driving circuit. The display panel can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. The specific implementation of the display panel can refer to the above-mentioned embodiment of the pixel driving circuit, and the repeated parts of the technical solution and technical effect will not be repeated.

[0050] like Figure 2 As shown, a waveform diagram of a pixel driving circuit provided by an embodiment of the present invention during operation. Based on the same inventive concept, another aspect of the embodiment of the present invention further provides a driving method of a pixel driving circuit, comprising the following stages: The t1 stage is the initialization stage: the fourth control signal terminal SN-1 is at an effective level, such as a low level, the sixth transistor T6 is turned on, the voltage of the first reference voltage input terminal Vint1 is applied to the second node N2, and the second node N2 is reset, so that the potential of the second node N2 is reset to the potential of the first reference voltage input terminal Vint1. The enable signal input terminal EM is an invalid level, i.e., a high level, the fourth transistor T4 and the fifth transistor T5 are turned off, and the second transistor T2 and the OLED do not work. The first control signal terminal SN_T1, the second control signal terminal SN_T3 and the third control signal terminal SN+1 are invalid levels (high levels), and the first transistor T1, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned off. The purpose of the t1 stage is to initialize the potential of the second node N2 to prepare for the subsequent Vth compensation.

[0051] Stage t2 is the Vth compensation stage: when the second control signal terminal SN_T3 is at a valid level, i.e., a low level, the third transistor T3, the ninth transistor T9, and the tenth transistor T10 are turned on. The ninth transistor T9 is turned on, and the voltage of the fourth reference voltage input terminal Vint4 is applied to the fourth node N4 to initialize the fourth node N4. The tenth transistor T10 is turned on, and the voltage of the first power supply terminal ELVDD is applied to the first node N1. The third transistor T3 is turned on, and the potential of the first node N1 is transmitted to the third node N3 through the second transistor T2. The potential of the second electrode of the second transistor T2 begins to rise, and then is transmitted to the second node N2 through the third transistor T3. Under the charging action of the first capacitor C1, the potential of the second node N2 gradually rises to the first power supply terminal ELVDD+Vth, and the potential of the gate of the second transistor T2, i.e., the second node N2, rises to ELVDD + Vth. The threshold voltage Vth of the second transistor T2 is compensated by the first power supply terminal ELVDD, i.e., The compensation time of this stage can be greater than a line scan time to ensure that Vth is fully compensated. The fourth control signal terminal SN-1, the first control signal terminal SN_T1, the enable signal input terminal EM and the third control signal terminal SN+1 are invalid levels, i.e., high levels, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. The purpose of the t2 stage is to perform Vth compensation on the second transistor T2 and ensure that the compensation time is greater than a line scan time.

[0052] Phase t3 is the data writing phase: the first control signal terminal SN_T1 is at a low level, the first transistor T1 is turned on, and the data signal of the data input terminal Data is written to the fourth node N4, so that the potential of the fourth node N4 changes from the potential of the fourth reference voltage input terminal Vint4 to the potential of the data input terminal Data, that is, ΔN4 = Data - Vint4. The potential of the second node N2 is coupled by ΔN4. Since the first capacitor C1 is connected between the fourth node N4 and the second node N2, the change of the potential of the fourth node N4 will affect the potential of the second node N2 through the capacitive coupling effect, so that Where A = C1 / C total_N2 , C total_N2 is the sum of all the capacitances of the second node N2. When the first capacitance C1 is relatively large relative to other capacitances, A ≈ 1, then N2 ≈ ELVDD + Vth + Data - Vint4. The fourth control signal terminal SN-1, the second control signal terminal SN_T3, the enable signal input terminal EM and the third control signal terminal SN+1 are at a high level, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned off. The purpose of this stage is to write the data signal into the pixel circuit and transmit the data signal to the gate of the driving unit, i.e., the second transistor T2, by using the capacitive coupling effect.

[0053] The t4 stage is the reset stage: the third control signal terminal SN+1 is at a low level, the seventh transistor T7 is turned on, and the potential of the fifth node N5 is pulled to the potential of the second reference voltage input terminal Vint2, resetting the OLED device. The eighth transistor T8 is turned on, and the potential of the first node N1 is pulled to the potential of the third reference voltage input terminal Vint3, and the seventh transistor T7 and the eighth transistor T8 are controlled to be turned on and off at the same time, so as to realize the pulse reset of the second transistor T2 of the driving unit and improve the hysteresis effect of the second transistor T2. The fourth control signal terminal SN-1, the first control signal terminal SN_T1, the second control signal terminal SN_T3 and the enable signal input terminal EM are at a high level, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9 and the tenth transistor T10 are turned off. The purpose of this stage is to reset the OLED device and realize the pulse reset by affecting the potential of the driving unit to reduce the hysteresis effect of the second transistor T2.

[0054] Phase t5 is the light-emitting phase: the enable signal input terminal EM is at a low level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the second transistor T2 of the driving unit starts to work, driving the OLED to emit light. The current I flowing through the OLED OLED It can be expressed by the following formula: It can be seen that the current of the OLED is proportional to the square of the difference between the Data signal and Vint4, and has nothing to do with the Vth of the driving unit, thereby achieving Vth compensation. The fourth control signal terminal SN-1, the first control signal terminal SN_T1, the second control signal terminal SN_T3 and the third control signal terminal SN+1 are at a high level, and the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned off. The purpose of this stage is to drive the OLED to emit light and achieve current output related to the data signal.

[0055] Through the above-mentioned driving method, the pixel driving circuit of the present invention can effectively separate the data writing and Vth compensation time, and make the Vth compensation time greater than the line scanning time, so that sufficient Vth compensation can be performed even at a high refresh rate, thereby improving the uniformity of the display image. At the same time, by performing a pulse reset during the light-emitting stage, the screen flicker at a low refresh rate can be effectively reduced. Therefore, the present invention is well compatible with high and low refresh rate displays, improving display quality and user experience. It should be pointed out that if Figure 2The waveform diagram shown and the above-mentioned driving method are only a preferred implementation method and are not intended to limit the present invention. The frequency, amplitude, duty cycle of the pulse signal, the timing relationship of each control signal, the voltage values ​​of the first reference voltage input terminal Vint1, the second reference voltage input terminal Vint2, the third reference voltage input terminal Vint3 and the fourth reference voltage input terminal Vint4 can all be adjusted according to specific circuit parameters and display requirements. Any driving method that can achieve the separation of data writing and Vth compensation time, Vth compensation time greater than a line scanning time, and pulse reset during the light-emitting stage should fall within the protection scope of the present invention.

[0056] In summary, the pixel driving circuit, driving method and display panel of the present invention accurately control the on and off of the switch unit through the timing control circuit, completely separate the data writing and Vth compensation process, so that the Vth compensation process is no longer limited to the scanning time of each row of pixels. This allows sufficient Vth compensation to be performed even at a high refresh rate, thereby supporting a higher refresh rate, such as higher than 240Hz. By accurately controlling the on time of the second switch unit, it is ensured that the Vth compensation time can be greater than a row of scanning time, which further enhances the effect of Vth compensation, and the accuracy of Vth compensation can be guaranteed even at a high refresh rate, thereby significantly improving the display quality at a high refresh rate. The source potential of the driving unit is pulsed reset by the timing control circuit during the light-emitting stage, which effectively suppresses the hysteresis effect of the driving transistor, thereby reducing the screen flicker at a low refresh rate. In combination with a low leakage transistor such as a dual-gate TFT or an IGZO TFT, charge leakage can be further reduced, thereby supporting a lower refresh rate, such as less than 30Hz, or even up to about ~1Hz. The 10T3C circuit proposed in some embodiments of the present invention is a pixel circuit including 10 transistors and 3 capacitors. Through the circuit design and timing control in the embodiments of the present invention, it is possible to better balance the Vth compensation under high refresh rate and the flicker suppression under low refresh rate, thereby achieving a wider range of dynamic refresh rate support. In particular, the use of dual-gate TFT or low-leakage IGZO TFT, in conjunction with the second capacitor C2 and the third capacitor C3, can further reduce the leakage current of the circuit, improve the low-frequency driving capability, and support a lower refresh rate, such as ~1Hz. Through the combined application of the above-mentioned technical means, the pixel drive circuit, drive method and display panel of the present invention can effectively support a wide range of dynamic refresh rates, at least 30Hz~240Hz dynamic refresh rates can be achieved, and by optimizing the circuit design and device selection, it can be further expanded to a high refresh rate higher than 240Hz and a low refresh rate lower than 30Hz, even reaching about ~1Hz. This enables display devices to flexibly switch refresh rates in different application scenarios. For example, high refresh rates are used to obtain smooth images when playing high-frame rate games or videos, and low refresh rates are used to reduce power consumption when browsing static web pages or reading e-books, thereby maximizing the user experience and extending device battery life.

[0057] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: A driving unit, used for driving the light-emitting element to emit light; A first switch unit, configured to receive a data signal from a data input terminal and transmit the data signal to a fourth node; A second switch unit, used for controlling threshold voltage compensation and transmitting the compensated voltage to a second node; a first storage unit connected between the fourth node and the second node; The timing control circuit is used to output control signals to the first control signal terminal, the second control signal terminal, the third control signal terminal and the fourth control signal terminal respectively, so as to control the on and off of the first switch unit and the second switch unit, thereby separating the data signal writing time from the threshold voltage compensation time, and controlling the on time of the second switch unit so that the threshold voltage compensation time is greater than a row scanning time; And in the light-emitting stage, a pulse signal is output to the third control signal terminal to perform a pulse reset on the driving unit.

2. The pixel driving circuit according to claim 1, characterized in that: The first switch unit includes a first transistor, a gate of the first transistor is connected to the first control signal terminal, a first electrode of the first transistor is connected to the data input terminal, and a second electrode of the first transistor is connected to the fourth node.

3. The pixel driving circuit according to claim 1, characterized in that: The second switch unit includes a third transistor, a gate of the third transistor is connected to the second control signal terminal, a first electrode of the third transistor is connected to a third node, and a second electrode of the third transistor is connected to the second node.

4. The pixel driving circuit according to claim 1, characterized in that: It also includes a third switching unit, which includes a sixth transistor. The sixth transistor is a dual-gate thin-film transistor, whose gate is connected to the fourth control signal terminal, the first electrode of the sixth transistor is connected to the first reference voltage input terminal, and the second electrode of the sixth transistor is connected to the second node.

5. The pixel driving circuit according to claim 4, characterized in that: It also includes a third storage unit, which is connected between the midpoint of the double-gate thin film transistor of the sixth transistor and the gate of the sixth transistor and is used to stabilize the potential of the second node.

6. The pixel driving circuit according to claim 1, characterized in that: Also includes: a fourth switch unit connected between the second reference voltage input terminal and the fifth node; a fifth switch unit, connected between the driving unit and a third reference voltage input terminal; The timing control circuit controls the on and off of the fourth switch unit and the fifth switch unit respectively through the third control signal terminal, so as to realize pulse reset of the driving unit.

7. The pixel driving circuit according to claim 6, characterized in that: The fourth switch unit includes a seventh transistor, the gate of the seventh transistor is connected to the third control signal terminal, the first electrode of the seventh transistor is connected to the second reference voltage input terminal, and the second electrode of the seventh transistor is connected to the fifth node; the fifth switch unit includes an eighth transistor, the gate of the eighth transistor is connected to the third control signal terminal, the first electrode of the eighth transistor is connected to the third reference voltage input terminal, and the second electrode of the eighth transistor is connected to the first node.

8. The pixel driving circuit according to any one of claims 1 to 7, characterized in that: At least the transistor in the first switch unit and the transistor in the second switch unit are dual-gate thin film transistors.

9. The pixel driving circuit according to any one of claims 1 to 7, characterized in that: The light emitting element is an organic light emitting diode.

10. A display panel, characterized in that: The invention comprises a pixel driving circuit according to any one of claims 1 to 9.

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