Semiconductor device for controlling operation power supplied to word line driver

Abstract

The invention relates to a semiconductor device for controlling operation power supplied to a word line driver. The semiconductor device may include: a power control signal generation circuit configured to generate an activated power control signal when at least one of a power-up period starts and a test mode operation is performed; and an operation power generation circuit configured to set the operation power supplied to the word line driver to a high voltage in response to the power control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0137165 filed on October 13, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device for controlling operating power supplied to a word line driver. Background Art

[0004] Generally, a semiconductor device such as a DRAM performs an operation of accessing a memory cell in order to perform a write operation of storing data in the memory cell and a read operation of outputting data already stored in the memory cell. The activation operation may be performed in the following manner: selecting one of the main word line signals in response to a row address; enabling the selected main word line signal; selecting at least one of the word line signals that have been assigned to the selected main word line signal; and enabling the selected at least one word line signal. Summary of the invention

[0005] In an embodiment, a semiconductor device may include: a power control signal generating circuit configured to generate a power control signal, which is activated in at least one case when a power-on period starts and a test mode operation is performed; and an operating power generating circuit configured to set the operating power supplied to a word line driver to a high voltage in response to the power control signal.

[0006] In one embodiment, a semiconductor device may include: a latch signal generating circuit configured to generate a latch signal in response to a power-on signal and a feedback voltage; a first voltage setting circuit configured to generate a first voltage in response to the latch signal and a test mode signal; a second voltage setting circuit configured to generate a second voltage in response to a storage matrix selection signal, and to generate a feedback voltage in response to the second voltage; and a control signal output circuit configured to generate a power control signal for setting a voltage level of operating power supplied to a word line driver in response to the first voltage and the second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is based on Figure 1 A circuit diagram of an example of a power control signal generating circuit included in a semiconductor device shown in FIG.

[0009] Figure 3 is based on Figure 1 A circuit diagram of an example of an operating power generating circuit included in a semiconductor device shown.

[0010] Figure 4 is based on Figure 1 FIG. 2 is a block diagram of an example of a word line driver included in a semiconductor device shown in FIG.

[0011] Figure 5 is based on Figure 4 A circuit diagram of an example of a main word line driver included in the word line driver shown.

[0012] Figure 6 is based on Figure 4 A circuit diagram of an example of a sub word line driver included in the word line driver shown.

[0013] Figure 7 and Figure 8 It is used to describe control Figure 1 FIG. 1 is a timing diagram of the operation of the power control signal for generating the operating power in the semiconductor device shown.

[0014] Fig. 9 is a block diagram showing a configuration of a semiconductor system according to an embodiment of the present disclosure.

[0015] Fig.10 is a block diagram showing a configuration of an electronic system according to an embodiment of the present disclosure.

[0016] Fig.11 is a block diagram illustrating a configuration of an electronic system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In the description of the following embodiments, the term "preset" means that the value of the parameter is predetermined when the parameter is used in a process or algorithm. According to the embodiment, the value of the parameter can be set at the beginning of the process or algorithm, or when the process or algorithm is executed.

[0018] Terms such as "first" and "second" are used to distinguish the identification of components and should not be interpreted as limiting the components. For example, for identification purposes, a "first" component may be referred to as a "second" component, and vice versa.

[0019] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other, or coupled or connected to each other with another component interposed therebetween. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without interposing another component therebetween.

[0020] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is different from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to an embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to an embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

[0021] "Logical bit group" may mean a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit group of the signal may be set differently. For example, if two bits are included in the signal, when the logic levels of the two bits included in the signal are "logic low level" and "logic low level", the logic bit group of the signal may be set to a first logic bit group, and when the logic levels of the two bits included in the signal are "logic low level" and "logic high level", the logic bit group of the signal may be set to a second logic bit group.

[0022] The present disclosure is described in more detail below through examples. The examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0023] Figure 1 1 is a block diagram showing the configuration of a semiconductor device 10 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor device 10 may include a command decoder (CMD DEC) 101, an address decoder (ADD DEC) 103, a power-on signal generating circuit (PWR GEN) 105, a power control signal generating circuit (VEN GEN) 107, an operating power generating circuit (VPPC GEN) 109, a word line driver (WL DRV) 111 and a cell array 113.

[0024] The command decoder 101 may generate an activation signal ACT, a refresh signal REF, and a precharge signal PCG in response to a command address CA. The command decoder 101 may generate an activation signal ACT, a refresh signal REF, and a precharge signal PCG by extracting a command from the command address CA and decoding the command extracted from the command address CA. The command decoder 101 may generate an activation signal ACT that is activated in an activation operation for accessing at least one memory cell of the cell array 113. The command decoder 101 may generate a refresh signal REF that is activated for a refresh operation of a memory cell of the cell array 113. The command decoder 101 may generate a precharge signal PCG that is activated for a precharge operation of the cell array 113. The command decoder 101 may be electrically connected to the address decoder 103, and may supply the activation signal ACT and the refresh signal REF to the address decoder 103.

[0025] The address decoder 103 may generate a memory matrix (mat) selection signal MAT_SEL and a row address RADD in response to a command address CA, an activation signal ACT, and a refresh signal REF. The address decoder 103 may generate a memory matrix selection signal MAT_SEL and a row address RADD by extracting an address from the command address CA when an activation operation or a refresh operation is performed and decoding the address that has been extracted from the command address CA. When the cell array 113 may be divided into a plurality of memory matrices (not shown) and may be controlled in memory matrix units, the memory matrix selection signal MAT_SEL may include a plurality of bits, whose logical bit groups are set so as to select at least one of the memory matrices of the cell array 113. When the memory cells of the cell array 113 are connected to a plurality of word lines WL, the row address RADD may include a bit that may be “set” to logic 1 or logic 0 so as to select at least one of the word lines connected to the memory cells in the cell array 113. The address decoder 103 may be electrically connected to the power control signal generating circuit 107 and the word line driver 111 , and may supply the memory matrix selection signal MAT_SEL to the power control signal generating circuit (VEN GEN) 107 , and supply the memory matrix selection signal MAT_SEL and the row address RADD to the word line driver 111 .

[0026] The power-on signal generating circuit 105 may generate a power-on signal PWR in response to a power supply voltage VDD. The power-on signal generating circuit 105 may generate a power-on signal PWR having a first logic level during a power-on period during which the power supply voltage VDD is received from a controller (eg, Fig. 931) is supplied to the semiconductor device 10, rising or increasing from a low level (typically 0V or close to 0V) to a target voltage level (which will depend on the semiconductor device and therefore may vary from one semiconductor technology to another), and then after the power-on period is completed, a power-on signal PWR having a second logic level may be generated. In an alternative embodiment, the first logic level may be set to a logic high level and the second logic level may be set to a logic low level. The power-on signal generating circuit 105 may be electrically connected to the power control signal generating circuit 107, and the power-on signal PWR may be supplied to the power control signal generating circuit 107.

[0027] The power control signal generating circuit 107 may generate a power control signal VEN in response to a memory matrix selection signal MAT_SEL, a power-on signal PWR, and a test mode signal TM. When the power-on signal PWR is activated in a power-on period, the power control signal generating circuit 107 may generate the power control signal VEN. That is, when the power-on period starts, the power control signal generating circuit 107 may generate an activated power control signal VEN. When the test mode signal TM is activated in a test mode, the power control signal generating circuit 107 may generate the power control signal VEN. When a precharge operation is performed after at least one of the memory matrices (not shown) of the memory cell array 113 is selected by the memory matrix selection signal MAT_SEL and at least one of an activation operation and a refresh operation is performed, the power control signal generating circuit 107 may generate the power control signal VEN. The memory matrix selection signal MAT_SEL may include bits corresponding to the selected memory matrices (not shown) included in the cell array 113, respectively. For example, if the cell array 113 may include a first memory matrix and a second memory matrix, the first bit MAT_SEL of the memory matrix selection signal MAT_SEL <1> The first storage matrix can be indicated, and the second bit MAT_SEL of the storage matrix selection signal MAT_SEL <2> The second storage matrix may be indicated. The power control signal generating circuit 107 may be electrically connected to the operating power generating circuit 109 , and may supply the power control signal VEN to the operating power generating circuit 109 .

[0028] The operating power generation circuit 109 may generate an operating power VPPC from a high voltage VPP in response to a power control signal VEN. When the power control signal VEN is activated, the operating power generation circuit 109 may set the operating power VPPC to the high voltage VPP. For example, the high voltage VPP may be a pumping voltage greater than the power supply voltage VDD. When the power control signal VEN is deactivated, the operating power generation circuit 109 may maintain the voltage level of the operating power VPPC so that the voltage level of the operating power VPPC does not drop to or below a voltage level obtained by subtracting a preset voltage level from the voltage level of the high voltage VPP. Although the power control signal VEN is deactivated, the operating power generation circuit 109 may prevent a sudden drop in the operating power VPPC.

[0029] The word line driver 111 may drive the word line WL in response to the memory matrix selection signal MAT_SEL, the row address RADD, and the word line off signal WLOFF. When an activation operation or a refresh operation is not performed, the word line off signal WLOFF may be activated. The word line driver 111 may drive the selected main word line (e.g., the main word line 110) by operating the power VPPC in response to the memory matrix selection signal MAT_SEL and the row address RADD in a state where the word line off signal WLOFF has been deactivated. Figure 4 The word line driver 111 may drive the word line WL in response to the main word line MWLB driven by the operation power VPPC.

[0030] The cell array 113 may include a plurality of memory matrices (not shown) selected by a memory matrix selection signal MAT_SEL. Each of the memory matrices of the cell array 113 may include a plurality of memory cells connected to a word line WL. When an activation operation or a refresh operation is performed, the memory cells of the cell array 113 connected to the word line WL selected and driven by the memory matrix selection signal MAT_SEL and the row address RADD may be accessed.

[0031] Figure 2 is based on Figure 1 FIG. 1 is a circuit diagram of an example of a power control signal generating circuit 107A. Figure 2 As shown, the power control signal generating circuit 107A may include a latch signal generating circuit 121 , a first voltage setting circuit 123 , a second voltage setting circuit 125 and a control signal output circuit 127 .

[0032] The latch signal generating circuit 121 may generate a latch signal LAT in response to the power-on signal PWR and the feedback voltage FV. The latch signal generating circuit 121 may generate a latch signal LAT having a logic high level in response to the power-on signal PWR activated to have a logic high level in the power-on period. In addition, when a word line (e.g., Figure 1 At least one of the connected memory matrices (not shown) is selected by a memory matrix selection signal MAT_SELB. <n>and MAT_SELB<n+1> When the voltage level of the second voltage V2 is selected and set to a logic high level, the latch signal generating circuit 121 may generate the latch signal LAT having a logic low level in response to the feedback voltage FV having a voltage level of a logic low level.

[0033] The first voltage setting circuit 123 may be electrically connected to the latch signal generating circuit 121, and may receive the latch signal LAT from the latch signal generating circuit 121. The first voltage setting circuit 123 may generate a first voltage V1 in response to the latch signal LAT and the test mode signal TM. The test mode signal TM may be activated to a logic high level for the test mode to set the operating power VPPC to the high voltage VPP. When the level of the latch signal LAT is set to a logic high level or the test mode signal TM is activated to a logic high level, the first voltage setting circuit 123 may generate a first voltage V1 having a logic high level. When the level of the latch signal LAT is set to a logic low level or the test mode signal TM is deactivated to a logic low level, the first voltage setting circuit 123 may generate a first voltage V1 having a logic low level.

[0034] The second voltage setting circuit 125 may respond to the memory matrix selection signal MAT_SELB <n>and MAT_SELB<n+1> The second voltage V2 is generated, and the feedback voltage FV can be generated in response to the second voltage V2. The memory matrix selection signal MAT_SELB <n>and MAT_SELB<n+1> Each of the memory matrix selection signals MAT_SELB and MAT_SELB may correspond to one of the memory matrixes (not shown) connected to the word lines (e.g., WL) driven by the supply of the operation power VPPC, and may be activated when the corresponding memory matrix is ​​selected for the activation operation or the refresh operation. <n>and MAT_SELB<n+1> When one of the memory matrix selection signals MAT_SELB is activated to a logic low level, the second voltage setting circuit 125 may generate a second voltage V2 having a logic high level. The second voltage setting circuit 125 may generate a feedback voltage FV having a logic low level by inverting and buffering the second voltage V2 having a logic high level. When all memory matrix selection signals MAT_SELB are activated after an activation operation or a refresh operation is performed <n>and MAT_SELB<n+1> When deactivated to a logic high level for a precharge operation, the second voltage setting circuit 125 may generate the second voltage V2 having a logic low level, and may generate the feedback voltage FV having a logic high level.

[0035] The control signal output circuit 127 may be electrically connected to the first voltage setting circuit 123 and the second voltage setting circuit 125, may receive the first voltage V1 from the first voltage setting circuit 123, and may receive the second voltage V2 from the second voltage setting circuit 125. The control signal output circuit 127 may generate a power control signal VEN in response to the first voltage V1 and the second voltage V2. When the voltage level of one of the first voltage V1 and the second voltage V2 is set to a logic high level, the control signal output circuit 127 may generate a power control signal VEN activated to a logic high level so as to set the operating power VPPC to a high voltage VPP. The control signal output circuit 127 may generate a power control signal VEN activated to a logic high level by receiving the first voltage V1 having a logic high level in a power-on period or a test mode. When the first voltage V1 and the second voltage V2 are set to a logic low level, the control signal output circuit 127 may generate a power control signal VEN deactivated to a logic low level. When in response to the storage matrix selection signal MAT_SELB <n>and MAT_SELB<n+1> When performing a precharge operation after performing an active operation or a refresh operation on a selected memory matrix, the control signal output circuit 127 may generate a power control signal VEN deactivated to a logic low level by receiving a first voltage V1 and a second voltage V2 having a logic low level.

[0036] Figure 3 is based on Figure 1 A circuit diagram of an operating power generating circuit 109A is shown as an example of an operating power generating circuit 109. Figure 3 As shown, the operating power generation circuit 109A may include an inverter 131, PMOS transistors 133_1 and 133_2, and an NMOS transistor 135. The inverter 131 may output a power control signal VEN by inverting and buffering the power control signal VEN. The PMOS transistor 133_1 may operate as a switch element that is turned on in response to the output signal of the inverter 131. When the power control signal VEN is activated to a logic high level, the PMOS transistor 133_1 may set the operating power VPPC to a high voltage VPP. The NMOS transistor 135 and the PMOS transistor 133_2 may operate as diode elements and clamp the voltage level of the operating power VPPC. That is, when the PMOS transistor 133_1 is in the off state, the voltage level of the operating power VPPC can be "adjusted" or changed by the NMOS transistor 135 and the PMOS transistor 133_2 so that the voltage level of the operating power VPPC output to the VPPC output voltage node (VPPC) of the same name does not drop to a voltage level that exceeds the voltage drop across the NMOS transistors 135 and 133_2. This voltage is calculated by subtracting the voltage level of the sum of the threshold voltage of the NMOS transistor 135 and the threshold voltage of the PMOS transistor 133_2 from the high voltage VPP.

[0037] Figure 4 is based on Figure 1 1A is a block diagram of an example of a word line driver 111. Figure 4 As shown, the word line driver 111A may include a main word line driver group 141 and a sub word line driver group 143 .

[0038] The main word line driver group 141 may include a plurality of main word line drivers MWL DRV. Each main word line driver MWLDRV may drive the main word line MWLB by operating power VPPC in response to the storage matrix selection signal MAT_SEL, the row address RADD, and the word line turn-off signal WLOFF. Each main word line driver MWL DRV may drive the main word line MWLB selected by the storage matrix selection signal MAT_SEL and the row address RADD by operating power VPPC in a state where the word line turn-off signal WLOFF has been deactivated. The main word line driver group 141 may be electrically connected to the sub-word line driver group 143 through the main word line MWLB. The main word line MWLB corresponding to the storage matrix selection signal MAT_SEL and the row address RADD may be differently set according to the embodiment.

[0039] The sub-word line driver group 143 may include a plurality of sub-word line drivers SWL DRV. Each sub-word line driver SWLDRV may drive a word line WL in response to a selection signal FX, an inverted selection signal FXB, and a main word line MWLB. Each sub-word line driver SWL DRV may drive a word line WL selected in response to the selection signal FX, the inverted selection signal FXB, and the main word line MWLB. The word line WL corresponding to the selection signal FX, the inverted selection signal FXB, and the main word line MWLB may be differently set according to the embodiment.

[0040] Figure 5 is a circuit diagram according to an example of a main word line driver MWL DRV. In an active operation or a refresh operation, one main word line driver MWL DRV may be selected among the main word line drivers MWL DRV of the main word line driver group 141 by a memory matrix selection signal MAT_SEL.

[0041] like Figure 5 As shown, the main word line driver MWL DRV may include a driving signal generating circuit 151, a driving circuit 153, and a driving signal driving circuit 155. When the driving signal generating circuit 151 may receive a row address RADD having a logic high level in a state where the word line off signal WLOFF has been deactivated to a logic low level, the driving signal generating circuit 151 may generate a driving signal DR_S driven by the operation power VPPC. The driving circuit 153 may be electrically connected to the driving signal generating circuit 151, and may receive the driving signal DR_S from the driving signal generating circuit 151. When receiving the driving signal DR_S driven by the operation power VPPC, the driving circuit 153 may activate the main word line MWLB by driving the main word line MWLB to a logic low level. In a state where the main word line MWLB is not driven because an activation operation or a refresh operation has not been performed, the operation power VPPC may have a low voltage level due to a leakage current. In a state where the main word line MWLB has been deactivated to a logic high level, the driving signal driving circuit 155 may set the level of the driving signal DR_S to a logic low level.

[0042] Figure 6 is a circuit diagram according to an example of a sub word line driver SWL DRV.

[0043] like Figure 6 As shown, the sub-word line driver SWL DRV may include a PMOS transistor 161 and NMOS transistors 163_1 and 163_2. When the main word line MWLB is in a state where the main word line MWLB has been activated to a logic low level, the PMOS transistor 161 may be turned on and the word line WL may be driven by the selection signal FX. The PMOS transistor 161 may be supplied with a high voltage VPP as a body voltage for setting a threshold voltage. The selection signal FX may be activated to an operating power VPPC so as to drive the word line WL corresponding to an activation operation or a refresh operation to a logic high level. When the main word line MWLB is in a state where the main word line MWLB has been driven by an operating power VPPC, the NMOS transistor 163_1 may be turned on and the word line WL may be driven by a reverse bias voltage VBBW. The reverse bias voltage VBBW may be generated by a pump circuit within the semiconductor device 10 so as to generate a voltage having a higher bias voltage than that generated by a controller (e.g., Figure 8 The NMOS transistor 163_2 may be turned on in response to the inverted selection signal FXB, and may drive the word line WL by the reverse bias voltage VBBW. When the activation operation or the refresh operation is not performed, the inverted selection signal FXB may be activated to the operation power VPPC so as to drive the word line WL to the reverse bias voltage VBBW.

[0044] Figure 7 and Figure 8 1 is a timing chart for describing the operation of the power control signal generating circuit 107 for controlling the generation of the operating power VPPC in the semiconductor device 10. Figure 2 , Figure 7 and Figure 8 The operation of the power control signal generating circuit 107 is described below by dividing the operation into a first case where a precharge operation is performed after an active operation or a refresh operation is performed in the semiconductor device 10 and a second case where a test mode operation is performed.

[0045] Below, refer to Figure 2 and Figure 7 The operation of the power control signal generating circuit 107 when the precharge operation is performed after the activation operation or the refresh operation is performed in the semiconductor device 10 is described. First, because the power-on signal PWR having a logic high level is received during the power-on period (i.e., during the period before T11) in which the power supply voltage VDD rises from 0V to the target voltage level, the power control signal generating circuit 107 can set the operating power VPPC to the high voltage VPP by generating the power control signal VEN activated to the logic high level. Because the operating power VPPC is set to the high voltage VPP in response to the power-on signal PWR before the activation operation or the refresh operation is performed, the voltage level of the operating power VPPC can be prevented from being excessively reduced. Next, the power control signal generating circuit (VEN GEN) 107 can maintain the state in which the operating power VPPC has been set to the high voltage VPP by generating the power control signal VEN activated to the logic high level during the period from T13 to T15, and in the period from T13 to T15, the storage matrix selection signal MAT_SELB having a logic low level is activated. <n>The selected memory matrix performs an activation operation or a refresh operation. Next, the power control signal generating circuit (VEN GEN) 107 can maintain the voltage level of the operating power VPPC by generating the power control signal VEN which is deactivated to a logic low level during the period from T15 to T17 so that the voltage level of the operating power VPPC does not drop to a voltage level calculated by subtracting a preset voltage level from the voltage level of the high voltage VPP or lower. In the period from T15 to T17, the memory matrix selection signal MAT_SELB <n>The level of is set to a logic high level to perform a precharge operation on the memory matrix on which an activation operation or a refresh operation has been performed.

[0046] Below, refer to Figure 2 and Figure 8 The operation of the power control signal generating circuit 107 is described when the test mode operation is performed in the semiconductor device 10. The power control signal generating circuit 107 can set the operating power VPPC to the high voltage VPP by generating the power control signal VEN activated to the logic high level during the period after T21 in which the test mode signal TM is activated to the logic high level for the test mode operation. Since the operating power VPPC is set to the high voltage VPP in the test mode operation, the voltage level of the operating power VPPC can be prevented from being excessively reduced.

[0047] Fig. 9 is a block diagram showing a semiconductor system 3 according to an embodiment of the present disclosure. Fig. 9 As shown, the semiconductor system 3 may include a controller 31 and a semiconductor device 33 .

[0048] The controller 31 may include a first control pin 31_1 and a second control pin 31_3. The semiconductor device 33 may include a first device pin 33_1 and a second device pin 33_3. The controller 31 may send a command address CA to the semiconductor device 33 through a first transmission line 32_1 connected between the first control pin 31_1 and the first device pin 33_1. Each of the first control pin 31_1, the first transmission line 32_1, and the first device pin 33_1 may be implemented in plural according to the number of bits of the command address CA. The controller 31 may apply a power supply voltage VDD to the semiconductor device 33 through a second transmission line 32_3 connected between the second control pin 31_3 and the second device pin 33_3.

[0049] The semiconductor device 33 can drive the operation power VPPC for driving the word line WL by receiving the command address CA and the power supply voltage VDD from the controller 31. The semiconductor device 33 can set the operation power VPPC to the high voltage VPP by generating a power control signal VEN that is activated during a power-on period when the power supply voltage VDD rises from 0V to a target voltage level or during a time interval when a test mode operation is performed. Therefore, the power-on period can be considered to be substantially equal to the time between when VDD reaches the target voltage level and when the test mode operation ends or is completed.

[0050] Refer to above Figure 1 The semiconductor device 10 described can be applied to electronic systems including storage systems, graphics systems, computing systems, and mobile systems. Fig.10 , an electronic system 1000 according to an embodiment of the present disclosure may include a data storage unit 1001 , a memory controller 1002 , a buffer memory 1003 , and an input and output (I / O) interface 1004 .

[0051] The data storage unit 1001 can store data (not shown) applied by the memory controller 1002, read the stored data (not shown), and output the read data to the memory controller 1002 in response to a control signal from the memory controller 1002. The data storage unit 1001 may include a non-volatile memory that can continuously store data without losing the data even when power is off. The non-volatile memory may be implemented as a flash memory (e.g., a NOR flash memory or a NAND flash memory), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), or a magnetic random access memory (MRAM).

[0052] The memory controller 1002 may decode a command applied by an external device (or a host device) through the I / O interface 1004, and may control input and output of data to and from the data storage unit 1001 and the buffer memory 1003 in response to the decoding result. Fig.10 , the memory controller 1002 is represented as one block, but the memory controller 1002 may include a controller for controlling the data storage unit 1001 and a controller for controlling the buffer memory 1003 which is a volatile memory, which are independently constructed.

[0053] The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002, that is, data (not shown) input to and output from the data storage unit 1001. The buffer memory 1003 may store data (not shown) applied by the memory controller 1002 in response to a control signal from the memory controller 1002. The buffer memory 1003 may include a reference Figure 1 The semiconductor device 10 described above. The buffer memory 1003 may read data already stored in the buffer memory 1003 and may output the read data to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a dynamic random access memory (DRAM), a mobile DRAM, and a static random access memory (SRAM).

[0054] The I / O interface 1004 may provide a physical connection between the memory controller 1002 and an external device (or host), so that the memory controller 1002 may receive control signals for inputting data to and outputting data from the external device, and may exchange data with the external device. The I / O interface 1004 may include one of a variety of interface protocols, such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE.

[0055] The electronic system 1000 may be used as an auxiliary storage device of a host device or an external storage device. The electronic system 1000 may include a solid state disk (SSD), a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro SD card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

[0056] Fig.11 2 is a block diagram showing the configuration of an embodiment of an electronic system 2000 according to another embodiment of the present disclosure. Fig.11 As shown, the electronic system 2000 may include a host 2100 and a semiconductor system 2200 .

[0057] The host 2100 and the semiconductor system 2200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 2100 and the semiconductor system 2200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB).

[0058] The semiconductor system 2200 may include a controller 2300 and semiconductor devices 2400 (1:K). The semiconductor devices 2400 (1:K) may each include a reference Figure 1 The semiconductor device 10. The semiconductor device 1400 (1:K) may each be implemented as one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0059] Embodiments of the present disclosure have been described so far. Those skilled in the art will appreciate that the present invention may be implemented in a modified form without departing from the essential features of the present disclosure. Therefore, the disclosed embodiments should be considered from a descriptive perspective rather than a restrictive perspective. The scope of the present disclosure is described in the claims rather than in the foregoing description, and all differences within their equivalent ranges should be interpreted as being included in the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A semiconductor device comprising: a power control signal generating circuit that generates a power control signal that is activated in at least one of the following situations: a power-on period starts and a test mode operation is performed; as well as An operating power generating circuit sets the operating power supplied to the word line driver to a high voltage in response to the power control signal.

2. The semiconductor device according to claim 1, wherein The power control signal generating circuit generates the power control signal by receiving a power-on signal during a power-on period.

3. The semiconductor device according to claim 1, wherein The power control signal generating circuit generates the power control signal by receiving a test mode signal when the test mode operation is performed.

4. The semiconductor device according to claim 1, wherein The power control signal generating circuit comprises: a latch signal generating circuit that generates a latch signal in response to a power-on signal and a feedback voltage; a first voltage setting circuit generating a first voltage in response to the latch signal and a test mode signal; a second voltage setting circuit that generates a second voltage in response to a memory matrix selection signal and generates the feedback voltage in response to the second voltage; and A control signal output circuit generates the power control signal in response to the first voltage and the second voltage.

5. The semiconductor device according to claim 4, wherein: The latch signal generating circuit generates the latch signal having a first logic level in response to the power-on signal during the power-on period.

6. The semiconductor device according to claim 5, wherein: When the latch signal has the first logic level, the first voltage setting circuit generates the first voltage having the first logic level.

7. The semiconductor device according to claim 5, wherein: When the latch signal has the first logic level, the control signal output circuit generates the activated power control signal in response to the first voltage.

8. The semiconductor device according to claim 4, wherein: The first voltage setting circuit generates the first voltage having a first logic level in response to the test mode signal in the test mode operation.

9. The semiconductor device according to claim 8, wherein: When the first voltage has the first logic level, the control signal output circuit generates the power control signal that is activated.

10. The semiconductor device according to claim 1, wherein The operating power generation circuit includes a switching element connected between an output voltage node and the high voltage, the switching element being turned on and off in response to the power control signal.

11. The semiconductor device according to claim 10, wherein The operation power generation circuit further includes at least one diode element connected in parallel with the switch element between an output voltage node and the high voltage.

12. The semiconductor device according to claim 1, wherein When the power control signal is deactivated, the operating power generation circuit maintains a voltage level of the operating power so that the voltage level of the operating power does not drop below a predetermined voltage level.

13. A semiconductor device comprising: a latch signal generating circuit that generates a latch signal in response to a power-on signal and a feedback voltage; a first voltage setting circuit generating a first voltage in response to the latch signal and a test mode signal; a second voltage setting circuit, which: generates a second voltage in response to a storage matrix selection signal, and generates the feedback voltage in response to the second voltage; as well as Control signal output circuit, It generates a power control signal for setting a voltage level of operating power in response to the first voltage and the second voltage, the operating power being supplied to a word line driver.

14. The semiconductor device according to claim 13, wherein: The latch signal generating circuit generates the latch signal having a first logic level, the latch signal being generated in response to the power-on signal during the power-on period.

15. The semiconductor device according to claim 14, wherein: The first voltage setting circuit generates the first voltage having the first logic level when the latch signal is set to the first logic level.

16. The semiconductor device according to claim 14, wherein: When the latch signal is at the first logic level, the control signal output circuit generates the power control signal in response to the first voltage.

17. The semiconductor device according to claim 13, wherein: The first voltage setting circuit generates the first voltage having the first logic level in response to the test mode signal in a test mode operation.

18. The semiconductor device according to claim 17, wherein: When the first voltage is set to the first logic level, the control signal output circuit generates the power control signal that is activated. 19 . The semiconductor device according to claim 13 , further comprising an operating power generating circuit that sets the operating power to a high voltage in response to the power control signal.

20. The semiconductor device according to claim 19, wherein The operating power generation circuit comprises: a switching element connected between an output voltage node and the high voltage and turned on and off in response to the power control signal; and At least one diode element is connected in parallel with the switch element between the output voltage node and the high voltage.

Images