Detection method and detection device for crystal orientation of substrate
By forming spaced active regions and corresponding gate structures on the substrate, forming multiple transistors, and obtaining the crystal direction of the substrate according to their electrical performance differences, the problem of time-consuming and laborious and costly acquisition of the crystal direction of the substrate in the prior art is solved, and rapid and accurate detection and improvement of production efficiency are achieved.
Patent Information
- Application Number
- CN202510019244.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-06
- Publication Date
- 2025-04-15
AI Technical Summary
The method of obtaining the crystal direction of the substrate in the prior art mainly relies on physically destructive methods, resulting in high production costs and low efficiency, and it is difficult to quickly and accurately obtain the crystal direction of the substrate.
A plurality of transistors are formed by forming a plurality of active regions spaced apart in the second direction on the substrate, and forming a plurality of gate structures corresponding to these active regions on the top surface of the substrate. The angle between the conductive layer extension direction of these gate structures and the second direction is different, so that the crystal direction of the substrate is obtained according to the difference in electrical properties of the transistor.
The rapid and accurate detection of the crystal direction of the substrate is achieved, which avoids physical damage to the substrate, reduces the production cost of the semiconductor structure, and improves the production efficiency.
Smart Images
Figure CN119833426A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method and a device for detecting the crystal orientation of a substrate. Background Art
[0002] Crystal orientation refers to the direction pointed by the line between any two atoms / molecules / ions in a unit cell. The crystal orientation of the substrate in a semiconductor structure has a great influence on the performance of the semiconductor structure. For example, the crystal orientation of the substrate affects the conduction performance of the transistor in the semiconductor structure. Therefore, it is necessary to obtain the crystal orientation of the substrate in the manufacturing process of the semiconductor structure. At present, the method for obtaining the crystal orientation of the substrate is mainly to obtain the crystal orientation of the substrate by a physical destructive method. However, the physical destruction method requires the introduction of a mask and a physical destruction step, which is not only time-consuming and labor-intensive, but also requires damage to the substrate, resulting in an increase in the production cost of the semiconductor structure and a decrease in production efficiency.
[0003] Therefore, how to quickly and accurately obtain the crystal orientation of a substrate while avoiding damage to the substrate, thereby reducing the production cost of semiconductor structures and improving the production efficiency of semiconductor structures, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a method and a device for detecting the crystal orientation of a substrate, which are used to quickly and accurately obtain the crystal orientation of a substrate while avoiding damage to the substrate, thereby reducing the production cost of a semiconductor structure and improving the production efficiency of the semiconductor structure.
[0005] According to some embodiments, the present invention provides a method for detecting the crystal orientation of a substrate, comprising the following steps:
[0006] Providing a substrate to be tested, wherein the substrate to be tested includes a top surface and a bottom surface that are relatively distributed along a first direction;
[0007] A plurality of active regions are formed in the substrate to be tested and arranged at intervals along a second direction, wherein the active regions include a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, and the second direction is parallel to the top surface of the substrate to be tested;
[0008] Forming a plurality of gate structures corresponding to the plurality of channel regions in the plurality of active regions on the top surface of the substrate to be tested, so as to form a plurality of transistors, each of the transistors comprising the gate structures and the active regions corresponding to each other, the gate structures comprising a gate conductive layer, and the angles between the extension directions of the gate conductive layers in the plurality of gate structures and the second direction are different;
[0009] The crystal orientation of the substrate to be tested is obtained according to the difference in electrical properties of the plurality of transistors.
[0010] In some embodiments, the specific steps of forming a plurality of gate structures corresponding to the plurality of channel regions in the plurality of active regions on the top surface of the substrate to be tested to form a plurality of transistors include:
[0011] forming a gate dielectric layer located on the top surface of the substrate to be tested and covering the channel regions in the plurality of active regions;
[0012] A gate conductive material is deposited on the top surface of the substrate to be tested to form a plurality of gate conductive layers covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions. The gate dielectric layer and the gate conductive layer on the surface thereof together constitute the gate structure.
[0013] In some embodiments, the width of the gate conductive layer is greater than or equal to the width of the channel region in the active region corresponding thereto.
[0014] In some embodiments, the gate conductive material is polysilicon or a conductive metal material.
[0015] In some embodiments, the specific steps of depositing a gate conductive material on the top surface of the substrate to be tested to form a plurality of gate conductive layers covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions include:
[0016] Depositing the gate conductive material on the top surface of the substrate to be tested to form a conductive material layer;
[0017] Patterning the conductive material layer to form a plurality of gate conductive layers covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions, the plurality of gate conductive layers being arranged at intervals along the second direction, and along the second direction, the size of the angle between the extension direction of the plurality of gate conductive layers and the second direction gradually changes along the second direction.
[0018] In some embodiments, along the second direction, sizes of angles between extension directions of the plurality of gate conductive layers and the second direction increase at equal intervals along the second direction.
[0019] In some embodiments, three active regions spaced apart along the second direction are formed in the substrate to be tested, and three gate structures corresponding to the three active regions are formed on the top surface of the substrate to be tested;
[0020] Along the second direction, angles between the extension directions of the gate conductive layers in the three gate structures arranged sequentially and the second direction are 45°, 60° and 90° respectively.
[0021] In some embodiments, the specific steps of obtaining the crystal orientation of the substrate to be tested according to the difference in electrical properties of the plurality of transistors include:
[0022] respectively obtaining the switching ratios of the plurality of transistors;
[0023] Determine whether the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer and the second direction, and if so, determine that the crystal orientation of the substrate to be tested is <110> .
[0024] In some embodiments, the specific steps of obtaining the crystal orientation of the substrate to be tested according to the difference in electrical properties of the plurality of transistors include:
[0025] respectively obtaining the switching ratios of the plurality of transistors;
[0026] Determine whether the switching ratio of the transistor decreases with the increase of the angle between the extension direction of the gate conductive layer and the second direction, and if so, determine that the crystal orientation of the substrate to be tested is <100> .
[0027] According to some other embodiments, the present invention further provides a device for detecting the crystal orientation of a substrate, comprising:
[0028] A carrying structure for carrying a substrate to be tested, the substrate to be tested comprising a top surface and a bottom surface relatively distributed along a first direction, a plurality of active regions spaced apart along a second direction formed in the substrate to be tested, the active region comprising a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, a plurality of gate structures corresponding to a plurality of the channel regions in the plurality of active regions are formed on the top surface of the substrate to be tested, so as to form a plurality of transistors, each of the transistors comprising the gate structures and the active regions corresponding to each other, the gate structure comprising a gate conductive layer, and the angles between the extension directions of the gate conductive layers in the plurality of the gate structures and the second direction are different, and the second direction is parallel to the top surface of the substrate to be tested;
[0029] The detection structure comprises a processor, wherein the processor is used to obtain the electrical properties of the plurality of transistors and obtain the crystal orientation of the substrate to be tested according to the difference in the electrical properties of the plurality of transistors.
[0030] In some embodiments, the detection structure further comprises:
[0031] A current detector, connected to the processor, for obtaining an on-current and an off-current of the transistor;
[0032] The processor obtains the switching ratio of the transistor according to the on-current and the off-current, and determines whether the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer and the second direction. If so, it is determined that the crystal orientation of the substrate to be tested is <110> .
[0033] The present invention provides a method and device for detecting the crystal orientation of a substrate. A plurality of active regions arranged along a second direction are formed in the substrate, wherein the active regions include a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, and a plurality of gate structures corresponding to the plurality of active regions are formed above the substrate, thereby forming a plurality of transistors. The gate structure includes a gate conductive layer, and the angles between the extension direction of the gate conductive layer and the second direction in the plurality of gate structures are different. Since the angles between the extension direction of the gate conductive layer and the second direction are different, the flow directions of carriers in the transistors are different. Therefore, the crystal orientation of the substrate to be tested can be quickly and accurately obtained according to the difference in electrical properties of the plurality of transistors. The detection method is simple, and there is no need to perform physical destructive detection on the substrate to be tested, thereby avoiding damage to the substrate, thereby reducing the production cost of the semiconductor structure and improving the production efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a flow chart of a method for detecting the crystal orientation of a substrate in a specific embodiment of the present invention;
[0035] Figure 2 is a schematic top view of a substrate to be tested in a specific embodiment of the present invention;
[0036] Figure 3 It is a schematic top view of a specific embodiment of the present invention after a plurality of gate structures are formed on a substrate to be tested. DETAILED DESCRIPTION
[0037] The specific implementation of the method and device for detecting the crystal orientation of a substrate provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0038] This specific embodiment provides a method for detecting the crystal orientation of a substrate. Figure 1 FIG. 1 is a flow chart of a method for detecting the crystal orientation of a substrate in a specific embodiment of the present invention. Figure 1 As shown, the method for detecting the crystal orientation of the substrate comprises the following steps:
[0039] Step S11, providing a substrate to be tested, wherein the substrate to be tested includes a top surface and a bottom surface that are relatively distributed along a first direction;
[0040] Step S12, forming a plurality of active regions spaced apart along a second direction in the substrate to be tested, wherein the active regions include a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, and the second direction is parallel to the top surface of the substrate to be tested;
[0041] Step S13, forming a plurality of gate structures corresponding to the plurality of channel regions in the plurality of active regions on the top surface of the substrate to be tested, so as to form a plurality of transistors, each of the transistors comprising the gate structures and the active regions corresponding to each other, the gate structures comprising a gate conductive layer, and the angles between the extension directions of the gate conductive layers in the plurality of gate structures and the second direction are different;
[0042] Step S14, obtaining the crystal orientation of the substrate to be tested according to the difference in electrical properties of the plurality of transistors.
[0043] Figure 2 is a schematic top view of a substrate to be tested in a specific embodiment of the present invention, Figure 3 2 is a top view schematic diagram of a specific embodiment of the present invention after forming multiple gate structures on the substrate to be tested. In some embodiments, the specific steps of forming multiple gate structures corresponding to the multiple channel regions in the multiple active regions AA on the top surface 201 of the substrate to be tested to form multiple transistors include:
[0044] forming a gate dielectric layer located on the top surface 201 of the substrate 20 to be tested and covering the channel regions in the plurality of active regions AA;
[0045] A gate conductive material is deposited on the top surface 201 of the substrate 20 to be tested, to form a plurality of gate conductive layers 30 covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions AA, wherein the gate dielectric layer and the gate conductive layers 30 located on the surface thereof together constitute the gate structure, such as Figure 2 and Figure 3 shown.
[0046] Specifically, the substrate to be tested 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate to be tested 20 as a single crystal silicon substrate as an example. For example, doping ions are implanted into the substrate to be tested 20 by an ion implantation process to form a plurality of active areas AA arranged at intervals along the second direction D2 in the substrate to be tested 20. In one example, adjacent active areas AA are electrically isolated by a shallow trench isolation structure. Among them, the sizes and structures (including the types of doping ions, doping concentrations, etc.) of the plurality of active areas AA are the same, thereby avoiding differences in electrical performance between different transistors due to differences in the structures of the active areas AA. Afterwards, the gate dielectric layer covering at least the channel area in the active area AA is formed on the top surface 201 of the substrate to be tested 20 by a deposition process or a thermal oxidation process. Next, a gate conductive material is deposited on the top surface 201 of the substrate 20 to be tested, and a plurality of gate conductive layers 30 covering the gate dielectric layer and corresponding to the channel regions in the plurality of active regions AA are simultaneously formed. The gate dielectric layer and the gate conductive layers 30 located on the surface thereof together constitute the gate structure. Figure 2 and Figure 3 As shown. In this specific embodiment, only ion implantation and deposition processes need to be performed on a part of the substrate 20 to be tested (e.g., the edge region), without physically destroying the substrate 20 to be tested, thereby achieving non-destructive testing of the crystal orientation of the substrate 20 to be tested. The multiple mentioned in this specific embodiment refers to more than two.
[0047] In one example, after forming the gate structure, a plurality of conductive connection pillars 31 electrically connected to the source region and the drain region respectively can be formed on the top surface of the substrate to be tested 20 to facilitate the subsequent application of a test electrical signal to the transistor and detection of the electrical performance of the transistor.
[0048] In some embodiments, the width of the gate conductive layer 30 is greater than or equal to the width of the channel region in the active area AA corresponding thereto.
[0049] For example, a plurality of active areas AA are arranged at intervals along the second direction D2, each of the active areas AA includes the channel area and the source area and the drain area distributed on opposite sides of the channel area along the second direction D2, and a plurality of the gate conductive layers 30 are also arranged at intervals along the second direction D2 accordingly. The length of the channel area refers to the length of the channel area along the second direction D2, and the width of the channel area refers to the width of the channel area along a third direction (not shown in the figure), wherein the third direction is parallel to the top surface of the substrate 20 to be tested, and the second direction D2 intersects with the third direction (for example, vertically intersects or obliquely intersects). Since the angles between the extension directions of the plurality of gate conductive layers 30 and the second direction D2 are different, the width of the gate conductive layer 30 refers to the length of the gate conductive layer 30 along its extension direction. This specific embodiment makes the width of each gate conductive layer 30 greater than or equal to the width of the channel region in the corresponding active area AA, thereby avoiding the difference in electrical performance between different transistors due to the difference in the width of the gate conductive layer 30, so as to further improve the accuracy and reliability of the detection of the crystal orientation of the substrate 20 to be tested.
[0050] In some embodiments, the gate conductive material is polysilicon. In other embodiments, the gate conductive material may also be a conductive metal material.
[0051] In some embodiments, the specific steps of depositing the gate conductive material on the top surface 201 of the substrate 20 to be tested to form a plurality of gate conductive layers 30 covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions AA include:
[0052] Depositing the gate conductive material on the top surface 201 of the substrate 20 to be tested to form a conductive material layer;
[0053] The conductive material layer is patterned to form a plurality of gate conductive layers 30 covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions AA, wherein the plurality of gate conductive layers 30 are arranged at intervals along the second direction D2, and the angles between the extension directions of the plurality of gate conductive layers 30 and the second direction D2 gradually change along the second direction D2.
[0054] In this specific embodiment, the angle between the extension direction of the gate conductive layer 30 and the second direction D2 refers to the angle between the extension direction of the projection of the gate conductive layer 30 on the top surface 201 of the substrate to be tested 20 and the length direction of the channel region in the active area AA corresponding thereto (i.e., the second direction D2). In this specific embodiment, the angle between the extension direction of the plurality of gate conductive layers 30 and the second direction D2 is gradually changed along the second direction D2, thereby facilitating the acquisition of the law of the change of the electrical performance of the transistor with the change of the angle between the extension direction of the gate conductive layer 30 and the second direction D2, so as to more accurately determine the crystal orientation of the substrate to be tested 20. In one example, the angle between the extension direction of the plurality of gate conductive layers 30 and the second direction D2 gradually increases along the second direction D2.
[0055] In some embodiments, along the second direction D2, the angles between the extension directions of the plurality of gate conductive layers 30 and the second direction D2 increase at equal intervals along the second direction D2, so as to obtain the law of how the electrical properties of the transistor change with the change of the angle between the extension direction of the gate conductive layer 30 and the second direction D2, so as to more accurately determine the crystal orientation of the substrate 20 to be tested.
[0056] In other embodiments, along the second direction D2, the angles between the extension directions of the plurality of gate conductive layers 30 and the second direction D2 increase at non-equal intervals along the second direction D2, so as to flexibly adjust the angles between the extension directions of the gate conductive layers 30 and the second direction D2 according to actual detection requirements, so as to meet the specific crystal orientation detection requirements of the substrate 20 to be tested.
[0057] In some embodiments, three active areas AA arranged at intervals along the second direction D2 are formed in the substrate to be tested 20, and three gate structures corresponding to the three active areas AA are formed on the top surface 201 of the substrate to be tested 20;
[0058] Along the second direction D2 , angles between the extension directions of the gate conductive layers 30 in the three gate structures arranged sequentially and the second direction D2 are 45°, 60° and 90° respectively.
[0059] For example, three active areas AA are formed in the substrate 20 to be tested and arranged in the second direction D2, and a gate structure is formed above each active area AA, thereby forming three transistors. The angles between the extension direction of the gate conductive layer 30 in the three transistors and the second direction D2 are 45°, 60° and 90° respectively. Figure 3 The above structure can not only reduce the area of the substrate 20 to be tested, but also quickly obtain the crystal orientation of the substrate 20 to be tested with a smaller number of transistors, thereby improving the detection efficiency of the substrate 20 to be tested.
[0060] In some embodiments, the specific steps of obtaining the crystal orientation of the substrate to be tested according to the difference in electrical properties of the plurality of transistors include:
[0061] respectively obtaining the switching ratios of the plurality of transistors;
[0062] Determine whether the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer 30 and the second direction D2. If so, determine that the crystal orientation of the substrate 20 to be tested is <110> .
[0063] In some embodiments, the specific steps of obtaining the crystal orientation of the substrate 20 to be tested according to the difference in electrical properties of the plurality of transistors include:
[0064] respectively obtaining the switching ratios of the plurality of transistors;
[0065] Determine whether the switching ratio of the transistor decreases with the increase of the angle between the extension direction of the gate conductive layer 30 and the second direction D2. If so, determine that the crystal orientation of the substrate 20 to be tested is <100> .
[0066] For example, due to the different angles between the extension direction of the gate conductive layer 30 and the second direction D2, that is, the different angles between the extension direction of the gate conductive layer 30 and the length direction of the channel region in the active area, the flow direction of the carriers in the channel region will be different. For example, the shortest path of the carriers from the drain region to the source region in the transistor is perpendicular to the extension direction of the gate conductive layer 30. Therefore, when the angle between the extension direction of the gate conductive layer 30 and the second direction D2 is different, the flow direction of the carriers in the channel region will change accordingly. In the detection process, by applying test electrical signals to the plurality of transistors respectively, and detecting the on-current and off-current of each transistor, and obtaining the switching ratio of the transistor by analyzing the on-current and the off-current of each transistor. When the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer 30 and the second direction D2, it is determined that the crystal orientation of the substrate 20 to be tested is <110> When the switching ratio of the transistor decreases with the increase of the angle between the extension direction of the gate conductive layer 30 and the second direction D2, it is determined that the crystal orientation of the substrate 20 to be tested is <100> .
[0067] This specific embodiment also provides a device for detecting the crystal orientation of a substrate. The device for detecting the crystal orientation of a substrate can be used as follows: Figure 1-Figure 3 The method for detecting the crystal orientation of a substrate shown in FIG. 1 detects the crystal orientation of a substrate to be tested. Figure 1-Figure 3 As shown, the device for detecting the crystal orientation of the substrate comprises:
[0068] A carrying structure for carrying a substrate 20 to be tested, wherein the substrate 20 to be tested comprises a top surface 201 and a bottom surface relatively distributed along a first direction D1, wherein a plurality of active areas AA arranged at intervals along a second direction D2 are formed in the substrate 20 to be tested, wherein the active area AA comprises a channel area and a source area and a drain area distributed on opposite sides of the channel area along the second direction D2, wherein a plurality of gate structures corresponding to a plurality of the channel areas in the plurality of active areas AA are formed on the top surface 201 of the substrate 20 to be tested, so as to form a plurality of transistors, wherein each of the transistors comprises the gate structures and the active area AA corresponding to each other, wherein the gate structure comprises a gate conductive layer 30, and the angles between the extension directions of the gate conductive layers 30 in the plurality of the gate structures and the second direction D2 are different, and the second direction D2 is parallel to the top surface 201 of the substrate 20 to be tested;
[0069] The detection structure includes a processor, wherein the processor is used to obtain the electrical properties of the plurality of transistors, and obtain the crystal orientation of the substrate 20 to be tested according to the difference in the electrical properties of the plurality of transistors.
[0070] In some embodiments, the detection structure further comprises:
[0071] A current detector, connected to the processor, for obtaining an on-current and an off-current of the transistor;
[0072] The processor obtains the switching ratio of the transistor according to the on-current and the off-current, and determines whether the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer 30 and the second direction D2. If so, it is determined that the crystal orientation of the substrate to be tested is <110> .
[0073] The present specific embodiment provides a method and device for detecting the crystal orientation of a substrate. A plurality of active regions arranged along a second direction are formed in the substrate, wherein the active regions include a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, and a plurality of gate structures corresponding to the plurality of active regions are formed above the substrate, thereby forming a plurality of transistors. The gate structure includes a gate conductive layer, and the angles between the extension direction of the gate conductive layer and the second direction in the plurality of gate structures are different. Since the angles between the extension direction of the gate conductive layer and the second direction are different, the flow directions of carriers in the transistors are different. Therefore, the crystal orientation of the substrate to be tested can be quickly and accurately obtained according to the difference in electrical properties of the plurality of transistors. The detection method is simple, and there is no need to perform physical destructive detection on the substrate to be tested, thereby avoiding damage to the substrate, thereby reducing the production cost of the semiconductor structure and improving the production efficiency of the semiconductor structure.
[0074] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for detecting the crystal orientation of a substrate, characterized in that: The steps include: Providing a substrate to be tested, wherein the substrate to be tested includes a top surface and a bottom surface that are relatively distributed along a first direction; A plurality of active regions are formed in the substrate to be tested and arranged at intervals along a second direction, wherein the active regions include a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, and the second direction is parallel to the top surface of the substrate to be tested; Forming a plurality of gate structures corresponding to the plurality of channel regions in the plurality of active regions on the top surface of the substrate to be tested, so as to form a plurality of transistors, each of the transistors comprising the gate structures and the active regions corresponding to each other, the gate structures comprising a gate conductive layer, and the angles between the extension directions of the gate conductive layers in the plurality of gate structures and the second direction are different; The crystal orientation of the substrate to be tested is obtained according to the difference in electrical properties of the plurality of transistors.
2. The method for detecting the crystal orientation of a substrate according to claim 1, characterized in that: The specific steps of forming a plurality of gate structures corresponding to the plurality of channel regions in the plurality of active regions on the top surface of the substrate to be tested to form a plurality of transistors include: forming a gate dielectric layer located on the top surface of the substrate to be tested and covering the channel regions in the plurality of active regions; A gate conductive material is deposited on the top surface of the substrate to be tested to form a plurality of gate conductive layers covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions. The gate dielectric layer and the gate conductive layer on the surface thereof together constitute the gate structure.
3. The method for detecting the crystal orientation of a substrate according to claim 2, characterized in that: The width of the gate conductive layer is greater than or equal to the width of the channel region in the active region corresponding thereto.
4. The method for detecting the crystal orientation of a substrate according to claim 2, characterized in that: The gate conductive material is polysilicon or a conductive metal material.
5. The method for detecting the crystal orientation of a substrate according to claim 2, characterized in that: The specific steps of depositing a gate conductive material on the top surface of the substrate to be tested to form a plurality of gate conductive layers covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions include: depositing the gate conductive material on the top surface of the substrate to be tested to form a conductive material layer; Patterning the conductive material layer to form a plurality of gate conductive layers covering the gate dielectric layer and corresponding one-to-one to the channel regions in the plurality of active regions, the plurality of gate conductive layers being arranged at intervals along the second direction, and along the second direction, the size of the angle between the extension direction of the plurality of gate conductive layers and the second direction gradually changes along the second direction.
6. The method for detecting the crystal orientation of a substrate according to claim 5, characterized in that: Along the second direction, the angles between the extension directions of the plurality of gate conductive layers and the second direction increase at equal intervals along the second direction.
7. The method for detecting the crystal orientation of a substrate according to claim 1, characterized in that: Three active regions spaced apart along the second direction are formed in the substrate to be tested, and three gate structures corresponding to the three active regions are formed on the top surface of the substrate to be tested; Along the second direction, angles between the extension directions of the gate conductive layers in the three gate structures arranged sequentially and the second direction are 45°, 60° and 90° respectively.
8. The method for detecting the crystal orientation of a substrate according to claim 1, characterized in that: The specific steps of obtaining the crystal orientation of the substrate to be tested according to the difference in electrical properties of the plurality of transistors include: respectively obtaining the switching ratios of the plurality of transistors; Determine whether the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer and the second direction, and if so, determine that the crystal orientation of the substrate to be tested is <110> .
9. The method for detecting the crystal orientation of a substrate according to claim 1, characterized in that: The specific steps of obtaining the crystal orientation of the substrate to be tested according to the difference in electrical properties of the plurality of transistors include: respectively obtaining the switching ratios of the plurality of transistors; Determine whether the switching ratio of the transistor decreases with the increase of the angle between the extension direction of the gate conductive layer and the second direction, and if so, determine that the crystal orientation of the substrate to be tested is <100> .
10. A device for detecting the crystal orientation of a substrate, characterized in that: include: A carrying structure for carrying a substrate to be tested, the substrate to be tested comprising a top surface and a bottom surface relatively distributed along a first direction, a plurality of active regions spaced apart along a second direction formed in the substrate to be tested, the active region comprising a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, a plurality of gate structures corresponding to a plurality of the channel regions in the plurality of active regions are formed on the top surface of the substrate to be tested, so as to form a plurality of transistors, each of the transistors comprising the gate structures and the active regions corresponding to each other, the gate structure comprising a gate conductive layer, and the angles between the extension directions of the gate conductive layers in the plurality of the gate structures and the second direction are different, and the second direction is parallel to the top surface of the substrate to be tested; The detection structure comprises a processor, wherein the processor is used to obtain the electrical properties of the plurality of transistors and obtain the crystal orientation of the substrate to be tested according to the difference in the electrical properties of the plurality of transistors.
11. The device for detecting the crystal orientation of a substrate according to claim 10, characterized in that: The detection structure also includes: A current detector, connected to the processor, for obtaining an on-current and an off-current of the transistor; The processor obtains the switching ratio of the transistor according to the on-current and the off-current, and determines whether the switching ratio of the transistor increases with the increase of the angle between the extension direction of the gate conductive layer and the second direction. If so, it is determined that the crystal orientation of the substrate to be tested is <110> .