Manufacturing method of semiconductor device
By using a mask process and load-effect etching technology in the production of semiconductor devices, synchronously etching the trap-rich layer through holes and electrode contact through holes, the problems of complex process flow and high cost in the prior art are solved, and process simplification and cost reduction are achieved.
Patent Information
- Application Number
- CN202311326440.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-13
- Publication Date
- 2025-04-15
AI Technical Summary
In the existing manufacturing methods of semiconductor devices, the etching process of trap-rich layer through holes and electrode contact through holes is complicated, resulting in high production costs.
A photomask process is used to define the location of the through holes of the trap-rich layer and the electrode contact through holes. Through two load-effect etching and one high-selectivity etching, the through holes of the trap-rich layer and the electrode contact through holes are synchronously etched.
The process flow is simplified, the production cost is reduced, and the process efficiency and accuracy is improved.
Smart Images
Figure CN119833473A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a semiconductor device. Background Art
[0002] In radio frequency (RF) integrated circuit applications, such as RF switch devices or power amplifier devices, performance will be affected by "parasitic surface charge", which will in turn produce harmonic effects and affect device performance. Usually, a design of trap-rich layer vias is added to the peripheral sealing area of the chip. The trap-rich layer vias are made by etching the interlayer dielectric layer (ILD) and the buried oxide layer (BOX) to connect the trap-rich layer to form an electron leakage channel. In the prior art semiconductor device manufacturing, due to the large difference in etching depth between the trap-rich layer through hole and the electrode contact through hole, and the different etching stop layers of the trap-rich layer through hole and the electrode contact through hole, the industry generally uses two photomask processes for manufacturing, and the process flow is as follows: (1) after coating the first photoresist layer, the first photomask is used to photolithography to define the position of the trap-rich layer through hole; (2) plasma etching is used to form the trap-rich layer through hole; (3) the remaining first photoresist layer is removed by ashing process; (4) the polymer generated by etching the trap-rich layer through hole is removed; (5) after coating the second photoresist layer, the second photomask is used to photolithography to define the position of the electrode contact through hole; (6) plasma etching is used to form the electrode contact through hole; (7) the polymer generated by etching the electrode contact through hole is removed by wet etching process. In the prior art, two photomask processes are used to etch the trap-rich layer through hole and the electrode contact through hole in steps, and the process flow is complicated and the manufacturing cost is high.
[0003] Therefore, how to provide a method for manufacturing a semiconductor device to simplify the process flow and reduce the manufacturing cost has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a semiconductor device, which is used to solve the problem that the prior art uses two photomask processes to form trap-rich layer through holes and electrode lead-out through holes, which has a complex step-by-step etching process and high manufacturing cost.
[0005] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
[0006] A structure to be etched is provided, the structure to be etched comprising a trap-rich layer, a buried oxide layer, a semiconductor layer, an etching stop layer and an interlayer dielectric layer stacked from bottom to top, the semiconductor layer is divided into a plurality of cell regions, adjacent cell regions are isolated by an isolation region composed of an oxide layer, wherein a stacked amorphous carbon mask layer and a hard mask layer are provided on the structure to be etched, a first opening and a second opening are provided in the hard mask layer, in a horizontal direction, the first opening is located in the isolation region, the second opening is located in the cell region, and a characteristic size of the first opening is greater than a characteristic size of the second opening;
[0007] Using the hard mask layer as a mask, etching with a first etching gas, so that the first opening penetrates the amorphous carbon mask layer to expose the interlayer dielectric layer, and the second opening extends into the amorphous carbon mask layer but does not penetrate the amorphous carbon mask layer;
[0008] Using the amorphous carbon mask layer as a mask, etching with a second etching gas, so that the first opening penetrates the interlayer dielectric layer and the etching stop layer, and the second opening extends into the interlayer dielectric layer without penetrating the interlayer dielectric layer;
[0009] Using the amorphous carbon mask layer as a mask, etching with a third etching gas, so that the first opening exposes the trap-rich layer, and the second opening exposes the etching stop layer;
[0010] The exposed etch stop layer is etched using a fourth etching gas, so that the second opening exposes the semiconductor layer.
[0011] Optionally, the step of providing the first opening and the second opening in the hard mask layer includes:
[0012] forming a photoresist layer on the hard mask layer, and patterning the photoresist layer to define positions of the first opening and the second opening;
[0013] The hard mask layer is etched based on the patterned photoresist layer to form the first opening and the second opening.
[0014] Optionally, the first etching gas includes O2 and SO2.
[0015] Optionally, the first etching gas includes O2, Cl2 and HBr.
[0016] Optionally, the second etching gas includes CF4 and C x H y F z (x>0, y>0, z>0).
[0017] Optionally, the third etching gas includes C4F8, O2 and Ar.
[0018] Optionally, the fourth etching gas includes C x H y F z (x>0, y>0, z>0), O2 and Ar.
[0019] Optionally, after the etch stop layer is exposed by etching with the fourth etching gas, N2 and H2 are used to remove polymers generated during the etching process.
[0020] Optionally, before the etch stop layer is exposed by etching with the fourth etching gas, the amorphous carbon mask layer is removed by etching with O2.
[0021] Optionally, the thickness of the etch stop layer is in the range of The thickness of the interlayer dielectric layer is in the range of The thickness range of the amorphous carbon mask layer is The thickness of the hard mask layer is in the range of
[0023] As described above, in the method for manufacturing a semiconductor device of the present invention, after a mask process is used to define the positions of the trap-rich layer through holes and the electrode contact through holes, the trap-rich layer through holes and the electrode contact through holes are simultaneously etched through two load effect etchings and one high selectivity etching. Compared with the prior art of etching the trap-rich layer through holes and the electrode contact through holes in steps, the present application can reduce the four main processes of photolithography, plasma etching, photoresist ashing and polymer removal of the trap-rich layer through holes, thereby greatly simplifying the process flow and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a schematic flow chart of the method for manufacturing a semiconductor device of the present invention.
[0025] Figure 2 It is a schematic diagram showing that a structure to be etched is provided in the method for manufacturing a semiconductor device of the present invention, and an amorphous carbon mask layer and a hard mask layer are disposed above the structure to be etched.
[0026] Figure 3 It is a schematic diagram showing the process of manufacturing a semiconductor device of the present invention after etching using a first etching gas.
[0027] Figure 4 It is a schematic diagram showing the semiconductor device after etching using a second etching gas in the method for manufacturing the semiconductor device of the present invention.
[0028] Figure 5It is a schematic diagram showing the semiconductor device after etching using the third etching gas in the method for manufacturing the semiconductor device of the present invention.
[0029] Figure 6 It is a schematic diagram showing the semiconductor device after etching using the fourth etching gas in the method for manufacturing the semiconductor device of the present invention.
[0030] Component number description
[0031] 1 Structure to be etched
[0032] 100 Rich Trap Layer
[0033] 101 buried oxide layer
[0034] 102 Semiconductor layer
[0035] 1020 Cell Area
[0036] 1021 Isolation Area
[0037] 103 Etch stop layer
[0038] 104 interlayer dielectric layer
[0039] 105 Gate
[0040] 2 Amorphous carbon mask layer
[0041] 3 Hard mask layer
[0042] 4 First opening
[0043] 5 Second opening
[0044] Steps S1 to S5 DETAILED DESCRIPTION
[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0046] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0047] This embodiment provides a method for manufacturing a semiconductor device. Figure 1 , shown as a process flow chart of the method, comprising the following steps:
[0048] S1: providing a structure to be etched, the structure to be etched comprising a trap-rich layer, a buried oxide layer, a semiconductor layer, an etching stop layer and an interlayer dielectric layer stacked from bottom to top, the semiconductor layer being divided into a plurality of cell regions, adjacent cell regions being isolated by an isolation region formed by an oxide layer, wherein a stacked amorphous carbon mask layer and a hard mask layer are arranged on the structure to be etched, a first opening and a second opening are arranged in the hard mask layer, in a horizontal direction, the first opening is located in the isolation region, the second opening is located in the cell region, and a characteristic size of the first opening is greater than a characteristic size of the second opening;
[0049] S2: using the hard mask layer as a mask and etching with a first etching gas, so that the first opening penetrates the amorphous carbon mask layer to expose the interlayer dielectric layer, and the second opening extends into the amorphous carbon mask layer but does not penetrate the amorphous carbon mask layer;
[0050] S3: using the amorphous carbon mask layer as a mask and etching with a second etching gas, so that the first opening penetrates the interlayer dielectric layer and the etching stop layer, and the second opening extends into the interlayer dielectric layer without penetrating the interlayer dielectric layer;
[0051] S4: using the amorphous carbon mask layer as a mask and etching with a third etching gas, so that the first opening exposes the trap-rich layer and the second opening exposes the etching stop layer;
[0052] S5: using a fourth etching gas to etch the exposed etching stop layer, so that the second opening exposes the semiconductor layer.
[0053] First, see Figure 2 , perform step S1: provide a structure to be etched 1, the structure to be etched 1 includes a trap-rich layer 100, a buried oxide layer 101, a semiconductor layer 102, an etching stop layer 103 and an interlayer dielectric layer 104 stacked from bottom to top, the semiconductor layer 102 is divided into a plurality of cell regions 1020, adjacent cell regions 1020 are isolated by an isolation region 1021 composed of an oxide layer, wherein a stacked amorphous carbon mask layer 2 and a hard mask layer 3 are arranged on the structure to be etched 1, a first opening 4 and a second opening 5 are arranged in the hard mask layer 3, in the horizontal direction, the first opening 4 is located in the isolation region 1021, the second opening 5 is located in the cell region 1020, and the characteristic size of the first opening 4 is larger than the characteristic size of the second opening 5.
[0054] As an example, the buried oxide layer 101 and the semiconductor layer 102 constitute an SOI substrate, and the semiconductor layer 102 is a silicon layer; wherein the source region, drain region, etc. of the device are arranged in the silicon layer of the cell region 1020, and the gate 105 of the device is formed above the silicon layer of the cell region 1020.
[0055] As an example, the isolation region 1021 is a silicon oxide shallow trench isolation (STI), and the bottom of the isolation region 1021 is connected to the buried oxide layer 101 .
[0056] As an example, the etch stop layer 103 comprises SiN and has a thickness ranging from The interlayer dielectric layer 104 includes a silicon oxide layer, and the thickness range is The thickness range of the amorphous carbon mask layer 2 is The hard mask layer 3 includes a low temperature silicon oxide layer (LTO) having a thickness ranging from Specifically, in this embodiment, the thickness of the etching stop layer 103 is The thickness of the interlayer dielectric layer 104 is The thickness of the amorphous carbon mask layer 2 is The thickness of the hard mask layer 3 is
[0057] As an example, the step of providing the first opening 4 and the second opening 5 in the hard mask layer 3 includes:
[0058] (i) forming a bottom anti-reflection layer and a photoresist layer in sequence on the hard mask layer 3, and patterning the photoresist layer to define the positions of the first opening 4 and the second opening 5, wherein the first opening 4 is used to form a trap-rich layer through hole, the second opening 5 is used to form an electrode contact through hole, and the opening width of the first opening 4 is greater than the opening width of the second opening 5;
[0059] (ii) The photoresist layer based on the patterning adopts CF4, C x H y F z (x>0, y>0, z>0) and O2 to etch the bottom anti-reflection layer and the hard mask layer 3 to form the first opening 4 and the second opening 5, wherein CF4 and C x H y F z (x>0, y>0, z>0) is used as an etching reaction gas, and O2 is used as an etching auxiliary gas to better transfer the pattern of the photoresist layer to the hard mask layer 3.
[0060] Next, see Figure 3, perform step S2: use the hard mask layer 3 as a mask and use a first etching gas to etch, so that the first opening 4 penetrates the amorphous carbon mask layer 2 to expose the interlayer dielectric layer 104, and the second opening 5 extends into the amorphous carbon mask layer 2 without penetrating the amorphous carbon mask layer 2.
[0061] As an example, the first etching gas uses O2 and SO2, O2 is used as the etching reaction gas, and SO2 is used as the etching auxiliary gas to provide sidewall protection and increase the directionality of etching. By adjusting the pressure and increasing the SO2 flow rate, load effect etching is achieved, so that the depth of the first opening 4 is greater than the depth of the second opening 5, the first opening 4 contacts the upper surface of the interlayer dielectric layer 104, and the lower part of the second opening 5 is about The amorphous carbon mask layer 2 has a thickness of 1000 Å. In other examples, the first etching gas may also be O2, Cl2 and HBr, with O2 serving as an etching reaction gas and Cl2 and HBr serving as etching auxiliary gases.
[0062] As an example, when the first etching gas is used for etching, the etching parameters include: etching pressure of 30-150mT, high frequency etching power of 800-2000W, and low frequency etching power of 200-800W. Specifically, in the embodiment, the etching pressure is 30mT, the high frequency etching power is 1000W, and the low frequency etching power is 400W.
[0063] Next, see Figure 4 , perform step S3: use the amorphous carbon mask layer 2 as a mask and use a second etching gas to etch, so that the first opening 4 penetrates the interlayer dielectric layer 104 and the etching stop layer 103, and the second opening 5 extends into the interlayer dielectric layer 104 without penetrating the interlayer dielectric layer 104.
[0064] As an example, the second etching gas includes CF4 and C x H y F z (x>0, y>0, z>0), the etching parameters include: etching pressure of 80-180mT, high frequency etching power of 200-800W, and low frequency etching power of 100-900W. Specifically, in this embodiment, the second etching gas uses CF4 and CHF3, the etching pressure is 160mT, the high frequency etching power is 450W, and the low frequency etching power is 550W.
[0065] As an example, since the second opening 5 needs to be etched about The amorphous carbon mask layer 2 has a thickness of 104, and the interlayer dielectric layer 104 is directly etched during the etching of the first opening 4, so that the etching rate of the first opening 4 is greater than the etching rate of the second opening 5; and since the opening width of the first opening 4 is greater than the opening width of the second opening 5, the larger the opening width, the easier it is to discharge the etching products during the etching process, and further the etching rate of the first opening 4 is greater than the etching rate of the second opening 5, thereby realizing load effect etching.
[0066] As an example, since the etching process of the second etching gas is load effect etching, during the etching of the second opening 5 into the interlayer dielectric layer 104, the first opening 4 has sufficient etching depth to penetrate the interlayer dielectric layer 104 and the etching stop layer 103 and extend into the buried oxide layer 101, wherein the distance between the bottom end of the second opening 5 and the top end of the gate 105 is greater than
[0067] Next, see Figure 5 , executing step S4: using the amorphous carbon mask layer 2 as a mask, etching with a third etching gas, so that the first opening 4 reveals the trap-rich layer 100 , and the second opening 5 reveals the etching stop layer 103 .
[0068] As an example, the third etching gas includes C4F8, O2 and Ar, wherein C4F8 is used as an etching reaction gas, O2 and Ar are used as etching auxiliary gases, and the selective etching ratio is adjusted, and the etching selectivity ratio of silicon oxide and silicon nitride is greater than 6, so that the first opening 4 and the second opening 5 have an etching height difference. After etching by the third etching gas, the first opening 4 completely opens the STI and the buried oxide layer 101, and the second opening 5 does not open the etching stop layer 103. Specifically, in this embodiment, when the third etching gas is used for etching, the etching flow rates of C4F8, O2, and Ar are 30sccm, 17sccm, and 500sccm, respectively, the etching chamber pressure is 20mT, and the temperature is 25°C.
[0069] Next, see Figure 6 , executing step S5: using a fourth etching gas to etch the exposed etching stop layer 103 so that the second opening 5 exposes the semiconductor layer 102 .
[0070] As an example, before the etch stop layer 103 is exposed by etching with the fourth etching gas, the remaining amorphous carbon mask layer 2 is removed by etching with O2, wherein the etching flow rate of O2 is 600 sccm.
[0071] As an example, the fourth etching gas includes C x H yF z (x>0, y>0, z>0), O2 and Ar, among which C x H y F z (x>0, y>0, z>0) is used as the etching reaction gas, and O2 and Ar are used as etching auxiliary gases; specifically, in this embodiment, CH2F2, O2 and Ar gases are used to etch the etching stop layer 103, and the etching flow rates of CH2F2, O2 and Ar are 30sccm, 14sccm and 400sccm respectively.
[0072] As an example, after the etching of the etch stop layer 103 is completed by using the fourth etching gas, gases such as N2 and H2 are used to remove polymers generated by the above etching process.
[0073] As an example, since a gate 105 of a device is formed above the silicon layer of the cell region 103 , a portion of the second opening 5 exposes the semiconductor layer 102 , and a portion of the second opening 5 exposes the gate 105 .
[0074] As an example, the first opening 4 is used as a trap-rich layer through hole for a leakage channel of "parasitic surface charge", and the second opening 5 is used as an electrode contact through hole for a lead-out channel of the source, drain and gate of the device.
[0075] In summary, in the method for manufacturing a semiconductor device of the present invention, after defining the positions of the trap-rich layer through-holes and the electrode contact through-holes by a photomask process, the trap-rich layer through-holes and the electrode contact through-holes are simultaneously etched by two load effect etchings and one high selectivity etching. Compared with the prior art of etching the trap-rich layer through-holes and the electrode contact through-holes in steps, the present application can reduce the four main processes of the trap-rich layer through-holes, such as photolithography, plasma etching, photoresist ashing and polymer removal, greatly simplify the process flow and reduce the cost. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: A structure to be etched is provided, the structure to be etched comprising a trap-rich layer, a buried oxide layer, a semiconductor layer, an etching stop layer and an interlayer dielectric layer stacked from bottom to top, the semiconductor layer is divided into a plurality of cell regions, adjacent cell regions are isolated by an isolation region composed of an oxide layer, wherein a stacked amorphous carbon mask layer and a hard mask layer are provided on the structure to be etched, a first opening and a second opening are provided in the hard mask layer, in a horizontal direction, the first opening is located in the isolation region, the second opening is located in the cell region, and a characteristic size of the first opening is greater than a characteristic size of the second opening; Using the hard mask layer as a mask, etching with a first etching gas, so that the first opening penetrates the amorphous carbon mask layer to expose the interlayer dielectric layer, and the second opening extends into the amorphous carbon mask layer but does not penetrate the amorphous carbon mask layer; Using the amorphous carbon mask layer as a mask, etching with a second etching gas, so that the first opening penetrates the interlayer dielectric layer and the etching stop layer, and the second opening extends into the interlayer dielectric layer without penetrating the interlayer dielectric layer; Using the amorphous carbon mask layer as a mask, etching with a third etching gas, so that the first opening exposes the trap-rich layer, and the second opening exposes the etching stop layer; The exposed etch stop layer is etched using a fourth etching gas, so that the second opening exposes the semiconductor layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of providing the first opening and the second opening in the hard mask layer comprises: forming a photoresist layer on the hard mask layer, and patterning the photoresist layer to define positions of the first opening and the second opening; The hard mask layer is etched based on the patterned photoresist layer to form the first opening and the second opening.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first etching gas includes O2 and SO2.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The first etching gas includes O2, Cl2 and HBr.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The second etching gas includes CF4 and C x H y F z (x>0, y>0, z>0).
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The third etching gas includes C4F8, O2 and Ar.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The fourth etching gas includes C x H y F z (where x > 0, y > 0, z > 0), O2 and Ar.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: After the etch stop layer is exposed by etching with the fourth etching gas, N2 and H2 are used to remove polymers generated during the etching process.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: Before the etch stop layer is exposed by etching with the fourth etching gas, the amorphous carbon mask layer is removed by etching with O2.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness range of the etch stop layer is The thickness range of the interlayer dielectric layer is The thickness range of the amorphous carbon mask layer is The thickness of the hard mask layer is in the range of