Chip and preparation method thereof, and chip packaging structure

Abstract

The invention discloses a chip, a preparation method thereof and a chip packaging structure, and the preparation method comprises the steps: forming a first wafer comprising a plurality of chips, the first wafer further comprises a first surface and a second surface which are opposite, the plurality of chips are arranged and distributed in a direction parallel to the first surface, the first surface is used for bonding the plurality of chips, and the second surface is used for bonding the plurality of chips; and etching the first surface to form a groove which surrounds each chip, and cutting the first wafer through the bottom surface of the groove to cut the first wafer into a plurality of chips. According to the technical scheme, the flatness of the edge of the chip is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip and a preparation method thereof, and a chip packaging structure. Background Art

[0002] Chips have become an indispensable part in the field of semiconductor technology. However, in the process of cutting wafers to form chips, cutting defects are easily caused on the edges of the chips.

[0003] How to improve the flatness of chip edges has become an urgent problem to be solved in this field. Summary of the invention

[0004] The present application proposes a chip and a preparation method thereof, and a chip packaging structure to improve the flatness of the chip edge.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] On the one hand, a chip preparation method is provided, which includes forming a first wafer including a plurality of chips, the first wafer also including a first surface and a second surface relative to each other, the plurality of chips are arranged and distributed in a direction parallel to the first surface, the first surface is used for bonding the plurality of chips, the first surface is etched to form a groove, the groove surrounds each chip, and the first wafer is cut through the bottom surface of the groove to cut the first wafer into a plurality of chips.

[0007] In some embodiments, the process of forming a groove includes forming a photoresist layer on a first surface, exposing and developing the photoresist layer to obtain a mask layer, wherein the mask layer covers multiple chips and exposes four sides of each chip, and etches the first surface through the mask layer to form a groove on the first surface.

[0008] In some embodiments, a plasma etching process is used to etch the first surface.

[0009] In some embodiments, after forming the groove and before cutting the first wafer, the preparation method further includes forming a protective layer on the first surface, wherein the protective layer covers the surfaces of the multiple chips and the groove, and cutting the first wafer, including using a mechanical cutting process to cut the protective layer and the first wafer.

[0010] In some embodiments, after the first wafer is cut through the bottom surface of the groove, the height of the bottom surface of the groove relative to the second surface is smaller than the height of the first surface.

[0011] In some embodiments, in a direction parallel to the first surface, a plurality of chips are arranged in an array, and the groove is located between two adjacent chips. The orthographic projection of the cutting area of ​​the first wafer on the second surface is located within the range of the orthographic projection of the bottom surface of the groove on the second surface, and in the spacing direction of the two adjacent chips, the width of the cutting area of ​​the first wafer is smaller than the width of the groove, and the center line of the cutting area of ​​the first wafer coincides with the center line of the groove.

[0012] In some embodiments, in the spacing direction between two adjacent chips, outer boundaries of two opposite sides of the groove extend beyond outer boundaries of two opposite sides of the cutting region by at least 5 μm.

[0013] In some embodiments, the first surface of the cut chip is a polygon, and there is a rounded corner between two connected sides.

[0014] The chip preparation method provided in the embodiment of the present application first etches a groove around each chip on the first surface of the first wafer, and then cuts the first wafer through the bottom surface of the groove to cut the first wafer into multiple chips. Since the bottom surface of the groove and the first surface for bonding are not on the same plane, and the cutting area of ​​the first wafer is located on the bottom surface of the groove, the cutting area and the first surface are not on the same surface, and there is a certain distance between the two. Therefore, in the process of cutting the first wafer, even if the cutting causes defects on the bottom surface of the groove, it will not cause defects on the first surface for bonding, that is, the cutting will not affect the edge morphology of the bonding surface of the chip, thereby effectively improving the flatness of the edge of the chip after cutting.

[0015] On the other hand, the present application also provides a chip, which is prepared by any of the preparation methods described above.

[0016] The chip provided in the present application, due to the improvement of its preparation process, the morphology of the chip edge will not be deformed due to cutting, which effectively improves the flatness of the edge of the chip after cutting. In addition, since edge defects such as chipping, deformation and contamination are reduced, the performance and reliability of the chip are also effectively improved.

[0017] On the other hand, the present application also provides a chip packaging structure, which includes the above-mentioned chip and a second wafer, wherein the first surfaces of multiple chips are bonded to the second wafer.

[0018] The chip packaging structure provided in the present application has improved edge flatness of the chip and improved cleanliness of the first surface serving as the bonding surface, thereby effectively improving the bonding strength between the chip and the second wafer, thereby improving the packaging effect and reliability of the chip packaging structure.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] Figure 1 A schematic diagram of a chip edge fragmentation phenomenon in the related art;

[0022] Figure 2 A schematic diagram of chip defects caused by wafer cutting in the related art;

[0023] Figure 3 The effect diagram of defective chip and wafer bonding in the related art;

[0024] Figure 4 A flow chart of a method for preparing a chip provided in an embodiment of the present application;

[0025] Figure 5 to Figure 13 A diagram of each step of the preparation method provided in the embodiment of the present application;

[0026] Fig.14 A schematic diagram of a chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0029] In the description of the present application, “plurality” means two or more.

[0030] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0031] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0032] In the semiconductor manufacturing process, the bonding of die to wafer is one of the key steps. The hybrid bonding or fusion bonding process of chip to wafer involves chip cutting. The chip cutting process is often accompanied by particle contamination caused by the chip bonding interface and defects caused by the surface morphology of the chip cutting edge. These two problems are the two main factors affecting the bonding effect of chip and wafer.

[0033] At present, the commonly used chip cutting solutions are laser cutting, mechanical cutting, and plasma cutting. The advantages and disadvantages of these three cutting methods are as follows:

[0034] Laser cutting, also known as laser cutting, is a non-contact processing method that uses high-temperature and high-power lasers to achieve laser ablation cutting. Its advantages are that compared with traditional mechanical cutting such as diamond cutting and grinding wheel cutting, laser cutting will not cause problems such as chipping, tool wear, water pollution, and slag inclusions that cannot be ignored. Its disadvantages are that the high-power laser used in laser ablation cutting will produce a high thermal effect during the working process. The thermal effect will cause the cutting edge to produce residue recasting (Recast), resulting in abnormalities in the surface and sidewall morphology of the chip, thereby affecting subsequent processes. In addition, the heat generated by laser cutting will affect the structure of the cutting tape used to fix the wafer at the bottom of the wafer, causing the tape to be denatured. In addition, its efficiency in splitting chips is low. If only laser cutting is used to cut the entire wafer, the process time will be too long.

[0035] Mechanical dicing is a method of cutting the chips on the wafer using a blade, which is a contact separation process. Its advantages are higher efficiency, simple process, and low process cost. At the same time, the damage to the dicing tape is only mechanical damage, which will not cause changes in the internal chemical structure of the tape and has little impact. Its disadvantages are that mechanical dicing is a contact separation process, and the particle contamination phenomenon is more serious, the pollution generated is more, and the cleanliness of the chip bonding surface is greatly affected.

[0036] Plasma cutting is similar to plasma etching process, which uses high-temperature plasma to etch the chips apart, thereby achieving the purpose of cutting wafers. Its advantages are that it uses the front-end process of the factory (Fab), with high preparation accuracy, small particle pollution, and no thermal effect. Its disadvantages are that it is necessary to make related masks to cover the wafer surface that does not need to be cut, and its overall process time is long, the complexity is high, and the overall cost is the highest.

[0037] However, no matter which of the above three cutting methods is used, the edge of the chip will be cut off, deformed or dirty (residual debris), etc. Figure 1 Schematic diagram of the chip edge fragmentation phenomenon in the related art, such as Figure 1 As shown, the defects on the edge of the chip 11 ′ will greatly reduce the bonding strength between the chip 11 ′ and the wafer, or between the chips 11 ′ and the chips 11 ′, and these defects on the edge of the chip 11 ′ cannot be alleviated by cleaning the chip 11 ′.

[0038] Even when plasma cutting is used to cut wafers, the width of the cutting path is usually 50um to 100um, and the cutting depth is 50um to 775um. At this time, the depth and width of the plasma cutting are very large, and the part of the chip edge close to the surface will experience a certain degree of lateral etching, which will also cause defects on the edge of the chip after cutting (such as deformation, broken edges, etc.).

[0039] Figure 2 A schematic diagram of chip defects caused by wafer cutting in the related art; Figure 3 This is a diagram showing the effect of defective chip-wafer bonding in the related art.

[0040] In summary, if Figure 2 As shown, after the chip 11' is cut, the surface flatness will decrease, causing the bonding surface of the chip 11' to be deformed, such as being cut off or having debris remaining. Figure 3As shown, in the subsequent bonding process of chip 11' and wafer 2', due to defects in the bonding surface morphology of 11', the bonding surfaces of wafer 2' and chip 11' cannot be completely fitted together, and the four sharp corners of chip 11' make it difficult to ensure that the transmission rate of the bonding wave in all directions is the same after wafer 2' and chip 11' are bonded, and it is more likely to generate bonding bubbles at the bonding interface, thereby greatly reducing the bonding strength.

[0041] In order to solve the above problems, the present application proposes a method for preparing a chip. Figure 4 A flow chart of a chip preparation method provided in an embodiment of the present application, Figure 5 to Figure 13 The steps of the preparation method provided in the application example are shown in FIG. Figure 4 As shown, the preparation method includes the following steps S1 to S3:

[0042] Step S1: Figure 5 As shown, a first wafer 1 including a plurality of chips 11 is formed, the first wafer 1 further includes a first surface 101 and a second surface 102 relative to each other, the first surface 101 is located in a plane XY, the plurality of chips 11 are arranged and distributed in a direction parallel to the first surface 101, that is, the plurality of chips 1 are arranged and distributed in a direction parallel to the plane XY, the first surface 101 is used for bonding of the plurality of chips 11, that is, the first surface 101 serves as a bonding interface for subsequent bonding of the plurality of chips 11. The first wafer 1 further includes a cutting area 10, which is disposed between two chips 11 to separate different chips 11.

[0043] Step S2: Figure 6 to Figure 9 As shown, the first surface 101 of the first wafer 1 is etched to form a groove 12 . The groove 12 formed by etching is arranged around each chip 11 , that is, the groove 12 is arranged around each chip 11 .

[0044] In some embodiments, in the above step S2, the process of forming the groove 12 includes the following steps S201 to S203:

[0045] Step S201: Figure 6 As shown, a photoresist layer 13 is formed on the first surface 101 .

[0046] Step S202: Figure 7 As shown, the photoresist layer 13 is exposed and developed to obtain a mask layer 14. The mask layer 14 covers the multiple chips 11 and exposes the four sides of each chip 11, at least exposing the cutting area 10. The mask layer 14 is used to protect the bonding portion of the chip 11 so that it will not be mistakenly etched when the first wafer 1 is subsequently etched.

[0047] Step S203: Figure 8As shown, the first surface 101 is etched through the mask layer 14 to form a groove 12 on the first surface 101 .

[0048] In some embodiments, the process of forming the groove 12 on the first surface 101 adopts a plasma etching process, which has better uniformity and controllability. In addition, by utilizing the anisotropy of the plasma etching process to etch the first wafer 1, the morphology of the etched groove 12 can be made clearer and more accurate.

[0049] Exemplarily, after the groove 12 is formed on the first surface 101, as shown in FIG. Fig. 9 As shown, the mask layer 14 is removed by chemical dissolution or heating to expose the first surface 101 so as to facilitate the following process steps.

[0050] In some embodiments, after the groove 12 is formed, a partial top view of the first wafer 1 along the plane XY is as follows: Fig.10 As shown, in a direction parallel to the first surface 101, that is, in a direction parallel to the plane XY, a plurality of chips 11 are arranged in an array. The embodiment of the present application is described by taking a plurality of chips 11 as a row along the direction X and a column along the direction Y as an example. The groove 12 is located between two adjacent chips 11. Fig.10 The example in which the groove 12 is located between two chips 11 arranged along the direction X is used for description.

[0051] Continue to see Fig.10 , the orthographic projection of the cutting area 10 of the first wafer 1 on the second surface 102 is within the range of the orthographic projection of the bottom surface of the groove 12 on the second surface 102, that is, on the plane XY, the area of ​​the orthographic projection of the cutting area 10 is smaller than the area of ​​the orthographic projection of the bottom surface of the groove 12. Moreover, in the spacing direction between two adjacent chips 11, that is, the direction Y in the embodiment of the present application, the width of the cutting area 10 of the first wafer 1 is smaller than the width of the groove 12, and the center line 100 of the cutting area 10 of the first wafer 1 coincides with the center line 120 of the groove 12. This arrangement ensures that during the process of cutting the first wafer 1, the portion of the first surface 101 used for bonding is not affected by the cutting, thereby ensuring the integrity of the bonding surface of the chip 11.

[0052] In some embodiments, Fig.10 As shown, in the spacing direction between two adjacent chips 11, that is, direction Y, the outer boundaries 121 on the opposite sides of the groove 12 extend at least 5 μm beyond the outer boundaries 10a on the opposite sides of the cutting area 10. Under this distance condition, the cutting process can be better ensured to proceed smoothly, the edge damage that may be suffered by the chip 11 during the cutting of the first wafer 1 can be reduced, and the flatness of the bonding surface of the chip 11 can be improved.

[0053] In some embodiments, Fig.10 As shown, the first surface 101 of the chip 11 after cutting is a polygon. The embodiment of the present application takes the first surface 101 of the chip 11 as a quadrilateral as an example, and there is a rounded corner between two connected edges on the first surface 101 of the chip 11. The rounded corner morphology avoids the problem of bonding bubbles generated at the bonding interface during the bonding process caused by the sharp corner morphology of the chip in the related art, ensures the uniform transmission of the bonding wave during the bonding process of the chip 11, and better ensures the subsequent bonding strength of the chip 11 with other chips or wafers.

[0054] In some embodiments, after forming the groove 12, as Fig.11 As shown, the preparation method further includes forming a protective layer 15 on the first surface 101, wherein the protective layer 15 covers the surfaces of the plurality of chips 11 and the grooves 12, and protects the surfaces of the plurality of chips 11 and the grooves 12, thereby preventing defects such as the edges of the plurality of chips 11 being cut off, deformed, and soiled during the cutting process of the first wafer 1, and protecting the bonding interfaces of the plurality of chips 11 from being contaminated by particles generated by the cutting, thereby ensuring the flatness and cleanliness of the bonding interfaces.

[0055] Step S3: Fig.12 As shown, the first wafer 1 is cut through the protective layer 15 and the bottom surface of the groove 12 close to the second surface 102 to cut the first wafer 1 into a plurality of chips 11 .

[0056] In some embodiments, the process of cutting the first wafer 1 into a plurality of chips 11 includes cutting the protective layer 15 and the first wafer 1 using a mechanical cutting process. Due to the presence of the protective layer 15, the first surface 101 does not come into contact with the cutting tool. At the same time, due to the presence of the groove 12, the bottom surface of the groove 12 is not on the same plane as the first surface 101 used for bonding. There is a certain distance between the first surface 101 and the tool, and the propagation distance of particle contaminants such as debris is limited, so the particle contaminants will not adhere to the first surface 101 of the chip 11. Even if the bottom surface of the groove 12 has defective morphology such as edge cutting and deformation during the cutting process, it will not affect the subsequent bonding of the chip 11. The mechanical cutting process has high cutting efficiency, simple process, and low process cost, which greatly improves the process feasibility of the embodiment provided by the present application. In addition, no thermal effect will be generated during the cutting of the first wafer 1, and the internal chemical structure of the tape used to fix the first wafer 1 will not be changed, which has little effect on the chip 11 finally formed by cutting.

[0057] For example, the process of cutting the first wafer 1 into a plurality of chips 11 may also be performed by laser cutting or plasma cutting. After the first wafer 1 is cut into a plurality of chips 11, Fig.13As shown, the protective layer 15 is removed, and the polluted particles generated by cutting are also removed along with the protective layer 15 , thereby further ensuring the cleanliness of the first surface 101 .

[0058] The chip preparation method provided in the embodiment of the present application first etches a groove 12 surrounding each chip 11 on the first surface 101 of the first wafer 1, and then cuts the first wafer 1 through the bottom surface of the groove 12 to cut the first wafer 1 into a plurality of chips 11. Since the bottom surface of the groove 12 and the first surface 101 for bonding are not on the same plane, and the cutting area 10 of the first wafer 1 is located on the bottom surface of the groove 12, the cutting area 10 and the first surface 101 are not on the same surface, and there is a certain distance between the two. Therefore, in the process of cutting the first wafer 1, even if the cutting causes defects on the bottom surface of the groove 12, it will not cause defects on the first surface 101 for bonding, that is, the cutting will not affect the edge morphology of the chip 11, thereby effectively improving the flatness of the edge of the chip 11 after cutting.

[0059] In some embodiments, Fig.13 As shown, after the first wafer 1 is cut through the bottom surface of the groove 12, the height of the bottom surface of the groove 12 is smaller than the height of the first surface 101 relative to the second surface 102, that is, along the direction Z, the first surfaces 101 of the plurality of chips 11 are higher than the bottom surface of the groove 12. It can be understood that a certain depression is generated around each chip 11. The existence of the depression prevents the first surface 101 from contacting the cutting device during the subsequent cutting of the first wafer 1, thereby avoiding defects on the bonding surface of the chip 11 due to cutting.

[0060] On the other hand, Fig.13 As shown, the present application also provides a chip 11, which is prepared by the preparation method in any of the above embodiments. Due to the improvement of the preparation process of the chip 11 provided in the present application, the morphology of the edge of the chip 11 will not be deformed due to cutting, which effectively improves the flatness of the edge of the chip 11 after cutting, and due to the reduction of edge defects such as chipping, deformation and contamination, the performance and reliability of the chip 11 are also effectively improved.

[0061] On the other hand, the present application also provides a chip packaging structure. Fig.14 A schematic diagram of a chip packaging structure provided in an embodiment of the present application, such as Fig.14 As shown, the chip packaging structure A includes the above-mentioned chip 11 and the second wafer 2, wherein the first surfaces 101 of the plurality of chips 11 are bonded to the second wafer 2. It is understandable that the first surfaces 101 of the plurality of chips 11 are bonded to the second wafer 2 as follows: Fig.14As shown, multiple chips 11 are bonded to the second wafer 2 to complete structural and electrical connections, or the second wafer 2 includes multiple second chips, and multiple chips 11 are bonded to multiple second chips to complete structural and electrical connections. Exemplarily, multiple chips 11 can also be structurally connected to a bonding panel, wherein the bonding panel, as a carrier of the chip 11, can protect and carry the first surface 101 and the second surface 102 of the chip 11.

[0062] Since the edge flatness of the chip 11 is improved and the cleanliness of the first surface 101 serving as the bonding surface is also improved, the bonding strength between the chip 11 and the second wafer 2 is effectively improved, thereby improving the packaging effect and reliability of the chip packaging structure A.

[0063] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a chip, characterized in that: include: Forming a first wafer including a plurality of chips, the first wafer further including a first surface and a second surface opposite to each other, the plurality of chips being arranged and distributed in a direction parallel to the first surface; The first surface is used for bonding the plurality of chips; etching the first surface to form a groove, wherein the groove surrounds each chip; The first wafer is cut through the bottom surface of the groove to cut the first wafer into a plurality of chips.

2. The preparation method according to claim 1, characterized in that: Forming the groove comprises: forming a photoresist layer on the first surface; Exposing and developing the photoresist layer to obtain a mask layer, wherein the mask layer covers the plurality of chips and exposes the periphery of each chip; The first surface is etched through the mask layer to form the groove on the first surface.

3. The preparation method according to claim 2, characterized in that: The first surface is etched using a plasma etching process.

4. The preparation method according to claim 1, characterized in that: After forming the groove and before cutting the first wafer, the preparation method further includes: forming a protective layer on the first surface, the protective layer covering the surfaces of the plurality of chips and the groove; Cutting the first wafer includes: The protective layer and the first wafer are cut by a mechanical cutting process.

5. The preparation method according to claim 1, characterized in that: After the first wafer is cut through the bottom surface of the groove, the height of the bottom surface of the groove is smaller than the height of the first surface relative to the second surface.

6. The preparation method according to claim 1, characterized in that: In a direction parallel to the first surface, the plurality of chips are arranged in an array, and the groove is located between two adjacent chips; The orthographic projection of the cutting area of ​​the first wafer on the second surface is located within the range of the orthographic projection of the bottom surface of the groove on the second surface; In the spacing direction between two adjacent chips, the width of the cutting area of ​​the first wafer is smaller than the width of the groove, and the center line of the cutting area of ​​the first wafer coincides with the center line of the groove.

7. The preparation method according to claim 6, characterized in that: In the spacing direction between two adjacent chips, outer boundaries of the groove on two opposite sides extend beyond outer boundaries of the cutting region on two opposite sides by at least 5 μm.

8. The preparation method according to claim 1, characterized in that: The first surface of the chip after cutting is polygonal, and there is a rounded corner between two connected sides.

9. A chip, characterized in that: The method is prepared according to any one of claims 1 to 8.

10. A chip packaging structure, characterized in that: include: The chip as claimed in claim 9; A second wafer, the first surfaces of the plurality of chips are bonded to the second wafer.

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