Packaging structure and forming method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging structure and a forming method thereof. The package structure includes: a substrate; the chip is mounted on the surface of the substrate, and the chip comprises a front surface facing the substrate and a back surface deviating from the substrate; the heat dissipation structure covers the back face of the chip, the heat dissipation structure comprises a heat dissipation cover and a micro-nano metal interconnection layer at least located between the heat dissipation cover and the chip, one end of the micro-nano metal interconnection layer is connected with the heat dissipation cover, and the other end of the micro-nano metal interconnection layer is connected with the back face of the chip. The heat dissipation performance of the packaging structure is remarkably improved, the manufacturing process of the packaging structure is simplified, and the yield of the packaging structure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] As the integration of packaging structures continues to increase and the frequency continues to increase, the heat dissipation of packaging structures has become increasingly prominent. Heat accumulation inside the packaging structure will cause the temperature of electronic structures such as functional chips and functional devices in the packaging structure to be too high, thereby affecting the performance of electronic structures such as functional chips and functional devices, and easily leading to a shortened service life of the packaging structure. In a semiconductor packaging structure, a heat dissipation cover is covered on the surface of the chip away from the substrate, and the heat dissipation cover and the chip are bonded together by adhesive materials such as TIM (Thermal Interface Material, thermal interface material), so that the adhesive material becomes one of the main factors affecting the heat dissipation of the packaging structure. Improving the thermal conductivity of the adhesive material can significantly improve the heat dissipation efficiency of the packaging structure. The current main adhesive materials include organic silica gel, graphene, nano silver glue and indium sheet, but the thermal conductivity of organic silica gel, graphene, nano silver glue and indium sheet does not exceed 100W / (mK), thereby limiting the improvement of the heat dissipation performance of the packaging structure. Moreover, adhesive materials such as organic silica gel, graphene, nano silver glue and indium sheet need to be formed on the surface of the package body or the surface of the heat dissipation cover by dispensing or welding process, and the process is relatively complicated, thereby limiting the improvement of the yield of the packaging structure.

[0003] Therefore, how to improve the heat dissipation performance of the packaging structure and simplify the formation process of the packaging structure, so as to improve the performance and yield of the packaging structure, is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a packaging structure and a forming method thereof, which are used to improve the heat dissipation performance of the packaging structure and simplify the forming process of the packaging structure, thereby improving the performance and yield of the packaging structure.

[0005] According to some embodiments, the present invention provides a packaging structure, comprising:

[0006] substrate;

[0007] A chip is mounted on the surface of the substrate, wherein the chip comprises a front side facing the substrate and a back side facing away from the substrate;

[0008] A heat dissipation structure is covered on the back side of the chip, and the heat dissipation structure includes a heat dissipation cover and a micro-nano metal interconnection layer at least located between the heat dissipation cover and the chip, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover, and the other end is connected to the back side of the chip.

[0009] In some embodiments, it also includes:

[0010] A plastic sealing layer is located on the surface of the substrate and seals the chip, and the surface of the plastic sealing layer facing away from the substrate is flush with the back surface of the chip;

[0011] The heat dissipation structure continuously covers the back side of the chip and the surface of the plastic packaging layer facing away from the substrate.

[0012] In some embodiments, the micro-nano metal interconnection layer includes:

[0013] A first micro-nano metal layer connected to the back side of the chip;

[0014] The second micro-nano metal layer is connected to the surface of the heat dissipation cover facing the chip, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

[0015] In some embodiments, the heat dissipation structure further includes:

[0016] A first metal coating layer covers the back side of the chip, and the first micro-nano metal layer is located on a surface of the first metal coating layer facing away from the chip;

[0017] The second metal plating layer covers the surface of the heat dissipation cover facing the chip, and the second micro-nano metal layer is located on the surface of the second metal plating layer facing the chip.

[0018] In some embodiments, the first micro-nano metal layer includes a plurality of first micro-nano metal wires arranged in parallel on the surface of the first metal coating layer, and the second micro-nano metal layer includes a plurality of second micro-nano metal wires arranged in parallel on the surface of the second metal coating layer, and the first micro-nano metal wires and the second micro-nano metal wires are parallel to each other and in contact with each other.

[0019] In some embodiments, the four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the sidewall of one second micro-nano metal wire is in contact with and connected to the sidewalls of the four first micro-nano metal wires distributed around the periphery thereof;

[0020] The four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the sidewall of one first micro-nano metal wire is in contact with and connected to the sidewalls of the four second micro-nano metal wires distributed around its periphery.

[0021] In some embodiments, the first metal coating layer and the second metal coating layer are both copper coating layers, and the first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers.

[0022] In some embodiments, the first micro-nano metal wire and the second micro-nano metal wire are both cylindrical or prismatic in shape.

[0023] In some embodiments, the thermal conductivity of the micro-nano metal interconnect layer is greater than 100 W / (mK).

[0024] According to some other embodiments, the present invention also provides a method for forming a packaging structure, comprising the following steps:

[0025] forming a package, the package comprising a substrate and a chip mounted on a surface of the substrate, the chip comprising a front side facing the substrate and a back side facing away from the substrate;

[0026] A heat dissipation structure is formed on the back side of the chip, the heat dissipation structure includes a heat dissipation cover and a micro-nano metal interconnection layer at least located between the heat dissipation cover and the chip, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover, and the other end is connected to the back side of the chip.

[0027] In some embodiments, the specific steps of forming the package body include:

[0028] Mounting the chip on the surface of the substrate;

[0029] A plastic sealing layer for sealing the chip is formed on the surface of the substrate, and the surface of the plastic sealing layer facing away from the substrate is flush with the back surface of the chip.

[0030] In some embodiments, the specific steps of forming a heat dissipation structure on the back side of the chip include:

[0031] forming a first micro-nano metal layer continuously distributed on the surface of the plastic packaging layer facing away from the substrate and on the back side of the chip;

[0032] forming a second micro-nano metal layer on the surface of the heat dissipation cover;

[0033] The heat dissipation cover is mounted on the back side of the chip in a direction in which the second micro-nano metal layer faces the first micro-nano metal layer, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

[0034] In some embodiments, the specific steps of forming a first micro-nano metal layer continuously distributed on the surface of the plastic encapsulation layer facing away from the substrate and the back side of the chip include:

[0035] forming a first metal plating layer continuously covering the surface of the plastic packaging layer away from the substrate and the back side of the chip;

[0036] The first micro-nano metal layer including a plurality of first micro-nano metal wires is grown on a surface of the first metal coating layer away from the chip, and the plurality of first micro-nano metal wires are arranged in parallel on the surface of the first metal coating layer.

[0037] In some embodiments, the specific steps of forming the second micro-nano metal layer on the surface of the heat dissipation cover include:

[0038] forming a second metal plating layer on the surface of the heat dissipation cover facing the chip;

[0039] The second micro-nano metal layer including a plurality of second micro-nano metal wires is grown on the surface of the second metal coating layer facing the chip. The plurality of second micro-nano metal wires are arranged in parallel on the surface of the second metal coating layer, and the second micro-nano metal wires are parallel to the first micro-nano metal wires.

[0040] In some embodiments, the heat dissipation cover is mounted on the back side of the chip with the second micro-nano metal layer facing the first micro-nano metal layer, and the first micro-nano metal layer is in contact with the second micro-nano metal layer. The specific steps include:

[0041] The heat dissipation cover is pressed onto the back side of the chip in the direction of the second micro-nano metal layer toward the first micro-nano metal layer, so that the four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the side wall of one second micro-nano metal wire is in contact with and connected to the side walls of the four first micro-nano metal wires distributed around its periphery, and the four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the side wall of one first micro-nano metal wire is in contact with and connected to the side walls of the four second micro-nano metal wires distributed around its periphery.

[0042] In some embodiments, the first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers; and the specific step of attaching the heat dissipation cover to the back side of the chip with the second micro-nano metal layer facing the first micro-nano metal layer further includes:

[0043] The heat dissipation cover is mounted on the back side of the chip in a reducing atmosphere with the second micro-nano metal layer facing the first micro-nano metal layer.

[0044] The packaging structure and the method for forming the same provided by the present invention provide a micro-nano metal interconnection layer between the heat dissipation cover and the back side of the chip, and connect the heat dissipation cover and the chip through the micro-nano metal interconnection layer. On the one hand, the heat dissipation performance of the packaging structure can be significantly improved by utilizing the micro-nano metal interconnection layer with high thermal conductivity, thereby improving the overall performance of the packaging structure. On the other hand, there is no need to form an adhesive layer connecting the chip and the heat dissipation cover through a glue dispensing process, thereby simplifying the process of the packaging structure and further improving the yield of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic cross-sectional view of a packaging structure in a specific embodiment of the present invention;

[0046] Figure 2 is a schematic top view of the first micro-nano metal layer in a specific embodiment of the present invention;

[0047] Figure 3 is a schematic top view of the second micro-nano metal layer in a specific embodiment of the present invention;

[0048] Figure 4A is a schematic cross-sectional view of a first micro-nano metal layer and a second micro-nano metal layer after being pressed and connected in a specific embodiment of the present invention;

[0049] Figure 4B is a partial top view schematic diagram of the first micro-nano metal layer and the second micro-nano metal layer after being pressed and connected in a specific embodiment of the present invention;

[0050] Figure 5 is a flow chart of a method for forming a packaging structure in a specific embodiment of the present invention;

[0051] Figure 6 is a schematic structural diagram of a specific embodiment of the present invention after forming a package body;

[0052] Figure 7 is a schematic structural diagram of a specific embodiment of the present invention after forming a first micro-nano metal layer;

[0053] Figure 8 It is a schematic diagram of the structure after forming a second micro-nano metal layer on the heat dissipation cover according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0054] The specific implementation manner of the packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0055] This specific embodiment provides a packaging structure. Figure 1 Schematic diagram of the cross-section of the packaging structure in a specific embodiment of the present invention. Figure 1 As shown, the packaging structure includes:

[0056] substrate 10;

[0057] A chip 11 is mounted on the surface of the substrate 10, and the chip 11 includes a front side facing the substrate 10 and a back side facing away from the substrate 10;

[0058] A heat dissipation structure is covered on the back side of the chip 11, and the heat dissipation structure includes a heat dissipation cover 18 and a micro-nano metal interconnection layer at least located between the heat dissipation cover 18 and the chip 11, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover 18, and the other end is connected to the back side of the chip 11.

[0059] Specifically, the substrate 10 may be, but is not limited to, a packaging substrate. The substrate 10 includes a top surface and a bottom surface that are relatively distributed, and a circuit layer 12 is provided in the substrate 10, and a plurality of lead-out solder balls 15 electrically connected to the circuit layer 12 are provided on the bottom surface of the substrate 10. The chip 11 includes a front surface facing the substrate 10 and a back surface facing away from the substrate 10, and the chip 11 is mounted on the top surface of the substrate 10 and is electrically connected to the circuit layer 12 in the substrate 10, so that control signals can be transmitted to the chip 11 or signals in the chip 11 can be led out through the circuit layer 12 and the lead-out solder balls 15. In one example, a plurality of conductive bumps 13 are provided on the front surface of the chip 11, and the conductive bumps 13 are soldered to the top surface of the substrate 10 through a solder layer 14. The substrate 10 is also provided with a filling glue layer 16 filled between the chip 11 and the substrate 10, the filling glue layer 16 covers part of the side surface of the chip 11 and part of the top surface of the substrate 10, and the filling glue layer 16 fills the gap between the adjacent conductive bumps 13 to enhance the connection strength between the chip 11 and the substrate 10. In one example, the material of the filling glue layer 16 can be an underfill. The heat dissipation structure is located on the back of the chip 11 and is used to dissipate heat from the chip 11. The heat dissipation structure includes the heat dissipation cover 18 and the micro-nano metal interconnection layer for connecting the chip 11 and the heat dissipation cover 18, the micro-nano metal interconnection layer can conduct the heat generated by the chip 11 to the heat dissipation cover 18, and transmit it to the outside through the heat dissipation cover 18. In one example, the material of the heat dissipation cover 18 can be a metal material, such as metal copper. The multiple described in this specific embodiment refers to more than two.

[0060] The micro-nano metal interconnection layer in this specific embodiment includes a plurality of interconnected micro-nano metal wires, and the line width of the micro-nano metal wires is in the micrometer level or nanometer level, for example, the line width of the micro-nano metal wires is 10nm to 100μm. This specific embodiment uses the micro-nano metal interconnection layer to connect the chip 11 and the heat dissipation cover 18. On the one hand, the micro-nano metal interconnection layer with high thermal conductivity can be used to significantly improve the heat dissipation performance of the packaging structure, avoid heat accumulation inside the chip 11, and thus improve the overall performance of the packaging structure; on the other hand, there is no need to form an adhesive layer connecting the chip and the heat dissipation cover through a dispensing process, which simplifies the process of the packaging structure, thereby improving the yield of the packaging structure.

[0061] In some embodiments, the thermal conductivity of the micro-nano metal interconnection layer is greater than 100 W / (mK). In one example, by adjusting the type of metal material in the micro-nano metal interconnection layer, for example, setting the material of the micro-nano metal interconnection layer to metal copper, the thermal conductivity of the micro-nano metal interconnection layer can reach 300 W / (mK), which is close to the thermal conductivity of pure copper, thereby further significantly improving the heat dissipation performance of the packaging structure.

[0062] In some embodiments, the packaging structure further includes:

[0063] A plastic encapsulation layer 17 is located on the surface of the substrate 10 and plastic encapsulates the chip 11. The surface of the plastic encapsulation layer 17 facing away from the substrate 10 is flush with the back surface of the chip 11.

[0064] The heat dissipation structure continuously covers the back side of the chip 11 and the surface of the plastic packaging layer 17 facing away from the substrate 10 .

[0065] Specifically, the plastic encapsulation layer 17 is located on the top surface of the substrate 10 and plastic encapsulates the chip 11. The plastic encapsulation layer 17 exposes the back of the chip 11, and the surface of the plastic encapsulation layer 17 facing away from the substrate 10 is flush with the exposed back of the chip 11. The heat dissipation structure continuously covers the back of the chip 11 and the surface of the plastic encapsulation layer 17 facing away from the substrate 10, thereby further enhancing the heat dissipation performance of the packaging structure and also helping to simplify the manufacturing process of the packaging structure. In one example, the material of the plastic encapsulation layer 17 is epoxy resin molding compound.

[0066] In some embodiments, Figure 1 As shown, the micro-nano metal interconnection layer includes:

[0067] A first micro-nano metal layer 21 connected to the back side of the chip 11;

[0068] The second micro-nano metal layer 20 is connected to the surface of the heat dissipation cover 18 facing the chip 11 , and the first micro-nano metal layer 21 is in contact with and connected to the second micro-nano metal layer 20 .

[0069] In some embodiments, the heat dissipation structure further includes:

[0070] A first metal coating layer 22 covers the back side of the chip 11, and the first micro-nano metal layer 21 is located on the surface of the first metal coating layer 22 facing away from the chip 11;

[0071] The second metal coating layer 19 covers the surface of the heat dissipation cover 18 facing the chip 11 , and the second micro-nano metal layer 20 is located on the surface of the second metal coating layer 19 facing the chip 11 .

[0072] Figure 2 is a schematic top view of the first micro-nano metal layer in a specific embodiment of the present invention, Figure 3 is a schematic top view of the second micro-nano metal layer in a specific embodiment of the present invention, Figure 4A is a schematic cross-sectional view of a first micro-nano metal layer and a second micro-nano metal layer after being pressed and connected in a specific embodiment of the present invention, Figure 4B is a partial top view schematic diagram of the first micro-nano metal layer and the second micro-nano metal layer after being pressed and connected in a specific embodiment of the present invention. Figure 1 , Figure 2 , Figure 3 , Figure 4A and Figure 4B As shown, the first micro-nano metal layer 21 includes a plurality of first micro-nano metal wires 211 arranged in parallel on the surface of the first metal coating 22, and the second micro-nano metal layer 20 includes a plurality of second micro-nano metal wires 201 arranged in parallel on the surface of the second metal coating 19, and the first micro-nano metal wires 211 and the second micro-nano metal wires 201 are parallel to each other and in contact with each other. It can be understood that one end of the first micro-nano metal wire 211 is arranged on the first metal coating 22 and the other end extends to the second metal coating 19, and one end of the second micro-nano metal wire 201 is arranged on the second metal coating 19 and the other end extends to the first metal coating 22, and each of the first micro-nano metal wires 211 and each of the second micro-nano metal wires 201 are parallel to each other.

[0073] For example, the heat dissipation structure includes the first metal plating layer 22 continuously covering the back side of the chip 11 and the surface of the plastic encapsulation layer 17 facing away from the substrate 10, the second metal plating layer 19 covering the surface of the heat dissipation cover 18 facing the chip 11, and the first micro-nano metal layer 21 and the second micro-nano metal layer 20 sandwiched between the first metal plating layer 22 and the second metal plating layer 19. In one example, the first metal plating layer 22 is formed on the back side of the chip 11 by electroplating or chemical plating, and the second metal plating layer 19 is formed on the surface of the heat dissipation cover 18 by electroplating or chemical plating. The first micro-nano metal layer 21 includes a plurality of the first micro-nano metal wires 211 arranged in an array, the second micro-nano metal layer 20 includes a plurality of the second micro-nano metal wires 201 arranged in an array, and the first micro-nano metal wires 211 are in contact and connected with the second micro-nano metal wires 201. It can be understood that the plurality of first micro-nano metal wires 211 are arranged in parallel on the surface of the first metal coating 22, and each of the first micro-nano metal wires 211 forms an angle with the plane where the first metal coating 22 is located, and the plurality of second micro-nano metal wires 201 are arranged in parallel on the surface of the second metal coating 19, and each of the second micro-nano metal wires 201 forms an angle with the plane where the second metal coating 19 is located, and the first micro-nano metal wires 211 and the second micro-nano metal wires 201 are parallel to each other. In one example, the line width of the first micro-nano metal wire 211 and the line width of the second micro-nano metal wire 201 are both 10nm to 100μm. The plurality of first micro-nano metal wires 211 grow on the surface of the first metal coating 22 away from the chip 11, and the plurality of second micro-nano metal wires 201 grow on the surface of the second metal coating 19 away from the heat dissipation cover 18. By providing the first metal coating 22 and the plurality of first micro-nano metal wires 211 grown on the surface of the first metal coating 22 and the second metal coating 19 and the plurality of second micro-nano metal wires 201 grown on the surface of the second metal coating 19, not only the connection strength between the package and the heat dissipation cover 18 can be enhanced, but also the heat dissipation performance of the heat dissipation structure can be further improved. The package includes the chip 11 and the plastic encapsulation layer 17.

[0074] In some embodiments, the four first micro-nano metal wires 211 in the first micro-nano metal layer 21 are distributed around the periphery of one second micro-nano metal wire 201 in the second micro-nano metal layer 20, and the sidewall of one second micro-nano metal wire 201 is in contact with and connected to the sidewalls of the four first micro-nano metal wires 211 distributed around the periphery thereof;

[0075] The four second micro-nano metal wires 201 in the second micro-nano metal layer 20 are distributed around the periphery of one first micro-nano metal wire 211 in the first micro-nano metal layer 21, and the sidewall of one first micro-nano metal wire 211 is in contact with and connected to the sidewalls of the four second micro-nano metal wires 201 distributed around its periphery.

[0076] For example, if Figure 1 , Figure 4A and Figure 4B As shown, the first micro-nano metal layer 21 and the second micro-nano metal layer 20 are connected by insertion and biting under the action of a pressing force, so that one of the first micro-nano metal wires 211 in the first micro-nano metal layer 21 is inserted into the gap area enclosed by four of the second micro-nano metal wires 201 in the second micro-nano metal layer 20, and one of the second micro-nano metal wires 201 in the second micro-nano metal layer 20 is inserted into the gap area enclosed by four of the first micro-nano metal wires 211 in the first micro-nano metal layer 21, and the side wall of one of the second micro-nano metal wires 201 is in contact with and connected to the side walls of the four first micro-nano metal wires 211 distributed around its periphery, and the side wall of one of the first micro-nano metal wires 211 is in contact with and connected to the side walls of the four second micro-nano metal wires 201 distributed around its periphery, so that heat is transferred to the heat dissipation cover 18 through the first micro-nano metal wires 211 and the second micro-nano metal wires 201 that are in contact with each other. By distributing four of the first micro-nano metal wires 211 around the periphery of one of the second micro-nano metal wires 201 and contacting and connecting with the second micro-nano metal wire 201, and distributing four of the second micro-nano metal wires 201 around the periphery of one of the first micro-nano metal wires 211 and contacting and connecting with the first micro-nano metal wire 211, not only can the first micro-nano metal wire 211 be in close contact with the second micro-nano metal wire 201, thereby further improving the heat dissipation performance of the heat dissipation structure, but also helping to reduce the size of the micro-nano metal interconnection layer.

[0077] In other embodiments, the first micro-nano metal wires 211 in the first micro-nano metal layer 21 and the second micro-nano metal wires 201 in the second micro-nano metal layer 20 are staggered so that one of the first micro-nano metal wires 211 is inserted between two adjacent second micro-nano metal wires 201, one of the second micro-nano metal wires 201 is inserted between two adjacent first micro-nano metal wires 211, one of the first micro-nano metal wires 211 is in contact and connected with two adjacent second micro-nano metal wires 201, and one of the second micro-nano metal wires 201 is in contact and connected with two adjacent first micro-nano metal wires 211, so that the first micro-nano metal wires 211 and the second micro-nano metal wires 201 in the micro-nano metal interconnection layer are alternately arranged. In one example, the spacing between two adjacent first micro-nano metal wires 211 in the first micro-nano metal layer 21 is equal to the line width of the second micro-nano metal wire 201 in the second micro-nano metal layer 20, and the spacing between two adjacent second micro-nano metal wires 201 in the second micro-nano metal layer 20 is equal to the line width of the first micro-nano metal wire 211 in the first micro-nano metal layer 21, so as to achieve close contact between the first micro-nano metal wire 211 and the second micro-nano metal wire 201, thereby further improving the heat dissipation performance of the heat dissipation structure.

[0078] In some embodiments, the first metal coating 22 and the second metal coating 19 are both copper coatings, and the first micro-nano metal wire 211 and the second micro-nano metal wire 201 are both micro-nano copper whiskers, so that the thermal conductivity of the micro-nano metal interconnection layer is close to that of pure copper, further improving the heat dissipation performance of the heat dissipation structure.

[0079] In some embodiments, the first micro-nano metal wire 211 and the second micro-nano metal wire 201 are both cylindrical or prism-shaped to simplify the micro-nano metal interconnection layer manufacturing process. In one example, the size and shape of the first micro-nano metal wire 211 are the same as the size and shape of the second micro-nano metal wire 201.

[0080] This specific embodiment also provides a method for forming a packaging structure. Figure 5 is a flow chart of a method for forming a packaging structure in a specific embodiment of the present invention. The schematic diagram of the packaging structure formed in this specific embodiment can be seen in Figure 1 , Figure 2 , Figure 3 , Figure 4A and Figure 4B .like Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B and Figure 5As shown, the method for forming the packaging structure includes the following steps:

[0081] Step S51, forming a package body, the package body comprising a substrate 10 and a chip 11 mounted on a surface of the substrate 10, the chip 11 comprising a front side facing the substrate 10 and a back side facing away from the substrate 10;

[0082] Step S52, forming a heat dissipation structure on the back side of the chip 11, the heat dissipation structure includes a heat dissipation cover 18 and a micro-nano metal interconnection layer at least located between the heat dissipation cover 18 and the chip 11, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover 18, and the other end is connected to the back side of the chip 11.

[0083] Figure 6 Schematic diagram of the structure of a specific embodiment of the present invention after forming a package body. Figure 6 As shown, the specific steps of forming the package body include:

[0084] Mounting the chip 11 on the surface of the substrate 10;

[0085] A plastic encapsulation layer 17 for encapsulating the chip 11 is formed on the surface of the substrate 10 , and the surface of the plastic encapsulation layer 17 facing away from the substrate 10 is flush with the back surface of the chip 11 .

[0086] Specifically, the substrate 10 may be, but is not limited to, a packaging substrate. The substrate 10 includes a top surface and a bottom surface that are relatively distributed, and a circuit layer 12 is provided in the substrate 10. The chip 11 includes a front surface and a back surface that are relatively distributed, and a plurality of conductive bumps 13 are provided on the front surface of the chip 11. The conductive bumps 13 are soldered to the top surface of the substrate 10 through a solder layer 14. Afterwards, the filling glue layer 16 is formed by a dispensing process, and the filling glue layer 16 covers part of the side surface of the chip 11 and part of the top surface of the substrate 10, and the filling glue layer 16 fills the gaps between adjacent conductive bumps 13. Next, a plastic encapsulation material such as epoxy resin is used to form the plastic encapsulation layer 17 that encapsulates the chip 11, and the surface of the plastic encapsulation layer 17 facing away from the substrate 10 is flush with the back surface of the chip 11, that is, the surface of the plastic encapsulation layer 17 exposes the back surface of the chip 11.

[0087] Figure 7 is a schematic diagram of the structure of a specific embodiment of the present invention after forming the first micro-nano metal layer, Figure 8 1 is a schematic diagram of a structure after forming a second micro-nano metal layer on the heat dissipation cover according to a specific embodiment of the present invention. In some embodiments, the specific steps of forming the heat dissipation structure on the back side of the chip 11 include:

[0088] A first micro-nano metal layer 21 is formed which is continuously distributed on the surface of the plastic encapsulation layer 17 away from the substrate 10 and the back surface of the chip 11. Figure 7 As shown;

[0089] A second micro-nano metal layer 20 is formed on the surface of the heat dissipation cover 18, such as Figure 8 As shown;

[0090] The heat dissipation cover 18 is mounted on the back side of the chip 11 in a direction in which the second micro-nano metal layer 20 faces the first micro-nano metal layer 21 , and the first micro-nano metal layer 21 is in contact with and connected to the second micro-nano metal layer 20 .

[0091] In some embodiments, the specific steps of forming the first micro-nano metal layer 21 continuously distributed on the surface of the plastic encapsulation layer 17 facing away from the substrate 10 and the back side of the chip 11 include:

[0092] Forming a first metal plating layer 22 that continuously covers the surface of the plastic packaging layer 17 away from the substrate 10 and the back side of the chip 11;

[0093] The first micro-nano metal layer 21 including a plurality of first micro-nano metal wires 211 is grown on a surface of the first metal coating layer 22 facing away from the chip 11 , and the plurality of first micro-nano metal wires 211 are arranged in parallel on the surface of the first metal coating layer 22 .

[0094] In some embodiments, the specific steps of forming the second micro-nano metal layer on the surface of the heat dissipation cover include:

[0095] A second metal plating layer 19 is formed on the surface of the heat dissipation cover 18 facing the chip 11;

[0096] The second micro-nano metal layer 20 including a plurality of second micro-nano metal wires 201 is grown on the surface of the second metal coating layer 19 facing the chip 11 . The plurality of second micro-nano metal wires 201 are arranged in parallel on the surface of the second metal coating layer 19 , and the second micro-nano metal wires 201 are parallel to the first micro-nano metal wires 211 .

[0097] In some embodiments, the heat dissipation cover 18 is mounted on the back side of the chip 11 in a direction where the second micro-nano metal layer 20 faces the first micro-nano metal layer 21, and the first micro-nano metal layer 21 is in contact with the second micro-nano metal layer 20. The specific steps include:

[0098] The heat dissipation cover 18 is pressed onto the back side of the chip 11 in the direction of the second micro-nano metal layer 20 toward the first micro-nano metal layer 21, so that the four first micro-nano metal wires 211 in the first micro-nano metal layer 21 are distributed around the periphery of one second micro-nano metal wire 201 in the second micro-nano metal layer 20, and the side wall of one second micro-nano metal wire 201 is in contact with and connected to the side walls of the four first micro-nano metal wires 211 distributed around its periphery, and the four second micro-nano metal wires 201 in the second micro-nano metal layer 20 are distributed around the periphery of one first micro-nano metal wire 211 in the first micro-nano metal layer 21, and the side wall of one first micro-nano metal wire 211 is in contact with and connected to the side walls of the four second micro-nano metal wires 201 distributed around its periphery.

[0099] In some embodiments, the first micro-nano metal wire 211 and the second micro-nano metal wire 201 are both micro-nano copper whiskers; the specific step of attaching the heat dissipation cover 18 to the back side of the chip 11 with the second micro-nano metal layer 20 facing the first micro-nano metal layer 21 also includes:

[0100] In a reducing atmosphere, the heat dissipation cover 18 is mounted on the back side of the chip 11 with the second micro-nano metal layer 20 facing the first micro-nano metal layer 21 .

[0101] For example, after the package is formed, a first metal coating layer 22 covering the surface of the package away from the substrate 10 is formed by an electroplating process or a chemical plating process, and a plurality of the first micro-nano metal wires 211 are grown on the surface of the first metal coating layer 22 by a printing process or the like to form the first micro-nano metal layer 21. Figure 7 As shown. Then, a second metal plating layer 19 covering the surface of the heat dissipation cover 18 is formed by an electroplating process or a chemical plating process, and a plurality of second micro-nano metal wires 201 are grown on the surface of the second metal plating layer 19 away from the heat dissipation cover 18 by a printing process or the like, so as to form the second micro-nano metal layer 20. Afterwards, under a reducing atmosphere, the heat dissipation cover 18 formed with the second micro-nano metal layer 20 is pressed onto the package body formed with the first micro-nano metal layer 21, and the first micro-nano metal wires 211 in the first micro-nano metal layer 21 and the second micro-nano metal wires 201 in the second micro-nano metal layer 20 form a stable physical and chemical synergistic connection through insertion and bite, thereby significantly improving the heat dissipation efficiency of the package structure. By performing the pressing connection between the first micro-nano metal layer 21 and the second micro-nano metal layer 20 under the reducing atmosphere, the oxidation reaction between the first micro-nano metal layer 21 and the second micro-nano metal layer 20 can be avoided, thereby improving the connection strength between the first micro-nano metal layer 21 and the second micro-nano metal layer 20.

[0102] The packaging structure and the method for forming the same provided in this specific embodiment provide a micro-nano metal interconnection layer between the heat dissipation cover and the back side of the chip, and connect the heat dissipation cover and the chip through the micro-nano metal interconnection layer. On the one hand, the heat dissipation performance of the packaging structure can be significantly improved by utilizing the micro-nano metal interconnection layer with high thermal conductivity, thereby improving the overall performance of the packaging structure. On the other hand, there is no need to form an adhesive layer connecting the chip and the heat dissipation cover through a glue dispensing process, thereby simplifying the process of the packaging structure and thereby improving the yield of the packaging structure.

[0103] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A packaging structure, characterized in that: include: substrate; A chip is mounted on the surface of the substrate, wherein the chip comprises a front side facing the substrate and a back side facing away from the substrate; A heat dissipation structure is covered on the back side of the chip, and the heat dissipation structure includes a heat dissipation cover and a micro-nano metal interconnection layer at least located between the heat dissipation cover and the chip, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover, and the other end is connected to the back side of the chip.

2. The packaging structure according to claim 1, characterized in that: Also includes: A plastic sealing layer is located on the surface of the substrate and seals the chip, and the surface of the plastic sealing layer facing away from the substrate is flush with the back surface of the chip; The heat dissipation structure continuously covers the back side of the chip and the surface of the plastic packaging layer facing away from the substrate.

3. The packaging structure according to claim 1, characterized in that: The micro-nano metal interconnection layer comprises: A first micro-nano metal layer connected to the back side of the chip; The second micro-nano metal layer is connected to the surface of the heat dissipation cover facing the chip, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

4. The packaging structure according to claim 3, characterized in that: The heat dissipation structure also includes: A first metal coating layer covers the back side of the chip, and the first micro-nano metal layer is located on a surface of the first metal coating layer facing away from the chip; The second metal plating layer covers the surface of the heat dissipation cover facing the chip, and the second micro-nano metal layer is located on the surface of the second metal plating layer facing the chip.

5. The packaging structure according to claim 4, characterized in that: The first micro-nano metal layer includes a plurality of first micro-nano metal wires arranged in parallel on the surface of the first metal coating layer, and the second micro-nano metal layer includes a plurality of second micro-nano metal wires arranged in parallel on the surface of the second metal coating layer. The first micro-nano metal wires and the second micro-nano metal wires are parallel to each other and in contact with each other.

6. The packaging structure according to claim 5, characterized in that: The four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the sidewall of one second micro-nano metal wire is in contact with and connected to the sidewalls of the four first micro-nano metal wires distributed around the periphery thereof; The four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the sidewall of one first micro-nano metal wire is in contact with and connected to the sidewalls of the four second micro-nano metal wires distributed around its periphery.

7. The packaging structure according to claim 5, characterized in that: The first metal coating and the second metal coating are both copper coatings, and the first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers.

8. The packaging structure according to claim 5, characterized in that: The first micro-nano metal wire and the second micro-nano metal wire are both cylindrical or prism-shaped.

9. The packaging structure according to claim 1, characterized in that: The thermal conductivity of the micro-nano metal interconnection layer is greater than 100 W / (mK).

10. A method for forming a packaging structure, characterized in that: The steps include: forming a package, the package comprising a substrate and a chip mounted on a surface of the substrate, the chip comprising a front side facing the substrate and a back side facing away from the substrate; A heat dissipation structure is formed on the back side of the chip, the heat dissipation structure includes a heat dissipation cover and a micro-nano metal interconnection layer at least located between the heat dissipation cover and the chip, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover, and the other end is connected to the back side of the chip.

11. The method for forming a packaging structure according to claim 10, characterized in that: The specific steps of forming the package body include: Mounting the chip on the surface of the substrate; A plastic sealing layer for sealing the chip is formed on the surface of the substrate, and the surface of the plastic sealing layer facing away from the substrate is flush with the back surface of the chip.

12. The method for forming a packaging structure according to claim 11, characterized in that: The specific steps of forming a heat dissipation structure on the back side of the chip include: forming a first micro-nano metal layer continuously distributed on the surface of the plastic packaging layer facing away from the substrate and on the back side of the chip; forming a second micro-nano metal layer on the surface of the heat dissipation cover; The heat dissipation cover is mounted on the back side of the chip in a direction in which the second micro-nano metal layer faces the first micro-nano metal layer, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

13. The method for forming a packaging structure according to claim 12, wherein: The specific steps of forming a first micro-nano metal layer continuously distributed on the surface of the plastic packaging layer facing away from the substrate and the back side of the chip include: forming a first metal plating layer continuously covering the surface of the plastic packaging layer away from the substrate and the back side of the chip; The first micro-nano metal layer including a plurality of first micro-nano metal wires is grown on a surface of the first metal coating layer away from the chip, and the plurality of first micro-nano metal wires are arranged in parallel on the surface of the first metal coating layer.

14. The method for forming a packaging structure according to claim 13, characterized in that: The specific steps of forming the second micro-nano metal layer on the surface of the heat dissipation cover include: forming a second metal plating layer on the surface of the heat dissipation cover facing the chip; The second micro-nano metal layer including a plurality of second micro-nano metal wires is grown on the surface of the second metal coating layer facing the chip. The plurality of second micro-nano metal wires are arranged in parallel on the surface of the second metal coating layer, and the second micro-nano metal wires are parallel to the first micro-nano metal wires.

15. The method for forming a packaging structure according to claim 14, characterized in that: The specific steps of mounting the heat dissipation cover on the back side of the chip with the second micro-nano metal layer facing the first micro-nano metal layer, and the first micro-nano metal layer being in contact with the second micro-nano metal layer include: The heat dissipation cover is pressed onto the back side of the chip in the direction of the second micro-nano metal layer toward the first micro-nano metal layer, so that the four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the side wall of one second micro-nano metal wire is in contact with and connected to the side walls of the four first micro-nano metal wires distributed around its periphery, and the four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the side wall of one first micro-nano metal wire is in contact with and connected to the side walls of the four second micro-nano metal wires distributed around its periphery.

16. The method for forming a packaging structure according to claim 15, characterized in that: The first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers; The specific step of attaching the heat dissipation cover to the back side of the chip in a direction where the second micro-nano metal layer faces the first micro-nano metal layer also includes: The heat dissipation cover is mounted on the back side of the chip in a reducing atmosphere with the second micro-nano metal layer facing the first micro-nano metal layer.

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