Packaging structure and forming method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging structure and a forming method thereof. The packaging structure comprises a substrate which comprises a top surface and a bottom surface which are oppositely distributed; the chip is mounted on the top surface of the substrate, and the chip comprises a front surface facing the substrate and a back surface deviating from the substrate; the heat dissipation structure comprises a heat dissipation cover and a micro-nano metal interconnection layer, the heat dissipation cover is attached to the top surface of the substrate, the micro-nano metal interconnection layer is at least distributed between the heat dissipation cover and the back surface of the chip, and the chip is located in a containing cavity defined by the heat dissipation cover and the substrate; and one end of the micro-nano metal interconnection layer is connected with the heat dissipation cover, and the other end of the micro-nano metal interconnection layer is connected with the back surface of the chip. The heat dissipation performance of the packaging structure is remarkably improved, and the manufacturing process of the packaging structure is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] As the integration of packaging structures continues to increase and the frequency continues to increase, the heat dissipation of packaging structures has become increasingly prominent. Heat accumulation inside the packaging structure will cause the temperature of electronic structures such as functional chips and functional devices in the packaging structure to be too high, thereby affecting the performance of electronic structures such as functional chips and functional devices, and easily leading to a shortened service life of the packaging structure. In a semiconductor packaging structure, a heat dissipation cover is covered on the surface of the chip away from the substrate, and the heat dissipation cover and the chip are bonded together by adhesive materials such as TIM (Thermal Interface Material, thermal interface material), so that the adhesive material becomes one of the main factors affecting the heat dissipation of the packaging structure. Improving the thermal conductivity of the adhesive material can significantly improve the heat dissipation efficiency of the packaging structure. The current main adhesive materials include organic silica gel, graphene, nano silver glue and indium sheet, but the thermal conductivity of organic silica gel, graphene, nano silver glue and indium sheet does not exceed 100W / (mK), thereby limiting the improvement of the heat dissipation performance of the packaging structure. Moreover, adhesive materials such as organic silica gel, graphene, nano silver glue and indium sheet need to be formed on the surface of the package body or the surface of the heat dissipation cover by dispensing or welding process, and the process is relatively complicated, thereby limiting the improvement of the yield of the packaging structure.

[0003] Therefore, how to improve the heat dissipation performance of the packaging structure and simplify the formation process of the packaging structure, so as to improve the performance and yield of the packaging structure, is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a packaging structure and a forming method thereof, which are used to improve the heat dissipation performance of the packaging structure and simplify the forming process of the packaging structure, thereby improving the performance and yield of the packaging structure.

[0005] According to some embodiments, the present invention provides a packaging structure, comprising:

[0006] A substrate, including a top surface and a bottom surface that are relatively distributed;

[0007] A chip is mounted on the top surface of the substrate, wherein the chip includes a front surface facing the substrate and a back surface facing away from the substrate;

[0008] The heat dissipation structure comprises a heat dissipation cover mounted on the top surface of the substrate and a micro-nano metal interconnection layer distributed at least between the heat dissipation cover and the back surface of the chip, wherein the chip is located in a receiving cavity enclosed by the heat dissipation cover and the substrate, and one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover and the other end is connected to the back surface of the chip.

[0009] In some embodiments, the heat dissipation cover comprises:

[0010] A first platform portion is located on the back side of the chip, and the micro-nano metal interconnection layer is at least located between the first platform portion and the back side of the chip;

[0011] A second platform portion is mounted on the top surface of the substrate;

[0012] A connecting portion, one end of which is connected to the first platform portion, and the other end of which is connected to the second platform portion.

[0013] In some embodiments, the micro-nano metal interconnection layer includes:

[0014] A first micro-nano metal layer connected to the back side of the chip;

[0015] The second micro-nano metal layer is connected to the surface of the heat dissipation cover facing the chip, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

[0016] In some embodiments, the heat dissipation structure further includes:

[0017] A first metal coating layer covers the back side of the chip, and the first micro-nano metal layer is located on a surface of the first metal coating layer facing away from the chip;

[0018] The second metal plating layer covers the surface of the heat dissipation cover facing the chip, and the second micro-nano metal layer is located on the surface of the second metal plating layer facing the chip.

[0019] In some embodiments, the first micro-nano metal layer includes a plurality of first micro-nano metal wires arranged in parallel on the surface of the first metal coating layer, and the second micro-nano metal layer includes a plurality of second micro-nano metal wires arranged in parallel on the surface of the second metal coating layer, and the first micro-nano metal wires and the second micro-nano metal wires are parallel to each other and in contact with each other.

[0020] In some embodiments, the four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the sidewall of one second micro-nano metal wire is in contact with and connected to the sidewalls of the four first micro-nano metal wires distributed around the periphery thereof;

[0021] The four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the sidewall of one first micro-nano metal wire is in contact with and connected to the sidewalls of the four second micro-nano metal wires distributed around its periphery.

[0022] In some embodiments, the first metal coating layer and the second metal coating layer are both copper coating layers, and the first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers.

[0023] In some embodiments, the first micro-nano metal wire and the second micro-nano metal wire are both cylindrical or prismatic in shape.

[0024] In some embodiments, the thermal conductivity of the micro-nano metal interconnect layer is greater than 100 W / (mK).

[0025] In some embodiments, a third micro-nano metal layer is formed on the surface of the second platform portion of the heat dissipation cover facing the substrate, the third micro-nano metal layer includes a plurality of third micro-nano metal wires arranged in an array, and a fourth micro-nano metal layer is formed on the top surface of the substrate at a position corresponding to the second platform portion, the fourth micro-nano metal layer includes a plurality of fourth micro-nano metal wires arranged in an array, and the third micro-nano metal wires are in contact and connected with the fourth micro-nano metal wires.

[0026] According to some other embodiments, the present invention further provides a method for forming a packaging structure, comprising the following steps:

[0027] Mounting a chip on the top surface of the substrate, wherein the chip includes a front side facing the substrate and a back side facing away from the substrate;

[0028] A heat dissipation structure is formed on the top surface of the substrate, the heat dissipation structure includes a heat dissipation cover mounted on the top surface of the substrate and a micro-nano metal interconnection layer distributed at least between the heat dissipation cover and the back side of the chip, the chip is located in a receiving cavity surrounded by the heat dissipation cover and the substrate, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover, and the other end is connected to the back side of the chip.

[0029] In some embodiments, the specific steps of forming a heat dissipation structure on the top surface of the substrate include:

[0030] forming a first micro-nano metal layer on the back side of the chip;

[0031] forming a heat dissipation cover and a second micro-nano metal layer located on the surface of the heat dissipation cover;

[0032] The heat dissipation cover is mounted on the top surface of the substrate in a direction in which the second micro-nano metal layer faces the first micro-nano metal layer, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

[0033] In some embodiments, the specific steps of forming the first micro-nano metal layer on the back side of the chip include:

[0034] forming a first metal plating layer on the back side of the chip;

[0035] The first micro-nano metal layer including a plurality of first micro-nano metal wires is grown on a surface of the first metal coating layer away from the chip, and the plurality of first micro-nano metal wires are arranged in parallel on the surface of the first metal coating layer.

[0036] In some embodiments, the specific steps of forming the heat dissipation cover and the second micro-nano metal layer located on the surface of the heat dissipation cover include:

[0037] forming the heat dissipation cover, wherein the heat dissipation cover comprises a first platform portion, a second platform portion located below the first platform portion, and a connecting portion connecting the first platform portion and the second platform portion;

[0038] forming a second metal plating layer on the inner surface of the first platform portion;

[0039] The second micro-nano metal layer including a plurality of second micro-nano metal wires is grown on the surface of the second metal coating layer away from the first platform portion. The plurality of second micro-nano metal wires are arranged in parallel on the surface of the second metal coating layer, and the second micro-nano metal wires are parallel to the first micro-nano metal wires.

[0040] In some embodiments, the specific steps of attaching the heat dissipation cover to the top surface of the substrate with the second micro-nano metal layer facing the first micro-nano metal layer include:

[0041] The second platform portion of the heat dissipation cover is mounted on the top surface of the substrate with the second micro-nano metal layer facing the first micro-nano metal layer, and the first platform portion is pressed onto the back side of the chip, so that the four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the side wall of one second micro-nano metal wire is in contact with and connected to the side walls of the four first micro-nano metal wires distributed around its periphery, and the four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the side wall of one first micro-nano metal wire is in contact with and connected to the side walls of the four second micro-nano metal wires distributed around its periphery.

[0042] In some embodiments, the first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers; the specific steps of attaching the second platform portion of the heat dissipation cover to the top surface of the substrate with the second micro-nano metal layer facing the first micro-nano metal layer, and pressing the first platform portion to the back side of the chip include:

[0043] The second platform portion of the heat dissipation cover is mounted on the top surface of the substrate in a reducing atmosphere with the second micro-nano metal layer facing the first micro-nano metal layer, and the first platform portion is pressed onto the back surface of the chip.

[0044] The packaging structure and the method for forming the same provided by the present invention provide a micro-nano metal interconnection layer between the heat dissipation cover and the back side of the chip, and connect the heat dissipation cover and the chip through the micro-nano metal interconnection layer. On the one hand, the micro-nano metal interconnection layer with high thermal conductivity can be used to significantly improve the heat dissipation performance of the packaging structure, thereby improving the overall performance of the packaging structure; on the other hand, there is no need to form an adhesive layer connecting the chip and the heat dissipation cover through a glue dispensing process, which simplifies the process of the packaging structure, thereby improving the yield of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic cross-sectional view of a packaging structure in a specific embodiment of the present invention;

[0046] Figure 2 is a cross-sectional schematic diagram of a heat dissipation cover in a specific embodiment of the present invention;

[0047] Figure 3 is a schematic cross-sectional view of a micro-nano metal interconnection layer in a specific embodiment of the present invention;

[0048] Figure 4 is a schematic top view of the first micro-nano metal layer in a specific embodiment of the present invention;

[0049] Figure 5 is a schematic top view of the second micro-nano metal layer in a specific embodiment of the present invention;

[0050] Figure 6 is a partial top view schematic diagram of a micro-nano metal interconnection layer in a specific embodiment of the present invention;

[0051] Figure 7 is a flow chart of a method for forming a packaging structure in a specific embodiment of the present invention;

[0052] Figure 8 is a schematic diagram of the structure after the chip is mounted on the surface of the substrate in a specific embodiment of the present invention;

[0053] Fig. 9is a schematic diagram of the structure after the first micro-nano metal layer is formed in a specific embodiment of the present invention;

[0054] Fig.10 It is a schematic diagram of the structure after the heat dissipation cover and the second micro-nano metal layer are formed in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0055] The specific implementation manner of the packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0056] This specific embodiment provides a packaging structure. Figure 1 Schematic diagram of the cross-section of the packaging structure in a specific embodiment of the present invention. Figure 1 As shown, the packaging structure includes:

[0057] The substrate 10 includes a top surface and a bottom surface that are relatively distributed;

[0058] A chip 11 is mounted on the top surface of the substrate 10, and the chip 11 includes a front surface facing the substrate 10 and a back surface facing away from the substrate 10;

[0059] The heat dissipation structure includes a heat dissipation cover 16 mounted on the top surface of the substrate 10 and a micro-nano metal interconnection layer 20 distributed at least between the heat dissipation cover 16 and the back side of the chip 11. The chip 11 is located in a receiving cavity 17 enclosed by the heat dissipation cover 16 and the substrate 10. One end of the micro-nano metal interconnection layer 20 is connected to the heat dissipation cover 16, and the other end is connected to the back side of the chip 11.

[0060] Specifically, the substrate 10 may be, but is not limited to, a packaging substrate. The substrate 10 includes a top surface and a bottom surface that are relatively distributed, and a circuit layer 12 is disposed in the substrate 10, and a plurality of lead solder balls 13 electrically connected to the circuit layer 12 are disposed on the bottom surface of the substrate 10. The chip 11 includes a front surface facing the substrate 10 and a back surface facing away from the substrate 10, and the chip 11 is mounted on the top surface of the substrate 10 and is electrically connected to the circuit layer 12 in the substrate 10, so that a control signal can be transmitted to the chip 11 or a signal in the chip 11 can be led out through the circuit layer 12 and the lead solder balls 13. In one example, the chip 11 is mounted on the top surface of the substrate 10 through a plurality of conductive connection structures 14. The substrate 10 is also provided with a filling glue layer 15 filled between the chip 11 and the substrate 10, the filling glue layer 15 covers part of the side surface of the chip 11 and part of the top surface of the substrate 10, and the filling glue layer 15 fills the gap between the adjacent conductive connection structures 14 to enhance the connection strength between the chip 11 and the substrate 10. In one example, the material of the filling glue layer 15 can be underfill. The heat dissipation structure is mounted on the top surface of the substrate 10 and connected to the back of the chip 11, and is used to dissipate heat from the chip 11 and the substrate 10. The heat dissipation structure includes the heat dissipation cover 16 and the micro-nano metal interconnection layer 20. The heat dissipation cover 16 is attached to the top surface of the substrate 10 through the thermal conductive adhesive layer 21 and connected to the back of the chip 11 through the micro-nano metal interconnection layer 20, so that the substrate 10 can conduct heat to the heat dissipation cover 16, and the chip 11 can also conduct heat to the heat dissipation cover 16 through the micro-nano metal interconnection layer 20, and then the heat dissipation cover 16 transfers the heat to the outside. In one example, the material of the heat dissipation cover can be a metal material, such as metallic copper. The multiple mentioned in this specific embodiment refers to more than two.

[0061] In one example, the thermally conductive adhesive layer 21 used to connect the heat dissipation cover 16 and the substrate 10 is a conductive adhesive layer, so that the heat dissipation cover 16 is grounded through the substrate 10, so that the heat dissipation cover 16 can also play an electromagnetic shielding effect, further improving the performance of the packaging structure.

[0062] In another example, the thermally conductive adhesive layer 21 used to connect the heat dissipation cover 16 and the substrate 10 is an insulating adhesive layer, so that the heat dissipation cover 16 and the substrate 10 are electrically isolated to simplify the packaging structure.

[0063] The micro-nano metal interconnection layer 20 in this specific embodiment includes a plurality of interconnected micro-nano metal wires, and the line width of the micro-nano metal wires is in the micrometer level or nanometer level, for example, the line width of the micro-nano metal wires is 10nm to 100μm. This specific embodiment uses the micro-nano metal interconnection layer 20 to connect the chip 11 and the heat dissipation cover 16. On the one hand, the micro-nano metal interconnection layer 20 with high thermal conductivity can be used to significantly improve the heat dissipation performance of the packaging structure, avoid heat accumulation inside the chip 11, and thus improve the overall performance of the packaging structure; on the other hand, there is no need to form an adhesive layer connecting the chip and the heat dissipation cover through a dispensing process, and the chip and the heat dissipation cover are connected wirelessly through an additional welding process, which simplifies the process of the packaging structure, thereby improving the yield of the packaging structure.

[0064] In some embodiments, the thermal conductivity of the micro-nano metal interconnection layer 20 is greater than 100 W / (mK). In one example, by adjusting the type of metal material in the micro-nano metal interconnection layer 20, for example, by setting the material of the micro-nano metal interconnection layer 20 to metal copper, the thermal conductivity of the micro-nano metal interconnection layer 20 can reach 300 W / (mK), which is close to the thermal conductivity of pure copper, thereby further significantly improving the heat dissipation performance of the packaging structure.

[0065] Figure 2 1 is a cross-sectional schematic diagram of a heat dissipation cover in a specific embodiment of the present invention. In some embodiments, the heat dissipation cover 16 includes:

[0066] The first platform portion 161 is located on the back side of the chip 11, and the micro-nano metal interconnection layer 20 is at least located between the first platform portion 161 and the back side of the chip 11;

[0067] The second platform portion 162 is mounted on the top surface of the substrate 10;

[0068] The connecting portion 163 has one end connected to the first platform portion 161 and the other end connected to the second platform portion 162 .

[0069] Specifically, the heat dissipation cover 16 includes the first platform portion 161 connected to the back side of the chip 11 through the micro-nano metal interconnection layer 20, the second platform portion 162 connected to the top surface of the substrate 10 through the thermal conductive adhesive layer 21, and the connecting portion 163 connecting the first platform portion 161 and the second platform portion 162. The first platform portion 161 includes an inner surface 1612 facing the chip 11 and an outer surface 1611 facing away from the chip 11. In one example, the connecting portion 163 is connected to the first platform portion 161 at an angle. By providing the first platform portion 161 in the heat dissipation cover 16, the top heat dissipation area of ​​the heat dissipation cover 16 and the connection area between the heat dissipation cover 16 and the chip 11 can be increased, which helps to further improve the upward heat dissipation performance of the packaging structure. By providing the second platform portion 162 in the heat dissipation cover 16, the connection area between the heat dissipation cover 16 and the substrate 10 can be increased, thereby not only increasing the connection strength between the heat dissipation cover 16 and the substrate 10, but also more efficiently guiding the heat in the substrate 10 to the heat dissipation cover 16, thereby further improving the heat dissipation performance of the packaging structure.

[0070] Figure 3 is a schematic cross-sectional view of a micro-nano metal interconnection layer in a specific embodiment of the present invention, Figure 4 is a schematic top view of the first micro-nano metal layer in a specific embodiment of the present invention, Figure 5 is a schematic top view of the second micro-nano metal layer in a specific embodiment of the present invention, Figure 6 2 is a partial top view schematic diagram of a micro-nano metal interconnection layer in a specific embodiment of the present invention. In some embodiments, the micro-nano metal interconnection layer 20 includes:

[0071] A first micro-nano metal layer 31 is connected to the back side of the chip 11;

[0072] The second micro-nano metal layer 32 is connected to the surface of the heat dissipation cover 16 facing the chip 11 , and the first micro-nano metal layer 31 is in contact with and connected to the second micro-nano metal layer 32 .

[0073] In some embodiments, the heat dissipation structure further includes:

[0074] A first metal coating layer 18 covers the back side of the chip 11, and the first micro-nano metal layer 31 is located on the surface of the first metal coating layer 18 facing away from the chip 11;

[0075] The second metal coating layer 19 covers the surface of the heat dissipation cover 16 facing the chip 11 , and the second micro-nano metal layer 32 is located on the surface of the second metal coating layer 19 facing the chip 11 .

[0076] In some embodiments, the first micro-nano metal layer 31 includes a plurality of first micro-nano metal wires 311 arranged in parallel on the surface of the first metal coating 18, and the second micro-nano metal layer 32 includes a plurality of second micro-nano metal wires 321 arranged in parallel on the surface of the second metal coating 19. The first micro-nano metal wires 311 and the second micro-nano metal wires 321 are parallel to each other and in contact with each other. It can be understood that one end of the first micro-nano metal wire 311 is arranged on the first metal coating 18, and the other end extends to the second metal coating 19, and one end of the second micro-nano metal wire 321 is arranged on the second metal coating 19, and the other end extends to the first metal coating 18. Each of the first micro-nano metal wires 311 and each of the second micro-nano metal wires 321 are parallel to each other.

[0077] For example, the heat dissipation structure includes the first metal plating layer 18 covering the back side of the chip 11, the second metal plating layer 19 covering the inner surface 1612 of the first platform portion 161 in the heat dissipation cover 16, and the first micro-nano metal layer 31 and the second micro-nano metal layer 32 sandwiched between the first metal plating layer 18 and the second metal plating layer 19. In one example, the first metal plating layer 18 is formed on the back side of the chip 11 by electroplating or chemical plating, and the second metal plating layer 19 is formed on the inner surface 1612 of the first platform portion 161 by electroplating or chemical plating. The first micro-nano metal layer 31 includes a plurality of the first micro-nano metal wires 311 arranged in an array, the second micro-nano metal layer 32 includes a plurality of the second micro-nano metal wires 321 arranged in an array, and the first micro-nano metal wires 311 are in contact with the second micro-nano metal wires 321. It can be understood that a plurality of the first micro-nano metal wires 311 are arranged in parallel on the surface of the first metal coating 18, and each of the first micro-nano metal wires 311 forms an angle with the plane where the first metal coating 18 is located, and a plurality of the second micro-nano metal wires 321 are arranged in parallel on the surface of the second metal coating 19, and each of the second micro-nano metal wires 321 forms an angle with the plane where the second metal coating 19 is located, and the first micro-nano metal wires 311 and the second micro-nano metal wires 321 are parallel to each other. In one example, the line width of the first micro-nano metal wire 311 and the line width of the second micro-nano metal wire 321 are both 10nm to 100μm. The first micro-nano metal wire 311 grows on the surface of the first metal coating 31 away from the chip 11, and a plurality of the second micro-nano metal wires 321 grow on the surface of the second metal coating 19 away from the first platform portion 161. By providing the first metal coating 18 and the plurality of first micro-nano metal wires 31 grown on the surface of the first metal coating 18 and the second metal coating 19 and the plurality of second micro-nano metal wires 321 grown on the surface of the second metal coating 19, not only can the connection strength between the chip 11 and the heat dissipation cover 16 be enhanced, but also it helps to further improve the heat dissipation performance of the heat dissipation structure.

[0078] In some embodiments, the four first micro-nano metal wires 311 in the first micro-nano metal layer 31 are distributed around the periphery of one second micro-nano metal wire 321 in the second micro-nano metal layer 32, and the sidewall of one second micro-nano metal wire 321 is in contact with and connected to the sidewalls of the four first micro-nano metal wires 311 distributed around the periphery thereof;

[0079] The four second micro-nano metal wires 321 in the second micro-nano metal layer 32 are distributed around the periphery of one first micro-nano metal wire 311 in the first micro-nano metal layer 31, and the sidewall of one first micro-nano metal wire 311 is in contact with and connected to the sidewalls of the four second micro-nano metal wires 321 distributed around its periphery.

[0080] For example, if Figure 1 , Figure 3 and Figure 6 As shown, the first micro-nano metal layer 31 and the second micro-nano metal layer 32 are connected by insertion and biting under the action of a pressing force, so that one of the first micro-nano metal wires 311 in the first micro-nano metal layer 31 is inserted into the gap area enclosed by four of the second micro-nano metal wires 321 in the second micro-nano metal layer 32, and one of the second micro-nano metal wires 321 in the second micro-nano metal layer 32 is inserted into the gap area enclosed by four of the first micro-nano metal wires 311 in the first micro-nano metal layer 31, and the side wall of one of the second micro-nano metal wires 321 is in contact with and connected to the side walls of the four first micro-nano metal wires 311 distributed around its periphery, and the side wall of one of the first micro-nano metal wires 311 is in contact with and connected to the side walls of the four second micro-nano metal wires 321 distributed around its periphery, so that heat is transferred to the heat dissipation cover 16 through the first micro-nano metal wires 311 and the second micro-nano metal wires 321 that are in contact with each other. By distributing four of the first micro-nano metal wires 311 around the periphery of one of the second micro-nano metal wires 321 and contacting and connecting with the second micro-nano metal wire 321, and distributing four of the second micro-nano metal wires 321 around the periphery of one of the first micro-nano metal wires 311 and contacting and connecting with the first micro-nano metal wire 311, not only can the first micro-nano metal wire 311 and the second micro-nano metal wire 321 be closely contacted and combined, thereby further improving the heat dissipation performance of the heat dissipation structure, but also it helps to reduce the size of the micro-nano metal interconnection layer.

[0081] In other embodiments, the first micro-nano metal wires 311 in the first micro-nano metal layer 31 and the second micro-nano metal wires 321 in the second micro-nano metal layer 32 are staggered so that one of the first micro-nano metal wires 311 is inserted between two adjacent second micro-nano metal wires 321, one of the second micro-nano metal wires 321 is inserted between two adjacent first micro-nano metal wires 311, one of the first micro-nano metal wires 311 is in contact and connected with two adjacent second micro-nano metal wires 321, and one of the second micro-nano metal wires 321 is in contact and connected with two adjacent first micro-nano metal wires 311, so that the first micro-nano metal wires 311 and the second micro-nano metal wires 321 in the micro-nano metal interconnection layer 20 are alternately arranged. In one example, the spacing between two adjacent first micro-nano metal wires 311 in the first micro-nano metal layer 31 is equal to the line width of the second micro-nano metal wire 321 in the second micro-nano metal layer 32, and the spacing between two adjacent second micro-nano metal wires 321 in the second micro-nano metal layer 32 is equal to the line width of the first micro-nano metal wire 311 in the first micro-nano metal layer 31, so as to achieve close contact and bonding between the first micro-nano metal wire 311 and the second micro-nano metal wire 321, thereby further improving the heat dissipation performance of the heat dissipation structure.

[0082] In some embodiments, the first metal coating 18 and the second metal coating 19 are both copper coatings, and the first micro-nano metal wire 311 and the second micro-nano metal wire 321 are both micro-nano copper whiskers, so that the thermal conductivity of the micro-nano metal interconnection layer is close to that of pure copper, further improving the heat dissipation performance of the heat dissipation structure.

[0083] In some embodiments, the first micro-nano metal wire 311 and the second micro-nano metal wire 321 are both cylindrical or prism-shaped to simplify the manufacturing process of the micro-nano metal interconnect layer 20. In one example, the size and shape of the first micro-nano metal wire 311 are the same as the size and shape of the second micro-nano metal wire 321.

[0084] In some embodiments, a third micro-nano metal layer is formed on the surface of the second platform portion 162 of the heat dissipation cover 16 facing the substrate 10, and the third micro-nano metal layer includes a plurality of third micro-nano metal wires arranged in an array. A fourth micro-nano metal layer is formed on the top surface of the substrate 10 at a position corresponding to the second platform portion 162, and the fourth micro-nano metal layer includes a plurality of fourth micro-nano metal wires arranged in an array, and the third micro-nano metal wires are in contact and connected with the fourth micro-nano metal wires.

[0085] This specific embodiment also provides a method for forming a packaging structure. Figure 7is a flow chart of a method for forming a packaging structure in a specific embodiment of the present invention. Figure 1-Figure 6 .like Figure 1-Figure 7 As shown, the method for forming the packaging structure includes the following steps:

[0086] Step S61, mounting a chip 11 on the top surface of a substrate 10, wherein the chip 11 includes a front side facing the substrate 10 and a back side facing away from the substrate 10;

[0087] Step S62, forming a heat dissipation structure on the top surface of the substrate 10, the heat dissipation structure includes a heat dissipation cover 16 mounted on the top surface of the substrate 10 and a micro-nano metal interconnection layer 20 distributed at least between the heat dissipation cover 16 and the back side of the chip 11, the chip 11 is located in the accommodating cavity 17 enclosed by the heat dissipation cover 16 and the substrate 10, one end of the micro-nano metal interconnection layer 20 is connected to the heat dissipation cover 16, and the other end is connected to the back side of the chip 11.

[0088] In some embodiments, the specific steps of forming the heat dissipation structure on the top surface of the substrate 10 include:

[0089] Forming a first micro-nano metal layer 31 on the back side of the chip 11;

[0090] Forming a heat dissipation cover 16 and a second micro-nano metal layer 32 located on the surface of the heat dissipation cover 16;

[0091] The heat dissipation cover 16 is mounted on the top surface of the substrate 10 in a direction where the second micro-nano metal layer 32 faces the first micro-nano metal layer 31 , and the first micro-nano metal layer 31 is in contact with and connected to the second micro-nano metal layer 32 .

[0092] In some embodiments, the specific steps of forming the first micro-nano metal layer 31 on the back side of the chip 11 include:

[0093] forming a first metal plating layer 18 on the back side of the chip 11;

[0094] The first micro-nano metal layer 31 including a plurality of first micro-nano metal wires 311 is grown on a surface of the first metal coating layer 18 facing away from the chip 11 , and the plurality of first micro-nano metal wires 311 are arranged in parallel on the surface of the first metal coating layer 18 .

[0095] In some embodiments, the specific steps of forming the heat dissipation cover 16 and the second micro-nano metal layer 32 located on the surface of the heat dissipation cover 16 include:

[0096] The heat dissipation cover 16 is formed, and the heat dissipation cover 16 includes a first platform portion 161, a second platform portion 162 located below the first platform portion 161, and a connecting portion 163 connecting the first platform portion 161 and the second platform portion 162;

[0097] forming a second metal plating layer 19 on the inner surface 1612 of the first platform portion 161;

[0098] The second micro-nano metal layer 32 including a plurality of second micro-nano metal wires 321 is grown on the surface of the second metal coating layer 19 away from the first platform portion 161 . The plurality of second micro-nano metal wires 321 are arranged in parallel on the surface of the second metal coating layer 19 . The second micro-nano metal wires 321 are parallel to the first micro-nano metal wires 311 .

[0099] In some embodiments, the specific steps of mounting the heat dissipation cover 16 on the top surface of the substrate 10 with the second micro-nano metal layer 32 facing the first micro-nano metal layer 31 include:

[0100] The second platform portion 162 of the heat dissipation cover 16 is mounted on the top surface of the substrate 10 with the second micro-nano metal layer 32 facing the first micro-nano metal layer 31, and the first platform portion 161 is pressed onto the back side of the chip 11, so that the four first micro-nano metal wires 311 in the first micro-nano metal layer 31 are distributed around the periphery of one second micro-nano metal wire 321 in the second micro-nano metal layer 32, and the side wall of one second micro-nano metal wire 321 is in contact with and connected to the side walls of the four first micro-nano metal wires 311 distributed around its periphery, and the four second micro-nano metal wires 321 in the second micro-nano metal layer 32 are distributed around the periphery of one first micro-nano metal wire 311 in the first micro-nano metal layer 31, and the side wall of one first micro-nano metal wire 311 is in contact with and connected to the side walls of the four second micro-nano metal wires 321 distributed around its periphery.

[0101] In some embodiments, the first micro-nano metal wire 311 and the second micro-nano metal wire 321 are both micro-nano copper whiskers; the specific steps of mounting the second platform portion 162 of the heat dissipation cover 16 on the top surface of the substrate 10 with the second micro-nano metal layer 32 facing the first micro-nano metal layer 31, and pressing the first platform portion 161 onto the back surface of the chip 11 include:

[0102] In a reducing atmosphere, the second platform portion 162 of the heat dissipation cover 16 is mounted on the top surface of the substrate 10 with the second micro-nano metal layer 32 facing the first micro-nano metal layer 31 , and the first platform portion 161 is pressed onto the back surface of the chip 11 .

[0103] Figure 8 is a schematic diagram of the structure after the chip is mounted on the surface of the substrate in a specific embodiment of the present invention, Fig. 9 is a schematic diagram of the structure after the first micro-nano metal layer is formed in a specific embodiment of the present invention, Fig.10 It is a schematic diagram of the structure after the heat dissipation cover and the second micro-nano metal layer are formed in a specific embodiment of the present invention. For example, the substrate 10 can be but is not limited to a packaging substrate. The substrate 10 includes a top surface and a bottom surface that are relatively distributed, and a circuit layer 12 is arranged in the substrate 10. The chip 11 includes a front side facing the substrate 10 and a back side facing away from the substrate 10, and the chip 11 is mounted on the top surface of the substrate 10 and is electrically connected to the circuit layer 12 in the substrate 10. In one example, the chip 11 is mounted on the top surface of the substrate 10 through a plurality of conductive connection structures 14. A filling glue layer 15 for connecting the chip 11 and the substrate 10 is also provided on the substrate 10, and the filling glue layer 15 covers part of the side surface of the chip 11 and part of the top surface of the substrate 10, and the filling glue layer 15 fills the gap between adjacent conductive connection structures 14, such as Figure 8 As shown, the connection strength between the chip 11 and the substrate 10 is enhanced. In one example, the material of the filling glue layer 15 can be underfill.

[0104] In the formation of Figure 8 After the structure shown in FIG. 1 , the first metal plating layer 18 covering the back side of the chip 11 is formed by an electroplating process or a chemical plating process, and a plurality of the first micro-nano metal wires 311 are grown on the surface of the first metal plating layer 18 by a printing process or the like to form the first micro-nano metal layer 31, as shown in FIG. Figure 1 and Fig. 9 Next, the heat dissipation cover 16 including the first platform portion 161, the second platform portion 162 and the connecting portion 163 is formed, and the second metal plating layer 19 is formed on the inner surface 1612 of the first platform portion 161 by electroplating or chemical plating, and a plurality of second micro-nano metal wires 321 are grown on the surface of the second metal plating layer 19 away from the first platform portion 161 by printing or other processes to form the second micro-nano metal layer 32, as shown in FIG. Fig.10As shown. Afterwards, under a reducing atmosphere, the second platform portion 162 in the heat dissipation cover 16 formed with the second micro-nano metal layer 32 is attached to the top surface of the substrate 10, and the first platform portion 161 is pressed onto the back of the chip 11, and the first micro-nano metal wire 311 in the first micro-nano metal layer 31 and the second micro-nano metal wire 321 in the second micro-nano metal layer 32 form a stable physical and chemical synergistic connection through insertion and bite, thereby significantly improving the heat dissipation efficiency of the packaging structure. By performing a press connection between the first micro-nano metal layer 31 and the second micro-nano metal layer 32 under the reducing atmosphere, it is possible to avoid oxidation reaction between the first micro-nano metal layer 31 and the second micro-nano metal layer 32, thereby improving the connection strength between the first micro-nano metal layer 31 and the second micro-nano metal layer 32.

[0105] The packaging structure and the method for forming the same provided in this specific embodiment provide a micro-nano metal interconnection layer between the heat dissipation cover and the back side of the chip, and connect the heat dissipation cover and the chip through the micro-nano metal interconnection layer. On the one hand, the micro-nano metal interconnection layer with high thermal conductivity can be used to significantly improve the heat dissipation performance of the packaging structure, thereby improving the overall performance of the packaging structure; on the other hand, there is no need to form an adhesive layer connecting the chip and the heat dissipation cover through a glue dispensing process, which simplifies the process of the packaging structure, thereby improving the yield of the packaging structure.

[0106] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A packaging structure, characterized in that: include: A substrate, including a top surface and a bottom surface that are relatively distributed; A chip is mounted on the top surface of the substrate, wherein the chip includes a front surface facing the substrate and a back surface facing away from the substrate; The heat dissipation structure comprises a heat dissipation cover mounted on the top surface of the substrate and a micro-nano metal interconnection layer distributed at least between the heat dissipation cover and the back surface of the chip, wherein the chip is located in a receiving cavity enclosed by the heat dissipation cover and the substrate, and one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover and the other end is connected to the back surface of the chip.

2. The packaging structure according to claim 1, characterized in that: The heat dissipation cover comprises: The first platform portion is located on the back side of the chip, and the micro-nano metal interconnection layer is at least located on the between the first platform portion and the back side of the chip; A second platform portion is mounted on the top surface of the substrate; A connecting portion, one end of which is connected to the first platform portion, and the other end of which is connected to the second platform portion.

3. The packaging structure according to claim 1, characterized in that: The micro-nano metal interconnection layer comprises: A first micro-nano metal layer connected to the back side of the chip; The second micro-nano metal layer is connected to the surface of the heat dissipation cover facing the chip, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

4. The packaging structure according to claim 3, characterized in that: The heat dissipation structure further includes: A first metal coating layer covers the back side of the chip, and the first micro-nano metal layer is located on a surface of the first metal coating layer facing away from the chip; The second metal plating layer covers the surface of the heat dissipation cover facing the chip, and the second micro-nano metal layer is located on the surface of the second metal plating layer facing the chip.

5. The packaging structure according to claim 4, characterized in that: The first micro-nano metal layer includes a plurality of first micro-nano metal wires arranged in parallel on the surface of the first metal coating layer, and the second micro-nano metal layer includes a plurality of second micro-nano metal wires arranged in parallel on the surface of the second metal coating layer. The first micro-nano metal wires and the second micro-nano metal wires are parallel to each other and in contact with each other.

6. The packaging structure according to claim 5, characterized in that: The four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the sidewall of one second micro-nano metal wire is in contact with and connected to the sidewalls of the four first micro-nano metal wires distributed around the periphery thereof; The four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the sidewall of one first micro-nano metal wire is in contact with and connected to the sidewalls of the four second micro-nano metal wires distributed around its periphery.

7. The packaging structure according to claim 5, characterized in that: The first metal coating and the second metal coating are both copper coatings, and the first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers.

8. The packaging structure according to claim 5, characterized in that: The first micro-nano metal wire and the second micro-nano metal wire are both cylindrical or prism-shaped.

9. The packaging structure according to claim 1, characterized in that: The thermal conductivity of the micro-nano metal interconnection layer is greater than 100 W / (mK).

10. The packaging structure according to claim 2, characterized in that: A third micro-nano metal layer is formed on the surface of the second platform portion of the heat dissipation cover facing the substrate, the third micro-nano metal layer includes a plurality of third micro-nano metal wires arranged in an array, and a fourth micro-nano metal layer is formed on the top surface of the substrate at a position corresponding to the second platform portion, the fourth micro-nano metal layer includes a plurality of fourth micro-nano metal wires arranged in an array, and the third micro-nano metal wires are in contact and connected with the fourth micro-nano metal wires.

11. A method for forming a packaging structure, characterized in that: The steps include: Mounting a chip on the top surface of the substrate, wherein the chip includes a front side facing the substrate and a back side facing away from the substrate; A heat dissipation structure is formed on the top surface of the substrate, the heat dissipation structure includes a heat dissipation cover mounted on the top surface of the substrate and a micro-nano metal interconnection layer distributed at least between the heat dissipation cover and the back side of the chip, the chip is located in a receiving cavity surrounded by the heat dissipation cover and the substrate, one end of the micro-nano metal interconnection layer is connected to the heat dissipation cover, and the other end is connected to the back side of the chip.

12. The method for forming a packaging structure according to claim 11, characterized in that: The specific steps of forming a heat dissipation structure on the top surface of the substrate include: forming a first micro-nano metal layer on the back side of the chip; forming a heat dissipation cover and a second micro-nano metal layer located on the surface of the heat dissipation cover; The heat dissipation cover is mounted on the top surface of the substrate in a direction in which the second micro-nano metal layer faces the first micro-nano metal layer, and the first micro-nano metal layer is in contact with and connected to the second micro-nano metal layer.

13. The method for forming a packaging structure according to claim 12, wherein: The specific steps of forming a first micro-nano metal layer on the back side of the chip include: forming a first metal plating layer on the back side of the chip; The first micro-nano metal layer including a plurality of first micro-nano metal wires is grown on a surface of the first metal coating layer away from the chip, and the plurality of first micro-nano metal wires are arranged in parallel on the surface of the first metal coating layer.

14. The method for forming a packaging structure according to claim 13, characterized in that: The specific steps of forming the heat dissipation cover and the second micro-nano metal layer located on the surface of the heat dissipation cover include: forming the heat dissipation cover, wherein the heat dissipation cover comprises a first platform portion, a second platform portion located below the first platform portion, and a connecting portion connecting the first platform portion and the second platform portion; forming a second metal plating layer on the inner surface of the first platform portion; The second micro-nano metal layer including a plurality of second micro-nano metal wires is grown on the surface of the second metal coating layer away from the first platform portion. The plurality of second micro-nano metal wires are arranged in parallel on the surface of the second metal coating layer, and the second micro-nano metal wires are parallel to the first micro-nano metal wires.

15. The method for forming a packaging structure according to claim 14, characterized in that: The specific steps of mounting the heat dissipation cover on the top surface of the substrate in a direction where the second micro-nano metal layer faces the first micro-nano metal layer include: The second platform portion of the heat dissipation cover is mounted on the top surface of the substrate with the second micro-nano metal layer facing the first micro-nano metal layer, and the first platform portion is pressed onto the back side of the chip, so that the four first micro-nano metal wires in the first micro-nano metal layer are distributed around the periphery of one second micro-nano metal wire in the second micro-nano metal layer, and the side wall of one second micro-nano metal wire is in contact with and connected to the side walls of the four first micro-nano metal wires distributed around its periphery, and the four second micro-nano metal wires in the second micro-nano metal layer are distributed around the periphery of one first micro-nano metal wire in the first micro-nano metal layer, and the side wall of one first micro-nano metal wire is in contact with and connected to the side walls of the four second micro-nano metal wires distributed around its periphery.

16. The method for forming a packaging structure according to claim 15, characterized in that: The first micro-nano metal wire and the second micro-nano metal wire are both micro-nano copper whiskers; the specific steps of attaching the second platform portion of the heat dissipation cover to the top surface of the substrate with the second micro-nano metal layer facing the first micro-nano metal layer, and pressing the first platform portion to the back side of the chip include: The second platform portion of the heat dissipation cover is mounted on the top surface of the substrate in a reducing atmosphere with the second micro-nano metal layer facing the first micro-nano metal layer, and the first platform portion is pressed onto the back surface of the chip.

Images