Semiconductor packaging structure and manufacturing method thereof

Abstract

The invention provides a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure includes a first package, an interposer, and a second package. The first package includes a substrate, a plurality of bonding components, and a sealing body. The plurality of joint assemblies are arranged on the substrate. Each joint assembly comprises a conductive column and a first conductive terminal, and a first distance is arranged between the adjacent conductive columns. The sealing body encloses the plurality of engagement assemblies. The interposer is disposed on the first package. The second package is disposed on the interposer and includes a plurality of second conductive terminals. The second conductive terminals have a second pitch greater than the first pitch, and the first package is electrically connected to the second package through the interposer.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor packaging technology is continuously improving in an attempt to develop more competitive products. For example, 3D stacking technologies such as PoP packaging have been developed. However, due to limitations such as ball implantation capabilities, the pitch cannot be effectively reduced, and thus cannot meet the requirements of higher packaging density. Summary of the invention

[0003] The present invention provides a semiconductor packaging structure and a manufacturing method thereof, which can meet the requirements of higher packaging density.

[0004] A semiconductor packaging structure of the present invention includes a first package, an interposer and a second package. The first package includes a substrate, a plurality of bonding components and a sealing body. The plurality of bonding components are arranged on the substrate. Each bonding component includes a conductive column and a first conductive terminal, and a first spacing is provided between adjacent conductive columns. The sealing body encapsulates the plurality of bonding components. The interposer is arranged on the first package. The second package is arranged on the interposer and includes a plurality of second conductive terminals. There is a second spacing between the second conductive terminals that is greater than the first spacing, and the first package is electrically connected to the second package through the interposer.

[0005] In one embodiment of the present invention, the plurality of joint components are recessed in the sealing body.

[0006] In one embodiment of the present invention, the intermediate component comprises a plurality of intermediate conductive terminals, wherein the intermediate conductive terminals extend into the sealing body and directly contact the first conductive terminals to form a bonding interface, and the bonding interface is lower than the top surface of the sealing body.

[0007] In one embodiment of the present invention, the height of the sealing body is greater than the height of each joining component.

[0008] In one embodiment of the present invention, the first package further comprises a chip, the chip is disposed on the substrate, and the sealing body encapsulates the chip and has a gap with the substrate of the interposer.

[0009] In one embodiment of the present invention, the chip includes a plurality of conductive bumps, and a portion of the sealing body fills the space between the plurality of conductive bumps.

[0010] In one embodiment of the present invention, the size of the interposer is smaller than that of the substrate.

[0011] In one embodiment of the present invention, the intermediary member includes a plurality of separated intermediary units, and a portion of the sealing body is filled between two adjacent intermediary units.

[0012] A method for manufacturing a semiconductor package structure of the present invention includes at least the following steps: forming a plurality of bonding components on a substrate, wherein each bonding component includes a conductive column and a first conductive terminal, and a first spacing is provided between adjacent conductive columns; forming a sealing body to encapsulate the plurality of bonding components; forming a plurality of openings in the sealing body to expose the plurality of bonding components to form a first package; bonding an interposer to the first package; and bonding a second package to the interposer, wherein the second package includes a plurality of second conductive terminals, and a second spacing greater than the first spacing is provided between adjacent second conductive terminals, and the first package is electrically connected to the second package through the interposer.

[0013] In an embodiment of the present invention, the method for manufacturing the semiconductor package structure further includes performing a laser drilling process to form a plurality of openings.

[0014] Based on the above, the bottom package of the semiconductor packaging structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I / O terminals of the semiconductor packaging structure, thereby meeting the requirements of higher packaging density.

[0015] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1F is a partial cross-sectional schematic diagram of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention;

[0017] Figure 2 According to some embodiments of the present invention, Figure 1D A partial top view schematic diagram of the stage;

[0018] Figure 3 , Figure 4 According to some embodiments of the present invention, Figure 1E Schematic diagram of a partial top view of the stage. DETAILED DESCRIPTION

[0019] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings may be exaggerated for clarity, and some components may be omitted for clarity of discussion. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0020] The directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings shown and are not intended to imply an absolute orientation.

[0021] The term "between" used in this specification to define a numerical range is intended to cover a range equal to the endpoint value and between the endpoint values. For example, a size range between a first value and a second value means that the size range can cover the first value, the second value, and any value between the first value and the second value.

[0022] Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0023] Figures 1A to 1F FIG. 4 is a partial cross-sectional schematic diagram of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Figure 2 According to some embodiments of the present invention, Figure 1D Schematic diagram of a partial top view of the stage. Figure 3 , Figure 4 According to some embodiments of the present invention, Figure 1E Schematic diagram of a partial top view of the stage.

[0024] Please refer to Figure 1A In this embodiment, the manufacturing process of the semiconductor package structure may include the following steps. First, a substrate 110 is provided, wherein the substrate 110 has a top surface 110t and a bottom surface 110b opposite to each other. Next, a plurality of bonding components 120 may be formed on the top surface 110t of the substrate 110, wherein each bonding component 120 includes a conductive column 121 and a conductive terminal 122 (which may be regarded as a first conductive terminal), and there is a spacing 121p (which may be regarded as a first spacing) between adjacent conductive columns 121. Here, the spacing 121p may be formed by the center point between adjacent conductive columns 121, and since the conductive columns 121 are formed using a fine process (made by photomask exposure followed by electroplating, and the accuracy of the photomask can provide a finer spacing), the spacing 121p is a fine pitch. For example, the spacing 121p may be at least less than 200 microns, but the present invention is not limited thereto, and the spacing may also have other suitable definition methods.

[0025] In some embodiments, the substrate 110 may be a circuit substrate including a circuit 111, a protective layer 112 and a conductive pad 113. For example, the substrate 110 is a plate made of an organic material or an inorganic material in which a circuit 111 is formed and a conductive pad 113 and a protective layer 112 electrically isolating the conductive pad 113 are formed on the opposite surface of the plate. The circuit 111 and the conductive pad 113 may be formed by, for example, aluminum, copper, tin, nickel, gold, silver or other suitable conductive materials, and the protective layer 112 may be formed by green paint or other suitable insulating materials. However, the present invention is not limited thereto and the substrate 110 may also be other suitable types of substrates.

[0026] In some embodiments, the conductive column 121 and the conductive terminal 122 are disposed on the conductive pad 113 and electrically connected to the substrate 110, and the conductive column 121 is a copper column (Cu post) made by an electroplating method, and the conductive terminal 122 is a solder formed by solder paste printing, micro-ball drop or electroplating, but the present invention is not limited thereto, and the conductive column 121 and the conductive terminal 122 can also be formed by other suitable conductive materials and deposition processes.

[0027] Please refer to Figure 1B , a chip 130 may be disposed on the top surface 110t of the substrate 110, and in the present embodiment, the chip 130 is electrically connected to the substrate 110 by a flip chip bonding technique through a plurality of bumps 131, such as the active surface 130a of the chip 130 faces the substrate 110, but the present invention is not limited thereto, and in an embodiment not shown, the chip may also be electrically connected to the substrate 110 by wire bonding, such as the active surface of the chip faces away from the substrate. In addition, although Figure 1A and Figure 1B It is shown that a plurality of bonding components 120 are formed first and then the chip 130 is formed, but the present invention is not limited thereto. In an embodiment not shown, the chip may be formed first and then the plurality of bonding components may be formed.

[0028] Please refer to Figure 1C , forming a sealing body 140 to encapsulate the bonding component 120 and the chip 130, wherein the height 140T of the sealing body 140 is greater than the height 120T of the bonding component 120. For example, the top surface 140t of the sealing body 140 can be higher than the top surface 122t of the conductive terminal 122 in the bonding component 120. In other words, the conductive terminal 122 can be located below the horizontal extension plane of the top surface 140t of the sealing body 140, but the present invention is not limited to this.

[0029] In some embodiments, part of the sealant 140 fills the space between the conductive bumps 131 , thereby replacing the underfill process to provide good electrical isolation between the conductive bumps 131 . This can effectively simplify the process and reduce manufacturing costs, but the present invention is not limited thereto.

[0030] In some embodiments, the top surface 140 t of the encapsulant 140 has a distance greater than zero from the back surface of the chip 130 , that is, the back surface of the chip 130 is covered by the encapsulant 140 and is not exposed, but the invention is not limited thereto.

[0031] In some embodiments, the sealing body 140 is formed of insulating materials such as epoxy resin or other suitable resins, and is, for example, a molding compound formed by a molding process. However, the present invention is not limited thereto, and the sealing body 140 may be formed by other suitable materials and methods.

[0032] Please refer to Figure 1D A plurality of openings 141 exposing a plurality of bonding components 120 are formed in the sealing body 140 to form a package 100 (which can be regarded as a first package). Therefore, the bonding components 120 can be recessed in the sealing body 140. In this way, the sealing body 140 can support the conductive pillar 121 to reduce the stress on the conductive pillar 121 and reduce the probability of the conductive pillar 121 breaking during the subsequent bonding process of the interposer 300, but the present invention is not limited to this.

[0033] In this embodiment, the opening 141 exposes a portion of the conductive pillar 121 and the conductive terminal 122 and the width of the bottom of the opening 141 is greater than the width of the conductive pillar 121 , but the present invention is not limited thereto. In an embodiment not shown, the opening may only expose the conductive terminal.

[0034] In some embodiments, the opening 141 is formed by laser drilling, so that in cross-section, the opening 141 has a conical shape (the top width is greater than the bottom width), and the bottom of the opening 141 can be lower than the conductive terminal 122 to effectively expose the conductive terminal 122, but the present invention is not limited thereto, and the opening 141 can also be formed by other suitable processes.

[0035] In some embodiments, in order to simplify the process, the conductive terminal 122 is formed before the opening 141, so the conductive terminal 122 may not fill the opening 141 and does not extend to the top surface 140t of the sealing body 140. In addition, the joint position of other components and the conductive terminal 122 is limited to the opening 141, but the present invention is not limited thereto.

[0036] In some embodiments, the bonding components 120 are located on two sides of the sealing body 140. In other words, the bonding components 120 are not disposed on four sides of the sealing body 140 at the same time. Figure 2 As shown, the present invention is not limited thereto.

[0037] Please refer to Figure 1E , the interposer 300 is bonded to the package 100, wherein the interposer 300 includes a substrate 310 and interposer components 320, and each interposer component 320 includes a conductive pillar 321 and a conductive terminal 322 (which can be regarded as an interposer conductive terminal). In addition, the interposer component 320 is in direct contact with the bonding component 120, so that the interposer 300 is electrically connected to the package 100.

[0038] In some embodiments, substrate 310 is similar to substrate 110, so substrate 310 can be a circuit substrate including circuit 311, protective layer 312 and conductive pad 313. For example, substrate 310 is a plate made of organic material or inorganic material, in which circuit 311 is formed, and conductive pad 313 and protective layer 312 electrically isolating conductive pad 313 are formed on the opposite surface thereof, wherein circuit 311 and conductive pad 313 can be formed by aluminum, copper, tin, nickel, gold, silver or other suitable conductive materials, and protective layer 312 is formed by green paint or other suitable insulating materials, but the present invention is not limited to this, and substrate 310 can also be other suitable types of substrates.

[0039] In some embodiments, the conductive column 321 and the conductive terminal 322 are disposed on the conductive pad 313 and electrically connected to the substrate 310, and the intermediate component 320 is similar to the bonding component 120, so the conductive column 321 is a copper column made by an electroplating method, and the conductive terminal 322 is a solder formed by solder paste printing, micro-balling or electroplating, but the present invention is not limited to this, and the conductive column 321 and the conductive terminal 322 can also be formed by other suitable conductive materials and deposition processes.

[0040] In some embodiments, when the conductive terminals 322 and the conductive terminals 122 are solder, a reflow process can be performed on the conductive terminals 322 and the conductive terminals 122 in the openings 141, so that the interposer 300 is electrically connected to the package 100. In addition, when the openings 141 are formed by a laser drilling process, a larger accommodation space can be formed, so the amount of solder used for the conductive terminals 122 and the conductive terminals 322 can be increased. In this way, after the reflow process, the non-wetting problem caused by the warping between the package 100 and the interposer 300 can be reduced, thereby improving the product quality, but the present invention is not limited thereto.

[0041] In some embodiments, after the interposer 300 is joined to the package 100, the conductive terminals 122 and the conductive terminals 322 are not respectively covered on the sidewalls of the conductive pillars 121 and the conductive pillars 321. In other words, the conductive terminals 122 and the conductive terminals 322 are respectively located only on the top surfaces of the conductive pillars 121 and the conductive pillars 321, so as to effectively avoid the risk of short circuits (shorts) caused by the overflow of the conductive material in the horizontal direction, thereby increasing product reliability. However, the present invention is not limited thereto. In embodiments not shown, the conductive terminals may be covered on the sidewalls of the conductive pillars and may optionally contact the sealing body. It should be noted that in any of the aforementioned embodiments, the conductive terminals 122 and the conductive terminals 322 will only flow in the openings 141, and will not overflow onto the top surface 140t of the sealing body 140.

[0042] In this embodiment, adjacent openings 141 are separated to prevent solder from horizontally overflowing to the tops of adjacent openings 141, thereby effectively preventing short circuits from occurring. However, the present invention is not limited thereto. In embodiments not shown, the tops of adjacent openings may be connected together (such as overlapping tops), so that adjacent conductive terminals may be considered to be exposed by the same opening.

[0043] In some embodiments, the conductive terminal 322 extends into the sealing body 140 to directly contact the conductive terminal 122 and form a bonding interface, and the bonding interface is lower than the top surface 140 t of the sealing body 140 , but the present invention is not limited thereto.

[0044] In some embodiments, a gap G is provided between the sealing body 140 and the substrate 310 of the interposer 300 . For example, the substrate 310 of the interposer 300 and the sealing body 140 may not be in direct contact with each other, but the present invention is not limited thereto.

[0045] In some embodiments, Figure 1E and Figure 3 As shown, the size of the interposer 300 is smaller than that of the substrate 110 , so the interposer 300 exposes the edge of the sealing body 140 , and the interposer 300 is a single component, but the present invention is not limited thereto.

[0046] In some embodiments, Figure 4 As shown, the interposer 300 includes a plurality of separated interposer units 300u, and a portion of the sealing body 140 is filled between two adjacent interposer units 300u, so that the stress on the conductive pillar 121 can be reduced, but the present invention is not limited thereto. Figure 4 Two intermediate units 300u are schematically shown in the figure, but the present invention does not limit the number of intermediate units 300u, which can be determined according to actual design requirements.

[0047] In some embodiments, multiple intermediate units 300u include cutting lanes (not shown), so after joining the intermediate component 300 to the package 100, a singulation process can be performed first, wherein the singulation process is, for example, cutting with a rotating blade or a laser beam to form multiple discrete intermediate units 300u and corresponding packages 100, but the present invention is not limited to this.

[0048] In some embodiments, the interposer 300 does not include a function die. In other words, it has a circuit fan-out function. Therefore, the thickness of the interposer 300 can be effectively reduced. The thickness range can be determined according to actual design requirements and is not limited by the present invention.

[0049] Please refer to Figure 1F , the package 200 (which can be regarded as the second package) is bonded to the interposer 300 to form a stacked semiconductor package structure 10 (which can be referred to as a PoP structure), wherein the package 200 includes a plurality of conductive terminals 220 (which can be regarded as the second conductive terminals), and there is a pitch 220p (which can be regarded as the second pitch) between adjacent conductive terminals 220 that is greater than the pitch 121p, and the package 100 can be electrically connected to the package 200 through the interposer 300. Here, the pitch 220p is formed by the center points between adjacent conductive terminals 220, and the pitch 220p can be at least greater than 400 microns, but the present invention is not limited thereto.

[0050] Accordingly, the bottom package 100 of the semiconductor package structure 10 of the present embodiment can effectively reduce the pitch through the design of the conductive pillar 121, and through the introduction of the interposer 300, the bottom package 100 with a fine pitch can be fanned out to the top package 200 with a coarse pitch, so as to increase the number of I / O terminals of the semiconductor package structure 10, thereby meeting the requirements of higher packaging density.

[0051] In some embodiments, the conductive terminal 220 may be a solder ball formed by a ball placement process, but the present invention is not limited thereto. Based on design requirements, the conductive terminal 220 may have other possible forms and shapes.

[0052] In some embodiments, other components of the package 200 have a similar formation structure to the package 100. For example, the package 200 includes a substrate 210, a chip 230 and a sealing body 240, wherein the substrate 210, the chip 230 and the sealing body 240 are similar to the substrate 110, the chip 130 and the sealing body 140, and are not repeated here.

[0053] It should be noted that package 100 and package 200 can be configured with other components according to actual design requirements, and chip 130 and chip 230 can select appropriate chip types according to actual design requirements, for example, chip 130 is an application-specific integrated circuit (ASIC) or the like and chip 230 is a dynamic random access memory (DRAM) or a NAND flash memory or the like, or it can also be the same application-specific integrated circuit (ASIC) as chip 130 or the like.

[0054] In some embodiments, the semiconductor package structure 10 also includes a conductive terminal 400 to further electrically connect to other semiconductor elements (not shown), wherein the conductive terminal 400 can be a solder ball formed by a ball implantation process or can have other possible forms and shapes based on design requirements, and the present invention is not limited thereto.

[0055] In summary, the bottom package of the semiconductor packaging structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I / O terminals of the semiconductor packaging structure, thereby meeting the requirements of higher packaging density.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first package comprises: substrate; A plurality of bonding components are disposed on the substrate, wherein each of the bonding components comprises a conductive column and a first conductive terminal, and adjacent conductive columns have a first spacing therebetween; and a sealing body encapsulating the plurality of engagement components; an interposer, disposed on the first package; and The second package is disposed on the interposer and includes a plurality of second conductive terminals, wherein adjacent second conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package through the interposer.

2. The semiconductor package structure according to claim 1, wherein: The plurality of engagement components are recessed within the sealing body.

3. The semiconductor package structure according to claim 1, wherein: The intermediate component includes a plurality of intermediate conductive terminals, wherein the intermediate conductive terminals extend into the sealing body and directly contact the first conductive terminals to form a bonding interface, and the bonding interface is lower than a top surface of the sealing body.

4. The semiconductor package structure according to claim 1, wherein: The height of the sealing body is greater than the height of each of the joining components.

5. The semiconductor package structure according to claim 1, wherein: The first package further includes a chip, wherein the chip is disposed on the substrate, and the sealing body encapsulates the chip and has a gap with the substrate of the interposer.

6. The semiconductor package structure according to claim 5, characterized in that: The chip includes a plurality of conductive bumps, and a portion of the sealing body fills the space between the plurality of conductive bumps.

7. The semiconductor package structure according to claim 1, wherein: The size of the intermediate member is smaller than that of the substrate.

8. The semiconductor package structure according to claim 1, wherein: The intermediary member includes a plurality of separated intermediary units, and a portion of the sealing body is filled between two adjacent ones of the plurality of intermediary units.

9. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Forming a plurality of bonding components on the substrate, wherein each of the bonding components comprises a conductive column and a first conductive terminal, and adjacent conductive columns have a first spacing therebetween; forming a sealing body to enclose the plurality of engagement components; forming a plurality of openings in the sealing body to expose the plurality of bonding components, so as to form a first package; bonding an interposer to the first package; as well as A second package is bonded to the interposer, wherein the second package comprises a plurality of second conductive terminals, adjacent second conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package through the interposer.

10. The method for manufacturing a semiconductor package structure according to claim 9, wherein: Also included is performing a laser drilling process to form the plurality of openings.

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