Semiconductor packaging structure and manufacturing method thereof

Abstract

A semiconductor package structure includes a first package and a second package. The first package includes a substrate, a plurality of conductive pillars, an interposer, and an encapsulant. The plurality of conductive columns are arranged on the substrate. A first distance is arranged between the adjacent conductive columns. The interposer is disposed on the plurality of conductive pillars. The encapsulant encapsulates the interposer and the plurality of conductive pillars. The second package is disposed on the first package and includes a plurality of conductive terminals. A second pitch greater than the first pitch is formed between adjacent conductive terminals, and the first package is electrically connected to the second package through the interposer. The invention also provides a manufacturing method of the semiconductor packaging structure.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor packaging technology is continuously improving in an attempt to develop more competitive products. For example, 3D stacking technologies such as PoP packaging have been developed. However, due to limitations such as ball implantation capabilities, the pitch cannot be effectively reduced, and thus cannot meet the requirements of higher packaging density. Summary of the invention

[0003] The present invention provides a semiconductor packaging structure and a manufacturing method thereof, which can meet the requirements of higher packaging density.

[0004] A semiconductor package structure of the present invention includes a first package and a second package. The first package includes a substrate, a plurality of conductive pillars, an interposer and a sealing body. The plurality of conductive pillars are arranged on the substrate. There is a first spacing between adjacent conductive pillars. The interposer is arranged on the plurality of conductive pillars. The sealing body encapsulates the interposer and the plurality of conductive pillars. The second package is arranged on the first package and includes a plurality of conductive terminals. There is a second spacing between adjacent conductive terminals that is greater than the first spacing, and the first package is electrically connected to the second package through the interposer.

[0005] In one embodiment of the present invention, the sealing body fills up the space between the interposer and the substrate.

[0006] In one embodiment of the present invention, the sealing body extends from the top surface of the interposer to the top surface of the substrate.

[0007] In an embodiment of the present invention, the interposer comprises a plurality of bonding terminals, and the sealing body covers the side walls of the plurality of bonding terminals and the side walls of the plurality of conductive pillars.

[0008] In one embodiment of the present invention, the top surface of the sealing body is coplanar with the top surface of the intermediate member.

[0009] In one embodiment of the present invention, the intermediate member is retracted into the sealing body.

[0010] In one embodiment of the present invention, the size of the interposer is smaller than that of the substrate.

[0011] In one embodiment of the present invention, the intermediary member includes a plurality of separated intermediary units, and a portion of the sealing body is filled between two adjacent intermediary units.

[0012] A method for manufacturing a semiconductor package structure of the present invention includes at least the following steps: forming a plurality of conductive pillars on a substrate, wherein adjacent conductive pillars have a first spacing; bonding an interposer to the plurality of conductive pillars; forming a sealing body to encapsulate the interposer and the plurality of conductive pillars to form a first package; and bonding a second package to the interposer, wherein the second package includes a plurality of conductive terminals, adjacent conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package through the interposer.

[0013] In one embodiment of the present invention, a singulation process is performed between forming the sealing body and bonding the second package.

[0014] Based on the above, the bottom package of the semiconductor packaging structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I / O terminals of the semiconductor packaging structure, thereby meeting the requirements of higher packaging density.

[0015] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1D is a partial cross-sectional schematic diagram of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention;

[0017] Figure 2 According to some embodiments of the present invention, Figure 1A A partial top view schematic diagram of the stage;

[0018] Figure 3 According to some embodiments of the present invention, Figure 1B A partial top view schematic diagram of the stage;

[0019] Figure 4 , Figure 5 According to some embodiments of the present invention, Figure 1C A partial top view schematic diagram of the stage; DETAILED DESCRIPTION

[0020] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings may be exaggerated for clarity, and some components may be omitted for clarity of discussion. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0021] The directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings shown and are not intended to imply an absolute orientation.

[0022] The term "between" used in this specification to define a numerical range is intended to cover a range equal to the endpoint value and between the endpoint values. For example, a size range between a first numerical value and a second numerical value means that the size range can cover the first numerical value, the second numerical value and any numerical value between the first numerical value and the second numerical value.

[0023] Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0024] Figures 1A to 1D FIG. 4 is a partial cross-sectional schematic diagram of a partial manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Figure 2 According to some embodiments of the present invention, Figure 1A Schematic diagram of a partial top view of the stage. Figure 3 According to some embodiments of the present invention, Figure 1B Schematic diagram of a partial top view of the stage. Figure 4 , Figure 5 According to some embodiments of the present invention, Figure 1C Schematic diagram of a partial top view of the stage.

[0025] Please refer to Figure 1A In this embodiment, the manufacturing process of the semiconductor package structure may include the following steps. First, a substrate 110 is provided, wherein the substrate 110 has a top surface 110t and a bottom surface 110b opposite to each other. Next, a plurality of conductive pillars 120 may be formed on the top surface 110t of the substrate 110, and a spacing 120p (which may be regarded as a first spacing) may be provided between adjacent conductive pillars 120. Here, the spacing 120p may be formed by the center points between adjacent conductive pillars 120, and since the conductive pillars 120 are formed using a fine process (made by electroplating after photomask exposure, and the accuracy of the photomask can indeed provide a finer spacing), the spacing 120p is a fine pitch. For example, the spacing 120p may be at least less than 200 microns, but the present invention is not limited thereto, and the spacing may also have other suitable definitions.

[0026] In addition, if Figure 1A As shown, a chip 130 may be disposed on the top surface 110t of the substrate 110. According to actual design requirements, in some embodiments, the conductive pillar 120 is formed first and then the chip 130 is disposed, while in other embodiments, the chip 130 is disposed first and then the conductive pillar 120 is formed.

[0027] In some embodiments, the substrate 110 may be a circuit substrate including a circuit 111, a protective layer 112 and a conductive pad 113. For example, the substrate 110 is a plate made of an organic material or an inorganic material in which a circuit 111 is formed and a conductive pad 113 and a protective layer 112 electrically isolating the conductive pad 113 are formed on the opposite surface of the plate. The circuit 111 and the conductive pad 113 may be formed by, for example, aluminum, copper, tin, nickel, gold, silver or other suitable conductive materials, and the protective layer 112 may be formed by green paint or other suitable insulating materials. However, the present invention is not limited thereto and the substrate 110 may also be other suitable types of substrates.

[0028] In some embodiments, the conductive post 120 is disposed on the conductive pad 113 and electrically connected to the substrate 110, and the conductive post 120 is a copper post (Cu post) made by an electroplating method, but the present invention is not limited thereto, and the conductive post 120 can also be formed by other suitable conductive materials and deposition processes.

[0029] On the other hand, in this embodiment, the chip 130 is electrically connected to the substrate 110 through multiple bumps 131 using flip chip bonding technology, such as the active surface 130a of the chip 130 faces the substrate 110, but the present invention is not limited to this. In an embodiment not shown, the chip can also be electrically connected to the substrate 110 by wire bonding, such as the active surface of the chip is facing away from the substrate.

[0030] Please refer to Figure 1B , the interposer 300 is joined to a plurality of conductive pillars 120, wherein the interposer 300 may include a substrate 310 and a joining terminal 320, and the joining terminal 320 is in direct contact with the conductive pillars 120, so that the conductive pillars 120 may become an electrical connection path between the interposer and the substrate 110 to achieve electrical conduction in the stacking direction, but the present invention is not limited thereto.

[0031] In some embodiments, substrate 310 is similar to substrate 110, so substrate 310 can be a circuit substrate including circuit 311, protective layer 312 and conductive pad 313. For example, substrate 310 is a plate made of organic material or inorganic material, in which circuit 311 is formed, and conductive pad 313 and protective layer 312 electrically isolating conductive pad 313 are formed on the opposite surface thereof, wherein circuit 311 and conductive pad 313 can be formed by aluminum, copper, tin, nickel, gold, silver or other suitable conductive materials, and protective layer 312 is formed by green paint or other suitable insulating materials, but the present invention is not limited to this, and substrate 310 can also be other suitable types of substrates.

[0032] In some embodiments, the portion of the circuit 311 that overlaps with the conductive pillar 120 in the orthographic projection direction includes a plated through hole (PTH), wherein the plated through hole is an electroplated layer formed in a through hole in the substrate 310. Since the plated through hole can also be made using a fine process, such as laser penetrating the base material of the interposer 300 and then electroplating, it can correspond to the fine pitch of the conductive pillar 120 through the precision of the laser. In addition, a suitable resin material 314 can be optionally formed in the aforementioned through hole to further improve the electrical performance, but the present invention is not limited thereto.

[0033] In some embodiments, the connection terminal 320 is solder formed by solder paste printing, micro ball dropping or electroplating, but the present invention is not limited thereto. The connection terminal 320 may also be formed by other suitable conductive materials and deposition processes.

[0034] In some embodiments, when the bonding terminal 320 is solder, the interposer 300 can be electrically connected to the plurality of conductive pillars 120 by performing a reflow process on the bonding terminal 320, wherein after the reflow process, the bonding terminal 320 can be coated onto the sidewalls of the conductive pillars 120 to increase adhesion and improve bonding quality, but the present invention is not limited thereto. It should be noted that in this step, if Figure 1C The sealing body 140 shown has not been formed yet, so during the reflow process, the interposer 300 may be supported only by the conductive pillars 120 .

[0035] In some embodiments, the interposer 300 does not include a function die. In other words, the interposer 300 only has a circuit fan-out function. Therefore, the thickness of the interposer 300 can be effectively reduced. The thickness range can be determined according to actual design requirements and is not limited by the present invention.

[0036] Please refer to Figure 1C , a sealing body 140 is formed to encapsulate the interposer 300, the chip 130, and the plurality of conductive pillars 120 to form a package 100 (which can be regarded as a first package), wherein the sealing body 140, for example, extends from the side wall 300a of the interposer 300 to the top surface 110t of the substrate 110 to completely encapsulate the components on the top surface 110t of the substrate 110, but the present invention is not limited thereto.

[0037] In some embodiments, the seal 140 is formed of insulating materials such as epoxy resin or other suitable resins. For example, the seal 140 is a molding compound formed by a molding process, and the molding process is performed after the conductive pillar 120 is bonded to the interposer 300. At this time, the conductive pillar 120 and the interposer 300 have been electrically connected. Therefore, it is not necessary to perform steps such as Through Mold Via (TMV) on the seal 140 in order to expose the conductive pillar for electrical connection. Therefore, the cost of performing steps such as Through Mold Via (TMV) can be reduced (such as the loss of the conductive pillar due to excessive laser power melting and shorting), thereby effectively reducing the manufacturing cost. Compared with V-shaped molded vias, the conductive pillar 120 can meet the requirements of fine pitch.

[0038] In some embodiments, part of the sealant 140 fills the space between the conductive bumps 131 , thereby replacing the underfill process to provide good electrical isolation between the conductive bumps 131 . This can more effectively simplify the process and reduce manufacturing costs, but the present invention is not limited thereto.

[0039] In some embodiments, the sealing body 140 may fill up the space between the interposer 300 and the substrate 110 . In other words, there is no gap between the interposer 300 and the substrate 110 , but the present invention is not limited thereto.

[0040] In some embodiments, the sealing body 140 covers the sidewalls 320s of the connecting terminal 320 and the sidewalls 120s of the connecting member 120 , so that the interposer 300 can be embedded in the sealing body 140 to be more completely protected and improve product reliability, but the present invention is not limited thereto.

[0041] In some embodiments, the top surface 140 t of the sealing body 140 and the top surface 300 t of the interposer 300 are substantially coplanar, that is, the top surface 140 t of the sealing body 140 and the top surface 300 t of the interposer 300 are located on the same horizontal plane, but the invention is not limited thereto.

[0042] In some embodiments, the intermediate member 300 is retracted into the sealing body 140, for example, Figures 2 to 4 As shown, the size of the interposer 300 is smaller than the size of the substrate 110 (the interposer 300 is, for example, Figure 3 ), so the interposer 300 will expose the edge of the substrate 110 to form a channel, and the sealing body 140 can flow into the space between the interposer 300 and the substrate 110 through the aforementioned channel, and the interposer 300 is a single component, but the present invention is not limited thereto. In other embodiments, such as Figure 5As shown, the interposer 300 includes a plurality of separated interposer units 300u, and a portion of the sealing body 140 is filled between two adjacent interposer units 300u, so that the stress on the conductive pillar 120 can be reduced, but the present invention is not limited thereto. Figure 5 Two intermediate units 300u are schematically shown in the figure, but the present invention does not limit the number of intermediate units 300u, which can be determined according to actual design requirements.

[0043] In some embodiments, a plurality of interposer units 300u include scribe lines (not shown) between them, so that after the interposer 300 is bonded (bonded Figure 1D Before the package 200 is formed, a singulation process may be performed, wherein the singulation process is performed by, for example, cutting with a rotating blade or a laser beam to form a plurality of discrete interposers 300u and corresponding packages 100, but the present invention is not limited thereto.

[0044] Please refer to Figure 1D , the package 200 (which can be regarded as a second package) is bonded to the interposer 300 to form a stacked semiconductor package structure 10 (which can be regarded as a PoP structure), wherein the package 200 includes a plurality of conductive terminals 220, and there is a pitch 220p (which can be regarded as a second pitch) between adjacent conductive terminals 220, which is greater than the pitch 120p, and the package 100 can be electrically connected to the package 200 through the interposer 300. Here, the pitch 220p is formed by the center points between adjacent conductive terminals 220, and the pitch 220p can be at least greater than 400 microns, but the present invention is not limited thereto, and the pitch can also have other suitable definition methods.

[0045] Accordingly, the bottom package 100 of the semiconductor package structure 10 of the present embodiment can effectively reduce the pitch through the design of the conductive pillar 121, and through the introduction of the interposer 300, the bottom package 100 with a fine pitch can be fanned out to the top package 200 with a coarse pitch, so as to increase the number of I / O terminals of the semiconductor package structure 10, thereby meeting the requirements of higher packaging density.

[0046] In some embodiments, the conductive terminal 220 may be a solder ball formed by a ball placement process, but the present invention is not limited thereto. Based on design requirements, the conductive terminal 220 may have other possible forms and shapes.

[0047] In some embodiments, other components of the package 200 have a similar formation structure to the package 100. For example, the package 200 also includes a substrate 210, a chip 230 and a sealing body 240, wherein the substrate 210, the chip 230 and the sealing body 240 are similar to the substrate 110, the chip 130 and the sealing body 140, and are not repeated here.

[0048] It should be noted that package 100 and package 200 can be configured with other components according to actual design requirements, and chip 130 and chip 230 can select appropriate chip types according to actual design requirements, for example, chip 130 is an application-specific integrated circuit (ASIC) or the like, and chip 230 is a dynamic random access memory (DRAM) or a NAND flash memory or the like, or it can also be the same application-specific integrated circuit (ASIC) as chip 130 or the like.

[0049] In some embodiments, before or after joining the package 200, a conductive terminal 400 is formed on the bottom surface 110b of the substrate 110 to further electrically connect with other semiconductor elements (not shown), wherein the conductive terminal 400 can be a solder ball formed by a ball implantation process or can have other possible forms and shapes based on design requirements, and the present invention is not limited thereto.

[0050] In summary, the bottom package of the semiconductor packaging structure of the present invention can effectively reduce the pitch through the design of the conductive column, and through the introduction of the interposer, the bottom package with a fine pitch can be fanned out to the top package with a coarse pitch to increase the number of I / O terminals of the semiconductor packaging structure, thereby meeting the requirements of higher packaging density.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first package comprises: substrate; A plurality of conductive pillars are disposed on the substrate, wherein adjacent conductive pillars have a first spacing therebetween; an interposer disposed on the plurality of conductive pillars; and a sealing body encapsulating the interposer and the plurality of conductive pillars; and The second package is disposed on the first package and includes a plurality of conductive terminals, wherein a second spacing greater than the first spacing exists between adjacent conductive terminals, and the first package is electrically connected to the second package through the interposer.

2. The semiconductor package structure according to claim 1, wherein: The sealing body fills the space between the intermediate component and the substrate.

3. The semiconductor package structure according to claim 1, wherein: The sealing body extends from the side wall of the intermediate component to the top surface of the substrate.

4. The semiconductor package structure according to claim 1, wherein: The interposer includes a plurality of bonding terminals, and the sealing body covers side walls of the plurality of bonding terminals and side walls of the plurality of conductive pillars.

5. The semiconductor package structure according to claim 1, wherein: A top surface of the sealing body is coplanar with a top surface of the intermediate member.

6. The semiconductor package structure according to claim 1, wherein: The intermediate member is retracted into the sealing body.

7. The semiconductor package structure according to claim 1, wherein: The size of the intermediate member is smaller than that of the substrate.

8. The semiconductor package structure according to claim 1, wherein: The intermediary member includes a plurality of separated intermediary units, and a portion of the sealing body is filled between two adjacent ones of the plurality of intermediary units.

9. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Forming a plurality of conductive pillars on a substrate, wherein adjacent conductive pillars have a first spacing therebetween; bonding an interposer to the plurality of conductive pillars; forming a sealing body to encapsulate the interposer and the plurality of conductive pillars to form a first package; as well as A second package is bonded to the interposer, wherein the second package comprises a plurality of conductive terminals, adjacent conductive terminals have a second spacing greater than the first spacing, and the first package is electrically connected to the second package through the interposer.

10. The method for manufacturing a semiconductor package structure according to claim 9, wherein: A singulation process is performed between forming the sealing body and bonding the second package.

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