Semiconductor package

Abstract

The present disclosure provides a semiconductor package including: a first substrate including a first insulating layer and a first wiring layer disposed on and / or in the first insulating layer; a first package and a second package disposed on the first substrate and each including a substrate, a semiconductor chip on the substrate, a connection member connecting the substrate to the semiconductor chip, and a SERDES chip embedded in the substrate; a 1-1 connection member that connects the first substrate to the first package; and a 2-1 connection member that connects the first substrate to the second package. The number of the connecting members of the first package is greater than the number of the 1-1 connecting members. The number of the connecting members of the second package is greater than the number of the 2-1 connecting members.

Description

[0001] This application claims the benefit of priority to U.S. patent application No. 18 / 379,304, filed in the U.S. Patent and Trademark Office on October 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor package. Background Art

[0003] Memory chips such as high bandwidth memory (HBM) and multi-chip packages including processor chips such as central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs) have been used to process data that has grown exponentially due to the recent development of artificial intelligence (AI) technology. In addition, as the number of CPU and GPU cores in server products has increased rapidly, die-split technology, which can effectively increase the number of cores, has been widely used, and the demand for high-density circuits connecting logic semiconductors and memory semiconductors or connecting logic semiconductors has also increased rapidly, and the demand for die-to-die interconnections that connect components has also increased. In order to design a substrate for performing die-to-die interconnections, a technology for realizing fine circuits is necessary, and research has been conducted on substrates and package structures that promote simplification to reduce high-density microcircuits and improve yields while improving the reliability of connection structures. Summary of the invention

[0004] An aspect of the present disclosure is to provide a semiconductor package which can perform chip-to-chip interconnection in a package including a semiconductor chip.

[0005] Another aspect of the present disclosure is to provide a semiconductor package including a simplified wiring structure in chip-to-chip interconnection.

[0006] Another aspect of the present disclosure is to provide a semiconductor package that can improve reliability.

[0007] According to one aspect of the present disclosure, a semiconductor package includes: a first substrate including a first insulating layer and a first wiring layer disposed on and / or in the first insulating layer; a first package disposed on the first substrate and including a second substrate, a first semiconductor chip disposed on the second substrate, a first connecting member connecting the second substrate to the first semiconductor chip, and a first SERDES chip embedded in the second substrate; a second package disposed on the first substrate and including a third substrate, a second semiconductor chip disposed on the third substrate, a second connecting member connecting the third substrate to the second semiconductor chip, and a second SERDES chip embedded in the third substrate; a 1-1 connecting member connecting the first substrate to the first package; and a 2-1 connecting member connecting the first substrate to the second package. The number of the first connecting members is greater than the number of the 1-1 connecting members. The number of the second connecting members is greater than the number of the 2-1 connecting members.

[0008] According to one aspect of the present disclosure, a semiconductor package includes: a first substrate including a first insulating layer and a first wiring layer disposed on and / or in the first insulating layer; a first package disposed on the first substrate and including a second substrate, a first semiconductor chip disposed on the second substrate, a first connecting member connecting the second substrate to the first semiconductor chip, and a first SERDES chip embedded in the second substrate; a second package disposed on the first substrate and including a third substrate, a second semiconductor chip disposed on the third substrate, a second connecting member connecting the third substrate to the second semiconductor chip, and a second SERDES chip embedded in the third substrate; a 1-1 connecting member connecting the first substrate to the first package; and a 2-1 connecting member connecting the first substrate to the second package. The first semiconductor chip and the second semiconductor chip are connected to each other through a path passing through the first SERDES chip, the second substrate, the first substrate, the third substrate, and the second SERDES chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an example of an electronic device system;

[0011] Figure 2 is a perspective view showing an example of an electronic device;

[0012] Figure 3 is a cross-sectional view showing a semiconductor package according to an embodiment;

[0013] Figure 4 is a cross-sectional view showing a first package of a semiconductor package according to an embodiment;

[0014] Figure 5 is a cross-sectional view showing a first package according to another embodiment;

[0015] Figure 6 is a cross-sectional view showing a semiconductor package according to another embodiment;

[0016] Figure 7 It shows that according to Figure 6 A cross-sectional view of a first package of a semiconductor package of another embodiment; and

[0017] Figure 8 is a cross-sectional view showing a first package according to still another embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0019] Figure 1 is a block diagram illustrating an example of an electronic device system.

[0020] Reference Figure 1 , a main board 1010 may be accommodated in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the main board 1010. These components may be connected to other electronic components described below through various signal lines 1090.

[0021] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0022] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Environment (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Wireless Local Area Network (Wireless LAN), Bluetooth, third generation mobile communication technology (3G) protocol, fourth generation mobile communication technology (4G) protocol and fifth generation mobile communication technology (5G) protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include a component compatible with or operating according to at least one of a plurality of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0023] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0024] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, the other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk) drive, a compact disk (CD) drive, and a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0025] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0026] Figure 2 is a perspective view showing an example of an electronic device.

[0027] Reference Figure 2 , the electronic device may be implemented as, for example, a smart phone 1100. A mainboard 1110 may be housed in a body 1101 of the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the main body 1101. A portion of the electronic components 1120 may be chip-related components, for example, a component package 1121, but is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0028] Semiconductor Package

[0029] Figure 3 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0030] Reference Figure 3 According to an embodiment, a semiconductor package may include a first substrate 100, a first package 200 disposed on the first substrate 100, a second package 300 disposed on the first substrate 100, a 1-1 connecting member 401 connecting the first substrate 100 to the first package 200, and a 2-1 connecting member 402 connecting the first substrate 100 to the second package 300.

[0031] The first substrate 100 may be disposed on a main board (not shown), may correspond to an intermediate component for mounting the first package 200 and the second package 300 on the main board, and may be configured as a printed circuit board. The first substrate 100 may include a first insulating layer 110, a first wiring layer 120 disposed on and / or in the first insulating layer 110, and a first via layer 130 penetrating at least a portion of the first insulating layer 110 to connect the first wiring layers 120 to each other.

[0032] The first insulating layer 110 may include a plurality of insulating layers, and each of the first insulating layers 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (for example, a glass fabric such as glass cloth) into a thermosetting resin and / or a thermoplastic resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 110 may be a prepreg (PPG) or a resin-coated copper (RCC) insulating material, but embodiments thereof are not limited thereto, and the insulating material may be an Ajinomoto deposited film (ABF), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), and the like. However, embodiments thereof are not limited thereto, and other polymer materials having excellent rigidity may be used if necessary. The first insulating layer 110 may include 1-2 insulating layers 112 corresponding to the core layer. As Figure 3 As shown in , the insulating layers other than the core layer of the first insulating layer 110 may be configured symmetrically with respect to the core layer, but embodiments thereof are not limited thereto, and the first insulating layer 110 may have a coreless structure, ie, not including the core layer.

[0033] The first insulating layer 110 may include a 1-1 insulating layer 111 located at the uppermost side. The 1-1 insulating layer 111 may include an insulating material. The 1-1 insulating layer 111 may include an insulating material having a signal loss rate lower than that of the other first insulating layers 110. For example, the 1-1 insulating layer 111 may include a material having a loss factor (Df) lower than that of the other first insulating layers 110, and may include a material having a relatively small dielectric constant (Dk), or may include a material having a relatively small loss factor (Df) and a relatively small dielectric constant (Dk).

[0034] The insulating material of the 1-1 insulating layer 111 may be a prepreg (PPG) or a resin-coated copper (RCC) insulating material, but embodiments thereof are not limited thereto, and the insulating material may be an Ajinomoto deposited film (ABF), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc., and its loss factor (Df) value may be smaller than the loss factor (Df) of other first insulating layers 110, and may include liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyphenylene ether (PPE), cycloolefin polymer (COP) and perfluoroalkoxy (PFA), but embodiments thereof are not limited thereto.

[0035] As described later, since a high-speed signal can be transmitted from the first package 200 to the second package 300 through the 1-1 insulating layer 111, the signal loss rate can be reduced by configuring the loss factor (Df) of the 1-1 insulating layer 111 to be lower than the loss factor (Df) of the other first insulating layers 110. Figure 3 In the embodiment, the 1-1 insulating layer 111 may be the uppermost insulating layer among the plurality of first insulating layers 110 of the first substrate 100, but the embodiment is not limited thereto, and any region in which the first wiring layer 120 can be disposed for transmitting the high-speed signal generated in the first package 200 to the second package 300 may be used. Figure 3 As shown, a single 1-1 insulating layer 111 may be provided, but embodiments thereof are not limited thereto, and when a signal is transmitted from the first package 200 to the second package 300 through a plurality of wiring layers, the 1-1 insulating layer 111 may also include a plurality of 1-1 insulating layers 111. That is, the 1-1 insulating layer 111 may be provided in any region in which the first wiring layer 120 is provided, so that a high-speed signal generated in the first package 200 may be transmitted to the second package 300.

[0036] The first wiring layer 120 may include a plurality of wiring layers, and each of the first wiring layers 120 may include a metal material. As the metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys may be used. Each of the first wiring layers 120 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but its embodiment is not limited thereto. A sputtering layer may be formed instead of the chemical copper plating layer as an electroless plating layer. If necessary, a copper foil may be further included. Each of the first wiring layers 120 may perform various functions according to the design of the corresponding layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Here, the signal pattern may include various signal (e.g., data signal) patterns other than the ground pattern and the power pattern. Each of the patterns may include a line pattern, a plane pattern and / or a pad pattern.

[0037] The first via layer 130 may include a plurality of via layers, and each of the first via layers 130 may include micro vias. The micro vias may be filled vias for filling the via holes or conformal vias arranged along the wall surface of the via holes. The micro vias may be arranged in a stacked and / or staggered manner. Each of the first via layers 130 may include a metal material. The metal material may include, for example, Cu, aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. Each of the first via layers 130 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but embodiments thereof are not limited thereto. A sputtering layer may be formed instead of a chemical copper plating layer as an electroless plating layer. The first via layer 130 may perform various functions according to the design of the corresponding layer. For example, a ground via, a power via, a signal via, etc. may be included. Here, the signal via may include vias for transmitting various signals (eg, data signals) in addition to the ground via and the power via.

[0038] The first wiring layer 120 and the first via layer 130 may be integrated with each other, respectively, but the embodiment is not limited thereto. The first wiring layer 120 and / or the first via layer 130 may be formed by a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT) method, or a subtractive method, but the embodiment is not limited thereto, and any construction method for constructing a circuit on a printed circuit board may be used without limitation.

[0039] The first substrate 100 may further include a first solder resist layer 140 located on the outermost side. The first solder resist layer 140 may protect the first substrate 100 from the influence of the external area, and may be arranged on the uppermost side of the first substrate 100 and / or the lowermost side of the first substrate 100. The first solder resist layer 140 may include a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, and may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but its embodiment is not limited thereto. However, the material of the first solder resist layer 140 is not limited thereto, and if necessary, any solder resist material (such as other polymer materials) used in the field of printed circuit boards may be used without limitation. The first solder resist layer 140 may include an opening, a portion of the first wiring layer 120 may be exposed through the opening, and the exposed portion of the first wiring layer 120 may perform the function of being connected to the pads of other components.

[0040] The number of the first insulating layer 110, the number of the first wiring layer 120, and the number of the first via layer 130 in the embodiment may vary, and the arrangement of the core layer (1-2 insulating layer 112) of the first insulating layer 110 in the embodiment may also vary. However, the embodiment is not limited thereto, and the first substrate 100 may be configured to be usable by a person skilled in the art of printed circuit boards.

[0041] The first package 200 may include a second substrate 201 , a first semiconductor chip 270 disposed on the second substrate 201 , a first connection member 271 connecting the second substrate 201 to the first semiconductor chip 270 , and a first SERDES chip 250 embedded in the second substrate 201 , which will be described in detail later.

[0042] The first package 200 may be configured as a chip package including a first semiconductor chip 270, and may have a structure in which the first semiconductor chip 270 is mounted on a second substrate 201. The second substrate 201 may be configured as a printed circuit board, and may have a fine structure to be connected to the first semiconductor chip 270. The second substrate 201 may include a second insulating layer 210, a second wiring layer 220 disposed on and / or in the second insulating layer 210, and a second via layer 230 penetrating at least a portion of the second insulating layer 210 to connect the second wiring layers 220 to each other.

[0043] The second insulating layer 210 may include a plurality of insulating layers, and each second insulating layer 210 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (e.g., a glass fabric such as a glass cloth) in a thermosetting resin and / or a thermoplastic resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the second insulating layer 210 may be a prepreg (PPG) or a resin coated copper (RCC) insulating material, but embodiments thereof are not limited thereto, and the insulating material may be an Ajinomoto deposited film (ABF), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, embodiments thereof are not limited thereto, and other polymer materials having excellent rigidity may be used if necessary. The second insulating layer 210 may include a plurality of second insulating layers 210, and the plurality of second insulating layers 210 may not include the same material, and the insulating materials included in each of the plurality of second insulating layers 210 may be different from each other. For example, in a region adjacent to the first semiconductor chip 270 , the second insulating layer 210 may be formed using a photosensitive dielectric (PID), but the embodiment is not limited thereto.

[0044] The second wiring layer 220 may include a plurality of wiring layers, and each second wiring layer 220 may include a metal material. As a metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys may be used. Each of the second wiring layers 220 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but its embodiment is not limited thereto. A sputtering layer may be formed instead of a chemical copper plating layer as an electroless plating layer. If necessary, a copper foil may be further included. The second wiring layer 220 may perform various functions according to the design of each corresponding layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Here, the signal pattern may include various signal (e.g., data signal) patterns other than the ground pattern and the power pattern. Each of these patterns may include a line pattern, a plane pattern and / or a pad pattern. The uppermost second wiring layer 220 among the plurality of second wiring layers 220 may have a structure exposed from the second insulating layer 210 , and the second substrate 201 may further include a surface treatment layer (not shown) on the exposed surface of the second wiring layer 220 .

[0045] The second via layer 230 may include a plurality of via layers, and each second via layer 230 may include a micro via. The micro via may be a filling via for filling a via hole or a conformal via arranged along the wall surface of the via hole. The micro via may be arranged in a stacked and / or staggered manner. Each second via layer 230 may include a metal material. The metal material may include, for example, Cu, aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. Each of the second via layers 230 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but embodiments thereof are not limited thereto. A sputtering layer may be formed instead of a chemical copper plating layer as an electroless plating layer. The second via layer 230 may perform various functions according to the design of the corresponding layer. For example, a ground via, a power via, a signal via, etc. may be included. Here, the signal via may include vias for transmitting various signals (eg, data signals) in addition to the ground via and the power via.

[0046] The second wiring layer 220 and the second via layer 230 may be integrated with each other, respectively, but the embodiment is not limited thereto. The second wiring layer 220 and / or the second via layer 230 may be formed by a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) method, or a subtractive method, but the embodiment is not limited thereto, and any method of constructing a circuit on a printed circuit board may be used without limitation.

[0047] The second substrate 201 may include a first column 221 for mounting a first semiconductor chip 270 to be described later. The first column 221 may protrude to the outermost side of the second substrate 201, and may perform the function of a column to facilitate connection with the first semiconductor chip 270. The first column 221 may include a metal material. As a metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof may be used. The first column 221 may be formed in the same manner as the second wiring layer 220, but its embodiment is not limited thereto, and any method commonly used to form a metal column may be used without limitation. For example, the first column 221 may be formed first, and then other components of the second substrate 201 may be formed, or a method such as combining other components of the second substrate 201 with a separately manufactured metal column may be used.

[0048] The second substrate 201 may further include a first surface treatment layer 222 disposed on the first pillar 221. When a first semiconductor chip 270 to be described later is mounted, the first surface treatment layer 222 may enhance the bonding between the first semiconductor chip 270 and the first pillar 221. The first surface treatment layer 222 may be formed by an organic solderability preservative (OSP) method, a hot air leveling (HASL) method, an electroless nickel / immersion gold (ENIG) method, an electroless nickel / electroless palladium / immersion gold (ENEPIG) method, and an electroless plating layer may also be formed as the first surface treatment layer 222.

[0049] The second substrate 201 may include a cavity penetrating at least a portion of the second insulating layer 210. The cavity may be used as a space for mounting a first SERDES chip 250 to be described later. Any general method of processing a cavity in a printed circuit board may be used as a method of forming the cavity without limitation.

[0050] The first semiconductor chip 270 may be disposed on the second substrate 201, and the first semiconductor chip 270 may be configured as an integrated circuit (IC) in which hundreds to millions of elements or more are integrated into the chip. The first semiconductor chip 270 may be a processor chip (specifically, an application processor (AP)) such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, but its embodiment is not limited thereto, and may be configured as a logic chip such as an analog-to-digital converter, an application specific IC (ASIC), a memory controller (MC) chip, or may be a memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, a resistive random access memory (RRAM) chip, an electrically erasable programmable read-only memory (EEPROM) chip, or a high bandwidth memory (HBM), and these chips may be configured to be combined with each other.

[0051] In the first semiconductor chip 270, a surface on which a pad for connecting to the second substrate 201 is provided may be an active surface, and a surface opposite to the active surface may be a passive surface. The first semiconductor chip 270 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material forming the body of the first semiconductor chip 270. Various circuits may be formed in the body of the first semiconductor chip 270.

[0052] The first semiconductor chip 270 can be connected to the second substrate 201 through the first connection member 271. The first connection member 271 can enable the first semiconductor chip 270 to be mounted on the second substrate 201, and can physically connect and / or electrically connect the first semiconductor chip 270 to the second substrate 201. The first connection member 271 can be formed using a conductive material (e.g., solder), but the material of the first connection member 271 is not limited thereto. In addition, the first connection member 271 can be configured as a pad, a solder ball, a pin, etc., but its embodiment is not limited thereto. The first connection member 271 can be formed as a multilayer or a single layer. When the first connection member 271 is formed as a multilayer, the first connection member 271 may include a copper column and a solder, and when formed as a single layer, the first connection member 271 may include a tin-silver solder or copper, but its embodiment is not limited thereto. The number, spacing, arrangement, etc. of the first connection member 271 are not limited to any specific example, and can be fully modified according to the design matters of those skilled in the art. For example, the number of the first connection member 271 can be tens to thousands, or it can be more or less than the above number.

[0053] The first package 200 of the semiconductor package according to the embodiment may include a first SERDES chip 250 embedded in the second substrate 201. In the embodiment, the SERDES chip may refer to a combination of a serializer and a deserializer, and may be expressed as a serializer / deserializer or may be expressed as a serializer / deserializer, but the embodiment thereof is not limited thereto, and the SERDES chip may refer to a semiconductor chip including a circuit for performing the functions of the serializer and the deserializer. However, the embodiment thereof is not limited thereto, and the SERDES chip may include an example in which an area in which a circuit for performing a SERDES function may be directly implemented in the second substrate 201 and the SERDES function may be performed in the area of ​​the second substrate 201. That is, the SERDES chip may be expressed as a chip for performing a SERDES function, but the embodiment thereof is not limited thereto, and an area in which a SERDES circuit in the second substrate 201 is implemented and integrated with the second substrate 201 may correspond to the SERDES chip.

[0054] The first SERDES chip 250 may receive a command from an external entity and may transmit the command to the external entity in the form of data, or may receive data from an external entity and convert the data into a command, the first SERDES chip 250 may divide the command and data, multiplex the command and data, serialize the command and data, and transmit the command and data in a simplified state, and may analyze the command and data by time-decomposition multiplexing. As described above, the first SERDES chip 250 may be used as an interconnection connecting an external entity to an external entity. Specifically, the first SERDES chip may correspond to an interface for performing a chip-to-chip interconnection between semiconductor chips, and more specifically, the first SERDES chip may be operated as an interface between a memory controller and a memory. For example, the first SERDES chip 250 may convert parallel data received from the first semiconductor chip 270 into serial data, and may transmit the serial data to the second semiconductor chip 370. Alternatively, the first SERDES chip 250 may convert serial data received from the second semiconductor chip 370 into parallel data, and may transmit the parallel data to the first semiconductor chip 270.

[0055] In a semiconductor package according to an embodiment, the first SERDES chip 250 may include a serializer chip. In this case, the first SERDES chip 250 may be used as a serializer for converting parallel data received from the first semiconductor chip 270 into serial data. However, its embodiments are not limited thereto, and the first SERDES chip 250 may include a deserializer chip. In this case, the first SERDES chip 250 may perform a function of converting serial data received from the second semiconductor chip 370 into parallel data. However, its embodiments are not limited thereto, and by adopting half-duplex, the first SERDES chip 250 may include a transmitter and a receiver, so that the first SERDES chip 250 may perform transmission and reception functions.

[0056] In the semiconductor package according to the embodiment, the first SERDES chip 250 included in the first package 200 may include a serializer chip. The first SERDES chip 250 may include a first connection pad 251, and the first connection pad 251 may include an input connection pad for receiving data from the first semiconductor chip 270 and an output connection pad for transmitting the converted data to an external entity. In addition, the first connection pad 251 may also include various connection pads connected to an external entity, such as a power connection pad.

[0057] The number of input connection pads may be greater than the number of output connection pads in the first connection pads 251 of the first SERDES chip 250. Since the serializer chip performs a function of converting parallel input signals into serial signals and transmitting the signals to the second package 300, the parallel input signals may be time-integrated and transmitted to the second package 300 in a uniform state. Therefore, the number of input connection pads for receiving data from the first semiconductor chip 270 may be greater than the number of output pads for transmitting the converted data to an external entity.

[0058] That is, the connection between the plurality of first semiconductor chips 270 can be simplified by the serializer. For example, when N parallel signals received from the first semiconductor chip 270 can be transmitted by converting into a serial signal, the first package 200 can reduce the number of connections at a ratio of N:1 compared to the first semiconductor chip 270. That is, by implementing the first package 200 in such a manner that the first SERDES chip 250 is embedded in the second substrate 201, it is not necessary to implement a redistribution layer (RDL) for direct connection with the first semiconductor chip 270. That is, the number of connections can be reduced by changing the design of the first SERDES chip 250 connected to the semiconductor chip and the second substrate 201 and the design of the first substrate 100 without implementing a redistribution layer, which can be very important in simplifying the redistribution layer including the microcircuit or even not providing the redistribution layer. Since the circuit with fine pitch is reduced, this construction can be very helpful in improving the yield of the second substrate 201 and the first substrate 100, and can further improve the reliability.

[0059] The first package 200 of the semiconductor package according to the embodiment may include a first adhesive member 260. The first SERDES chip 250 may be disposed in the cavity of the second substrate 201, and the first SERDES chip 250 may be attached to the bottom surface of the cavity by the first adhesive member 260. As the first adhesive member 260, an adhesive film such as a universal die attach film (DAF) may be used, but the embodiment thereof is not limited thereto, and any means (such as, a generally used tape) for attaching other components such as electronic components or semiconductor chips to a printed circuit board may be used without limitation. In the first SERDES chip 250, the first connection pad 251 may be disposed only on the upper surface, and in this case, the upper surface on which the first connection pad 251 is disposed may be an active surface. The lower surface on which the first connection pad 251 is not disposed may become a passive surface, and the first adhesive member 260 may be bonded to the passive surface of the first SERDES chip 250, so that the first SERDES chip 250 may be attached to the second substrate 201.

[0060] The second substrate 201 may further include a second solder resist layer 240 located on the outermost side. The second solder resist layer 240 may protect the second substrate 201 from the influence of external entities, and may be disposed on the uppermost side of the second substrate 201 and / or the lowermost side of the second substrate 201. The second solder resist layer 240 may include a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, and may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but its embodiment is not limited thereto. However, the material of the second solder resist layer 240 is not limited thereto, and if necessary, any solder resist material (such as a polymer material) used in the field of printed circuit boards may be used without limitation. The second solder resist layer 240 may include an opening, and a portion of the second wiring layer 220 may be exposed to an external entity through the opening and may perform the function of a pad connected to other components, or a first column 221 protruding from the second solder resist layer 240 may be provided to perform the function of a pad connected to other components.

[0061] The number of layers of the second insulating layer 210, the second wiring layer 220, and the second via layer 230 and the depth of the cavity may vary according to the design. Figure 3 As shown in , the second substrate 201 may have a pattern structure in which the lowermost second wiring layer 220 is partially buried by the lowermost second insulating layer 210, and may have a coreless structure that does not include a core insulating layer. However, embodiments thereof are not limited thereto, and the second substrate 201 may have a coreless structure in which the uppermost second wiring layer 220 is partially buried by the uppermost second insulating layer 210. However, embodiments thereof are not limited thereto, and the second substrate 201 may have a structure of a core substrate.

[0062] The first package 200 may further include a molding material (not shown) provided to surround the second substrate 201 and the first semiconductor chip 270 and protect the first package 200. In this case, the molding material may be an epoxy molding compound (EMC), but the embodiment is not limited thereto, and any material used as a molding material in the technical field of semiconductor packages may be used without limitation. Figure 3 The configuration shown in , as the first package 200 , may use any component that can be used by those skilled in the art of printed circuit boards and semiconductor packages without limitation, and may further include other components.

[0063] The second package 300 may include a third substrate 301 , a second semiconductor chip 370 disposed on the third substrate 301 , a second connection member 371 connecting the third substrate 301 and the second semiconductor chip 370 to each other, and a second SERDES chip 350 embedded in the third substrate 301 .

[0064] The second package 300 may be configured as a chip package including a second semiconductor chip 370, and may have a structure in which the second semiconductor chip 370 is mounted on a third substrate 301. The third substrate 301 may be configured as a printed circuit board, and may have a fine structure to be connected to the second semiconductor chip 370. The third substrate 301 may include a third insulating layer 310, a third wiring layer 320 disposed on and / or in the third insulating layer 310, and a third via layer 330 penetrating at least a portion of the third insulating layer 310 to connect the third wiring layers 320 to each other.

[0065] The third insulating layer 310 may include a plurality of insulating layers, and each third insulating layer 310 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (e.g., a glass cloth and / or a glass fabric) in a thermosetting resin and / or a thermoplastic resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the third insulating layer 310 may be a prepreg (PPG) or a resin coated copper (RCC) insulating material, but embodiments thereof are not limited thereto, and the insulating material may be an Ajinomoto deposited film (ABF), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, embodiments thereof are not limited thereto, and other polymer materials having excellent rigidity may be used if necessary. The third insulating layer 310 may include a plurality of third insulating layers, and the plurality of third insulating layers 310 may not include the same material, and the insulating materials included in each insulating layer in the plurality of third insulating layers 310 may be different from each other. For example, in a region adjacent to the second semiconductor chip 370 , the third insulating layer 310 may be formed using a photosensitive dielectric (PID), but the embodiment is not limited thereto.

[0066] The third wiring layer 320 may include a plurality of wiring layers, and each of the third wiring layers 320 may include a metal material. As the metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys may be used. Each of the third wiring layers 320 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but its embodiment is not limited thereto. A sputtering layer may be formed instead of the chemical copper plating layer as an electroless plating layer. If necessary, a copper foil may be further included. The third wiring layer 320 may perform various functions according to the design of each layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Here, the signal pattern may include various signal (e.g., data signal) patterns other than the ground pattern and the power pattern. Each of these patterns may include a line pattern, a plane pattern and / or a pad pattern. The third wiring layer 320 located at the uppermost side among the plurality of third wiring layers 320 may have a structure exposed from the third insulating layer 310 , and the third substrate 301 may further include a surface treatment layer (not shown) located on the exposed surface of the third wiring layer 320 .

[0067] The third via layer 330 may include a plurality of via layers, and each of the third via layers 330 may include micro vias. The micro via may be a filling via for filling a via hole or a conformal via arranged along the wall surface of the via hole. The micro via may be arranged in a stacked and / or staggered manner. Each of the third via layers 330 may include a metal material. The metal material may include (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. Each of the third via layers 330 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but embodiments thereof are not limited thereto. A sputtering layer may be formed instead of a chemical copper plating layer as an electroless plating layer. The third via layer 330 may perform various functions according to the design of the corresponding layer. For example, a ground via, a power via, a signal via, etc. may be included. Here, the signal via may include vias for transmitting various signals (eg, data signals) in addition to the ground via and the power via.

[0068] The third wiring layer 320 and the third via layer 330 may be integrated with each other, respectively, but the embodiment is not limited thereto. The third wiring layer 320 and / or the third via layer 330 may be formed by a semi-additive process (SAP), a modified semi-additive process (MSAP), a via sealing (TT) method, or a subtractive process, but the embodiment is not limited thereto, and any construction method for constructing a circuit on a printed circuit board may be used without limitation.

[0069] The third substrate 301 may include a second column 321 for mounting a second semiconductor chip 370 to be described later. The second column 321 may protrude to the outermost side of the third substrate 301, and may perform the function of a column to easily connect to the second semiconductor chip 370. The second column 321 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The second column 321 may be formed in the same manner as the third wiring layer 320, but its embodiment is not limited thereto, and any method commonly used to form a metal column may be used without limitation. For example, the second column 321 may be formed first, and then other components of the third substrate 301 may be formed, or a method of combining other components of the third substrate 301 with a separately manufactured metal column may be used.

[0070] The third substrate 301 may further include a second surface treatment layer 322 disposed on the second pillar 321. When a second semiconductor chip 370 to be described later is mounted, the second surface treatment layer 322 may enhance the bonding between the second semiconductor chip 370 and the second pillar 321. The second surface treatment layer 322 may be formed by an organic solderability preservative (OSP) method, a hot air leveling (HASL) method, an electroless nickel / immersion gold (ENIG) method, an electroless nickel / electroless palladium / immersion gold (ENEPIG) method, and an electroless plating layer may be formed as the second surface treatment layer 322.

[0071] The third substrate 301 may include a cavity penetrating at least a portion of the third insulating layer 310. The cavity may be used as a space for mounting a second SERDES chip 350 to be described later. As a method of forming the cavity, any general method of processing a cavity in a printed circuit board may be used without limitation. Figure 3 As shown in FIG, the first substrate 100, the second substrate 201, and the third substrate 301 are disposed to be spaced apart from each other.

[0072] The second semiconductor chip 370 may be disposed on the third substrate 301, and the second semiconductor chip 370 may be an integrated circuit (IC) in which hundreds to millions of elements or more are integrated into the chip. The second semiconductor chip 370 may be a processor chip (specifically, an application processor (AP)) such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, but its embodiment is not limited thereto, and may be configured as a logic chip such as an analog-to-digital converter, an application specific IC (ASIC), a memory controller (MC) chip, or may be a memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, a resistive random access memory (RRAM) chip, an electrically erasable programmable read-only memory (EEPROM) chip, or a high bandwidth memory (HBM), and these chips may be configured to be combined with each other.

[0073] In the second semiconductor chip 370, a surface on which a pad for connecting to the third substrate 301 is provided may be an active surface, and a surface opposite to the active surface may be a passive surface. The second semiconductor chip 370 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a substrate for forming the body of the second semiconductor chip 370. Various circuits may be formed in the body of the second semiconductor chip 370.

[0074] The second semiconductor chip 370 can be connected to the third substrate 301 through the second connection member 371. The second connection member 371 can mount the second semiconductor chip 370 on the third substrate 301, and can physically connect and / or electrically connect the second semiconductor chip 370 to the third substrate 301. The second connection member 371 can be formed using a conductive material (e.g., solder), but the material of the second connection member 371 is not limited thereto. In addition, the second connection member 371 may include a pad, a solder ball, a pin, etc., but its embodiment is not limited thereto. The second connection member 371 can be formed as a multilayer or a single layer. When formed as a multilayer, the second connection member 371 may include a copper column and a solder, and when formed as a single layer, the second connection member 371 may include a tin-silver solder or copper, but its embodiment is not limited thereto. The number, spacing, and arrangement of the second connection member 371 are not limited to any specific example, and can be fully modified according to the design matters of those skilled in the art. For example, the number of the second connection member 371 can be tens to thousands, and can be more or less than the above number.

[0075] The second package 300 of the semiconductor package according to the embodiment may include a second SERDES chip 350 embedded in the third substrate 301. The description of the second SERDES chip may be as follows.

[0076] The second SERDES chip 350 may receive data from an external entity and may transmit the data by converting the data into commands, or the second SERDES chip 350 may receive commands from an external entity and may convert the commands into a data format, the second SERDES chip 350 may divide the commands and data to multiplex the commands and data, may serialize the commands and data, may transmit the commands and data in a simplified state, and may analyze the commands and data again by time division multiplexing.

[0077] As described above, the second SERDES chip 350 may be used as an interconnect for connecting an external entity to an external entity. Specifically, the second SERDES chip 350 may correspond to an interface for performing chip-to-chip interconnection between semiconductor chips together with the first SERDES chip 250, and more specifically, the second SERDES chip 350 may operate as an interface between a memory controller and a memory. For example, the second SERDES chip 350 may convert serial data received from the first package 200 into parallel data, and may transmit the converted data to the second semiconductor chip 370. Optionally, the second SERDES chip 350 may convert parallel data received from the second semiconductor chip 370 into serial data, and may transmit the serial data to the first semiconductor chip 270 of the first package 200.

[0078] In the semiconductor package according to the embodiment, the second SERDES chip 350 may include a deserializer chip. In this case, the following functions may be performed by the second SERDES chip 350: the command received from the first semiconductor chip 270 through the first SERDES chip 250 and the serial signal transmitted through the first package 200 and the first substrate 100 are converted into parallel data, and the converted parallel data may be transmitted to the second semiconductor chip 370. That is, the second SERDES chip 350 may perform the function of a deserializer or a parallelizer. However, its embodiment is not limited thereto, and the second SERDES chip 350 may include a serializer chip, and in this case, the second SERDES chip 350 may be used as a serializer for converting the parallel data received from the second semiconductor chip 370 through the second SERDES chip 350 into serial data. However, its embodiment is not limited thereto, and by adopting half-duplex, the second SERDES chip 350 may have a transmitter and a receiver, so that one second SERDES chip 350 may perform the transmission and reception functions.

[0079] In the semiconductor package according to the embodiment, the second SERDES chip 350 included in the second package 300 may include a deserializer chip. The second SERDES chip 350 may include a second connection pad 351, and the second connection pad 351 may include an input connection pad for receiving data from the second semiconductor chip 370 of the second package 300, and an output connection pad for transmitting the converted data to the second semiconductor chip 370. In addition, the second connection pad 351 may also include various connection pads connected to an external entity, such as a power connection pad.

[0080] In the second connection pads 351 of the second SERDES chip 350, the number of output connection pads may be more than the number of input connection pads. The deserializer chip may convert the serial input signal into a parallel signal, and may transmit the parallel signal to the second semiconductor chip 370, so the serial signal passing through the second SERDES chip 350 may be analyzed into commands and data again by time decomposition multiplexing. The parallel signal analyzed above may be sent to the second semiconductor chip 370 in a multiplexed state. Therefore, the number of input connection pads for receiving the serial signal converted by the first SERDES chip 250 may be less than the number of output connection pads for sending the converted parallel signal to the second semiconductor chip 370, which may mean that the number of output connection pads of the second connection pad 351 may be more than the number of input connection pads.

[0081] That is, the signal simplified by the serializer can be reversely converted into the original command and data by the deserializer. That is, the simplified signal can be converted again and transmitted to another semiconductor chip. For example, in the case where a serial signal transmitted from the first package 200 can be converted into N parallel signals, the second package 300 can reduce the number of connections at a ratio of N:1 compared to the second semiconductor chip 370. That is, even when a single connection is included between the second package 300 and the first substrate 100, the third substrate 301 and the second semiconductor chip 370 can also achieve N connections, which can analyze the signal converted by the serializer, and therefore, the redistribution layer including the microcircuit can be simplified, and even the redistribution layer may not be provided, which can be very important. Since the circuit with fine pitch is reduced, this construction can be very helpful to improve the yield of the third substrate 301 and the first substrate 100, and can further improve reliability. As an example, the second SERDES chip 350 may perform conversion at a ratio of 1:N, but embodiments thereof are not limited thereto, and the second SERDES chip 350 may perform serial-parallel conversion at a ratio of 1:M different from that of the first SERDES chip 250. Here, N and M may refer to natural numbers greater than 1.

[0082] The second package 300 of the semiconductor package according to the embodiment may include a second adhesive member 360. The second SERDES chip 350 may be disposed in the cavity of the third substrate 301, and the second SERDES chip 350 may be attached to the bottom surface of the cavity by the second adhesive member 360. As the second adhesive member 360, an adhesive film such as a universal die attach film (DAF) may be used, but its embodiment is not limited thereto, and any means (such as, a commonly used tape) for attaching other components such as electronic components or semiconductor chips to a printed circuit board may be used without limitation. In the second SERDES chip 350, the second connection pad 351 may be disposed only on the upper surface, and in this case, the upper surface on which the second connection pad 351 is disposed may be an active surface. The lower surface on which the second connection pad 351 is not disposed may become a passive surface, and the second adhesive member 360 may be bonded to the passive surface of the second SERDES chip 350, so that the second SERDES chip 350 may be attached to the third substrate 301.

[0083] The third substrate 301 may further include a third solder resist layer 340 located on the outermost side. The third solder resist layer 340 may protect the third substrate 301 from the influence of external entities, and may be disposed on the uppermost side of the third substrate 301 and / or the lowermost side of the third substrate 301. The third solder resist layer 340 may include a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, and may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but its embodiment is not limited thereto. However, the material of the third solder resist layer 340 is not limited thereto, and if necessary, any solder resist material (such as other polymer materials) used in the field of printed circuit boards may be used without limitation. The third solder resist layer 340 may include an opening, and a portion of the third wiring layer 320 may be exposed to an external entity through the opening and may perform the function of a pad connected to other components, or a second column 321 protruding from the third solder resist layer 340 may be provided to perform the function of a pad connected to other components.

[0084] The number of layers of the third insulating layer 310, the third wiring layer 320 and the third via layer 330 and the depth of the cavity may vary according to the design. Figure 3 As shown in , the third substrate 301 may have a structure of a pattern in which the third wiring layer 320 on the lowermost side is partially buried by the third insulating layer 310 on the lowermost side, and may have a coreless structure that does not include a core insulating layer. However, embodiments thereof may not be limited thereto, and the third substrate 301 may have a coreless structure in which the third wiring layer 320 on the uppermost side is partially buried by the third insulating layer 310 on the uppermost side. However, embodiments thereof may not be limited thereto, and the third substrate 301 may have a structure of a core substrate.

[0085] The second package 300 may further include a molding material (not shown) provided to surround the third substrate 301 and the second semiconductor chip 370 and protect the second package 300. In this case, the molding material may be an epoxy molding compound (EMC), but the embodiment is not limited thereto, and any material used as a molding material in the field of semiconductor packages may be used without limitation. As such, the second package 300 may not be limited to Figure 3 The configuration shown in FIG. 1 and any components available to those skilled in the technical fields of printed circuit boards and semiconductor packages may be used without limitation, and may further include other electronic components.

[0086] The second package 300 may be symmetrical with the first package 200 , but this is merely for ease of description, and the second package 300 may have a configuration different from that of the first package 200 .

[0087] The semiconductor package according to the embodiment may include a 1-1 connection member 401 connecting the first substrate 100 to the first package 200 and a 2-1 connection member 402 connecting the first substrate 100 to the second package 300. Each of the 1-1 connection member 401 and the 2-1 connection member 402 may be formed using a conductive material (e.g., solder), but the materials of the 1-1 connection member 401 and the 2-1 connection member 402 are not limited to any specific example. In addition, the 1-1 connection member 401 and / or the 2-1 connection member 402 may be configured as a pad, a solder ball, a pin, etc., but the embodiment thereof is not limited thereto. The 1-1 connection member 401 and the 2-1 connection member 402 may be formed as a multilayer or a single layer. When formed as a multilayer, each of the 1-1 connection member 401 and the 2-1 connection member 402 may include a copper column and solder, and when formed as a single layer, each of the 1-1 connection member 401 and the 2-1 connection member 402 may include tin-silver solder or copper, but the embodiment thereof is not limited thereto. The number, intervals, and arrangement of the 1-1 connection members 401 and the 2-1 connection members 402 are not limited to any specific example and may be adequately modified according to design matters of those skilled in the art.

[0088] In the first package 200, the number of first connection members 271 connecting the first semiconductor chip 270 to the second substrate 201 may be greater than the number of 1-1 connection members 401 connecting the first substrate 100 to the first package 200. Since parallel signals generated by the first semiconductor chip 270 are converted into serial signals by the first SERDES chip 250 and transmitted to the first substrate 100, the number of signal paths between the first package 200 and the first substrate 100 may be set to be less than the number of signal paths (for transmitting the signals generated by the first semiconductor chip 270) between the first semiconductor chip 270 and the second substrate 201, so that the first substrate 100 and the first package 200 may be connected to each other with fewer connections.

[0089] Furthermore, in the second package 300, the number of second connection members 371 connecting the second semiconductor chip 370 to the third substrate 301 may be greater than the number of 2-1 connection members 402 connecting the first substrate 100 to the second package 300. That is, since the signal is transmitted to the second package 300 in a state where the number of paths of the signal transmitted from the first package 200 to the first substrate 100 is relatively small, the number of connections between the first substrate 100 and the second package 300 may be kept small, but since the serial signal is converted back into a parallel signal through the second SERDES chip 350 and transmitted to the second semiconductor chip 370, the signal path between the second substrate 201 and the second semiconductor chip 370 may need to be greater than the number of signal paths between the first substrate 100 and the second package 300. Therefore, even when the first substrate 100 and the second package 300 are connected with fewer connections, the required connection between the third substrate 301 and the second semiconductor chip 370 may be sufficiently performed.

[0090] In addition, the pitch of the first connection member 271 may be formed to be smaller than the pitch of the 1-1 connection member 401, which may mean that the pitch of the second wiring layer 220 connected to the first connection member 271 in the second substrate 201 may be smaller than the pitch of the second wiring layer 220 connected to the 1-1 connection member 401 in the second substrate 201. In an embodiment, the pitch may be measured by imaging a cross section of the printed circuit board using a scanning microscope, and the average pitch may be the average value of the pitches between the wirings measured at five random points adjacent to each other. That is, the wiring included in the second wiring layer 220 connected to the uppermost side of the first connection member 271 may be a high-density circuit having a smaller line / space (L / S) than the wiring included in the second wiring layer 220 connected to the lowermost side of the 1-1 connection member 401. As described above, since the number of first connecting members 271 is greater than the number of 1-1 connecting members 401, the pitch of the first connecting members 271 can be smaller than the pitch of the 1-1 connecting members 401, which is similar to the construction in which the pitch of the second connecting members 371 is formed to be smaller than the pitch of the 2-1 connecting members 402, and this can mean that the pitch of the third wiring layer 320 connected to the second connecting members 371 in the third substrate 301 can be smaller than the pitch of the third wiring layer 320 connected to the 2-1 connecting members 402 in the third substrate 301.

[0091] In the case of a general fan-in package or fan-out package for mounting a semiconductor chip on a printed circuit board, the semiconductor chip can be connected by a redistribution layer. However, a general redistribution layer may be a fine wiring layer, and may not be easy to implement, and defects may often occur in the process of implementing a fine redistribution layer. In addition, as the size of the semiconductor chip increases, the size of the redistribution layer used in the fan-in package or the fan-out package may also increase. As the size of the redistribution layer increases, defects in the redistribution layer including fine wiring may occur more frequently. However, according to the semiconductor package of the embodiment, the first semiconductor chip 270 and the second semiconductor chip 370 can be used to easily perform signal transmission without implementing a redistribution layer. In addition, since the redistribution layer with fine wiring can be designed to be reduced or almost non-existent, reliability can be greatly improved, and since each semiconductor chip is mounted on the first substrate 100 after packaging, yield can be improved. In addition, since the packaged first package 200 and the second package 300 are respectively mounted on the first substrate 100 , each package may be mounted on the first substrate 100 through the 1-1 connection members 401 and the 2-1 connection members 402 at a sufficiently expanded pitch.

[0092] In the semiconductor package according to the embodiment, the first semiconductor chip 270 and the second semiconductor chip 370 may be electrically connected to each other. Specifically, the first semiconductor chip 270 and the second semiconductor chip 370 may be electrically connected to each other through a path passing through the first SERDES chip 250, the second substrate 201, the first substrate 100, the third substrate 301, and the second SERDES chip 350. Figure 3 As shown in , a plurality of parallel signals from the first semiconductor chip 270 may be converted into a unified serial signal by the first SERDES chip 250, and the serial signal from the first SERDES chip 250 may be transmitted from the second substrate 201 of the first package 200 to the first substrate 100. The high-speed serial signal transmitted through the first wiring layer 120 of the first substrate 100 may move to the third substrate 301 of the second package 300, and may be input to the second SERDES chip 350. The second SERDES chip 350 may convert the serial signal back into a parallel signal, and the parallel signal may be transmitted to the second semiconductor chip 370. The signal transmission path may be confirmed by analyzing the finished semiconductor package layer by layer. That is, in the case of removing the first semiconductor chip 270 and the second semiconductor chip 370, the surface may be removed one by one relative to the second wiring layer 220 connected to the first SERDES chip 250 and the third wiring layer 320 connected to the second SERDES chip 350, so that the formation of the signal path may be confirmed by repeatedly checking whether the subsequent second wiring layer 220 and the third wiring layer 320 are connected to the aforementioned wiring layer. For example, after recording the second wiring layer 220, the second via layer 230, the third wiring layer 320, and the third via layer 330 on the uppermost side, the second wiring layer 220, the second via layer 230, the third wiring layer 320, and the third via layer 330 on the uppermost side may be removed. Afterwards, the second insulating layer 210 and the third insulating layer 310 on the uppermost side may be removed. Then, the second wiring layer 220, the second via layer 230, the third wiring layer 320, and the third via layer 330 disposed in the lower layer and exposed by removing each insulating layer may be recorded. By repeating this step, the signal transmission paths connected to each other may be identified. At this time, a process such as etching or layering may be used. However, embodiments thereof are not limited thereto, and in the case where there are other methods for analyzing the signal path, the method may be used without limitation.

[0093] In this case, each path can be connected by the shortest distance. In addition, the signal transmission in the first substrate 100 can be connected by the shortest path, but its embodiment is not limited thereto. Since the signal transmission through the first wiring layer 120 in the first substrate 100 corresponds to the transmission of a high-speed signal converted into a serial signal by the first SERDES chip 250, the signal transmission in the first substrate 100 may have a reduced signal loss. Therefore, as described above, the 1-1 insulating layer 111 may include an insulating material having a lower loss factor (Df) compared to the other first insulating layers 110 to minimize the signal loss. In addition, in order to minimize the loss of high-speed signals, each of the second via layer 230 used as the high-speed signal transmission path of the second substrate 201 and the third via layer 330 used as the high-speed signal transmission path of the third substrate 301 may have a stacked via form. In addition, when selecting materials for each component, a method for reducing signal loss may be considered so that any construction used in the technical field related to printed circuit boards and semiconductor packages can be used without limitation.

[0094] exist Figure 3 In the embodiment, the signal path may be represented as an example only, and it may not be necessary to convert two parallel signals or a plurality of parallel signals into a serial signal. However, the embodiment is not limited thereto, and there may be more signal paths, and there may be various signal paths such as a power line and a ground line as the signal path connected to the semiconductor chip.

[0095] Figure 4 FIG. 1 is a cross-sectional view showing a first package of a semiconductor package according to an embodiment. Figure 4 Only the Figure 3 The first package 200 in the semiconductor package of the embodiment is described above, and thus repeated description will not be provided.

[0096] In the first package 200, the width of the first semiconductor chip 270 may be narrower than the width of the second substrate 201, and the first package 200 may correspond to a fan-out package. Unlike the general fan-out package as described above, the first package 200 may be implemented to correspond to the fan-out package without including a redistribution layer. For example, the pitch may be adjusted so that the number of 1-1 connection members 401 may be less than the number of first connection members 271, and the wiring density of the second wiring layer 220 may be substantially the same instead of being different for each layer.

[0097] In an embodiment, substantially the same configuration may include similar configurations and may include, for example, an error in a manufacturing process or an error in a measurement process.

[0098] although Figure 4Only the first package 200 is illustrated as an embodiment, but the embodiment thereof is not limited thereto and the same description may be applied to the second package 300 .

[0099] Figure 5 is a cross-sectional view showing a first package according to another embodiment. Figure 5 Among the components in FIG. 1 , repeated description will not be provided for the first package 200 .

[0100] In the first package 200, the width of the first semiconductor chip 270 may be similar to or substantially the same as the width of the second substrate 201, and the first package 200 may correspond to a fan-in type package. Unlike the general fan-in type package as described above, the first package 200 may be implemented to correspond to the fan-in type package without including fine wiring in the second substrate 201. For example, the pitch may be adjusted so that the number of 1-1 connection members 401 may be less than the number of first connection members 271, and the wiring density of the second wiring layer may be substantially the same instead of being different for each layer.

[0101] although Figure 5 Only the first package 200 is illustrated as an embodiment, but the same description may be applied to the second package 300 , but embodiments thereof are not limited thereto.

[0102] Figure 6 is a cross-sectional view showing a semiconductor package according to another embodiment.

[0103] Reference Figure 6 , the first package 200 of the semiconductor package according to another embodiment may be configured as a core-type substrate. The second insulating layer 210 may include a first core layer 211 and a second insulating layer 212 other than the first core layer 211. Specifically, the second substrate 201 may include a first core layer 211, a second insulating layer 212 disposed on or below the first core layer 211, a second wiring layer 220 disposed on and / or in the first core layer 211 and disposed on and / or in the second insulating layer 212, and a first cavity penetrating at least a portion of the first core layer 211. The first SERDES chip 250 is disposed in the first cavity.

[0104] In addition, the third insulating layer 310 may include a second core layer 311 and a third insulating layer 312 other than the second core layer 311. Specifically, the third substrate 301 may include a second core layer 311, a third insulating layer 312 disposed on or below the second core layer 311, a third wiring layer 320 disposed on and / or in the second core layer 311 and disposed on and / or in the third insulating layer 312, and a second cavity penetrating at least a portion of the second core layer 311. The second SERDES chip 350 is disposed in the second cavity.

[0105] The core layers 211 and 311 of the second substrate 201 and the third substrate 301 may include materials different from those of the second insulating layer 212 and the third insulating layer 312, respectively. For example, the materials of the core layers 211 and 311 may be insulating materials such as prepreg (PPG), resin coated copper (RCC), or copper clad laminate (CCL), but embodiments are not limited thereto. The first SERDES chip 250 may be mounted in a cavity formed in the core layer, but embodiments are not limited thereto.

[0106] Figure 6 The second substrate 201 of the first package 200 and the third substrate 301 of the second package 300 are illustrated as core type substrates, but embodiments thereof are not limited thereto, and the first package 200 and the second package 300 may not necessarily be limited to the same type of substrates.

[0107] In the components of the first package 200 except the second insulating layer 210, Figure 3 The components of the semiconductor package of the illustrated embodiment are the same as those of the semiconductor package of the embodiment shown in FIG. Figure 6 A semiconductor package of another embodiment is shown, and therefore, a repeated description will not be provided.

[0108] Figure 7 It shows that according to Figure 6 A cross-sectional view of a first package of a semiconductor package according to another embodiment of the present invention. Figure 8 is a cross-sectional view showing a first package according to still another embodiment.

[0109] because Figure 7 Only the Figure 6 The first package 200 in the semiconductor package of another embodiment is described above, and therefore, no repeated description will be provided. Figure 7 ,according to Figure 6 The first package of the semiconductor package of another embodiment may correspond to a fan-out type package.

[0110] Reference Figure 8 , the first package according to still another embodiment may correspond to a fan-in type package.

[0111] although Figure 7 and Figure 8 Only the first package 200 is illustrated as an embodiment, but the embodiment is not limited thereto, and the same description may be applied to the second package 300 .

[0112] According to the aforementioned example embodiments, a semiconductor package may be provided which may perform chip-to-chip interconnection in a package including a semiconductor chip.

[0113] Furthermore, a semiconductor package including a simplified wiring structure in chip-to-chip interconnection can be provided.

[0114] Furthermore, a semiconductor package for improving reliability can be provided.

[0115] In the present disclosure, the shape on the cross section may refer to the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from a side view. In addition, the shape on the plane may be the shape when the object is cut horizontally, or the plane shape when the object is viewed from a top view or an upward view.

[0116] In the present disclosure, the lower side, lower part, lower surface, etc. are used to refer to the direction toward the mounting surface of the semiconductor package based on the cross section of the drawings, and the upper side, upper part, upper surface, etc. are used to indicate the opposite direction. However, the direction is defined for convenience of description, and the scope of the claims is not limited to any specific example described by the direction.

[0117] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection", for example, connection through an adhesive layer, etc. In addition, the term "electrical connection" may include both a case where an element is "physically connected" and a case where an element is "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of rights of example embodiments.

[0118] In the example embodiments, the term "example embodiment" may not refer to the same example embodiment, and may be provided to describe and emphasize different unique features of each example embodiment. The example embodiments suggested above may be implemented, and the possibility of combining with features of other example embodiments is not excluded. For example, even if a feature described in one example embodiment is not described in another example embodiment, the description may be understood to be related to another example embodiment unless otherwise stated.

[0119] An expression used in the singular includes an expression in the plural unless it has an apparently different meaning in the context.

[0120] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A first substrate including a first insulating layer and a first wiring layer disposed on and / or in the first insulating layer; a first package disposed on the first substrate and comprising a second substrate, a first semiconductor chip disposed on the second substrate, a first connecting member connecting the second substrate to the first semiconductor chip, and a first SERDES chip embedded in the second substrate; a second package disposed on the first substrate and comprising a third substrate, a second semiconductor chip disposed on the third substrate, a second connecting member connecting the third substrate to the second semiconductor chip, and a second SERDES chip embedded in the third substrate; 1-1 a connecting member, connecting the first substrate to the first package; as well as 2-1 a connecting member, connecting the first substrate to the second package, wherein the number of the first connecting members is greater than the number of the 1-1 connecting members, and Wherein, the number of the second connecting components is greater than the number of the 2-1 connecting components.

2. The semiconductor package according to claim 1, in, The second substrate includes a second insulating layer and a second wiring layer disposed on and / or in the second insulating layer, and The pitch of one of the second wiring layers connected to the first connection member is smaller than the pitch of another of the second wiring layers connected to the 1-1 connection member.

3. The semiconductor package according to claim 2, in, The third substrate includes a third insulating layer and a third wiring layer disposed on and / or in the third insulating layer, and Among them, a pitch of one of the third wiring layers connected to the second connection member is smaller than a pitch of another of the third wiring layers connected to the 2-1 connection member.

4. The semiconductor package according to claim 1, in, The first insulating layer includes a plurality of first insulating layers, and The loss factor of the uppermost 1-1 insulation layer among the plurality of first insulation layers is smaller than the loss factors of other first insulation layers among the plurality of first insulation layers.

5. The semiconductor package according to claim 4, wherein: The first semiconductor chip is connected to the second semiconductor chip through the first wiring layer provided on and / or in the 1-1 insulating layer.

6. The semiconductor package according to any one of claims 1 to 5, in, The first SERDES chip includes a serializer chip, and Wherein, the second SERDES chip includes a deserializer chip.

7. The semiconductor package according to claim 6, in, The serializer chip comprises a first connection pad, Wherein, the deserializer chip includes a second connection pad, Among the first connection pads, the number of input connection pads is greater than the number of output connection pads, and Among the second connection pads, the number of output connection pads is greater than the number of input connection pads.

8. The semiconductor package according to claim 1, in, The second substrate includes a second insulating layer, a second wiring layer disposed on and / or in the second insulating layer, and a first cavity penetrating at least a portion of the second insulating layer, and Wherein, the first SERDES chip is arranged in the first cavity.

9. The semiconductor package according to claim 8, in, The third substrate includes a third insulating layer, a third wiring layer disposed on and / or in the third insulating layer, and a second cavity penetrating at least a portion of the third insulating layer, and Wherein, the second SERDES chip is arranged in the second cavity.

10. The semiconductor package according to claim 9, in, The second substrate further includes a first bonding member between the first SERDES chip and a bottom surface of the first cavity, and The third substrate further includes a second adhesive member between the second SERDES chip and the bottom surface of the second cavity.

11. The semiconductor package according to claim 1, in, The second substrate includes a first core layer, a second insulating layer disposed on or below the first core layer, a second wiring layer disposed on and / or in the first core layer and disposed on and / or in the second insulating layer, and a first cavity penetrating at least a portion of the first core layer, wherein the first SERDES chip is disposed in the first cavity, and Wherein, the first core layer comprises a material different from that of the second insulating layer.

12. The semiconductor package according to claim 11, in, The third substrate includes a second core layer, a third insulating layer disposed on or below the second core layer, a third wiring layer disposed on and / or in the second core layer and disposed on and / or in the third insulating layer, and a second cavity penetrating at least a portion of the second core layer, wherein the second SERDES chip is disposed in the second cavity, and Wherein, the second core layer comprises a material different from that of the third insulating layer.

13. The semiconductor package according to claim 1, in, The second substrate includes a second insulating layer and a second wiring layer disposed on and / or in the second insulating layer. The third substrate includes a third insulating layer and a third wiring layer arranged on and / or in the third insulating layer, and Wherein, the second insulating layer and the third insulating layer include organic materials.

14. The semiconductor package according to claim 1, wherein The first substrate, the second substrate, and the third substrate are disposed to be spaced apart from each other.

15. A semiconductor package, comprising: A first substrate including a first insulating layer and a first wiring layer disposed on and / or in the first insulating layer; a first package disposed on the first substrate and comprising a second substrate, a first semiconductor chip disposed on the second substrate, a first connecting member connecting the second substrate to the first semiconductor chip, and a first SERDES chip embedded in the second substrate; a second package disposed on the first substrate and comprising a third substrate, a second semiconductor chip disposed on the third substrate, a second connecting member connecting the third substrate to the second semiconductor chip, and a second SERDES chip embedded in the third substrate; 1-1 a connecting member, connecting the first substrate to the first package; as well as 2-1 a connecting member, connecting the first substrate to the second package, The first semiconductor chip and the second semiconductor chip are connected to each other through a path passing through the first SERDES chip, the second substrate, the first substrate, the third substrate, and the second SERDES chip.

16. The semiconductor package according to claim 15, in, The first SERDES chip includes a serializer chip, and Wherein, the second SERDES chip includes a deserializer chip.

17. The semiconductor package according to claim 16, in, The serializer chip includes a circuit configured to convert a parallel signal into a serial signal, and The deserializer chip includes a circuit configured to convert a serial signal into a parallel signal.

18. The semiconductor package according to claim 17, in, The number of signal paths output through the serializer chip is less than the number of signal paths output from the first semiconductor chip, and The number of signal paths input to the deserializer chip is less than the number of signal paths input to the second semiconductor chip.

19. The semiconductor package according to claim 15, in, The second substrate includes a second insulating layer, a second wiring layer disposed on and / or in the second insulating layer, and a first cavity penetrating at least a portion of the second insulating layer, and Wherein, the first SERDES chip is arranged in the first cavity.

20. The semiconductor package according to claim 15, in, The second substrate includes a first core layer, a second insulating layer disposed on or below the first core layer, a second wiring layer disposed on and / or in the first core layer and disposed on and / or in the second insulating layer, and a first cavity penetrating at least a portion of the first core layer, wherein the first SERDES chip is disposed in the first cavity, and Wherein, the first core layer comprises a material different from that of the second insulating layer.

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