Synchronous rectification circuit and control method thereof

Abstract

The invention relates to the technical field of synchronous rectification control, and relates to a synchronous rectification circuit and a control method thereof. The method comprises the following steps: in a first working stage, controlling to switch on a first MOS (Metal Oxide Semiconductor) tube, a fourth MOS tube and a fifth MOS tube and switch off other MOS tubes; in the second working stage, the full-bridge rectifying circuit and the sixth MOS tube are controlled to be switched off, and the fifth MOS tube is switched on; in the third working stage, the full-bridge rectification circuit is controlled to be switched off, and a fifth MOS tube and a sixth MOS tube are switched on; in the fourth working stage, the full-bridge rectifying circuit and the fifth MOS tube are controlled to be switched off, and the sixth MOS tube is switched on; in the fifth working stage, the second MOS tube, the third MOS tube and the sixth MOS tube are controlled to be switched on, and other MOS tubes are switched off; in the sixth working stage, the full-bridge rectifying circuit and the fifth MOS tube are controlled to be switched off, and the sixth MOS tube is switched on; in the seventh working stage, the full-bridge rectification circuit is controlled to be switched off, and a fifth MOS tube and a sixth MOS tube are controlled to be switched on; in the eighth working stage, the full-bridge rectifying circuit and the sixth MOS tube are controlled to be disconnected, and the fifth MOS tube is controlled to be connected. According to the invention, loss can be reduced and efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of synchronous rectification control, and in particular to a synchronous rectification circuit and a control method thereof. Background Art

[0002] The synchronous rectification circuit is suitable for medium and high power applications. It uses synchronous rectification MOS tubes to replace the rectifier diodes in general applications. That is, MOS tubes are used for rectification on the secondary side of the transformer. Compared with the diode rectification method, it reduces losses and improves system efficiency.

[0003] However, in the existing synchronous rectification method using MOS tubes, the turn-on and turn-off of the synchronous rectification MOS tube are completely synchronized and consistent with the diagonal MOS tube on the primary side, which will cause the secondary side freewheeling inductor current to flow through the body diode of the synchronous rectification MOS tube, causing large losses, thereby reducing system efficiency.

[0004] Therefore, the existing synchronous rectification method using MOS tubes is not ideal in terms of loss and system efficiency and needs to be further optimized. Summary of the invention

[0005] The technical problem to be solved by the embodiments of the present invention is to provide a synchronous rectification circuit and a control method thereof to solve the problem that the synchronous rectification method using MOS tubes in the prior art is not ideal in terms of loss and system efficiency.

[0006] The present invention discloses a synchronous rectification control method, which is applied to a synchronous rectification circuit. The synchronous rectification circuit comprises a fifth MOS tube, a sixth MOS tube, a transformer, an inductor, an energy storage capacitor, and a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube connected to form a full-bridge rectification circuit. The intermediate nodes of the first MOS tube and the second MOS tube are connected to the same-name end of the primary side of the transformer, the intermediate nodes of the third MOS tube and the fourth MOS tube are connected to the opposite-name end of the primary side of the transformer, the fifth MOS tube is connected in parallel with the sixth MOS tube, the drain of the fifth MOS tube is connected to the opposite-name end of the secondary side of the transformer, the drain of the sixth MOS tube is connected to the same-name end of the secondary side of the transformer, the source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the negative electrode of the power output end, the inductor is connected in series between the tap end of the secondary side of the transformer and the positive electrode of the power output end, the energy storage capacitor is connected in parallel between the positive electrode and the negative electrode of the power output end, and one switching cycle comprises a plurality of continuous working stages. The synchronous rectification control method comprises:

[0007] In the first working stage, the first MOS transistor, the fourth MOS transistor and the fifth MOS transistor are controlled to be turned on, and the other MOS transistors are turned off, so as to transfer energy from the primary side of the transformer to the secondary side;

[0008] In the second working stage, all MOS tubes and the sixth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the fifth MOS tube is controlled to be turned on to provide freewheeling for the inductor;

[0009] In the third working stage, all MOS tubes of the full-bridge rectifier circuit are controlled to be turned off, and the fifth MOS tube and the sixth MOS tube are controlled to be turned on to provide freewheeling current for the inductor;

[0010] In the fourth working stage, all MOS tubes and the fifth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the sixth MOS tube is controlled to be turned on to provide freewheeling for the inductor;

[0011] In the fifth working stage, the second MOS transistor, the third MOS transistor and the sixth MOS transistor are controlled to be turned on, and the other MOS transistors are turned off, so as to transfer energy from the primary side of the transformer to the secondary side;

[0012] In the sixth working stage, all MOS tubes and the fifth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the sixth MOS tube is controlled to be turned on to provide freewheeling for the inductor;

[0013] In the seventh working stage, all MOS tubes of the full-bridge rectifier circuit are controlled to be turned off, and the fifth MOS tube and the sixth MOS tube are controlled to be turned on to provide freewheeling for the inductor;

[0014] In the eighth working stage, all the MOS tubes and the sixth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the fifth MOS tube is controlled to be turned on to provide freewheeling for the inductor.

[0015] Optionally, a first drive signal is used to control the first MOS transistor and the fourth MOS transistor, a second drive signal is used to control the second MOS transistor and the third MOS transistor, a third drive signal is used to control the fifth MOS transistor, and a fourth drive signal is used to control the sixth MOS transistor, the first drive signal is 180° out of phase with the second drive signal, the first drive signal is complementary to the third drive signal, and the second drive signal is complementary to the fourth drive signal.

[0016] Optionally, the maximum duty cycle of the first driving signal and the second driving signal does not exceed 50%.

[0017] Optionally, the durations of the second working stage, the fourth working stage, the sixth working stage and the eighth working stage are all the same.

[0018] Optionally, the synchronous rectification control method further includes:

[0019] Sampling the inductor current value and comparing it with the preset current value;

[0020] If the inductor current value is greater than the preset current value, a normal driving signal is generated to control the conduction state of the fifth MOS tube and the sixth MOS tube;

[0021] If the inductor current value is less than the preset current value, no driving signal is generated to disconnect the fifth MOS transistor and the sixth MOS transistor.

[0022] The present invention also discloses a synchronous rectification circuit, which comprises a main control chip, a fifth MOS tube, a sixth MOS tube, a transformer, an inductor, an energy storage capacitor, and a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube connected to form a full-bridge rectification circuit, wherein the intermediate node of the first MOS tube and the second MOS tube is connected to the same-name end of the primary side of the transformer, the intermediate node of the third MOS tube and the fourth MOS tube is connected to the opposite-name end of the primary side of the transformer, the fifth MOS tube is connected in parallel with the sixth MOS tube, the drain of the fifth MOS tube is connected to the opposite-name end of the secondary side of the transformer, the drain of the sixth MOS tube is connected to the same-name end of the secondary side of the transformer, the source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the negative electrode of the power output end, the inductor is connected in series between the tap end of the secondary side of the transformer and the positive electrode of the power output end, the energy storage capacitor is connected in parallel between the positive electrode and the negative electrode of the power output end, the main control chip is connected to the gates of all MOS tubes and is controlled by applying the synchronous rectification control method according to any one of claims 1 to 5.

[0023] Optionally, the synchronous rectification circuit further includes a current sampling unit, a current comparison unit, a wave-by-wave current limiting unit and a driving unit. The current sampling unit is used to sample and obtain the inductor current and transmit it to the current comparison unit. The current comparison unit compares the received inductor current with a preset current value and outputs a wave-by-wave current limiting signal. The wave-by-wave current limiting unit generates a PWM signal based on the drive signal for the fifth MOS tube and the sixth MOS tube output by the main control chip and the wave-by-wave current limiting signal. The driving unit generates a synchronous rectification driving signal based on the PWM signal to drive the fifth MOS tube and the sixth MOS tube.

[0024] Optionally, the wave-by-wave current limiting unit includes a first Schmitt trigger, a second Schmitt trigger, a first AND gate and a second AND gate, the clock input end of the first Schmitt trigger receives the PWMH signal output by the main control chip, and the output end is connected to the first input end of the first AND gate, the clock input end of the second Schmitt trigger receives the PWML signal output by the main control chip, and the output end is connected to the first input end of the second AND gate, the reset input end of the first Schmitt trigger and the reset input end of the second Schmitt trigger both receive the wave-by-wave current limiting signal output by the current comparison unit, the second input end of the first AND gate receives the PWMH signal output by the main control chip, the second input end of the second AND gate receives the PWML signal output by the main control chip, and the output ends of the first AND gate and the second AND gate are both connected to the driving unit.

[0025] Optionally, the current sampling unit includes a sampling resistor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator, the sampling resistor is connected in series between the source of the fifth MOS tube and the negative electrode of the power supply output end, the first resistor is connected in series between one end of the sampling resistor and the in-phase input end of the first comparator, the second resistor is connected in series between the other end of the sampling resistor and the inverting input end of the first comparator, the third resistor is connected in series between an external reference voltage point and the in-phase input end of the first comparator, the fourth resistor is connected in series between the output end and the inverting input end of the first comparator, and the output end of the first comparator is also connected to the wave-by-wave current limiting unit.

[0026] Optionally, the wave-by-wave current limiting unit includes a second comparator, a fifth resistor and a sixth resistor, the fifth resistor is connected in series between the output of the first comparator and the in-phase input of the second comparator, the inverting input of the second comparator is used to receive a preset current value, the sixth resistor is connected in series between an external power supply and the output of the second comparator, and the output of the second comparator is also connected to the reset input of the first Schmitt trigger and the second Schmitt trigger.

[0027] Compared with the prior art, the synchronous rectification circuit and control method thereof provided by the embodiments of the present invention have the beneficial effect that: by dividing the switching cycle of the MOS tube into a plurality of continuous working stages, on the basis of normal control to transfer energy from the primary side of the transformer to the secondary side, the conduction time of the fifth MOS tube and the sixth MOS tube is increased when all four MOS tubes on the primary side are turned off, the inductor is freewheeled, and the dead time, i.e., the second, fourth, sixth and eighth working stages, is reasonably increased in the control of the fifth MOS tube and the sixth MOS tube to avoid short circuit and ensure reliable operation of the system. Compared with the existing method of turning off the freewheeling of the body diode of the MOS tube through the MOS tube, the loss is reduced and the system efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments, in which:

[0029] Figure 1 1 is a circuit diagram of an embodiment of a synchronous rectification circuit provided by an embodiment of the present invention;

[0030] Figure 2 It is a flow chart of an embodiment of a synchronous rectification control method provided by an embodiment of the present invention;

[0031] Figure 3 is a driving waveform diagram for driving the first to sixth MOS tubes in the synchronous rectification control method provided by an embodiment of the present invention;

[0032] Figure 4 is a module schematic diagram of another embodiment of a synchronous rectification circuit provided in an embodiment of the present invention;

[0033] Figure 5 It is a circuit diagram of a wave-by-wave current limiting unit connected to a main control chip and a driving unit provided by an embodiment of the present invention;

[0034] Figure 6 It is a circuit diagram of a current sampling unit connected to a current comparison unit provided by an embodiment of the present invention.

[0035] The reference numerals in the figures are:

[0036] U1, main control chip; Q1, first MOS tube; Q2, second MOS tube; Q3, third MOS tube; Q4, fourth MOS tube; Q5, fifth MOS tube; Q6, sixth MOS tube; T1, transformer; L1, inductor; C1, energy storage capacitor; Q1A, first Schmitt trigger; Q1B, second Schmitt trigger; U1A, first AND gate; U1B, second AND gate; R1, sampling resistor; R2, first resistor; R3, second resistor; R4, third resistor; R5, fourth resistor; R6, fifth resistor; R7, sixth resistor; U2A, first comparator; U2B, second comparator; 110, current sampling unit; 120, current comparison unit; 130, wave-by-wave current limiting unit; 140, driving unit. DETAILED DESCRIPTION

[0037] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. Now, in conjunction with the accompanying drawings, a preferred embodiment of the present invention is described in detail.

[0038] The embodiment of the present invention provides a synchronous rectification control method, which is applied to a synchronous rectification circuit. Figure 1The synchronous rectification circuit includes a fifth MOS transistor Q5, a sixth MOS transistor Q6, a transformer T1, an inductor L1, an energy storage capacitor C1, and a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, and a fourth MOS transistor Q4 connected to form a full-bridge rectification circuit. The middle node of the first MOS transistor Q1 and the second MOS transistor Q2 is connected to the same-name end of the primary side of the transformer T1, the middle node of the third MOS transistor Q3 and the fourth MOS transistor Q4 is connected to the opposite-name end of the primary side of the transformer T1, the fifth MOS transistor Q5 is connected in parallel with the sixth MOS transistor Q6, the drain of the fifth MOS transistor Q5 is connected to the opposite-name end of the secondary side of the transformer T1, the drain of the sixth MOS transistor Q6 is connected to the same-name end of the secondary side of the transformer T1, the source of the fifth MOS transistor Q5 and the source of the sixth MOS transistor Q6 are both connected to the negative electrode of the power output end, the inductor L1 is connected in series between the tap end of the secondary side of the transformer T1 and the positive electrode of the power output end, and the energy storage capacitor C1 is connected in parallel between the positive electrode and the negative electrode of the power output end.

[0039] The existing control of the synchronous rectification circuit is that, during the time period when all MOS tubes of the full-bridge rectification current are disconnected, the fifth MOS tube Q5 and the sixth MOS tube Q6 for realizing synchronous rectification on the secondary side are not turned on, and the inductor L1 current uses the body diodes of the fifth MOS tube Q5 and the sixth MOS tube Q6 for freewheeling. The body diodes of the fifth MOS tube Q5 and the sixth MOS tube Q6 both flow through half of the inductor L1 current, and the length of this time period increases with the increase of the input voltage, thereby causing the time for the synchronous rectification freewheeling current to flow through the body diode to become longer, resulting in greater conduction losses and lower system efficiency.

[0040] In the embodiment of the present application, a switching cycle includes a plurality of consecutive working stages, such as Figure 1 and Figure 2 As shown, the synchronous rectification control method of the embodiment of the present application includes:

[0041] S110, in the first working stage, the first MOS transistor Q1, the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are controlled to be turned on, and other MOS transistors are turned off to transfer energy from the primary side of the transformer T1 to the secondary side;

[0042] S120, in the second working stage, all MOS tubes and the sixth MOS tube Q6 of the full-bridge rectifier circuit are controlled to be disconnected, and the fifth MOS tube Q5 is controlled to be turned on to provide freewheeling for the inductor L1;

[0043] S130, in the third working stage, all MOS tubes of the full-bridge rectifier circuit are controlled to be turned off, and the fifth MOS tube Q5 and the sixth MOS tube Q6 are controlled to be turned on to provide freewheeling for the inductor L1;

[0044] S140, in the fourth working stage, all MOS tubes and the fifth MOS tube Q5 of the full-bridge rectifier circuit are controlled to be turned off, and the sixth MOS tube Q6 is controlled to be turned on to provide freewheeling for the inductor L1;

[0045] S150, the fifth working stage, controlling the second MOS transistor Q2, the third MOS transistor Q3 and the sixth MOS transistor Q6 to be turned on, and disconnecting other MOS transistors, so as to transfer energy from the primary side of the transformer T1 to the secondary side;

[0046] S160, sixth working stage, controlling to disconnect all MOS tubes and the fifth MOS tube Q5 of the full-bridge rectifier circuit, and controlling to turn on the sixth MOS tube Q6 to provide freewheeling for the inductor L1;

[0047] S170, the seventh working stage, controlling to disconnect all MOS tubes of the full-bridge rectifier circuit, and controlling to turn on the fifth MOS tube Q5 and the sixth MOS tube Q6 to provide freewheeling for the inductor L1;

[0048] S180, the eighth working stage, controlling to disconnect all MOS tubes and the sixth MOS tube Q6 of the full-bridge rectifier circuit, and controlling to turn on the fifth MOS tube Q5 to provide freewheeling for the inductor L1.

[0049] The present application divides the switching cycle of the MOS tube into a plurality of continuous working stages. On the basis of normally controlling the energy to be transferred from the primary side to the secondary side of the transformer T1, the conduction time of the fifth MOS tube Q5 and the sixth MOS tube Q6 is increased when all four MOS tubes on the primary side are turned off, so as to freewheel the inductor L1, and reasonably increase the dead time, i.e., the second, fourth, sixth and eighth working stages, in the control of the fifth MOS tube Q5 and the sixth MOS tube Q6 to avoid short circuit and ensure reliable operation of the system. Compared with the existing method of turning off the freewheeling of the body diode of the MOS tube by the MOS tube, the loss is reduced and the system efficiency is improved.

[0050] Specifically, in the first working stage, the first MOS tube Q1 and the fourth MOS tube Q4 in the full-bridge rectifier circuit are turned on, the input voltage is added to the primary side of the transformer T1, the voltage of the transformer T1 is positive at the top and negative at the bottom, and according to the polarity of the transformer T1, the fifth MOS tube Q5 on the secondary side is turned on to provide a current path, and the input energy is transferred to the secondary side; in the second working stage, the four MOS tubes of the full-bridge rectifier circuit on the primary side of the transformer T1 are all disconnected, the voltage on the primary side of the transformer T1 is 0, the fifth MOS tube Q5 on the secondary side is turned on, and the current of the inductor L1 is continued, and the sixth MOS tube Q6 on the secondary side is turned off and does not continue; in the third working stage, the four MOS tubes of the full-bridge rectifier circuit on the primary side are all disconnected, the voltage on the primary side of the transformer T1 is 0, and the fifth MOS tube Q6 on the secondary side is turned on to continue the current of the inductor L1. 5 and the sixth MOS tube Q6 are turned on at the same time, the fifth MOS tube Q5 and the sixth MOS tube Q6 simultaneously provide the inductor L1 with current freewheeling, each providing half of the inductor L1 current freewheeling path, each providing half of the inductor L1 current freewheeling path, because the inductor L1 current freewheeling path is divided into two parts, the voltage drop borne by each synchronous rectifier is reduced by half, which helps to reduce the power consumption and heat loss of each synchronous rectifier; in the fourth working stage, the four MOS tubes of the full-bridge rectifier circuit are all disconnected, and the primary voltage of the transformer T1 is 0. This period of time is the dead time set to avoid short circuit of the secondary side of the transformer T1. During this time, the four MOS tubes of the primary full-bridge rectifier circuit are all disconnected, and the sixth MOS tube Q6 of the secondary side is turned on, and the four MOS tubes of the primary full-bridge rectifier circuit are continuously disconnected. The current of the inductor L1 is freewheeling, and the fifth MOS tube Q5 on the secondary side is turned off and does not freewheel; in the fifth working stage, the second MOS tube Q2 and the third MOS tube Q3 of the input full-bridge rectifier circuit are turned on, and the input voltage Vin is added to the primary side of the transformer T1. The voltage of the transformer T1 is positive at the bottom and negative at the top. According to the polarity of the transformer T1, the sixth MOS tube Q6 on the secondary side is turned on to provide a current path, and the input energy is transferred to the secondary side; in the sixth working stage, the four MOS tubes of the primary full-bridge rectifier circuit are all disconnected, and the primary voltage of the transformer T1 is 0. This period of time is the dead time set to avoid short circuit of the secondary side of the transformer T1. During this time, the four MOS tubes on the primary side are all turned off, and the sixth MOS tube Q6 on the secondary side is turned on to freewheel the current of the inductor L1. , the fifth MOS tube Q5 on the secondary side is turned off and does not continue current; in the seventh working stage, the four MOS tubes of the primary full-bridge rectifier circuit are all disconnected, the primary voltage of the transformer T1 is 0, the fifth MOS tube Q5 and the sixth MOS tube Q6 are turned on at the same time, and the two synchronous rectifiers continue current to the inductor L1 at the same time, each providing half of the current continue current path of the inductor L1; in the eighth working stage, the four MOS tubes of the primary full-bridge rectifier circuit are all disconnected, and the primary voltage of the transformer T1 is 0. This period of time is the dead time set to avoid short circuit of the secondary side of the transformer T1. During this time, the four MOS tubes on the primary side are all turned off, the fifth MOS tube Q5 on the secondary side is turned on, and continues to continue current to the inductor L1, and the sixth MOS tube Q6 on the secondary side is turned off and does not continue current.

[0051] In this embodiment, the first drive signal is used to control the first MOS transistor Q1 and the fourth MOS transistor Q4, the second drive signal is used to control the second MOS transistor Q2 and the third MOS transistor Q3, the third drive signal is used to control the fifth MOS transistor Q5, and the fourth drive signal is used to control the sixth MOS transistor Q6. The first drive signal is 180° out of phase with the second drive signal, and the conduction state of the first MOS transistor Q1 and the fourth MOS transistor Q4 is staggered from the conduction state of the second MOS transistor Q2 and the third MOS transistor Q3. The first drive signal is complementary to the third drive signal, and the second drive signal is complementary to the fourth drive signal, so that the synchronous rectification function is realized with a relatively simple control logic.

[0052] In an optional embodiment of the present application, the maximum duty cycle of the first drive signal and the second drive signal does not exceed 50% to prevent the upper and lower tubes of the primary side of the transformer T1 from being directly connected. At the same time, the switching loss of the corresponding MOS tube can be reduced to improve efficiency. Optionally, the maximum duty cycle of the first drive signal and the second drive signal is 45%.

[0053] The driving waveforms of the first driving signal, the second driving signal, the third driving signal and the fourth driving signal are as follows: Figure 3 As shown, the T0-T1 time period corresponds to the first working stage, the T1-T2 time period corresponds to the second working stage, the T2-T3 time period corresponds to the third working stage, the T3-T4 time period corresponds to the fourth working stage, the T4-T5 time period corresponds to the fifth working stage, the T5-T6 time period corresponds to the sixth working stage, the T6-T7 time period corresponds to the seventh working stage, and the T7-T8 time period corresponds to the eighth working stage.

[0054] In an optional embodiment of the present application, the time of the second working stage, the fourth working stage, the sixth working stage and the eighth working stage are the same. The time of the second working stage, the fourth working stage, the sixth working stage and the eighth working stage is the dead time set to avoid short circuit of the secondary side of the transformer T1. Setting these dead times to be the same can simplify the control logic and reduce the complexity of the design.

[0055] In an optional embodiment of the present application, the synchronous rectification control method further includes:

[0056] Sampling and obtaining the current value of the inductor L1, and comparing it with the preset current value;

[0057] If the current value of the inductor L1 is greater than the preset current value, a normal driving signal is generated to control the conduction state of the fifth MOS transistor Q5 and the sixth MOS transistor Q6;

[0058] If the current value of the inductor L1 is less than the preset current value, no driving signal is generated to disconnect the fifth MOS transistor Q5 and the sixth MOS transistor Q6.

[0059] The current value of the inductor L1 is obtained by sampling and compared with the preset current value, and the conduction state of the fifth MOS tube Q5 and the sixth MOS tube Q6 is controlled according to the comparison result. When the current of the inductor L1 is less than the preset current value, the fifth MOS tube Q5 and the sixth MOS tube Q6 are disconnected to realize automatic detection of the direction of the output current of the inductor L1. When the current of the inductor L1 is reversed, the synchronous rectifier tube is automatically turned off to prevent current backflow, protect the synchronous rectifier circuit, improve the stability of the circuit system operation, and extend the service life of the circuit.

[0060] The present application also provides a synchronous rectification circuit. Figure 1 and Figure 2 As shown, the synchronous rectification circuit includes a main control chip U1, a fifth MOS tube Q5, a sixth MOS tube Q6, a transformer T1, an inductor L1, an energy storage capacitor C1, and a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3, and a fourth MOS tube Q4 connected to form a full-bridge rectification circuit. The middle node of the first MOS tube Q1 and the second MOS tube Q2 is connected to the same-name end of the primary side of the transformer T1, the middle node of the third MOS tube Q3 and the fourth MOS tube Q4 is connected to the opposite-name end of the primary side of the transformer T1, and the fifth MOS tube Q5 and the sixth MOS tube Q6 are connected to the same-name end of the primary side of the transformer T1. The MOS tubes Q6 are connected in parallel, the drain of the fifth MOS tube Q5 is connected to the opposite-name terminal of the secondary side of the transformer T1, the drain of the sixth MOS tube Q6 is connected to the same-name terminal of the secondary side of the transformer T1, the source of the fifth MOS tube Q5 and the source of the sixth MOS tube Q6 are both connected to the negative electrode of the power output terminal, the inductor L1 is connected in series between the tap end of the secondary side of the transformer T1 and the positive electrode of the power output terminal, the energy storage capacitor C1 is connected in parallel between the positive and negative electrodes of the power output terminal, and the main control chip U1 is connected to the gates of all MOS tubes and controls them by applying the above-mentioned synchronous rectification control method.

[0061] The present application divides the switching cycle of the MOS tube into a plurality of continuous working stages. On the basis of normally controlling the energy to be transferred from the primary side of the transformer T1 to the secondary side, the main control chip U1 increases the conduction time of the fifth MOS tube Q5 and the sixth MOS tube Q6 when all four MOS tubes on the primary side are turned off, so as to freewheel the inductor L1, and reasonably increases the dead time, i.e., the second, fourth, sixth and eighth working stages, in the control of the fifth MOS tube Q5 and the sixth MOS tube Q6 to avoid short circuit and ensure reliable operation of the system. Compared with the existing method of freewheeling through the body diode of the MOS tube by turning off the MOS tube, the loss is reduced and the system efficiency is improved.

[0062] The synchronous rectification circuit of the embodiment of the present application can be applied in a DC converter.

[0063] refer to Figure 4The synchronous rectification circuit also includes a current sampling unit 110, a current comparison unit 120, a wave-by-wave current limiting unit 130 and a driving unit 140. The current sampling unit 110 is used to sample and obtain the current of the inductor L1 and transmit it to the current comparison unit 120. The current comparison unit 120 compares the received current of the inductor L1 with a preset current value and outputs a wave-by-wave current limiting signal. The wave-by-wave current limiting unit 130 generates a PWM signal based on the drive signal of the fifth MOS tube Q5 and the sixth MOS tube Q6 output by the main control chip U1 and the wave-by-wave current limiting signal. The driving unit 140 generates a synchronous rectification drive signal based on the PWM signal to drive the fifth MOS tube Q5 and the sixth MOS tube Q6.

[0064] The current sampling unit 110 can effectively sample the current of the inductor L1, and transmit the sampled current of the inductor L1 to the current comparison unit 120. In this embodiment, by obtaining the current of the inductor L1 and comparing it with the preset current value, and based on the comparison result and the driving signal for the fifth MOS tube Q5 and the sixth MOS tube Q6 output by the main control chip U1, a synchronous rectification driving signal is generated to drive the fifth MOS tube Q5 and the sixth MOS tube Q6, so that when the current of the inductor L1 is reversed, the fifth MOS tube Q5 and the sixth MOS tube Q6 are automatically and timely controlled to be disconnected to prevent current backflow.

[0065] refer to Figure 4 and Figure 5 In an optional embodiment of the present application, the wave-by-wave current limiting unit 130 includes a first Schmitt trigger Q1A, a second Schmitt trigger Q1B, a first AND gate U1A and a second AND gate U1B, a clock input end of the first Schmitt trigger Q1A receives a PWMH signal output by the main control chip U1, and an output end is connected to a first input end of the first AND gate U1A, a clock input end of the second Schmitt trigger Q1B receives a PWML signal output by the main control chip U1, and an output end is connected to a first input end of the second AND gate U1B, a reset input end of the first Schmitt trigger Q1A and a reset input end of the second Schmitt trigger Q1B both receive a wave-by-wave current limiting signal output by the current comparison unit 120, a second input end of the first AND gate U1A receives a PWMH signal output by the main control chip U1, a second input end of the second AND gate U1B receives a PWML signal output by the main control chip U1, and output ends of the first AND gate U1A and the second AND gate U1B are both connected to the driving unit 140.

[0066] The Schmitt trigger is a comparator circuit that includes positive feedback. For a standard Schmitt trigger, when the input voltage is higher than the positive threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output does not change, that is, when the output flips from a high level to a low level, or from a low level to a high level, the corresponding threshold voltage is different.

[0067] The AND gate is a basic logic gate circuit that performs an AND operation.

[0068] By setting the first Schmitt trigger Q1A, the second Schmitt trigger Q1B, the first AND gate U1A and the second AND gate U1B, the current sampling unit 110 samples the output inductor L1 current, and the sampled single current of the inductor L1 is compared with a preset current value, that is, a preset inductor L1 current reverse threshold to generate a wave-by-wave current limiting signal. The wave-by-wave current limiting signal and the PWM signal generated and output by the main control are passed through the first Schmitt trigger Q1A, the second Schmitt trigger Q1B, the first AND gate U1A and the second AND gate U1B to generate a PWM driving signal, which is then driven by the driving unit 140 to drive the fifth MOS tube Q5 and the sixth MOS tube Q6.

[0069] When the current of the inductor L1 is greater than the preset current value, the current comparison unit 120 outputs a high level of a normal signal. When the current of the inductor L1 is less than the preset current value, the current comparison unit 120 outputs a low level of an abnormal signal. Both the high level and the low level are input to the reset input terminal of the first Schmitt trigger Q1A and the reset input terminal of the second Schmitt trigger Q1B. Specifically, the clock input end of the first Schmitt trigger Q1A inputs the PWMH signal generated by the main control chip U1, and the clock input end of the second Schmitt trigger Q1B inputs the PWML signal generated by the main control chip U1. When the current of the inductor L1 is normal, the output of the first Schmitt trigger Q1A is equivalent to the PWMH signal output by the main control chip U1, and the PWMH signal is sent to the second input end of the first AND gate U1A, and is sent to the drive unit 140 after the first AND gate U1A outputs the signal PWMH; the output of the second Schmitt trigger Q1B is equivalent to the PWML signal output by the main control chip U1, and the PWML signal is sent to the second input end of the second AND gate U1B, and is sent to the drive unit 140 after the second AND gate U1B outputs the signal PWML. When the current of the inductor L1 is abnormal, the current comparison unit 120 outputs a low level of the abnormal signal, and the PWMLH signal and the PWML signal generated by the main control chip U1 are processed by the wave-by-wave current limiting unit 130 without generating a driving signal, thereby turning off the synchronous rectifier tube. This operation can prevent the current backflow caused by long-term conduction of the synchronous rectifier MOSFET when charging with a low-power current.

[0070] like Figure 4 and Figure 6As shown, in an optional embodiment of the present application, the current sampling unit 110 includes a sampling resistor R1, a first resistor R2, a second resistor R3, a third resistor R4, a fourth resistor R5 and a first comparator U2A, the sampling resistor R1 is connected in series between the source of the fifth MOS tube Q5 and the negative electrode of the power output end, the first resistor R2 is connected in series between one end of the sampling resistor R1 and the non-inverting input end of the first comparator U2A, the second resistor R3 is connected in series between the other end of the sampling resistor R1 and the reverse input end of the first comparator U2A, the third resistor R4 is connected in series between the external reference voltage point and the non-inverting input end of the first comparator U2A, the fourth resistor R5 is connected in series between the output end and the reverse input end of the first comparator U2A, and the output end of the first comparator U2A is also connected to the wave-by-wave current limiting unit 130.

[0071] By setting the sampling resistor R1, the current of the inductor L1 is sampled by the current differential method to obtain a current differential signal. Since the differential signal contains the difference between the two signals, it has a good suppression effect on common-mode interference, which makes the differential sampling method more stable in a noisy environment; and the differential sampling method does not require a very precise reference voltage, it only needs to ensure that the reference voltages of the two signals are the same, which reduces the system's requirements for the stability of the reference voltage.

[0072] The first resistor R2, the second resistor R3, the third resistor R4, and the fourth resistor R5, together with the first comparator U2A, form an operational amplifier circuit to amplify the current differential signal so that the amplitude of the output signal increases by a required multiple of the input signal, thereby enhancing the signal strength; the operational amplifier circuit has the characteristics of high input impedance and low output impedance, can effectively isolate the input signal source and the output load, ensure the stability and reliability of signal transmission, and has a simple circuit structure.

[0073] refer to Figures 4 to 6 In an optional embodiment of the present application, the wave-by-wave current limiting unit 130 includes a second comparator U2B, a fifth resistor R6 and a sixth resistor R7. The fifth resistor R6 is connected in series between the output end of the first comparator U2A and the non-inverting input end of the second comparator U2B. The inverting input end of the second comparator U2B is used to receive a preset current value. The sixth resistor R7 is connected in series between the external power supply and the output end of the second comparator U2B. The output end of the second comparator U2B is also connected to the reset input end of the first Schmitt trigger Q1A and the second Schmitt trigger Q1B.

[0074] A current comparison circuit is formed by setting a second comparator U2B, a fifth resistor R6 and a sixth resistor R7 to compare the sampled current of the inductor L1 with a preset current value to obtain a wave-by-wave current limiting signal. The wave-by-wave current limiting signal is used as an input signal of the reset input terminal of the first Schmitt trigger Q1A and the second Schmitt trigger Q1B. After being processed by the Schmitt trigger and the corresponding logic gate, a normal driving signal is output, or no driving signal is generated.

[0075] In an optional embodiment of the present application, the driving unit 140 may adopt a dual-channel MOS transistor driving chip, and may output a synchronous rectification driving signal for driving the fifth MOS transistor Q5 and the sixth MOS transistor Q6 based on the PWMH signal output by the first AND gate U1A and the PWML signal output by the second AND gate U1B.

[0076] The dual-channel MOS tube driver chip has the characteristics of fast response speed, strong driving capability and low power consumption. It integrates multiple functional modules, which can simplify circuit design, reduce the number of external components, reduce the overall circuit complexity, and improve the stability and reliability of the system.

[0077] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. For those skilled in the art, the technical solutions described in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents; and all these modifications and replacements should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A synchronous rectification control method, applied to a synchronous rectification circuit, characterized in that: The synchronous rectification circuit includes a fifth MOS tube, a sixth MOS tube, a transformer, an inductor, an energy storage capacitor, and a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube connected to form a full-bridge rectification circuit. The intermediate node of the first MOS tube and the second MOS tube is connected to the same-name end of the primary side of the transformer, and the intermediate node of the third MOS tube and the fourth MOS tube is connected to the opposite-name end of the primary side of the transformer. The fifth MOS tube is connected in parallel with the sixth MOS tube. The drain of the fifth MOS tube is connected to the opposite-name end of the secondary side of the transformer, and the drain of the sixth MOS tube is connected to the same-name end of the secondary side of the transformer. The source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the negative electrode of the power output end. The inductor is connected in series between the tap end of the secondary side of the transformer and the positive electrode of the power output end. The energy storage capacitor is connected in parallel between the positive and negative electrodes of the power output end. One switching cycle includes multiple continuous working stages. The synchronous rectification control method includes: In the first working stage, the first MOS transistor, the fourth MOS transistor and the fifth MOS transistor are controlled to be turned on, and the other MOS transistors are turned off, so as to transfer energy from the primary side of the transformer to the secondary side; In the second working stage, all MOS tubes and the sixth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the fifth MOS tube is controlled to be turned on to provide freewheeling for the inductor; In the third working stage, all MOS tubes of the full-bridge rectifier circuit are controlled to be turned off, and the fifth MOS tube and the sixth MOS tube are controlled to be turned on to provide freewheeling current for the inductor; In the fourth working stage, all MOS tubes and the fifth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the sixth MOS tube is controlled to be turned on to provide freewheeling for the inductor; In the fifth working stage, the second MOS transistor, the third MOS transistor and the sixth MOS transistor are controlled to be turned on, and the other MOS transistors are turned off, so as to transfer energy from the primary side of the transformer to the secondary side; In the sixth working stage, all MOS tubes and the fifth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the sixth MOS tube is controlled to be turned on to provide freewheeling for the inductor; In the seventh working stage, all MOS tubes of the full-bridge rectifier circuit are controlled to be turned off, and the fifth MOS tube and the sixth MOS tube are controlled to be turned on to provide freewheeling for the inductor; In the eighth working stage, all the MOS tubes and the sixth MOS tube of the full-bridge rectifier circuit are controlled to be disconnected, and the fifth MOS tube is controlled to be turned on to provide freewheeling for the inductor.

2. The synchronous rectification control method according to claim 1, characterized in that: A first drive signal is used to control the first MOS transistor and the fourth MOS transistor, a second drive signal is used to control the second MOS transistor and the third MOS transistor, a third drive signal is used to control the fifth MOS transistor, and a fourth drive signal is used to control the sixth MOS transistor, the first drive signal is 180° out of phase with the second drive signal, the first drive signal is complementary to the third drive signal, and the second drive signal is complementary to the fourth drive signal.

3. The synchronous rectification control method according to claim 2, characterized in that: The maximum duty cycle of the first driving signal and the second driving signal does not exceed 50%.

4. The synchronous rectification control method according to claim 1, characterized in that: The durations of the second working stage, the fourth working stage, the sixth working stage and the eighth working stage are all the same.

5. The synchronous rectification control method according to any one of claims 1 to 4, characterized in that: The synchronous rectification control method further includes: Sampling the inductor current value and comparing it with the preset current value; If the inductor current value is greater than the preset current value, a normal driving signal is generated to control the conduction state of the fifth MOS tube and the sixth MOS tube; If the inductor current value is less than the preset current value, no driving signal is generated to disconnect the fifth MOS transistor and the sixth MOS transistor.

6. A synchronous rectification circuit, characterized in that: The synchronous rectification circuit includes a main control chip, a fifth MOS tube, a sixth MOS tube, a transformer, an inductor, an energy storage capacitor, and a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube connected to form a full-bridge rectification circuit, wherein the intermediate node of the first MOS tube and the second MOS tube is connected to the same-name end of the primary side of the transformer, the intermediate node of the third MOS tube and the fourth MOS tube is connected to the opposite-name end of the primary side of the transformer, the fifth MOS tube is connected in parallel with the sixth MOS tube, the drain of the fifth MOS tube is connected to the opposite-name end of the secondary side of the transformer, the drain of the sixth MOS tube is connected to the same-name end of the secondary side of the transformer, the source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the negative electrode of the power output end, the inductor is connected in series between the tap end of the secondary side of the transformer and the positive electrode of the power output end, the energy storage capacitor is connected in parallel between the positive electrode and the negative electrode of the power output end, the main control chip is connected to the gates of all MOS tubes and is controlled by applying the synchronous rectification control method according to any one of claims 1 to 5.

7. The synchronous rectification circuit according to claim 6, characterized in that: The synchronous rectification circuit also includes a current sampling unit, a current comparison unit, a wave-by-wave current limiting unit and a driving unit. The current sampling unit is used to sample and obtain the inductor current and transmit it to the current comparison unit. The current comparison unit compares the received inductor current with a preset current value and then outputs a wave-by-wave current limiting signal. The wave-by-wave current limiting unit generates a PWM signal based on the drive signal output by the main control chip to the fifth MOS tube and the sixth MOS tube and the wave-by-wave current limiting signal. The driving unit generates a synchronous rectification driving signal based on the PWM signal to drive the fifth MOS tube and the sixth MOS tube.

8. The synchronous rectification circuit according to claim 7, characterized in that: The wave-by-wave current limiting unit includes a first Schmitt trigger, a second Schmitt trigger, a first AND gate and a second AND gate. The clock input end of the first Schmitt trigger receives the PWMH signal output by the main control chip, and the output end is connected to the first input end of the first AND gate. The clock input end of the second Schmitt trigger receives the PWML signal output by the main control chip, and the output end is connected to the first input end of the second AND gate. The reset input end of the first Schmitt trigger and the reset input end of the second Schmitt trigger both receive the wave-by-wave current limiting signal output by the current comparison unit. The second input end of the first AND gate receives the PWMH signal output by the main control chip, and the second input end of the second AND gate receives the PWML signal output by the main control chip. The output ends of the first AND gate and the second AND gate are both connected to the driving unit.

9. The synchronous rectification circuit according to claim 8, characterized in that: The current sampling unit includes a sampling resistor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator. The sampling resistor is connected in series between the source of the fifth MOS tube and the negative electrode of the power output end. The first resistor is connected in series between one end of the sampling resistor and the in-phase input end of the first comparator. The second resistor is connected in series between the other end of the sampling resistor and the inverting input end of the first comparator. The third resistor is connected in series between an external reference voltage point and the in-phase input end of the first comparator. The fourth resistor is connected in series between the output end and the inverting input end of the first comparator. The output end of the first comparator is also connected to the wave-by-wave current limiting unit.

10. The synchronous rectification circuit according to claim 9, characterized in that: The wave-by-wave current limiting unit includes a second comparator, a fifth resistor and a sixth resistor. The fifth resistor is connected in series between the output of the first comparator and the non-inverting input of the second comparator. The inverting input of the second comparator is used to receive a preset current value. The sixth resistor is connected in series between an external power supply and the output of the second comparator. The output of the second comparator is also connected to the reset input of the first Schmitt trigger and the second Schmitt trigger.

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