Hall sensor fault identification circuit and method for brushless direct current motor

Abstract

The invention discloses a brushless direct current motor-oriented Hall sensor fault identification circuit and identification method, and aims to improve the reliability and safety of a motor control system in the fields of electric vehicles and the like. The fault identification circuit comprises a signal detection and recording module, a fault identification module, a fault detection module, a fault recovery detection module and an overtime detection module, and can identify faults of one or more Hall sensors in time and provide signals when the sensors are recovered. Through the three parallel detection circuits, faults are accurately detected, different installation and rotation modes are supported, and the fault detection speed and accuracy of the brushless direct current motor are improved.

Description

Technical Field

[0001] The invention relates to a Hall sensor fault identification circuit for a brushless DC motor and also relates to a corresponding Hall sensor fault identification method, belonging to the technical field of motor control. Background Art

[0002] In the field of electric vehicles, brushless DC motors are widely used in multiple key systems due to their precise speed control capabilities, including electric power steering systems, electronic suspension systems, vehicle stability control systems, vehicle cruise control systems, anti-lock braking systems (ABS), and body control systems, etc. These systems have extremely high requirements for the reliability and stability of the motors to ensure the driving safety and performance of the vehicle.

[0003] However, the six-step commutation technology commonly used in existing brushless DC motors has a potential risk, which requires that all three Hall sensors must work normally to ensure that the motor can commutate and operate normally in six directions. If any Hall sensor fails, the motor may stop suddenly, which may cause serious safety problems in electric vehicles traveling at high speeds. Therefore, when the Hall sensor is damaged, how to ensure that the motor can maintain normal commutation and operation has become a technical issue that needs to be solved urgently. Especially during the driving of electric vehicles, if the motor suddenly stops due to damage to the Hall sensor, it may directly lead to traffic accidents. Therefore, when the Hall sensor is damaged, it is necessary to timely and automatically identify which path has failed, which helps to achieve rapid recovery. Even better, after taking recovery measures, it is also necessary to automatically identify whether multiple Hall sensors have all recovered.

[0004] In the Chinese invention patent with patent number ZL 201811482358.7, a real-time fault identification and reconstruction method for the Hall sensor of a brushless DC motor is disclosed. This method can identify the Hall sensor fault of the brushless DC motor in real time and complete the Hall signal reconstruction when the brushless DC motor is running. As long as one phase of the Hall signal of the brushless DC motor is correct, the other Hall signals can be reconstructed to ensure the normal operation of the high-speed motor; when all the Hall signals fail, it can ensure that the motor does not have overcurrent and ensure the safety of the motor. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a Hall sensor fault identification circuit for a brushless DC motor.

[0006] Another technical problem to be solved by the present invention is to provide a Hall sensor fault identification method for a brushless DC motor.

[0007] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a Hall sensor fault identification circuit for a brushless DC motor is provided, comprising a signal detection and recording module, a fault identification module and a fault detection module; wherein:

[0009] The signal detection and recording module includes a three-way DFF trigger, whose input signals are the Hall sensor input signals of the three channels A, B, and C, a reset signal, a clock signal, and a Hall sensor start signal; wherein, the output of a high pulse of the Hall sensor start signal represents the start of automatic fault identification of the Hall sensor; when any one of the three channels A, B, and C has an edge change, the signal detection and recording module generates three pulse signals and inputs them into the fault identification module;

[0010] The fault identification module includes three detection modules, which are used to receive a clock signal, a reset signal and three pulse signals, and each detection module outputs a corresponding Hall sensor damage signal according to the three state change signals of the Hall sensor;

[0011] The fault detection module generates a comprehensive Hall sensor damage signal through logic operation according to the Hall sensor damage signals output by the three detection modules.

[0012] Preferably, the signal detection and recording module includes a D-type trigger and three XOR gate modules, the input end of the D-type trigger receives the Hall sensor input signals of three channels A, B, and C respectively, and under the control of the clock signal, the Hall sensor input signals of the three channels are cached in three DFF triggers respectively; in the three XOR gate modules, one input signal of each XOR gate is the output signal of the DFF trigger, and the other input signal is the original Hall sensor input signal.

[0013] Preferably, the first Hall sensor damage signal output by the first detection module and the second Hall sensor damage signal output by the second detection module are both input to the first OR gate; the first Hall sensor damage signal output by the third detection module and the first Hall sensor damage signal output by the fourth detection module are both input to the second OR gate; the second Hall sensor damage signal output by the fifth detection module and the second Hall sensor damage signal output by the sixth detection module are also input to the third OR gate; the first Hall sensor recovery signal of the seventh detection module and the eighth detection module are input to the fourth OR gate; the third Hall sensor recovery signal of the ninth detection module and the output of the fourth OR gate are input to the fifth OR gate; if the Hall sensor recovery signal of any fault detection module is high, the output of the fifth OR gate is high; if the fifth OR gate is low, it means that all Hall sensors have recovered from the fault state.

[0014] Preferably, in the detection module, the first Hall sensor state change signal is sent to the DFF register and the first AND gate; the first Hall sensor state change register signal generated by the DFF register is input to the DFF register record enable register to obtain an enable signal for controlling the recording of the 180° point periodic signal; the enable signal is sent to the first AND gate, the second AND gate and the third AND gate; the second AND gate receives the second Hall sensor state change signal and the enable signal; the output of the second AND gate is sent to the sixth OR gate; the input of the fourth AND gate is the output of the sixth OR gate and the output of the first NOT gate, and its output is sent to the second Hall sensor record front register end of the register; the second Hall sensor record signal output by the register is sent to the sixth OR gate, the second NOT gate and the fifth AND gate; its output of the third Hall sensor record signal is sent to the seventh OR gate, the first NOT gate and the second AND gate. Three NOT gates and a sixth AND gate; the third AND gate receives the third Hall sensor state change signal and the enable signal, and its output is sent to the seventh OR gate; the output of the seventh OR gate and the output of the first NOT gate are both sent to the seventh AND gate, and the output of the seventh AND gate is sent to the third Hall sensor recording front register end of the register; the first AND gate receives the enable signal and the first Hall sensor state change signal, and the output is sent to the fifth AND gate, the fourth AND gate, the sixth AND gate and the first NOT gate; the input of the sixth AND gate is the output of the fifth AND gate and the third Hall sensor recording signal, and the output is a Hall sensor recovery signal; the input of the fourth AND gate is the output of the first AND gate and the output of the second NOT gate, and the output of the fourth AND gate is the first Hall sensor damage signal; the input of the sixth AND gate is the output of the first AND gate and the output of the third NOT gate, and the output of the sixth AND gate is the second Hall sensor damage signal.

[0015] Preferably, the Hall sensor fault identification circuit also includes a timeout detection module, and the input signals of the timeout detection module are a Hall sensor start signal, a reset signal, a clock signal, and a first Hall sensor state change signal, a second Hall sensor state change signal, and a third Hall sensor state change signal; wherein the first Hall sensor state change signal, the second Hall sensor state change signal, and the third Hall sensor state change signal enter an eighth OR gate, a ninth OR gate, and a tenth OR gate respectively, and the outputs of these OR gates are connected to an eleventh AND gate for integrating the state changes of the Hall sensor; the timeout signal output by the eleventh AND gate is input to the eighth OR gate for indicating whether the state change of the Hall sensor is detected within the expected time.

[0016] Preferably, the clock signal drives two sequential logic blocks simultaneously, and the sequential logic blocks are responsible for generating a control signal, a timeout enable signal and a timeout counter clear signal, and managing the timeout counter; the timeout counter counts under the control of the timeout enable signal, and the timeout counter clear signal is used to clear the timer and reset the detection process.

[0017] Preferably, the timeout signal is also compared with the output of the timeout counter to determine whether a timeout fault occurs; if the Hall sensor does not change within the expected time, the timeout signal will remain at a high level, triggering the fault detection logic, thereby generating a corresponding fault indication signal.

[0018] Preferably, the Hall sensor of each channel is independently provided with a Hall sensor damage signal line for indicating whether a corresponding Hall sensor fails.

[0019] Preferably, the Hall sensor fault identification circuit further includes a fault recovery detection module, which determines whether all Hall sensors have been restored based on the Hall sensor recovery signals output by each of the three detection modules; if all Hall sensors have been restored, it outputs a fault recovery signal.

[0020] According to a second aspect of an embodiment of the present invention, a method for identifying a Hall sensor fault for a brushless DC motor is provided, comprising the following steps:

[0021] (1) Configure the forward and reverse direction of the motor and the installation method of the Hall sensor;

[0022] (2) The signal detection and recording module receives the Hall sensor input signals, reset signals, clock signals and Hall sensor start signals of the three channels A, B and C; when the Hall sensor start signal outputs a high pulse, it indicates that the automatic fault identification of the Hall sensor has begun; under the control of the clock signal, the signal detection and recording module caches the input signal into the DFF trigger and generates three pulse signals;

[0023] (3) The fault identification module receives the clock signal, the reset signal and the three-way pulse signal, and outputs the first Hall sensor damage signal and the second Hall sensor damage signal by each detection module according to these signals;

[0024] (4) The fault detection module generates a comprehensive Hall sensor damage signal through logical operation according to the first Hall sensor damage signal and the second Hall sensor damage signal output by the three detection modules.

[0025] Compared with the prior art, the present invention can provide a sensor damage signal in time when the Hall sensor is damaged or completely damaged, and can provide a recovery signal in time when the Hall sensor is restored; by utilizing three-way parallel detection circuits, the occurrence of damage can be accurately detected when any one way is damaged, and different installation methods and rotation methods of Hall sensors are supported; by using digital circuits, compared with independent components or analog circuits, the recognition is more accurate and the real-time performance is good, and it can be more conveniently integrated in the system circuit for use, and is suitable for harsh use environments such as electric vehicles. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the Hall sensor output waveform under different motor forward and reverse rotation and installation methods;

[0027] Figure 2 This is a schematic diagram of the principle of a first type of failure of a Hall sensor of a brushless DC motor in the first embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the principle of the second fault of the Hall sensor of the brushless DC motor in the first embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the principle of the third fault of the Hall sensor of the brushless DC motor in the first embodiment of the present invention;

[0030] Figure 5 A circuit block diagram of a Hall sensor fault identification circuit for a brushless DC motor in a first embodiment of the present invention;

[0031] Figure 6 A circuit schematic diagram of a Hall sensor fault identification circuit for a brushless DC motor in a first embodiment of the present invention;

[0032] Figure 7 This is a circuit schematic diagram of a detection module (u_hallX_autodet) in the first embodiment of the present invention;

[0033] Figure 8 FIG. 4 is a circuit schematic diagram of a timeout detection module in the first embodiment of the present invention. DETAILED DESCRIPTION

[0034] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] The technical concept of the embodiment of the present invention is: in a brushless DC motor system, Hall sensor fault detection is divided into three cases: the timeout fault is handled by the timeout detection module, and the other two faults are identified by the detection module (u_hallX_autodet). This module uses three DFF registers (D flip-flops) to monitor the waveform changes of hall0_change, hall1_change and hall2_change signals based on the principle that any one-phase Hall sensor must have two commutation points within a 180° electrical cycle, and promptly determines the occurrence of a fault and accurately points out which specific Hall sensor has a fault, thereby improving the speed and accuracy of fault detection.

[0036] First embodiment

[0037] In the six-step commutation control technology of brushless DC motors, Hall sensors can be used to detect the rotor position to control the motor commutation. Figure 1 As shown in the figure, before turning on the automatic commutation function, the circuit needs to be configured with motor parameters. Once the motor's forward or reverse direction (forward or reverse) and the installation method of the Hall sensor (60° or 120°) are determined, the commutation point of the other two Hall sensors can be estimated by the change of one Hall sensor. Specifically, Figure 1 It is shown in the figure that in the case of 120° forward rotation, within the 180° electrical cycle, channel B lags channel A by 120°; channel C lags channel B by 120°. In the case of 120° reverse rotation, within the 180° electrical cycle, channel B leads channel A by 120°; channel C leads channel B by 120°. In the case of 60° forward rotation, within the 180° electrical cycle, channel B lags channel A by 60°; channel C lags channel B by 60°. In the case of 60° reverse rotation, within the 180° electrical cycle, channel B leads channel A by 60°; channel C leads channel B by 60°. It can be seen that within the 180° electrical cycle of one phase, the other two phases must have two commutation points. There is no need to distinguish between true reversal and installation methods. Based on this point, it can be determined whether a Hall sensor failure occurs.

[0038] The Hall sensor fault identification circuit for a brushless DC motor provided in the first embodiment of the present invention distinguishes the situations where the Hall sensor fails into the following situations: Figures 2 to 4 Three situations are shown.

[0039] exist Figure 2 In the fault condition shown, when the motor is running normally and the automatic fault detection function is turned on, the Hall sensor fault identification circuit will automatically monitor the working status of the Hall sensor. Specifically, if less than two physical commutation points of the Hall sensor of channel B or channel C are observed within the 180° electrical cycle of channel A, this will be identified as a damage to the Hall sensor. Once this situation is detected, the circuit will generate a damage pulse event and send this event as an interrupt signal to the microcontroller (MCU) or other peripherals. At the same time, the ACE signal (enable signal) is set to indicate that the Hall sensor is damaged. On the contrary, if at least two physical commutation points are detected for each of channel B and channel C within the next 180° electrical cycle of channel A, this will be identified as the Hall sensor automatically recovering to normal. In this case, a recovery pulse event will be generated and this event will be sent as an interrupt signal to the MCU or other peripherals. At the same time, the ACE signal will be automatically cleared to indicate that the Hall sensor has resumed normal working state.

[0040] exist Figure 3In the fault condition shown, a parallel judgment method is used to detect the fault of the Hall sensor. Specifically, when using channel A for fault judgment, if channel A is damaged within the 180° electrical cycle, that is, channel B or channel C has less than two commutation points within the 180° electrical cycle, channel A is judged to be in a stagnant state until the 180° electrical cycle of channel A ends. In the present invention, the modules of the three channels A, B, and C work in parallel, which means that they can perform fault judgment at the same time. If module A fails, module B will take over the judgment work. During the judgment of module B, if it is found that there are less than two commutation points of channels A and C within the 180° electrical cycle of channel B, module B will generate a damage pulse signal. This design allows timely switching to a normal channel to continue fault judgment when any one or both channels are damaged.

[0041] exist Figure 4 In the fault condition shown, after Hall sensor A records only one commutation point, if channels A, B, and C fail at the same time, the automatic fault detection circuits of the three channels will not work properly and all will be in a failed state. At this time, the automatic timeout detection circuit will start to operate. If channels A, B, and C do not record any commutation points within the preset maximum time limit, a timeout pulse event will be triggered. This event indicates that all three Hall sensors have failed and an interrupt signal needs to be sent to the microcontroller or other peripherals. The timeout circuit is equipped with a counter that can provide a timeout period of up to 167 milliseconds when the clock frequency is 50MHz, which is the maximum time for timeout detection. The length of this counter can be adjusted according to the needs of the actual application scenario, but it must be ensured that this maximum timeout period is less than the time of 180° electrical cycle of the motor at the slowest speed. This design ensures that when all Hall sensors fail, the Hall sensor fault identification circuit can identify and respond in time to prevent potential global failures.

[0042] like Figure 5 and Figure 6As shown, the Hall sensor fault identification circuit provided by the embodiment of the present invention includes a signal detection and recording module, a fault identification module, a fault detection module, a fault recovery detection module and a timeout detection module. The signal detection and recording module includes three DFF triggers, and its input signals are: the hall_din signal of the three channels A, B, and C, the reset signal rst_n, the clock signal clk, and the hall_start signal (pulse input signal). The output of the hall_start signal high pulse represents the start of automatic fault identification of the Hall sensor. When any of the three channels A, B, and C has an edge change (rising edge or falling edge), the signal detection and recording module will generate three pulse signals (hall0_change, hall1_change, hall2_change) and input them into the fault identification module.

[0043] The fault identification module includes three detection modules, inputting clock signal (clk), reset signal (rst_n) and three pulse signals. According to the hall0_change, hall1_change, hall2_change signals, each detection module outputs hall1_damage and hall2_damage signals. If the damage signal outputs a high pulse, it means that the Hall sensor is damaged; if the recovery signal outputs a high pulse, it means that all the three Hall sensor signals have returned to normal.

[0044] The fault detection module generates a hall_damage signal according to the hall1_damage and hall2_damage signals output by the three detection modules.

[0045] The fault recovery detection module determines that all Hall sensors have recovered according to the hall_recovery signals output by the three detection modules respectively, and outputs a fault recovery signal (recovery).

[0046] Specifically, if Figure 6 As shown, the signal detection and recording module includes a D-type flip-flop (DFlip-Flop, DFF) and three XOR gate modules (RTL_XORx3). The inputs of the D-type flip-flop hall_din[0], hall_din[1], and hall_din[2] receive the hall_din inputs of the three channels A, B, and C respectively. Under the control of the clock signal (clk), the input data (hall_din) is latched to the output (hall_reg0) at the rising or falling edge of the clock. In this way, the signals of the three channels are cached in the three DFF flip-flops hall_reg0_reg[0], hall_reg0_reg[1], and hall_reg0_reg[2].

[0047] In the three XOR gate modules, one input of each XOR gate is the output of DFF (hall_reg0), and the other input is the original input signal (hall_din). When hall_din changes on the rising edge of the clock, since the output of DFF has latched the old value in the previous clock cycle, there will be a difference between the new input value and the output value of DFF, resulting in the XOR gate outputting a high-level pulse signal. That is, the three outputs of the DFF trigger, hall_reg0_reg[0], hall_reg0_reg[1], and hall_reg0_reg[2], respectively, perform XOR operations with the input signals hall_din[0], hall_din[1], and hall_din[2]. When any of the three channels A, B, and C has an edge change (rising edge or falling edge), a pulse signal will be generated, thereby obtaining three pulse signals, hall0_change, hall1_change, and hall2_change.

[0048] The pulse signals hall0_change, hall1_change, hall2_change are sent to the three detection modules (u_hall0_autodet, u_hall1_autodet, u_hall2_autodet) in the automatic fault detection module. Each detection module is responsible for detecting the fault of the corresponding channel. If a fault is detected, the module will output the hallX_damage signal.

[0049] The hall1_damage signal output by the detection module u_hall0_autodet and the hall2_damage signal output by the detection module u_hall2_autodet are input to an OR gate rtlc_124. The hall1_damage signal output by the detection module u_hall1_autodet and the hall1_damage signal output by the detection module u_hall2_autodet are input to another OR gate rtlc_122. The hall2_damage signal output by the detection module u_hall0_autodet and the hall2_damage signal output by the detection module u_hall1_autodet are also input to a third OR gate rtlc_126.

[0050] Moreover, the hall_recovery signals of the detection modules u_hall1_autodet and u_hall0_autodet are input to the OR gate rtlc_l31; the hall_recovery signal of the detection module hall2_autodet and the output of the OR gate rtlc_l31 are input to the OR gate rtlc_l32. Therefore, if the hall_recovery signal of any fault detection module is high, the output of the OR gate rtlc_l32 is high. If the OR gate rtlc_l32 is low (the hall_recovery signals of all fault detection modules are low), it means that all Hall sensors have recovered from the fault state.

[0051] In this way, the fault can be identified by detecting the edge change of the Hall sensor input signal, and it can be distinguished which sensor has a problem, and a clear indication is provided when the fault is restored.

[0052] When any of the Hall sensor damage signals (i.e. hall1_damage, hall2_damage, etc.) is triggered, it activates a composite Hall sensor damage signal (hall_damage). The activation of this composite signal indicates that at least one Hall sensor has failed. If this composite hall_damage signal is further subdivided into three separate signal lines, it is possible to accurately identify which specific Hall sensor has failed. This design can not only detect the failure of the Hall sensor, but also locate the specific faulty sensor, thereby improving the accuracy of fault diagnosis and the pertinence of the response.

[0053] like Figure 7 As shown, in the circuit of each detection module (u_hallX_autodet), the hall0_change signal (high level) is sent to a DFF register hall0_change_r_reg and an AND gate rtlc_130. Under the control of the clock signal, the pulse signal is recorded and delayed by one clock cycle, and the hall0_change_r signal obtained from the DFF register hall0_change_r_reg is input to the DFF register record_ena_reg to obtain the enable signal record_ena, which is used to control the recording of the 180° dot period signal. The enable signal record_ena is sent to the AND gate rtlc_130, the AND gate rtlc_116 and the AND gate rtlc_128.

[0054] The input signals of AND gate rtlc_116 are hall1_change signal and enable signal record_ena. The output of AND gate rtlc_116 is sent to OR gate rtlc_141. The input of AND gate rtlc_144 is the output of OR gate rtlc_141 and the output of NOT gate rtlc_147, and its output is sent to the hall1_record_pre terminal of the register. The hall1_record signal output by the register is sent to OR gate rtlc_141, NOT gate rtlc_132 and AND gate rtlc_138; its output hall2_record signal is sent to OR gate rtlc_145, NOT gate rtlc_135 and AND gate rtlc_139. The input of AND gate rtlc_128 is hall2_change signal and enable signal record_ena, and its output is sent to OR gate rtlc_145. The output of the OR gate rtlc_145 and the output of the NOT gate rtlc_147 are both sent to the AND gate rtlc_148, and the output of the AND gate rtlc_148 is sent to the hall2_record_pre terminal of the register.

[0055] The inputs of AND gate rtlc_130 are the enable signal record_ena and the hall0_change signal, and the output is sent to AND gate rtlc_138, AND gate rtlc_133, rtlc_136, and NOT gate rtlc_147. The inputs of AND gate rtlc_139 are the output of AND gate rtlc_138 and the hall2_record signal, and the output is the hall_recover signal. The inputs of AND gate rtlc_133 are the output of AND gate rtlc_130 and the output of NOT gate rtlc_132, and the output of AND gate rtlc_133 is the hall1_damage signal. The inputs of AND gate rtlc_136 are the output of AND gate rtlc_130 and the output of NOT gate rtlc_135, and the output of AND gate rtlc_136 is the hall2_damage signal.

[0056] During the period when record_ena_reg is high, that is, during the 180° electrical cycle of hall0, the changes of the hall1_change and hall2_change signals are recorded. These signals are processed by NAND gates (such as rtlc_122 and rtlc_128) to detect their edge changes. Then, these changes are combined with the state of record_ena_reg through OR gates (such as rtlc_138 and rtlc_139) to record the changes of the signals.

[0057] When the 180° electrical cycle ends, that is, record_ena_reg returns to 0, the automatic fault identification circuit will check the status of hall1_record_reg and hall2_record_reg. If both registers are 0, or one of them is 0, indicating that at least one Hall sensor signal has not changed, the automatic fault identification circuit will generate a corresponding damage pulse signal (hall1_damage or hall2_damage). On the contrary, if hall1_record_reg and hall2_record_reg are both 1, indicating that both phases are working normally, the automatic fault identification circuit will generate a fault recovery signal (recovery), indicating that the three phases of the Hall sensor are working normally.

[0058] In addition, the automatic fault identification circuit also includes a sequential logic module controlled by the record_ena signal. This module may be used to record changes in sensor status, or enable or disable the recording function under certain conditions, increasing the flexibility of the automatic fault identification circuit and enabling it to adapt to different application requirements. Through this design, the automatic fault identification circuit can accurately detect the signal changes of the Hall sensor, and record and respond to these changes at the appropriate time, thereby realizing the monitoring of the Hall sensor status and fault detection.

[0059] It should be noted that the u_hall1_autodet module or the u_hall2_autodet module is similar to the aforementioned u_hall0_autodet module and will not be described in detail here.

[0060] In order to accurately detect and distinguish the three types of Hall sensor faults— Figure 2 The Hall signal shown is lost (broken), Figure 3 Hall signal error (damage) and Figure 4 The following is a detailed description of the circuit to implement these detections:

[0061] Hall signal lost (broken) fault: such as Figure 2 As shown, this fault can be identified by detecting whether the signal of Hall sensor B or C changes within the expected time. If the signal of these sensors does not change as expected within the time when it should change from 60° to 90° or from 90° to 60°, it can be judged as a signal loss fault.

[0062] Hall signal error (damage) fault: such as Figure 3As shown, this fault refers to the signal of Hall sensor B or C not flipping correctly within the expected 180° electrical cycle. If the signal of Hall sensor B fails to properly transition state within the entire 180° electrical cycle, or the signal of Hall sensor C does not flip correctly within the expected 180° change, this indicates that a signal error fault may have occurred.

[0063] Timeout failure: Figure 4 As shown, a timeout fault usually means that the output of the Hall sensor does not change within a certain period of time, which means that the sensor does not detect any event. By setting a timer, if the output of the Hall sensor does not change within a predetermined time, a timeout fault will be triggered.

[0064] Assuming that the hall0_change signal is high, it is first sent to the DFF register hall0_change_r_reg to output the record_ena signal. The record_ena signal is sent to the AND gate rtlc_130. In the DFF register hall0_change_r_reg, if record_ena_reg is currently 0, the high level of record_ena will cause record_ena_reg to become 1 at the next edge of the clock signal. If record_ena_reg is already 1, the high level of record_ena will cause record_ena_reg to become 0 at the next edge of the clock signal. In this way, in each cycle of hall0_change, the record_ena signal switches between 1 and 0 under the control of the clock signal. Therefore, the inputs of the AND gate rtlc_130 are the enable signal record_ena and the hall0_change signal, and when the hall0_change signal is high in the current electrical cycle, the output of the AND gate rtlc_130 is controlled by record_ena. When record_ena is low, AND gates rtlc_138, rtlc_133, and rtlc_136 connected to the output of AND gate rtlc_130 are all low, and AND gate rtlc_139 connected to the output of AND gate rtlc_138 is also low. When record_ena and hall0_change are both high, AND gate rtlc_130 outputs a high level. AND gate rtlc_130 and hall1_record are inverted when the input of AND gate rtlc_133 is high. At the end of the 180° electrical cycle, the hall1_record state is written at a specific edge of the clock signal. Only when the AND gate rtlc_130 outputs a low level and is inverted by the NOT gate rtlc_147, it is input into the AND gate rtlc_144; and record_ena and hall1_change are both high levels, after passing through the AND gate rtlc_116, the OR gate rtlc_141 and the AND gate rtlc_144, the register hall1_record_pre is high level. At this time, the output signal hall1_damage of the AND gate rtlc_133 is high level, indicating that the B channel Hall sensor is faulty.

[0065] If the signal of Hall sensor B or C does not change as expected within a predetermined time (for example, the signal does not switch correctly between 60° to 90° or 90° to 60°), it may be identified as a broken fault. In addition, if the signal of Hall sensor B or C fails to flip correctly within a full 180° electrical cycle, this may also indicate that the sensor is faulty.

[0066] When phase A completes the recording of 180° electrical cycle, if both the record_ena signal and the hall1_change signal are 1, but the hall1_record signal fails to record any changes (i.e., the output of the inverter rtlc132 is 0), then after passing through the inverter rtlc132, the signal becomes 1. If both inputs of the AND gate rtlc133 are 1, this will cause the hall1_damage signal to output a high level, indicating that the Hall sensor B has failed.

[0067] Figure 8 The timeout detection module is shown to detect timeout faults. Timeout faults usually occur when the output of the Hall sensor does not change within a certain period of time, which means that the sensor has not detected any event. Therefore, by setting a timer, if the output of the Hall sensor does not change within a predetermined time, a timeout fault can be triggered.

[0068] The input signals of the timeout detection module are hall_start, rst_n, clk (clock signal) and the state change signals of the Hall sensor hall0_change, hall1_change and hall2_change. The hall_start signal is used to start the detection process, and the rst_n signal is used to reset the circuit.

[0069] In the Hall sensor fault identification circuit provided by the embodiment of the present invention, the first Hall sensor state change signal hall0_change and the output signal timeout of the multiplexer rtlc_17 are used as inputs and enter the OR gate rtlc_111. The output of the OR gate rtlc_111 is then connected to the second Hall sensor state change signal hall1_change and input to the OR gate rtlc_113. Then, the output of the OR gate rtlc_113 is connected to the third Hall sensor state change signal hall2_change and used as the input of the OR gate rtlc_115. The output of the OR gate rtlc_115 is connected to the timeout counter clearing terminal timout_cnt_clr of the second timer, and the first timer outputs the timeout enable signal timeout_ena to control the start of the second timer.

[0070] It should be noted that the clock signal clk drives two sequential logic blocks at the same time, namely the first timer and the second timer. These sequential logic blocks are responsible for generating two key control signals: the timeout enable signal timeout_ena and the timeout counter clear signal timout_cnt_clr, and managing the timeout counter timeout_cnt at the same time. The timeout counter timeout_cnt counts under the control of the timeout enable signal timeout_ena, and the timeout counter clear signal timout_cnt_clr is used to clear the timer and reset the entire detection process.

[0071] The output of the timeout counter timeout_cnt also controls the multiplexer rtlc_17 to select the signal, and its output signal is input to the OR gate rtlc_111 again to form a feedback loop. In addition, the timeout signal timeout is compared with the output of the timeout counter timeout_cnt to determine whether a timeout fault has occurred. If the Hall sensor does not undergo any state change within a predetermined time, the timeout signal timeout will remain in a high level state, triggering the fault detection logic, and then generating a corresponding fault indication signal. This design ensures that when the Hall sensor fails to respond within the expected time, the timeout fault can be identified and responded to in a timely manner.

[0072] As mentioned above, in the Hall sensor fault identification circuit, there are three input signals: the first Hall sensor state change signal hall0_change, the second Hall sensor state change signal hall1_change and the third Hall sensor state change signal hall2_change. If any of these three signals generates a pulse, an internal register will be automatically cleared. This register is responsible for counting, and when it reaches the maximum value, a timeout interrupt will be generated. This maximum value is implemented by a multiplexer rtlc_l7, which ensures that the timeout interrupt can be triggered in time when the Hall sensor state does not change within the predetermined time.

[0073] It can be seen that the present invention can provide a sensor damage signal in time when the Hall sensor is damaged or completely damaged, and can provide a recovery signal in time when the Hall sensor is restored; by utilizing a three-way parallel detection circuit, the occurrence of damage can be accurately detected when any one way is damaged, and different installation methods and rotation methods of Hall sensors are supported; by using a digital circuit, compared with independent components or analog circuits, the recognition is more accurate and the real-time performance is good, and it can be more conveniently integrated into the system circuit for use, and is suitable for harsh use environments such as electric vehicles.

[0074] Second embodiment

[0075] Based on the above-mentioned Hall sensor fault identification circuit, the second embodiment of the present invention provides a Hall sensor fault identification method. The method at least includes the following steps:

[0076] (1) Configure motor parameters: Before enabling the automatic commutation function, you need to configure the motor's forward and reverse directions and the Hall sensor installation method (60° or 120°).

[0077] (2) The signal detection and recording module receives the hall_din signal, reset signal rst_n, clock signal clk and hall_start signal of the three channels A, B and C. When the hall_start signal outputs a high pulse, it indicates that the automatic fault identification of the Hall sensor has begun. Under the control of the clock signal, the detection module caches the input signal into the DFF trigger and generates three pulse signals (hall0_change, hall1_change, hall2_change);

[0078] (3) The fault identification module receives the clock signal, the reset signal and the three-way pulse signal, and outputs the hall1_damage and hall2_damage signals from each detection module according to these signals;

[0079] (4) The fault detection module generates a hall_damage signal based on the hall1_damage and hall2_damage signals output by the three detection modules.

[0080] When a damage pulse event is detected, it is sent to the MCU or other peripherals as an interrupt signal, and the ACE signal is automatically set. When a recovery pulse event is detected, it is also sent to the MCU or other peripherals as an interrupt signal, and the ACE signal is automatically cleared.

[0081] Through the above steps, the Hall sensor failure and recovery can be automatically and timely detected, and it can be distinguished which sensor has a problem.

[0082] In a preferred embodiment of the present invention, the input signals of the timeout detection module include hall_start, reset signal, clock signal and state change signals of the Hall sensor (hall0_change, hall1_change and hall2_change). If the Hall sensor does not change within the expected time, the timeout signal will remain at a high level, triggering the fault detection logic and generating a corresponding fault indication signal.

[0083] It should be noted that the above multiple embodiments are only examples. The technical solutions of various embodiments can be combined, and the order of various steps can be changed, all within the scope of protection of this patent.

[0084] The above is a detailed description of the Hall sensor fault identification circuit and identification method for brushless DC motors provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A Hall sensor fault identification circuit for a brushless DC motor, characterized in that It includes a signal detection and recording module, a fault identification module and a fault detection module; wherein, The signal detection and recording module includes three DFF triggers, whose input signals are the Hall sensor input signals (hall_din), reset signals (rst_n), clock signals (clk) and Hall sensor start signals (hall_start) of the three channels A, B and C; wherein, the output of a high pulse of the Hall sensor start signal represents the start of automatic fault identification of the Hall sensor; when any one of the three channels A, B and C has an edge change, the signal detection and recording module generates three pulse signals and inputs them into the fault identification module; The fault identification module includes three detection modules, which are used to receive a clock signal, a reset signal and three pulse signals, and according to three state change signals (hall 0_change, hall 1_change, hall 2_change) of the Hall sensor, each detection module outputs a corresponding Hall sensor damage signal (hall 1_damage, hall 2_damage); The fault detection module generates a comprehensive Hall sensor damage signal (hall_damage) through logic operation according to the Hall sensor damage signals output by the three detection modules.

2. The Hall sensor fault identification circuit according to claim 1, characterized in that: The signal detection and recording module includes a D-type trigger and three XOR gate modules. The input end of the D-type trigger receives the Hall sensor input signals of three channels A, B, and C respectively. Under the control of the clock signal, the Hall sensor input signals of the three channels are cached in three DFF triggers respectively; in the three XOR gate modules, one input signal of each XOR gate is the output signal of the DFF trigger, and the other input signal is the original Hall sensor input signal.

3. The Hall sensor fault identification circuit according to claim 1, characterized in that: The first Hall sensor damage signal (hall 1_damage) output by the first detection module (u_hall 0_autodet) and the second Hall sensor damage signal (hall 2_damage) output by the second detection module (u_hall 2_autodet) are both input to the first OR gate (rtlc_124); the first Hall sensor damage signal (hall 1_damage) output by the third detection module (u_hall 1_autodet) and the first Hall sensor damage signal (hall 1_damage) output by the fourth detection module (u_hall 2_autodet) are both input to the second OR gate (rtlc_122); the second Hall sensor damage signal (hall 2_damage) output by the fifth detection module (u_hall0_autodet) and the second Hall sensor damage signal (hall 2_damage) output by the sixth detection module (u_hall 1_autodet) are also input to the third OR gate (rtlc_126); The first Hall sensor recovery signal (hall_recovery) of the seventh detection module (u_hall 1_autodet) and the eighth detection module (u_hall 0_autodet) is input to the fourth OR gate (rtlc_1 31); the third Hall sensor recovery signal (hall_recovery) of the ninth detection module (hall 2_autodet) and the output of the fourth OR gate (rtlc_1 31) are input to the fifth OR gate (rtlc_1 32); If the Hall sensor recovery signal (hall_recovery) of any fault detection module is high, the output of the fifth OR gate (rtlc_l 32) is high; if the fifth OR gate (rtlc_l 32) is low, it means that all Hall sensors have recovered from the fault state.

4. The Hall sensor fault identification circuit according to claim 1, characterized in that: In the detection module, the first Hall sensor state change signal (hall 0_change signal) is sent to the DFF register (hall 0_change_r_reg) and the first AND gate (rtlc_130); the first Hall sensor state change register signal (hall 0_change_r) generated by the DFF register (hall 0_change_r_reg) is input to the DFF register record enable register (record_ena_reg) to obtain an enable signal (record_ena) for controlling the recording of a 180° dot period signal; the enable signal (record_ena) is sent to the first AND gate (rtlc_130), the second AND gate (rtlc_116) and the third AND gate (rtlc_128); the second AND gate (rtlc_116) receives the second Hall sensor state change signal (hall 1_change) and enable signal (record_ena); the output of the second AND gate (rtlc_116) is sent to the sixth OR gate (rtlc_141); the input of the fourth AND gate (rtlc_144) is the output of the sixth OR gate (rtlc_141) and the output of the first NOT gate (rtlc_147), and its output is sent to the second Hall sensor record pre-register end (hall 1_record_pre) of the register; the second Hall sensor record signal (hall 1_record) output by the register is sent to the sixth OR gate (rtlc_141), the second NOT gate (rtlc_132) and the fifth AND gate (rtlc_138); the third Hall sensor record signal (hall 2_record) output by it is sent to the seventh OR gate (rtlc_145), the third NOT gate (rtlc_135) and the sixth AND gate (rtlc_139); the third AND gate (rtlc_128) receives the third Hall sensor state change signal (hall 2_change) and the enable signal (record_ena), and its output is sent to the seventh OR gate (rtlc_145); the output of the seventh OR gate (rtlc_145) and the output of the first NOT gate (rtlc_147) are both sent to the seventh AND gate (rtlc_148), and the output of the seventh AND gate (rtlc_148) is sent to the third Hall sensor record pre-register end (hall 2_record_pre end) of the register; the first AND gate (rtlc_130) receives the enable signal (record_ena) and the first Hall sensor state change signal (hall 0_change), and the output is sent to the fifth AND gate (rtlc_138), the fourth AND gate (rtlc_133), the sixth AND gate (rtlc_136) and the first NOT gate (rtlc_147);The input of the sixth AND gate (rtlc_139) is the output of the fifth AND gate (rtlc_138) and the third Hall sensor record signal (hall 2_record), and the output is the Hall sensor recovery signal (hall_recover); the input of the fourth AND gate (rtlc_133) is the output of the first AND gate (rtlc_130) and the output of the second NOT gate (rtlc_132), and the output of the fourth AND gate (rtlc_133) is the first Hall sensor damage signal (hall 1_damage); the input of the sixth AND gate (rtlc_136) is the output of the first AND gate (rtlc_130) and the output of the third NOT gate (rtlc_135), and the output of the sixth AND gate (rtlc_136) is the second Hall sensor damage signal (hall 2_damage). ; 5. The Hall sensor fault identification circuit as claimed in claim 1, characterized in that Also includes a timeout detection module, the input signals of the timeout detection module are a Hall sensor start signal (hall_s tart), a reset signal, a clock signal, and a first Hall sensor state change signal (hall 0_change), a second Hall sensor state change signal (hall1_change) and a third Hall sensor state change signal (hall 2_change); Among them, the first Hall sensor state change signal (hall 0_change), the second Hall sensor state change signal (hall 1_change) and the third Hall sensor state change signal (hall 2_change) respectively enter the eighth OR gate (rtlc_111), the ninth OR gate (rtlc_113) and the tenth OR gate (rtlc_115), and the outputs of these OR gates are connected to the eleventh AND gate (rtlc_17) for integrating the state changes of the Hall sensors; the timeout signal (timeout) output by the eleventh AND gate (rtlc_17) is input to the eighth OR gate (rtlc_111) to indicate whether the state change of the Hall sensor is detected within the expected time.

6. The Hall sensor fault identification circuit according to claim 5, characterized in that: The clock signal drives two sequential logic blocks at the same time, and the sequential logic blocks are responsible for generating control signals, a timeout enable signal (timeout_ena) and a timeout counter clear signal (timout_cnt_clr), and managing a timeout counter (timeout_cnt); the timeout counter (timeout_cnt) counts under the control of the timeout enable signal (timeout_ena), and the timeout counter clear signal (timout_cnt_clr) is used to clear the timer and reset the detection process.

7. The Hall sensor fault identification circuit according to claim 6, characterized in that: The timeout signal (timeout) is also compared with the output of the timeout counter (timeout_cnt) to determine whether a timeout fault occurs; if the Hall sensor does not change within the expected time, the timeout signal (timeout) will remain at a high level, triggering the fault detection logic, thereby generating a corresponding fault indication signal.

8. The Hall sensor fault identification circuit according to claim 1, characterized in that: The Hall sensor of each channel is independently provided with a Hall sensor damage signal line to indicate whether the corresponding Hall sensor fails.

9. The Hall sensor fault identification circuit according to claim 1, characterized in that It also includes a fault recovery detection module, which determines whether all Hall sensors have recovered according to the Hall sensor recovery signals (hall_recovery) output by the three detection modules; if all Hall sensors have recovered, it outputs a fault recovery signal (recovery).

10. A Hall sensor fault identification method for a brushless DC motor, implemented based on the Hall sensor fault identification circuit according to any one of claims 1 to 9, characterized in that The steps include: (1) Configure the forward and reverse direction of the motor and the installation method of the Hall sensor; (2) The signal detection and recording module receives the Hall sensor input signals (hall_din), reset signals, clock signals and Hall sensor start signals (hall_start) of the three channels A, B and C. When the Hall sensor start signal outputs a high pulse, it indicates that the automatic fault identification of the Hall sensor has started. Under the control of the clock signal, the signal detection and recording module caches the input signals into the DFF trigger and generates three pulse signals. (3) The fault identification module receives the clock signal, the reset signal and the three-way pulse signal, and outputs the first Hall sensor damage signal (hall 1_damage) and the second Hall sensor damage signal (hall2_damage) by each detection module according to these signals; (4) The fault detection module generates a comprehensive Hall sensor damage signal (hall_damage) through logical operation according to the first Hall sensor damage signal (hall1_damage) and the second Hall sensor damage signal (hall2_damage) output by the three detection modules.

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