Semiconductor device

Abstract

The invention provides a semiconductor device which suppresses surge voltage generated by parasitic inductance of wiring. A semiconductor device (1) includes a semiconductor chip (Q1) and a Miller clamp circuit (Q2). The semiconductor chip (Q1) includes a switching element (11) as a main switch. The Miller clamp circuit (Q2) suppresses an increase in the potential of a gate electrode (G1) (first control electrode) of the switching element (11) when the switching element (11) is in an off state. Furthermore, a switching element (21) for a Miller clamp circuit is disposed on a gate electrode (G1) provided on the front surface of the semiconductor chip (Q1), and the semiconductor chip (Q1) and the switching element (21) for the Miller clamp circuit are built in the same package.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In a semiconductor device, the gate diode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is configured in a package body with an anode connected to a source sense terminal, and the source pad electrode-gate pad electrode of the MISFET is configured at a position on the surface side (for example, see Patent Document 1). In addition, a short-circuit MOSFET is connected between the gate and source of a main circuit MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the main circuit MOSFET and the short-circuit MOSFET are configured on different connection pads, and the source electrodes of the main circuit MOSFET and the short-circuit MOSFET are connected by wires (for example, see Patent Document 2).

[0003] In addition, a MOSFET formed of a SiC (Silicon carbide) substrate has a Miller clamp circuit region between a cell region where a plurality of vertical MOSFET elements are arranged and a gate wiring region (see, for example, Patent Document 3). In addition, a Miller clamp source wire is connected from an active Miller clamp transistor toward a source sensing signal wiring pattern, and a Miller clamp gate wire is connected toward a gate signal wiring pattern (see, for example, Patent Document 4).

[0004] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2015-126342 Patent Document 2: International Publication No. 2012 / 018073 Patent Document 3: Japanese Patent Application Publication No. 2016-174033 Patent Document 4: International Publication No. 2018 / 186353 Summary of the invention

[0005] Technical issues An object of the present invention is to suppress a surge voltage caused by parasitic inductance of wiring.

[0006] Technical Solution In order to solve the above-mentioned problem, a semiconductor device is provided. The semiconductor device has: a semiconductor chip including a switching element; and a Miller clamp circuit that suppresses the potential rise of the first control electrode of the switching element when the switching element is in an off state. In addition, a Miller clamp circuit switching element is arranged on the first control electrode provided on the front surface of the semiconductor chip, and the semiconductor chip and the Miller clamp circuit switching element are built into the same package.

[0007] Technical Effects According to one aspect, it is possible to suppress a surge voltage caused by parasitic inductance of wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a diagram for explaining an example of a semiconductor device.

[0009] Figure 2 A diagram showing an example of a circuit configuration of a semiconductor device.

[0010] Figure 3 A diagram showing an example of the structure of a semiconductor device.

[0011] Figure 4 A diagram showing an example of a cross-sectional view of a semiconductor device.

[0012] Figure 5 A diagram showing an example of the structure of a semiconductor device.

[0013] Figure 6 A diagram showing an example of a cross-sectional view of a semiconductor device.

[0014] Figure 7 It is a diagram showing a comparative example and a modified example of the arrangement position of a MOSFET for a Miller clamp circuit.

[0015] Figure 8 It is a diagram showing a comparative example and a modified example of the arrangement position of a MOSFET for a Miller clamp circuit.

[0016] Fig. 9 The diagrams show comparative examples and modified examples of the arrangement positions of gate electrodes of a semiconductor chip.

[0017] Fig.10 The diagrams show comparative examples and modified examples of the arrangement positions of gate electrodes of a semiconductor chip.

[0018] Explanation of symbols 1.1-1.1-2 Semiconductor devices 3 Lead frame 4 Outer edge 11 Switching element (main MOSFET) 21 Switching elements for Miller clamp circuits (MOSFETs for Miller clamp circuits) 12, 22 Base material 31, 32 Bonding materials Q1 Semiconductor Chip Q2 Miller clamp circuit G1 Gate electrode (first control electrode) G2 gate electrode (second control electrode) D Drain electrode S Source electrode d1 Drain of the switching element d2 Drain of the switching element used in the Miller clamp circuit g1 Gate of the switching element g2 Gate of the switching element used in the Miller clamp circuit s1 Source of the switching element s2 Source of the switching element used in the Miller clamp circuit w1, w2, w3, w11, w12, w13 wire wg1, wg2 wire group L1, L2, L3, L11, L12, L13 Lead frame columns pa1, pa2, pa3, pa4, pb1, pb2, pb3, pb4, pb5, pb6, pb7 terminals d11, d12, d21, d22 wiring length DETAILED DESCRIPTION

[0019] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. It should be noted that, for elements having substantially the same function in this specification and the accompanying drawings, repeated descriptions are sometimes omitted by marking the same symbols. In addition, in the following description, "upper surface" means the surface facing upward when viewed from the paper surface. Similarly, "upper" and "upper part" refer to the direction facing upward when viewed from the paper surface. "Lower surface" means the surface facing downward when viewed from the paper surface. Similarly, "below" refers to the direction facing downward when viewed from the paper surface. Such directionality is meant in all the accompanying drawings. "Upper surface", "upper", "upper part", "lower surface", and "below" are merely expressions for the convenience of determining relative positional relationships, and do not limit the technical ideas of the present invention.

[0020] Figure 1 1 is a diagram for explaining an example of a semiconductor device. The semiconductor device 1 includes a semiconductor chip Q1 and a Miller clamp circuit Q2. The semiconductor chip Q1 includes a switch element 11 as a main switch. The Miller clamp circuit Q2 suppresses a potential rise in a gate electrode G1 (first control electrode) of the switch element 11 when the switch element 11 is in an off state.

[0021] Furthermore, the Miller clamp circuit switching element 21 is disposed on the gate electrode G1 provided on the front surface of the semiconductor chip Q1 , and the semiconductor chip Q1 and the Miller clamp circuit switching element 21 are built into the same package.

[0022] As described above, the semiconductor device 1 adopts a configuration in which the Miller clamp circuit switching element 21 is disposed on the gate electrode G1 provided on the front surface of the switching element 11 and is built into the same package.

[0023] This makes it possible to shorten the wiring connecting the switching element 11 of the semiconductor chip Q1 and the Miller clamp circuit switching element 21 , thereby suppressing a surge voltage caused by parasitic inductance of the wiring when the switching element 11 is turned off.

[0024] Next, the surge voltage generated in semiconductor devices and the suppression of the surge voltage will be described. Semiconductor devices are widely used in power conversion circuits mounted in applications such as DC (Direct Current) / DC converters and inverters.

[0025] In applications where such semiconductor devices are mounted, the semiconductor devices are often used in switching operations that repeatedly turn on and off at high speed. At this time, due to the parasitic inductance of the wiring in the semiconductor device, an overvoltage called a surge voltage may be generated between the control electrode and the output electrode of the switching element, causing the device to malfunction, and a countermeasure for suppressing the surge voltage is sought.

[0026] In recent years, wide bandgap semiconductors represented by SiC (e.g., SiC-MOSFET, SiC-Diode, etc.) have attracted attention as high-performance semiconductor chips. One of the characteristics of these wide bandgap semiconductors is that they can increase the switching frequency compared to conventional Si semiconductors.

[0027] Therefore, since surge voltage is easily generated by increasing the switching frequency, it is necessary to suppress the surge voltage even when a wide bandgap semiconductor is used.

[0028] As a method for suppressing surge voltage, there is a method of connecting a Miller clamp circuit between the control electrode and the output electrode of a switching element. In such a configuration, the Miller clamp circuit connected between the control electrode and the output electrode is driven only when the switching element is turned off, thereby suppressing the potential rise of the control electrode of the switching element, thereby suppressing the surge voltage.

[0029] However, for example, when the Miller clamp circuit is configured separately from the switching element, the parasitic inductance of the wiring connecting the switching element and the Miller clamp circuit may increase, resulting in a decrease in the surge voltage suppression effect of the Miller clamp circuit. Therefore, it is desired to design a substrate that suppresses the surge voltage by reducing the potential rise of the control electrode without increasing the parasitic inductance of the wiring.

[0030] Next, the configuration of the semiconductor device of the present invention that improves the effect of suppressing surge voltage will be described in detail below. Figure 2 1 is a diagram showing an example of a circuit configuration of a semiconductor device. The semiconductor device 1 includes a semiconductor chip (main circuit) Q1 and a Miller clamp circuit Q2 .

[0031] The switch element 11 of the semiconductor chip Q1 is composed of, for example, a MOSFET and a parasitic diode of the MOSFET. The switch element 21 for the Miller clamp circuit of the Miller clamp circuit Q2 is composed of, for example, a MOSFET and a parasitic diode of the MOSFET. It should be noted that the switch element 11 and the switch element 21 for the Miller clamp circuit may also be composed of other types of elements such as an IGBT (Insulated Gate Bipolar Transistor) and a diode connected in reverse parallel to the IGBT.

[0032] In the following description, MOSFETs are used for the switch element 11 and the Miller clamp circuit switch element 21 , respectively. The switch element 11 may be referred to as a main MOSFET 11 , and the Miller clamp circuit switch element 21 may be referred to as a Miller clamp circuit MOSFET 21 .

[0033] The semiconductor device 1 is connected to gate electrodes G1 and G2 , a drain electrode D, and a source electrode S. The gate electrode G1 (first control electrode) is connected to a gate g1 of the main MOSFET 11 and a drain d2 (second input electrode) of the Miller clamp MOSFET 21 .

[0034] The gate electrode G2 (second control electrode) is connected to the gate g2 of the Miller clamp MOSFET 21. The drain electrode D is connected to the drain d1 (first input electrode) of the main MOSFET 11. The source electrode S is connected to the source s1 (first output electrode) of the main MOSFET 11 and the source s2 (second output electrode) of the Miller clamp MOSFET 21.

[0035] Here, when an H-level driving signal is applied to the gate electrode G1, the main MOSFET 11 is turned on. At this time, an L-level driving signal is applied to the gate electrode G2 to turn off the Miller clamp MOSFET 21, and the Miller clamp Q2 is put into a non-driving state.

[0036] When an L-level drive signal is applied to the gate electrode G1, the main MOSFET 11 is turned off. At this time, an H-level drive signal is applied to the gate electrode G2 to turn on the Miller clamp MOSFET 21, thereby setting the Miller clamp Q2 to a driven state.

[0037] When the Miller clamp MOSFET 21 is driven and turned on, when the main MOSFET 11 is turned off from being turned on, charge is extracted from the gate g1 of the main MOSFET 11 through the Miller clamp MOSFET 21. As a result, the voltage drop of the gate g1 is clamped to a predetermined voltage.

[0038] By providing the Miller clamp circuit Q2 between the gate g1 and the source s1 of the main MOSFET 11 and performing the above control, a surge voltage generated between the gate g1 and the source s1 when the main MOSFET 11 is turned off can be suppressed. In addition, false turn-on of the main MOSFET 11 can be suppressed.

[0039] Next, a configuration in which the semiconductor device 1 is applied to a package element (discrete element) will be described. Figure 3 is a diagram showing an example of the configuration of a semiconductor device. Figure 4 FIG. 1 is a diagram showing an example of a cross-sectional view of a semiconductor device. Figure 4 Shown in Figure 3 The cross section at X1-X2. Figure 3 , Figure 4 The semiconductor device 1 - 1 shown is an example of a package element having four terminals extending to the outside.

[0040] exist Figure 4 The semiconductor chip Q1 is arranged on the upper surface of the lead frame 3 shown. The drain electrode D formed on the back surface of the substrate 12 (silicon, etc.) of the semiconductor chip Q1 is connected to the lead frame 3 via a bonding material 31 (solder, etc.). The source electrode S is formed on the front surface of the substrate 12 of the semiconductor chip Q1, and the gate electrode G1 is formed at a position away from the source electrode S.

[0041] The Miller clamp circuit MOSFET 21 is arranged on the gate electrode G1, which is provided on the front surface of the semiconductor chip Q1. A drain d2 is formed on the back surface of the substrate 22 (silicon, etc.) of the Miller clamp circuit MOSFET 21, and the drain d2 is connected to the gate electrode G1 via a bonding material 32 (a conductive bonding component such as solder or plating solution). That is, the drain d2 (second input electrode) of the Miller clamp circuit MOSFET 21 and the gate electrode G1 (first control electrode) of the semiconductor chip Q1 are connected via the bonding material 32. The source s2 of the Miller clamp circuit MOSFET 21 is formed on the front surface of the substrate 22 of the Miller clamp circuit MOSFET 21, and the gate electrode G2 is formed at a position away from the source s2.

[0042] The source electrode S is connected to the source electrode s2 of the Miller clamp circuit MOSFET 21 through the wire w1. That is, the source electrode s2 (second output electrode) of the Miller clamp circuit MOSFET 21 is connected to the source electrode S (first output electrode) of the semiconductor chip Q1. The gate electrode G1 is connected to the lead frame column (connection portion) L1 through the wire w2, and the gate electrode G2 is connected to the lead frame column L2 through the wire w3. In addition, the source electrode S is connected to the lead frame column L3 through the wire group wg1 composed of a plurality of wires. It should be noted that the above-mentioned gate electrodes G1, G2, drain electrode D and source electrode S can be formed with, for example, an electrode (Al-Si electrode) covered with an Al-Si alloy film.

[0043] Among the terminals pa1, pa2, pa3, and pa4 that are led out to the outside, the terminal pa1 (first terminal) is integrally connected to the lead frame column L1 and becomes an external terminal of the gate electrode G1. The terminal pa2 (second terminal) is integrally connected to the lead frame column L2 and becomes an external terminal of the gate electrode G2. That is, the gate electrode G1 (first control electrode) is connected to the terminal pa1 (first terminal) through the wire w2, and the gate electrode G2 (second control electrode) is connected to the terminal pa2 (second terminal) through the wire w3.

[0044] In addition, the terminal pa3 (third terminal) is integrally connected to the lead frame column L3 and becomes an external terminal of the source electrode S. That is, the source electrode S (first output electrode) is connected to the terminal pa3 (third terminal) through the wire group wg1 composed of a plurality of wires. The terminal pa4 is connected to the lead frame 3 and becomes an external terminal of the drain electrode D.

[0045] Figure 5 is a diagram showing an example of the configuration of a semiconductor device. Figure 6 A diagram showing an example of a cross-sectional view of a semiconductor device. Figure 6 Shown above Figure 5 The cross section at X3-X4. Figure 5 , Figure 6The semiconductor device 1 - 2 shown is an example of a package element having seven terminals extending to the outside.

[0046] exist Figure 6 The semiconductor chip Q1 is arranged on the upper surface of the lead frame 3 shown. The drain electrode D formed on the back surface of the substrate 12 of the semiconductor chip Q1 is connected to the lead frame 3 via the bonding material 31. The source electrode S is formed on the front surface of the substrate 12 of the semiconductor chip Q1, and the gate electrode G1 is formed at a position away from the source electrode S.

[0047] The Miller clamp MOSFET 21 is arranged on the gate electrode G1, which is provided on the front surface of the semiconductor chip Q1. A drain d2 is formed on the back surface of the substrate 22 of the Miller clamp MOSFET 21, and the drain d2 is connected to the gate electrode G1 via a bonding material 32. A source s2 of the Miller clamp MOSFET 21 is formed on the front surface of the substrate 22 of the Miller clamp MOSFET 21, and a gate electrode G2 is formed at a position away from the source s2.

[0048] The source electrode S is connected to the source electrode s2 of the Miller clamp circuit MOSFET 21 via a wire w11. The gate electrode G1 is connected to the lead frame column L11 via a wire w12, and the gate electrode G2 is connected to the lead frame column L12 via a wire w13. In addition, the source electrode S is connected to the lead frame column L13 via a wire group wg2 composed of a plurality of wires.

[0049] Among the terminals pb1, pb2, pb3, pb4, pb5, pb6, and pb7 that are led out to the outside, the terminal pb1 (first terminal) is integrally connected to the lead frame column L11 and becomes an external terminal of the gate electrode G1. The terminal pb2 (second terminal) is integrally connected to the lead frame column L12 and becomes an external terminal of the gate electrode G2. In addition, the terminals pb3, pb4, pb5, pb6, and pb7 (third terminals) are integrally connected to the lead frame column L13 and become external terminals of the source electrode S. That is, the gate electrode G1 is connected to the terminal pb1 (first terminal) through the wire w12, the gate electrode G2 is connected to the terminal pb2 (second terminal) through the wire w13, and the source electrode S is connected to the terminals pb3, pb4, pb5, pb6, and pb7 (third terminals) through the wire group wg2 composed of a plurality of wires.

[0050] It should be noted that the above-mentioned wires w1, w2, w3, w11, w12, w13, and the plurality of wires used in the wire groups wg1 and wg2 are, for example, aluminum wires with a wire diameter of 300 μm to 500 μm. In addition, as the joining of the wires, wire bonding based on ultrasound or load is performed. It should be noted that connectors and strip wires can also be used instead of wires. In this case, a single connector can be used instead of the plurality of wires of the wire group wg1. Similarly, a single connector can be used for the wire group wg2. As the connector, for example, a conductor metal sheet with copper as the main component can be used.

[0051] Next, the arrangement position of the Miller clamp MOSFET 21 will be described. Figure 7 , Figure 8 It is a diagram showing a comparative example and a modified example of the arrangement position of a MOSFET for a Miller clamp circuit. Figure 7 FIG. 2 shows a state where the Miller clamp circuit MOSFET 21 is arranged near the center of the gate electrode G1. Figure 8 The state where the Miller clamp MOSFET 21 is arranged at a position on the outer edge portion 4 side of the gate electrode G1 is shown.

[0052] exist Figure 7 In the embodiment, the wiring length of the wire w1 connecting the source s2 of the Miller clamp circuit MOSFET 21 and the source electrode S provided on the front surface of the semiconductor chip Q1 is d11. Figure 8 In FIG. 5 , the wiring length of the wire w1 connecting the source s2 and the source electrode S is d12, and d12<d11.

[0053] In this way, when the Miller clamp circuit MOSFET 21 is arranged at a position on the outer edge 4 side of the gate electrode G1 (first control electrode), the wiring length d12 of the wire w1 connecting the source s2 of the Miller clamp circuit MOSFET 21 to the source electrode S can be shorter than the wiring length d11 of the wire w1 connecting the source s2 of the Miller clamp circuit MOSFET 21 to the source electrode S, which is provided near the center of the gate electrode G1. Therefore, by arranging the Miller clamp circuit MOSFET 21 at a position on the outer edge 4 side of the gate electrode G1 of the semiconductor chip Q1, the parasitic inductance of the wiring can be further reduced. In addition, it is preferred that the source s2 of the Miller clamp circuit MOSFET 21 is arranged at a position on the outer edge 4 side of the gate electrode G1. In this case, the wiring length d12 of the wire w1 connecting the source s2 to the source electrode S can be further shortened, thereby further reducing the parasitic inductance of the wiring.

[0054] Next, the arrangement position of the gate electrode G1 will be described. Fig. 9 , Fig.10The diagrams show comparative examples and modified examples of the arrangement positions of gate electrodes of a semiconductor chip. Fig. 9 1 shows a state where the gate electrode G1 is formed at a position not close to the terminal pa1 (first terminal). Fig.10 The state where the gate electrode G1 is formed at a position close to the terminal pa1 is shown.

[0055] exist Fig. 9 In the embodiment, the wiring length of the wire w2 connecting the gate electrode G1 to the lead frame column L1 is d21. The lead frame column L1 is connected to the terminal pa1. Fig.10 In FIG. 1 , the wiring length of the wire w2 connecting the gate electrode G1 and the lead frame column L1 is d22 , and d22 < d21 .

[0056] Thus, when the gate electrode G1 (first control electrode) of the semiconductor chip Q1 is formed at a position close to the terminal pa1 (first terminal), the wiring length d22 of the wire w2 that connects the gate electrode G1 to the lead frame column L1 integrally connected to the terminal pa1 can be made shorter than the wiring length d21 of the wire w2 when the gate electrode G1 is formed at a position not close to the terminal pa1. Therefore, by forming the gate electrode G1 of the semiconductor chip Q1 at a position close to the first terminal, the parasitic inductance of the wiring can be further reduced. In addition, since the wiring length d22 of the wire w2 is shorter than the wiring length d21 of the wire w2, the wire W2 can be prevented from falling.

[0057] As described above, according to the present invention, the Miller clamp circuit switching element 21 is disposed on the gate electrode G1 provided on the front surface of the semiconductor chip Q1 and is built into the same package.

[0058] Thus, the switching element 11 and the switching element 21 for the Miller clamp circuit can be configured at the shortest distance, the wiring length of the wire w1 connecting the source s2 of the switching element 21 for the Miller clamp circuit and the source electrode S of the switching element 11 of the semiconductor chip Q1 can be shortened, and the parasitic inductance of the wiring can be reduced, thereby suppressing the surge voltage caused by the parasitic inductance of the wiring.

[0059] Furthermore, since the Miller clamp switching element 21 is disposed on the gate electrode G1 of the semiconductor chip Q1 , it is not necessary to ensure an area for disposing the Miller clamp switching element 21 on the lead frame 3 of the semiconductor device 1 , and the semiconductor device 1 can be miniaturized.

[0060] Although the above embodiments are exemplified, the configuration of each part shown in the embodiments may be replaced with another mode having the same function. In addition, any other components and processes may be applied. In addition, any two or more configurations (features) in the above embodiments may be combined.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor chip including a switching element; and a Miller clamp circuit that suppresses a potential rise of a first control electrode of the switching element when the switching element is in an off state, The semiconductor device includes a Miller clamp circuit switching element disposed on the first control electrode provided on the front surface of the semiconductor chip, and the semiconductor chip and the Miller clamp circuit switching element are built into the same package.

2. The semiconductor device according to claim 1, wherein: The input electrode of the Miller clamp circuit switching element is connected to the first control electrode of the semiconductor chip via a bonding material. The second output electrode of the Miller clamp circuit switching element is connected to the first output electrode provided on the front surface of the semiconductor chip.

3. The semiconductor device according to claim 2, wherein: The first control electrode of the semiconductor chip is connected to the first terminal by wire bonding, The second control electrode of the switch element for the Miller clamp circuit is connected to the second terminal by wire bonding. The first output electrode of the semiconductor chip is connected to a third terminal through a plurality of wire bonds or connectors.

4. The semiconductor device according to claim 1, wherein: The Miller clamp circuit switching element is disposed on the outer edge side of the first control electrode.

5. The semiconductor device according to claim 3, wherein: The first control electrode of the semiconductor chip is formed at a position close to the first terminal.

Images