Split type switch structure and electronic product

Abstract

The invention provides a split type switch structure and an electronic product, and the structure comprises a single-pole N-throw switch, N being a natural number greater than or equal to 1; wherein the single-pole N-throw switch comprises N switching paths, the switching paths are switched on and off through switching tubes, and devices in the single-pole N-throw switch are at least arranged on two chips. According to the split type switch structure and the electronic product, a device of a single-pole multi-throw switch is split to at least two chips, so that the area and the cost of the chips are reduced, the isolation degree is improved through flexible space placement, high isolation degree and low cost are considered, and the split type switch structure and the electronic product are suitable for large-scale production and application.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a split switch structure and an electronic product. Background Art

[0002] Single Pole N Throw (SPNT) is one of the most commonly used devices in the circuit field, especially in the fields of communication, radar, electronic countermeasures, etc. The SPNT can be used to switch different paths.

[0003] The existing single-pole multi-throw switch is set on a chip. In order to improve the isolation, the pads (PAD) of the single-pole multi-throw switch need to be as far away as possible, which leads to a larger chip size for preparing the single-pole multi-throw switch and an increase in the corresponding cost. Conversely, in order to reduce the cost, the chip area is reduced, which will lead to insufficient isolation between the signals.

[0004] Therefore, how to propose a single-pole multi-throw switch that takes into account both high isolation and low cost has become one of the problems that technical personnel in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a split switch structure and an electronic product for solving the problem that the single-pole multi-throw switch in the prior art is difficult to achieve both high isolation and low cost.

[0007] To achieve the above objectives and other related objectives, the present invention provides a split switch structure, the split switch structure comprising:

[0008] A single-pole N-throw switch, wherein N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch includes N switch paths, each switch path is switched by turning on and off a switch tube, and the devices in the single-pole N-throw switch are arranged on at least two chips.

[0009] Optionally, the split switch structure further includes a packaging shell, the single-pole N-throw switch is disposed in the packaging shell, and each pad of the single-pole N-throw switch is electrically connected to a corresponding pin on the packaging shell.

[0010] Optionally, each switch path includes M-level switch tubes and m-level pull-down modules, where M is a natural number greater than or equal to 1, and m is a natural number greater than or equal to 0 and less than or equal to M+1; when the number M of switch tubes in a switch path is greater than or equal to 2, the switch tubes at each level are cascaded in sequence; one end of each pull-down module is respectively connected to one end of the corresponding switch tube, and the other end is grounded or connected to a specific impedance; the number M of switch tubes and the number m of pull-down modules in each switch path are the same or different.

[0011] More optionally, the pull-down module includes P-level transistors, where P is a natural number greater than or equal to 1, and when P is greater than or equal to 2, transistors of each level are connected in series in sequence; the number P of transistors in each pull-down module is the same or different.

[0012] More optionally, the switch tube is an NMOS tube, and the transistor in the pull-down module is an NMOS tube.

[0013] More optionally, when N is greater than or equal to 2, the N switch paths are arranged on at least two chips, and the same switch path is located on the same chip.

[0014] More optionally, n1 switch paths in the single-pole N-throw switch are arranged on the first chip, and n2 switch paths are arranged on the second chip; n1+n2=N, and n1 is a natural number greater than or equal to 1 and less than N.

[0015] More optionally, when n2 is greater than or equal to 2, the number of the second chips is set to n2, and taking a switch path as a unit, the n2 switch paths are respectively arranged on the n2 second chips in a one-to-one correspondence.

[0016] More optionally, at least one switch path among the N switch paths is split into at least two parts, and the parts of the same switch path are located on different chips.

[0017] More optionally, the n3 switch paths in the single-pole N-throw switch are arranged on the first chip; the n4 switch paths are divided into a first section and a second section, wherein the first section of each switch path is arranged on the first chip, and the second section of each switch path is arranged on the second chip; n3+n4=N, n4 is a natural number greater than or equal to 1 and less than or equal to N.

[0018] More optionally, the first section and the second section of each switch path are connected in series, and one ends of the N switch paths on the first chip are connected together.

[0019] More optionally, when N and n4 are both greater than or equal to 2, the number of the second chips is set to n4, and taking the switch path as a unit, the n4 switch paths are respectively arranged on the n4 second chips in a one-to-one correspondence.

[0020] More optionally, the circuit structures on each second chip are the same.

[0021] More optionally, the pins on the packaging shell include 1 antenna pin and N radio frequency pins.

[0022] In order to achieve the above-mentioned object and other related objects, the present invention further provides an electronic product, which at least includes: the above-mentioned split switch structure.

[0023] As described above, the split switch structure and electronic product of the present invention have the following beneficial effects:

[0024] The split switch structure of the present invention splits the originally larger single-pole N-throw switch chip into several small chips, and the total chip area becomes relatively smaller to achieve low cost; since the chip size is smaller, it can be set at a suitable position, and the chips are electrically connected through metal leads or substrates, which greatly improves flexibility and is beneficial to the optimization of indicators such as isolation (when the size of each chip has been determined, the distance between each chip can be maximized as needed to achieve higher isolation).

[0025] The cost and isolation requirements of the split switch structure of the present invention are not mutually constrained, and high isolation can be achieved while taking low cost into account, and is suitable for large-scale production and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a structural schematic diagram of a single-pole triple-throw switch chip.

[0027] Figure 2 Shown is a circuit structure schematic diagram of a single-pole N-throw switch of the present invention.

[0028] Figure 3 Shown is a schematic diagram of a splitting method of the single-pole N-throw switch of the present invention.

[0029] Figure 4 Display as Figure 3 Schematic diagram of the split switch structure corresponding to the split method.

[0030] Figure 5 Shown is a schematic diagram of another splitting method of the single-pole N-throw switch of the present invention.

[0031] Figure 6 Display as Figure 5 Schematic diagram of the split switch structure corresponding to the split method.

[0032] Figure 7 Shown is a schematic diagram of another splitting method of the single-pole N-throw switch of the present invention.

[0033] Figure 8 Shown is a schematic diagram of another splitting method of the single-pole N-throw switch of the present invention.

[0034] Fig. 9 Display as Figure 7 and Figure 8 Schematic diagram of the split switch structure corresponding to the split method.

[0035] Component number description

[0036] 1 SP3T switch chip

[0037] 10 Package shell

[0038] Pins 101, 102, 103, 104

[0039] 11 Chip

[0040] 12, 13, 14, 15 pads

[0041] 2 Split switch structure

[0042] 20 Package shell

[0043] 21 SPN switch

[0044] 211 Switching Tube

[0045] 212 Drop-down module

[0046] 21a First switch path

[0047] 21b Second switch path

[0048] 21c Third switch path

[0049] 21d Fourth switch path

[0050] 22 First Chip

[0051] 23, 23a, 23b, 23c Second chip DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] See also Figures 1 to 9It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] like Figure 1 As shown, a single-pole three-throw switch chip 1 is shown, wherein the single-pole three-throw switch is prepared on a chip 11 in a packaging shell 10, and the four pads 12, 13, 14 and 15 of the single-pole three-throw switch are respectively connected to the pins 101, 102, 103 and 104; the distance between each pad needs to meet the isolation requirement. In this scheme, the higher the isolation, the larger the chip area; the smaller the chip area, the poorer the isolation; the two restrict each other. In order to take into account both isolation and cost, the distance between each pad can be set to just meet the isolation requirement to minimize the chip size, but the performance of isolation and cost is not outstanding, and it is impossible to achieve high isolation while taking into account low cost.

[0055] In order to achieve low cost and high isolation, the present invention proposes a split switch structure 2, the split switch structure 2 comprising:

[0056] A single-pole N-throw switch 21, wherein N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch 21 includes N switch paths, each switch path is switched by turning on and off a switch tube, and the devices in the single-pole N-throw switch 21 are arranged on at least two chips.

[0057] Specifically, the single-pole N-throw switch 21 can be configured as a single-pole single-throw switch, a single-pole double-throw switch, a single-pole triple-throw switch, or a single-pole multi-throw switch providing more paths as required.

[0058] Specifically, in one example, each chip of the single-pole N-throw switch 21 can be used as an independent individual in the circuit, that is, each pad of the single-pole N-throw switch 21 is directly electrically connected to other devices without connecting the package pins. In another example, each chip of the single-pole N-throw switch 21 is packaged in a package shell 20 and used as a whole in the circuit. At this time, the split switch structure 2 also includes a package shell 20, the single-pole N-throw switch 21 is arranged in the package shell 20, and each pad of the single-pole N-throw switch 21 is electrically connected to the corresponding pin on the package shell 20; in this embodiment, the pins on the package shell 20 include an antenna pin ANT and N radio frequency pins RF1, RF2...RFN, that is, N radio frequency channels share one antenna through time division multiplexing; each pin is electrically connected to the corresponding pad through a metal lead or a substrate or other packaging method. In actual use, the application of the split switch structure 2 can be set according to needs, and the definition of each pin can be configured, which is not limited to this embodiment.

[0059] Specifically, Figure 2 As shown, in this embodiment, each switch path includes M-level switch tubes 211 and m-level pull-down modules 212, M is a natural number greater than or equal to 1, and m is a natural number greater than or equal to 0 and less than or equal to M+1. When the number M of the switch tubes 211 in a switch path is greater than or equal to 2, the switch tubes 211 of each level are cascaded in sequence, and the number M of the switch tubes 211 is determined according to design requirements. One end of each pull-down module 212 is respectively connected to the connection node of the corresponding switch tube 211 (the input and / or output end of each switch tube can be provided with the pull-down module), and the other end is grounded or connected to a specific impedance (the impedance value is set as required); the pull-down module 212 is used to improve the isolation between the switch paths (when the current switch path is turned off, the connection node between the switch tubes is configured to a preset potential), and the number m of the pull-down modules 212 is determined according to design requirements. The larger the m, the higher the isolation between the channels. The number M of switch tubes 211 in each switch path can be configured to be the same or different. Similarly, the number m of pull-down modules 212 in each switch path can be configured to be the same or different, depending on actual needs. In this embodiment, the structure and number of components of each switch path are the same.

[0060] More specifically, as an example, the switch tube 211 is set as an NMOS tube, wherein each NMOS tube is connected in series in sequence, the drain of the previous stage NMOS tube is connected to the source of the next stage NMOS tube, the source of the first stage NMOS tube is connected to the antenna pin ANT (moving contact), and the source of the last stage NMOS tube is connected to the corresponding RF pin (static contact). The pull-down module 212 includes a P-level NMOS tube, P is a natural number greater than or equal to 1, and when P is greater than or equal to 2, each stage NMOS tube is connected in series in sequence, wherein each NMOS tube is connected in series in sequence, the source of the previous stage NMOS tube is connected to the drain of the next stage NMOS tube, the drain of the first stage NMOS tube is connected to the connection node of the adjacent two stages of switch tubes, and the source of the last stage NMOS tube is grounded. The number P of cascaded NMOS tubes in the pull-down module 212 is determined according to design requirements; the number P of NMOS tubes in each pull-down module 212 can be configured to be the same or different. In this example, the number P of NMOS tubes in each pull-down module 212 is the same.

[0061] It should be noted that in actual use, the structure and device type of each switch path can be set as needed, and any circuit structure that can realize switching operation and meet signal transmission requirements is applicable to the present invention, and is not limited to this embodiment.

[0062] The single-pole N-throw switch of the present invention is split into at least two parts, each part is prepared on a different chip; the splitting form can be set according to actual needs, including but not limited to: when N is greater than or equal to 2, N-way switch paths are set on at least two chips, and the same switch path is located on the same chip; at least one switch path in the N-way switch path is split into at least two parts, and each part of the same switch path is located on a different chip. The switch control signal of each switch path is controlled by a control module, and the control module can be prepared on one chip or multiple chips on which the single-pole N-throw switch is arbitrarily set, and can also be set on other chips.

[0063] Several specific implementations of the split switch structure 2 are listed and described below.

[0064] Embodiment 1

[0065] like Figure 3 to Figure 6 As shown, in this embodiment, the n1 switch path in the single-pole N-throw switch 21 is arranged on the first chip, and the n2 switch path is arranged on the second chip; n1+n2=N, n1 is a natural number greater than or equal to 1 and less than N, that is, each switch path is split as a whole, one part is arranged on the first chip, and the other part is arranged on the second chip.

[0066] Specifically, when n2 is greater than or equal to 2, the switch paths set on the second chip can be further split into switch paths as units, that is, the second chip includes at least two; as an example, the number of second chips is set to n2, and in switch paths as units, the n2 switch paths are respectively set one by one on the n2 second chips.

[0067] like Figure 3 and Figure 5 As shown, in this embodiment, N is set to 4, n1 is set to 2, and n2 is set to 2. The single-pole N-throw switch 21 is a single-pole four-throw switch, including a first switch path 21a, a second switch path 21b, a third switch path 21c, and a fourth switch path 21d. Among them, the structure of each switch path is the same, including five-stage switch tubes and four-stage pull-down modules, each stage of the switch tube is cascaded in sequence, and each stage of the pull-down module is arranged between two adjacent stages of the switch tube; each stage of the pull-down module includes two cascaded NMOS tubes.

[0068] As an example, Figure 3 As shown, the chip for setting the SP4T switch includes (one) first chip 22 and (one) second chip 23; the first switch path 21a and the second switch path 21b are set on the first chip 22, and the third switch path 21c and the fourth switch path 21d are set on the second chip 23; Figure 4 As shown, the moving contact of the single-pole four-throw switch is split into two, which are respectively located on the first chip 22 and the second chip 23. The two moving contacts can be electrically connected through a metal lead or a substrate, or can be directly electrically connected to the corresponding pins through a metal lead or a substrate. Since the four-way switch path is split on two chips, the position arrangement between the pads is more flexible while meeting the isolation requirements. The sum of the sizes of the first chip 22 and the second chip 23 is smaller than the size of the four-way switch path set on the same chip, meeting the requirements of reducing costs and ensuring isolation.

[0069] As another example, Figure 5 As shown, the chip for setting the SP4T switch includes (one) first chip 22 and (two) second chips 23a, 23b; the first switch path 21a and the second switch path 21b are arranged on the first chip 22, the third switch path 21c is arranged on the second chip 23a, and the fourth switch path 21d is arranged on the second chip 23b; Figure 6As shown, the moving contact of the single-pole four-throw switch is split into three, which are respectively located on the first chip 22, the second chip 23a and 23b. The three moving contacts can be electrically connected through metal leads or substrates, and can also be directly electrically connected to corresponding pins through metal leads or substrates. The four-way switch path is split on three chips, which can achieve low cost and high isolation requirements.

[0070] It should be noted that in Figure 3 and Figure 4 In the example shown, if the switch paths on the first chip 22 and the second chip 23 have the same structure (the number of components and the connection relationship are the same), the first chip and the second chip are the same chip, which can simplify the manufacturing process (only one chip needs to be manufactured) and reduce the inventory pressure. Figure 5 and Figure 6 In the example shown, the switch paths on the second chips 23a and 23b can also be configured with the same structure. In actual use, the structure of each switch path and the switch path structure on each chip can be set as needed; in addition, on the basis of this embodiment, each switch path can also be further divided into at least two sections, and each section is set on a different chip (such as a third chip, a fourth chip, etc.), further improving flexibility and reducing costs, which will not be described in detail here.

[0071] Embodiment 2

[0072] like Figure 7 to Figure 9 As shown, in this embodiment, the n3 switch paths in the single-pole N-throw switch 21 are arranged on the first chip; the n4 switch paths are divided into a first part (including at least one device) and a second part (including at least one device), wherein the first part of each switch path is arranged on the first chip, and the second part of each switch path is arranged on the second chip; n3+n4=N, n4 is a natural number greater than or equal to 1 and less than or equal to N (when N=1, n3=0, n4=1); that is, at least one switch path is split into two parts, and the two parts are arranged on different chips.

[0073] Specifically, in this embodiment, each switch path is divided into a first section and a second section (two parts), and both the first section and the second section are continuous circuit structures. The first section and the second section of each switch path are connected in series, and one end of the N switch paths on the first chip is connected together; that is, a switch path is divided into two continuous parts, and the first part and the second part are connected in series to obtain a complete switch path, and one end of each switch path on the first chip is connected together to obtain the single-pole N-throw switch structure. In actual use, the first part and the second part can be configured as a discontinuous circuit structure, for example, a switch path is divided into three sections in a cascade order, the front section belongs to the first section, the middle section belongs to the second section, and the rear section belongs to the first section. At this time, it is necessary to add pads and metal leads to realize the electrical connection of the switch path, but the purpose of low cost and high isolation can still be achieved.

[0074] Specifically, when N and n4 are both greater than or equal to 2, the switch paths set on the second chip can be further split into switch paths as units, that is, the second chip includes at least two; the number of the second chips is set to n4, and the n4 switch paths are set one by one on the n4 second chips in units of switch paths.

[0075] like Figure 7 and Figure 8 As shown, in this embodiment, N is set to 3, n3 is set to 0, and n4 is set to 3. The single-pole N-throw switch 21 is a single-pole three-throw switch, including a first switch path 21a, a second switch path 21b, and a third switch path 21c. Among them, the structures of each switch path are the same, and all include five-stage switch tubes and four-stage pull-down modules. The switch tubes of each stage are cascaded in sequence, and the pull-down modules of each stage are arranged between two adjacent switch tubes; each pull-down module includes two cascaded NMOS tubes.

[0076] As an example, Figure 7 As shown, the chip for setting the single-pole three-throw switch includes (one) first chip 22 and (three) second chips 23a, 23b, 23c. The first switch path 21a, the second switch path 21b and the third switch path 23c are divided into a first part and a second part, the first part includes a two-stage switch tube and a two-stage pull-down module, and the second part includes a three-stage switch tube and a two-stage pull-down module; the first part of each switch path is arranged on the first chip 22, the second part of the first switch path 21a is arranged on the second chip 23a, the second part of the second switch path 21b is arranged on the second chip 23b, and the second part of the third switch path 21c is arranged on the second chip 23c. Since the structures of the second parts are the same, the second chips are the same chip.

[0077] As another example, Figure 8 As shown, the chip for setting the single-pole three-throw switch includes (one) first chip 22 and (three) second chips 23a, 23b, 23c. The first switch path 21a, the second switch path 21b and the third switch path 23c are all divided into a first part and a second part; the first part of the first switch path 21a includes a primary switch tube and a primary pull-down module, and the second part includes a fourth switch tube and a third pull-down module; the first part of the second switch path 21b includes a two-stage switch tube and a two-stage pull-down module, and the second part includes a three-stage switch tube and a second-stage pull-down module; the first part of the third switch path 21c includes a three-stage switch tube and a three-stage pull-down module, and the second part includes a second-stage switch tube and a primary pull-down module; the first part of each switch path is arranged on the first chip 22, the second part of the first switch path 21a is arranged on the second chip 23a, the second part of the second switch path 21b is arranged on the second chip 23b, and the second part of the third switch path 21c is arranged on the second chip 23c. In this example, each second chip is a different chip.

[0078] like Fig. 9 As shown, one end of the first part of each switch path on the first chip 22 is connected together as a moving contact, and the other end is respectively connected to one end of the corresponding second part on each second chip, and the other end of the second part on each second chip serves as a static contact. The electrical connection between the chips is achieved through a metal lead or a substrate. The size of the first chip is greatly reduced, and the position of each second chip can be set as needed. Therefore, low cost and high isolation can be effectively taken into account.

[0079] It should be noted that the second part of each switch path can be set on a second chip; the circuit structure of the first part of each switch path can be set to be different, and the circuit structure of the second part of each switch path can also be set to be different; of course, each switch path can also be divided into three or more parts, each part is set on a different chip (for example, the third chip, the fourth chip...), and the complete switch path is obtained through the first chip, the second chip, the third chip... in sequence; I will not go into details here.

[0080] In summary, the present invention can meet the isolation requirements of each pad by placing each chip, and each chip can realize the circuit structure of the single-pole N-throw switch 21 through the electrical connection of metal leads or substrates. At the same time, the area of ​​the chip can be greatly reduced. In one solution, when the circuit structure is exactly the same, compared with Figure 1 The area of ​​the chip in the split switch structure of the present invention is reduced to Figure 1The splitting method of the single-pole N-throw switch of the present invention needs to be determined in combination with the application scenario, performance requirements, packaging requirements, cost, etc. There is no absolute limit on the number and form. Any solution of splitting the single-pole N-throw switch 21 and setting it on different chips belongs to the protection scope of the present invention and will not be described in detail here.

[0081] The present invention further provides an electronic product, which at least comprises: the split switch structure 2 of the present invention. The electronic product includes but is not limited to an electronic switch and a communication device, which will not be described in detail.

[0082] In summary, the present invention provides a split switch structure and electronic product, including: a single-pole N-throw switch, N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch includes N switch paths, each switch path realizes switching by turning on and off a switch tube, and the components in the single-pole N-throw switch are arranged on at least two chips. The split switch structure and electronic product of the present invention split the components of the single-pole multi-throw switch onto at least two chips, thereby reducing the chip area and cost, improving isolation through flexible spatial placement, and thus taking into account both high isolation and low cost, and are suitable for large-scale production and application. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A split switch structure, characterized in that: The split switch structure comprises: A single-pole N-throw switch, wherein N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch includes N switch paths, each switch path is switched by turning on and off a switch tube, and the devices in the single-pole N-throw switch are arranged on at least two chips.

2. The split switch structure according to claim 1, characterized in that: The split switch structure further includes a packaging shell, the single-pole N-throw switch is arranged in the packaging shell, and each pad of the single-pole N-throw switch is electrically connected to a corresponding pin on the packaging shell.

3. The split switch structure according to claim 1, characterized in that: Each switch path includes M-level switch tubes and m-level pull-down modules, where M is a natural number greater than or equal to 1, and m is a natural number greater than or equal to 0 and less than or equal to M+1; when the number M of switch tubes in a switch path is greater than or equal to 2, the switch tubes at each level are cascaded in sequence; one end of each pull-down module is respectively connected to one end of the corresponding switch tube, and the other end is grounded or connected to a specific impedance; the number M of switch tubes and the number m of pull-down modules in each switch path are the same or different.

4. The split switch structure according to claim 3, characterized in that: The pull-down module includes P-level transistors, where P is a natural number greater than or equal to 1. When P is greater than or equal to 2, transistors of each level are connected in series in sequence; the number P of transistors in each pull-down module is the same or different.

5. The split switch structure according to claim 4, characterized in that: The switch tube is an NMOS tube, and the transistor in the pull-down module is an NMOS tube.

6. The split switch structure according to any one of claims 1 to 5, characterized in that: When N is greater than or equal to 2, N switch paths are arranged on at least two chips, and the same switch path is located on the same chip.

7. The split switch structure according to claim 6, characterized in that: In the single-pole N-throw switch, n1 switch paths are arranged on the first chip, and n2 switch paths are arranged on the second chip; n1+n2=N, and n1 is a natural number greater than or equal to 1 and less than N.

8. The split switch structure according to claim 7, characterized in that: When n2 is greater than or equal to 2, the number of the second chips is set to n2, and taking a switch path as a unit, the n2 switch paths are respectively arranged on the n2 second chips in a one-to-one correspondence.

9. The split switch structure according to any one of claims 1 to 5, characterized in that: At least one of the N switch paths is divided into at least two parts, and the parts of the same switch path are located on different chips.

10. The split switch structure according to claim 9, characterized in that: The n3 switch paths in the single-pole N-throw switch are arranged on the first chip; the n4 switch paths are divided into a first section and a second section, wherein the first section of each switch path is arranged on the first chip, and the second section of each switch path is arranged on the second chip; n3+n4=N, n4 is a natural number greater than or equal to 1 and less than or equal to N.

11. The split switch structure according to claim 10, characterized in that: The first section and the second section of each switch path are connected in series, and one ends of the N switch paths on the first chip are connected together.

12. The split switch structure according to claim 11, characterized in that: When N and n4 are both greater than or equal to 2, the number of the second chips is set to n4, and the n4 switch paths are respectively arranged on the n4 second chips in a one-to-one correspondence, taking the switch path as a unit.

13. The split switch structure according to claim 8 or 12, characterized in that: The circuit structures on each second chip are the same.

14. The split switch structure according to any one of claims 1 to 5, characterized in that: The pins on the packaging shell include 1 antenna pin and N radio frequency pins.

15. An electronic product, characterized in that: The electronic product at least includes: a split switch structure as described in any one of claims 1-14.

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