Fractional frequency divider with low quantization noise

Abstract

The invention relates to a fractional frequency divider with low quantization noise. The device comprises a signal selector for receiving a clock signal group and selectively outputting two reference clock signals with adjacent phases in the clock signal group based on a fractional configuration bit in a fractional frequency division ratio signal, and a phase shift circuit for receiving the two reference clock signals with adjacent phases output by the signal selector and selectively outputting the two reference clock signals with adjacent phases in the clock signal group based on the fractional configuration bit in the fractional frequency division ratio signal. The phase-shift circuit is used for receiving reference clock signals and performing clock synthesis based on phase-shift control signals loaded by the delta-sigma modulator so as to synthesize the two reference clock signals with adjacent phases into phase-shift clock signals, and the configurable frequency divider is used for receiving the phase-shift clock signals of the phase-shift circuit and performing integer frequency division on the phase-shift clock signals based on received integer frequency division ratio signals so as to obtain frequency division signals of the phase-shift clock signals. And after integer frequency division, a frequency division clock signal in an effective state is loaded to the delta-sigma modulator, so that the delta-sigma modulator updates the phase shift control signal under the frequency division clock signal in the effective state. According to the invention, the circuit can work at a higher clock frequency, and has low quantization noise.

Description

Technical Field

[0001] The invention relates to a fractional frequency divider, in particular to a fractional frequency divider with low quantization noise. Background Art

[0002] A fractional frequency divider is a circuit used to achieve non-integer frequency division. Its design and application are very important in many fields. For example, fractional frequency dividers are often used in frequency synthesizers to achieve more precise frequency control and optimize phase noise performance.

[0003] According to the characteristics of the fractional frequency divider, it is known to those skilled in the art that any frequency divider cannot really work at a non-integer frequency division. Specifically, the frequency division ratio may use different integer values ​​under different reference clock cycles, but over a long period of time, the average frequency division ratio is a non-integer. It should be noted that this frequency division ratio averaging method will definitely introduce some problems, such as residual error noise. Generally, the residual noise error is caused by the instantaneous phase error of each cycle.

[0004] If the range of the instantaneous frequency division ratio can be reduced and / or the phase difference between the instantaneous frequency division ratio and the target frequency division ratio can be reduced, the phase noise will be reduced, thereby reducing the residual error noise. In order to reduce the instantaneous phase error of each cycle, phase interpolation is currently used. When phase interpolation is used, different phase clocks can be used for frequency division.

[0005] The traditional phase interpolation method is to switch the clock phase of the voltage-controlled oscillator output while the Δ-Σ modulator updates the binary code, which can reduce the instantaneous phase error of each cycle to one-quarter of the oscillation period of the voltage-controlled oscillator. However, existing literature and design experience have shown that the phase switching mechanism needs to be completed within one-quarter of the clock cycle of the voltage-controlled oscillator, otherwise the effective clock signal will be missed.

[0006] From the above description, it can be seen that when using traditional phase interpolation, it is necessary to face the limitation of one-quarter clock cycle of the voltage-controlled oscillator, which makes the fractional divider only suitable for application scenarios with not too high clock frequency, limiting the expansion of application scenarios of the fractional divider. Summary of the invention

[0007] The object of the present invention is to overcome the deficiencies in the prior art and provide a fractional frequency divider with low quantization noise, which can operate at a higher clock frequency and has low quantization noise.

[0008] According to the technical solution provided by the present invention, a fractional frequency divider with low quantization noise comprises:

[0009] A signal selector receives a clock signal group, and selects and outputs two reference clock signals with adjacent phases in the clock signal group based on the fractional configuration bit in the fractional frequency division ratio signal, wherein the clock signal group includes a plurality of reference clock signals, and the clock phase difference values ​​of any two adjacent reference clock signals are consistent;

[0010] A phase shift circuit receives two reference clock signals with adjacent phases output by a signal selector, and performs clock synthesis based on a phase shift control signal loaded by a delta-sigma modulator, so as to synthesize the two reference clock signals with adjacent phases into a phase-shifted clock signal, wherein the frequency of the phase-shifted clock signal is consistent with that of the two reference clock signals with adjacent phases, and the phase of the phase-shifted clock signal is between the corresponding phases of the two adjacent reference clock signals;

[0011] A configurable frequency divider receives a phase-shifted clock signal from a phase-shifting circuit, performs integer frequency division on the phase-shifted clock signal based on a received integer frequency division ratio signal, and loads a frequency-divided clock signal in a valid state to a Δ-Σ modulator after the integer frequency division, so that the Δ-Σ modulator updates the phase-shifted control signal under the frequency-divided clock signal in a valid state.

[0012] The phase shift circuit includes at least two phase shift processing units, wherein:

[0013] The two phase shift processing units are adaptively connected so as to respectively receive two reference clock signals output by the signal selector by using the two phase shift processing units, and the phase shift control signal generated by the delta-sigma modulator is simultaneously loaded into the two phase shift processing units;

[0014] When the phase shift control signal is a binary sequence, each phase shift processing unit includes a plurality of phase shift processing branches, and the number of phase shift processing branches in each phase shift processing unit is not less than the bit width of the phase shift control signal, so that each phase shift control bit in the phase shift control signal corresponds to a phase shift processing branch in each phase shift processing unit;

[0015] Any phase shift processing branch includes a phase shift differential input section, a tail current source and a tail current switch section, wherein:

[0016] The phase-shift differential input section is connected to the tail current switch section through a tail current source;

[0017] All phase-shift differential input parts in the phase-shift circuit are adapted and connected to the passive load;

[0018] In the phase shift processing section, the phase shift differential input section corresponds to the corresponding received reference clock signal, wherein the reference clock signal is directly loaded into an input power tube in the phase shift differential input section, and the reference clock signal is inverted and loaded into another input power tube in the same phase shift differential input section;

[0019] In the phase shift processing section, a tail current switch section of a phase shift processing branch corresponds to a phase shift control bit in the phase shift control signal, wherein:

[0020] For the phase shift processing unit that receives the phase-delayed reference clock signal, each phase shift control bit is directly loaded into the tail current switch unit of the corresponding phase shift processing unit.

[0021] For the phase shift processing section receiving the phase leading reference clock signal, each phase shift control bit is inverted and then loaded into the tail current switch section in the corresponding phase shift processing section.

[0022] When the tail current source adopts a MOS tube, the conductive channel width-to-length ratios of the MOS tubes adopted by the tail current source in the same phase shift processing unit are different, wherein:

[0023] For the phase shift processing unit receiving the phase-delayed reference clock signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually increases according to the sequence of the phase shift control bits in the phase shift control signal;

[0024] In the phase shift processing section for receiving the phase-advanced reference clock signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually decreases according to the sequence of the phase shift control bits in the phase shift control signal.

[0025] In the two phase-shift processing sections, the input power tubes used in all phase-shift differential input sections have the same conductive channel width-to-length ratio;

[0026] In the two phase-shift processing sections, the tail current switch sections all use phase-shift control power tubes, the types of the phase-shift control power tubes used in the tail current switch sections are the same, and all the phase-shift control power tubes have the same conductive channel width-to-length ratio.

[0027] For the phase-shifted clock signal generated by the phase-shifting circuit, we have:

[0028]

[0029] Among them, Δ yx is the phase difference between the phase of the phase-shifted clock signal and the phase of the corresponding phase of the phase-leading reference clock signal, Δ jz A is the phase difference between the phase of the phase-lag reference clock signal and the corresponding phase of the phase-shift clock signal. 1 is the decimal value corresponding to the phase shift control signal of the binary sequence, A 2 It is a decimal value corresponding to the inverted phase shift control signal of the binary sequence, wherein when the phase shift control signal is inverted, the phase shift control signal is inverted, and an accumulation operation of adding 1 is performed after the inversion.

[0030] The signal selector includes a first multiplexer and a second multiplexer, wherein:

[0031] Each reference clock signal in the clock signal group is simultaneously loaded to the corresponding input terminals of the first multiplexer and the second multiplexer;

[0032] The fractional configuration bits in the fractional frequency division ratio signal are loaded to the corresponding control terminals of the first multiplexer and the second multiplexer, wherein:

[0033] Based on the fractional configuration bit, the ordinal number n of the reference clock signal is determined, and thereafter, the nth reference clock signal loaded into the first multiplexer is selected and output based on the ordinal number n, and the n+1th reference clock signal loaded into the second multiplexer is selected and output.

[0034] All reference clock signals in the clock signal group are provided by the same voltage-controlled oscillator, and all reference clock signals have the same frequency, where:

[0035] When the number of reference clock signals in the clock signal group is m, the m reference clock signals are sequentially sorted in the order of 0 to m-1;

[0036] If the ordinal number n determined by the fractional configuration bit is m-1, the reference clock signal ranked 0 is used as the n+1th reference clock signal.

[0037] The divided clock signal output by the fractional frequency divider is also loaded into a frequency detector, the input end of the frequency detector receives a reference clock signal Fref, the output end of the frequency detector is connected to a charge pump, the output end of the charge pump is connected to a loop filter, and the loop filter is connected to a voltage-controlled oscillator.

[0038] The voltage-controlled oscillator is a ring voltage-controlled oscillator, wherein:

[0039] When the number m of reference clock signals provided by the voltage-controlled oscillator is 8, then: the reference clock signal VCO with the order of 0 is <0> The phase is 0° and the sequence is 1. <1> The phase is 45° and the reference clock signal VCO is sequenced as 2 <2> The phase is 90° and the sequence is 3 reference clock signal VCO <3> The phase is 135° and the sequence is 4 reference clock signal VCO <4> The phase is 180° and the sequence is 5 reference clock signal VCO <5> The phase is 225° and the sequence is 6 reference clock signal VCO <6> The phase is 270° and the sequence is 7. <7> The phase is 315°.

[0040] The configurable frequency divider comprises a dual-mode pre-divider, wherein:

[0041] In the case of integer frequency division, the frequency division count information is determined based on the integer frequency division ratio signal, and the phase-shifted clock signal is divided based on the frequency division count information. After the phase-shifted clock signal is divided, the dual-mode pre-divider generates a high-level frequency-divided clock signal, so as to use the high-level frequency-divided clock signal as the frequency-divided clock signal in a valid state;

[0042] After one clock cycle of the phase-shifted clock signal, the divided clock signal returns to a low level.

[0043] The advantages of the present invention are as follows: the combination of a signal selector and a phase shift circuit replaces the function of phase switching, wherein the signal selector is used to select two reference clock signals with adjacent phases, and the phase shift circuit is used to perform clock synthesis on the two reference clock signals. During clock synthesis, a phase shift control signal generated by a Δ-Σ modulator is used so that the clock signal of the phase-shifted clock signal generated by the clock synthesis is located between the two reference clock signals, and the phase step of the phase-shifted clock signal is smaller. The smaller quantization step makes the quantization noise of the fractional divider transferred to a higher frequency area and easier to be filtered out by the loop filter. The fractional divider contributes less to the quantization noise of the phase-locked loop, thereby enabling the fractional divider to cope with scenarios with higher clock frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 The figure is a structural block diagram of an embodiment of the fractional frequency divider of the present invention.

[0045] Figure 2 The structure block diagram of an embodiment of the fractional frequency divider working scenario of the present invention.

[0046] Figure 3 The figure is a circuit diagram of an embodiment of the signal selector of the present invention.

[0047] Figure 4 The figure is a circuit diagram of an embodiment of the phase shifting circuit of the present invention.

[0048] Figure 5 The figure is a circuit block diagram of an embodiment of a configurable frequency divider of the present invention.

[0049] Figure 6 The following is a flowchart of an embodiment of a configurable frequency divider of the present invention.

[0050] Explanation of the reference numerals: 1-signal selector, 2-phase shift circuit, 3-configurable frequency divider, 4-Δ-Σ modulator, 5-first multiplexer, 6-second multiplexer, 7-frequency detector and phase detector, 8-charge pump, 9-loop filter, 10-voltage controlled oscillator, 11-fractional frequency divider, 12-counting controller, 13-multi-mode frequency divider. DETAILED DESCRIPTION

[0051] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0052] In order to enable the fractional frequency divider 11 to operate at a higher clock frequency and have low quantization noise, the present invention provides a fractional frequency divider 11 with low quantization noise. Specifically, the fractional frequency divider 11 includes:

[0053] A signal selector 1 receives a clock signal group, and selects and outputs two reference clock signals with adjacent phases in the clock signal group based on the fractional configuration bit in the fractional frequency division ratio signal, wherein the clock signal group includes a plurality of reference clock signals, and the clock phase difference values ​​of any two adjacent reference clock signals are consistent;

[0054] A phase shift circuit 2 receives two reference clock signals with adjacent phases output by a signal selector 1, and performs clock synthesis based on a phase shift control signal loaded by a delta-sigma modulator 4, so as to synthesize the two reference clock signals with adjacent phases into a phase-shifted clock signal, wherein the frequency of the phase-shifted clock signal is consistent with that of the two reference clock signals with adjacent phases, and the phase of the phase-shifted clock signal is between the corresponding phases of the two adjacent reference clock signals;

[0055] The configurable divider 3 receives the phase-shifted clock signal of the phase-shifting circuit 2, and performs integer division on the phase-shifted clock signal based on the received integer division ratio signal, and loads a divided clock signal in a valid state to the Δ-Σ modulator 4 after the integer division, so that the Δ-Σ modulator 4 updates the phase-shifted control signal under the divided clock signal in a valid state.

[0056] Figure 1 An embodiment of a fractional frequency divider 11 is shown in FIG. In the figure, the fractional frequency divider 11 may include a signal selector 1, a phase shift circuit 2, a configurable frequency divider 3 and a delta-sigma modulator 4, wherein the signal selector 1 is used to receive the externally loaded clock signal group and the fractional configuration bit in the fractional frequency division ratio signal, and the clock signal group may include multiple reference clock signals, and the number of reference clock signals in the clock signal group should be no less than 3, and the number of reference clock signals in the clock signal group can be selected according to actual needs. For the multiple reference clock signals in the clock signal group, the clock phase difference between two adjacent reference clock signals is consistent, and a cyclic clock signal can be formed between the multiple reference clock signals, wherein the multiple reference clock signals are arranged in sequence and connected head to tail. At this time, the first reference clock signal and the second reference clock signal are two clock signals with adjacent phases, and the first reference clock signal and the last reference clock signal also constitute two clock signals with adjacent phases. Other situations are similar, and they are not listed one by one here.

[0057] For the two reference clock signals with adjacent phases in the above clock signal group, the difference between the corresponding clock phases of the second reference clock signal and the first reference clock signal is consistent with the difference between the corresponding clock phases of the last reference clock signal and the first reference clock signal, and the same applies to other cases, which are not listed here one by one. After all the reference clock signals in the clock signal group are loaded into the signal selector 1, the two reference clock signals with adjacent phases can be selected for output through the fractional configuration bits in the fractional frequency division ratio signal, that is, the two reference clock signals with adjacent phases selected and output by the signal selector 1 are related to the fractional configuration bits. The following is an example of the clock signal group, the signal selector 1, and the case where the signal selector 1 selects two reference clock signals with adjacent phases under the fractional configuration bits.

[0058] Figure 2 FIG. 1 shows an embodiment of a fractional frequency divider 11 applied in a phase-locked loop. When the fractional frequency divider 11 is applied in a phase-locked loop, the phase-locked loop should include a voltage-controlled oscillator 10, a frequency detector 7, a charge pump 8, and a loop filter 9, wherein:

[0059] The divided clock signal output by the fractional frequency divider 11 is also loaded into the frequency detector 7, the input end of the frequency detector 7 receives the reference clock Fref, the output end of the frequency detector 7 is connected to the charge pump 8, the output end of the charge pump 8 is connected to the loop filter 9, and the loop filter 9 is connected to the voltage controlled oscillator 10.

[0060] In a specific implementation, the voltage-controlled clock signal output by the voltage-controlled oscillator 10 is divided by the fractional frequency divider 11 to form a divided clock signal loaded into the frequency detector 7. Figure 1 and Figure 2 In the example, FB is the divided clock signal. In addition, the frequency detector 7 also receives a reference clock. Figure 1 Where Fref is the reference clock. The frequency detector and phase detector 7 can generate a voltage-controlled voltage VCTRL through a charge pump 8, and the voltage-controlled voltage VCTRL is filtered by a loop filter 9 and then loaded into a voltage-controlled oscillator 10.

[0061] It should be noted that the phase frequency detector 7, charge pump 8, loop filter 9 and voltage controlled oscillator 10 in the phase-locked loop circuit can adopt existing commonly used circuit forms, which are based on the working requirements of the phase-locked loop circuit. The phase-locked loop circuit can achieve frequency locking. After the phase-locked loop is formed by the voltage controlled oscillator 10, the phase frequency detector 7, the charge pump 8, the loop filter 9 and the fractional frequency divider 11, the way in which the phase-locked loop achieves frequency locking can be consistent with the prior art, and the specific way and process of achieving frequency locking will not be repeated here.

[0062] right Figure 2FIG. 1 shows an embodiment in which the fractional frequency divider 11 is applied to a phase-locked loop, in which all reference clock signals in the clock signal group are provided by the same voltage-controlled oscillator 10, and all reference clock signals have the same frequency, wherein:

[0063] When the number of reference clock signals in the clock signal group is m, the m reference clock signals are sequentially sorted in the order of 0 to m-1;

[0064] If the ordinal number n determined by the fractional configuration bit is m-1, the reference clock signal ranked 0 is used as the n+1th reference clock signal.

[0065] It can be understood that when all the reference clock signals are generated and provided by the same voltage-controlled oscillator 10, the frequencies of all the reference clock signals should be the same, that is, for the clock signal group to be loaded into the signal selector 1, the frequencies of the reference clock signals in the clock signal group are the same. The voltage-controlled oscillator 10 can generate m reference clock signals at the same time, and then the m reference clock signals can be numbered sequentially, such as the first reference clock signal can be numbered 0, the second reference clock signal can be numbered 1, and the last reference clock signal should be numbered m-1.

[0066] When selecting the reference clock signal in the clock signal group, the ordinal number n of the reference clock signal to be selected should be determined based on the fractional configuration bit in the fractional frequency division ratio signal, and then the reference clock signals corresponding to the ordinal number n and the ordinal number n+1 are respectively used as the two clock reference signals with adjacent phases to be selected and output. Since the reference clock signals in the clock signal group are connected end to end, when the ordinal number n determined based on the fractional configuration bit is m-1, the reference clock signal with the ordinal number 0 is used as the n+1th reference clock signal.

[0067] In one embodiment of the present invention, the voltage controlled oscillator 10 is a ring voltage controlled oscillator, wherein:

[0068] When the number m of reference clock signals provided by the voltage controlled oscillator 10 is 8, the reference clock signal VCO with the order of 0 is <0> The phase is 0° and the sequence is 1. <1> The phase is 45° and the reference clock signal VCO is sequenced as 2 <2> The phase is 90° and the sequence is 3 reference clock signal VCO <3> The phase is 135° and the sequence is 4 reference clock signal VCO <4> The phase is 180° and the sequence is 5 reference clock signal VCO <5> The phase is 225° and the sequence is 6 reference clock signal VCO <6> The phase is 270° and the sequence is 7. <7> The phase is 315°.

[0069] In order to make the generated reference clock signal constitute a cyclic clock signal, the voltage-controlled oscillator 10 should be selected as a ring voltage-controlled oscillator, wherein the ring voltage-controlled oscillator can adopt the existing commonly used form, specifically based on the ability to generate a reference clock signal that can constitute a cyclic clock signal. When the number m of reference clock signals provided by the voltage-controlled oscillator 10 is 8, it can be seen from the above description that the 8 reference clock signals should be numbered 0 to 7, and then the corresponding phases of the 8 reference clock signals can be obtained. When the voltage-controlled oscillator 10 provides other numbers of reference clock signals, the numbers and corresponding phase relationships between the reference clock signals can all refer to the above description, and no examples are given here one by one.

[0070] In one embodiment of the present invention, the signal selector 1 includes a first multiplexer 5 and a second multiplexer 6, wherein:

[0071] Each reference clock signal in the clock signal group is simultaneously loaded to the corresponding input terminals of the first multiplexer 5 and the second multiplexer 6;

[0072] The fractional configuration bits in the fractional frequency division ratio signal are loaded to the corresponding control terminals of the first multiplexer 5 and the second multiplexer 6, wherein:

[0073] Based on the fractional configuration bit, the ordinal number n of the reference clock signal is determined, and thereafter, the nth reference clock signal loaded into the first multiplexer 5 is selected and output based on the ordinal number n, and the n+1th reference clock signal loaded into the second multiplexer 6 is selected and output.

[0074] Figure 3 An embodiment of the signal selector 1 is shown in the figure. In the figure, the signal selector 1 includes at least a first multiplexer 5 and a second multiplexer 6. For example, when the number m of reference clock signals is 8, the first multiplexer 5 and the second multiplexer 6 can both adopt 8-to-1 multiplexers. When m is other values, the corresponding types of the first multiplexer 5 and the second multiplexer 6 can be determined accordingly.

[0075] In order to select two reference clock signals with adjacent phases, all reference clock signals in the clock signal group should be simultaneously loaded to the corresponding input terminals of the first multiplexer 5 and the second multiplexer 6. However, the corresponding connection relationship between the reference clock signals and the corresponding input terminals of the first multiplexer 5 and the second multiplexer 6 should be different. Figure 3In the embodiment shown in FIG. 1 , the first multiplexer 5 and the second multiplexer 6 each have 8 input terminals, which are input terminals I0 to I7. At this time, the reference clock signal VCO <0> ~Reference clock signal VCO <7> The reference clock signal VCO <0> Corresponding to the I7 input terminal of the second multiplexer 6, the reference clock signal VCO <1> ~Reference clock signal VCO <7> They correspond to the I0 input terminal to the I6 input terminal of the second multiplexer 6 respectively.

[0076] Figure 1 and Figure 2 In the example, Frac<23:0> is the fractional frequency division ratio signal. At this time, the data bit width of the fractional frequency division ratio signal is 24. Figure 1 In the example, the upper three bits of the fractional frequency division ratio signal are used as the fractional configuration bits, and the fractional configuration bits should be Frac<23:21>, that is, the fractional configuration bits have three binary data bits. At this time, the ordinal number n of the reference clock signal can be determined by the fractional allocation bits. For example, when the fractional configuration bits are 001, the corresponding ordinal number n should be 1. The reference clock signal VCO is converted to the reference clock signal VCO by the first multiplexer 5. <1> The reference clock signal VCO can be selected and output through the second multiplexer 6. <2> Select output; if the fraction configuration bit is 010, the corresponding ordinal number n should be 2, and the reference clock signal VCO is transmitted through the first multiplexer 5 <2> The reference clock signal VCO can be selected and output through the second multiplexer 6. <3> Select output; for other selected output situations, please refer to the instructions here and will not be repeated here.

[0077] In a specific implementation, the fractional frequency division ratio signal Frac<23:0> may be externally loaded, that is, provided by an external circuit, etc. Figure 1 In the embodiment, the fractional frequency division ratio signal Frac<23:0> should also be loaded to the delta-sigma modulator 4, but the signal selector 1 only uses the upper three bits of the fractional frequency division ratio signal Frac<23:0> as the fractional configuration bits.

[0078] Depend on Figure 3 As can be seen from the above description, regardless of the fractional configuration bit in the fractional frequency division ratio signal Frac<23:0>, the reference clock signal VCO selected and output by the signal selector 1 is<n+1> and the reference clock signal VCO <n>must be adjacent in phase, and the reference clock signal VCO<n+1> The clock phase lags behind the reference clock signal VCO <n>phase.

[0079] In one embodiment of the present invention, the phase shift circuit 2 includes at least two phase shift processing units, wherein:

[0080] The two phase shift processing units are adaptively connected so as to utilize the two phase shift processing units to respectively receive the two reference clock signals output by the signal selector 1, and the phase shift control signal generated by the delta-sigma modulator 4 is simultaneously loaded into the two phase shift processing units;

[0081] When the phase shift control signal is a binary sequence, each phase shift processing unit includes a plurality of phase shift processing branches, and the number of phase shift processing branches in each phase shift processing unit is not less than the bit width of the phase shift control signal, so that each phase shift control bit in the phase shift control signal corresponds to a phase shift processing branch in each phase shift processing unit;

[0082] Any phase shift processing branch includes a phase shift differential input section, a tail current source and a tail current switch section, wherein:

[0083] The phase-shift differential input section is connected to the tail current switch section through a tail current source;

[0084] All phase-shift differential input parts in the phase-shift circuit are adapted and connected to the passive load;

[0085] In the phase shift processing section, the phase shift differential input section corresponds to the corresponding received reference clock signal, wherein the reference clock signal is directly loaded into an input power tube in the phase shift differential input section, and the reference clock signal is inverted and loaded into another input power tube in the same phase shift differential input section;

[0086] In the phase shift processing section, a tail current switch section of a phase shift processing branch corresponds to a phase shift control bit in the phase shift control signal, wherein:

[0087] For the phase shift processing unit that receives the phase-delayed reference clock signal, each phase shift control bit is directly loaded into the tail current switch unit of the corresponding phase shift processing unit.

[0088] For the phase shift processing section receiving the phase leading reference clock signal, each phase shift control bit is inverted and then loaded into the tail current switch section in the corresponding phase shift processing section.

[0089] In order to realize the generation of a phase-shifted clock signal after phase shifting of two reference clock signals, the phase shift circuit 2 should include at least two phase shift processing units, and the two phase shift processing units are adaptively connected. At this time, for the signal selector 1 outputs two reference clock signals with adjacent phases, the two reference clock signals can be loaded into the two phase shift processing units respectively, that is, the two reference clock signals correspond to the two phase shift processing units one by one. It can be seen from the above description that the phase shift circuit 2 should perform clock synthesis based on the phase shift control signal generated by the Δ-Σ modulator 4. Specifically, when based on the phase shift control signal generated by the Δ-Σ modulator 4, the phase shift control signal should be loaded into each phase shift processing unit at the same time.

[0090] In a specific implementation, the phase shift control signal may be a binary sequence, that is, the phase shift control signal is binary data, and the data bit width of the phase shift control signal may be 2 or 3. In this case, the phase shift control signal may include 2 binary phase shift control bits or 3 binary phase shift control bits. Figure 1 Bit<2:0> in is the phase shift control signal generated by the Δ-Σ modulator 4. It can be seen that Figure 1 An embodiment in which the phase shift control signal includes three phase shift control bits is shown. It can be understood that the phase shift control signal can vary between 000 and 111. When the phase shift control signal includes two phase shift control bits, please refer to the description here and no longer list them one by one.

[0091] It should be noted that each phase shift processing unit can adopt the same structural form, wherein each phase shift processing unit can include a plurality of phase shift processing branches, and the number of phase shift processing branches in each phase shift processing unit is preferably the same, and the number of phase shift processing branches in each phase shift processing unit is preferably consistent with the number of phase shift control bits in the phase shift control signal. Figure 1 In the embodiment, each phase shift processing unit includes three phase shift processing branches. At this time, each phase shift control bit of the phase shift control signal can correspond to a phase shift processing branch. Specifically, each phase shift control bit can correspond to a phase shift processing branch, which specifically means loading a phase shift control bit to a corresponding phase shift processing branch.

[0092] In specific implementation, each phase-shift processing branch may adopt the same structural form, such as each phase-shift processing branch may include a phase-shift differential input part, a tail current source and a tail current switch part, wherein, in the same phase-shift processing branch, the phase-shift differential input part is connected to the tail current switch part through the tail current source, and the phase-shift differential input part includes two input power tubes, and the two input power tubes are used to form a differential input form. The two input power tubes in the phase-shift differential input part generally use the same type of power tubes, such as two input power tubes can be formed by two NMOS tubes. In addition, all the phase-shift differential input parts in the two phase-shift processing parts are connected to a passive load, so that the adaptive connection between the two phase-shift processing parts can be achieved. The passive load, the phase-shift processing part and the phase-shift processing branch in the phase-shift processing part will be combined below. Figure 4 Provide detailed explanation.

[0093] It can be seen from the above description that each phase shift processing unit will receive a phase shift control signal and a reference clock signal. Specifically, for each phase shift processing unit, the received reference clock signal is loaded into the phase shift differential input unit, and a phase shift control bit in the phase shift control signal corresponds to a tail current switch unit; wherein, since each phase shift differential input unit has two input power tubes, when a reference clock signal is loaded into the corresponding phase shift differential input unit, the reference clock signal is generally directly loaded into the gate end of one of the input power tubes, and the gate end of the other input power tube receives the inverted reference clock signal.

[0094] It should be noted that the phase shift control bit corresponds to the tail current switch part, specifically refers to using the phase shift control bit to control the switching state of the corresponding tail current switch part, such as controlling the tail current switch part to be in the on state or the tail current switch part to be in the off state through the phase shift control bit. When the tail current switch part is in the on state, the tail current source corresponding to the tail current switch part is in the working state, and the phase shift processing branch where the tail current switch part is located is in the working state.

[0095] It can be seen from the above description that the two reference clock signals output by the signal selector 1 have the same frequency, but the phases of the two reference clock signals are different. In order to realize clock synthesis, in one embodiment of the present invention, for the phase shift processing unit that receives the phase-lag reference clock signal, each phase shift control bit is directly loaded to the tail current switch unit of the corresponding phase shift processing unit; and for the phase shift processing unit that receives the phase-advanced reference clock signal, each phase shift control bit is inverted and loaded to the tail current switch unit in the corresponding phase shift processing unit. Specifically, the reference clock signal VCO<n+1> The clock phase lags behind the reference clock signal VCO <n>The phase of the reference clock signal VCO<n+1> That is, the phase-delayed reference clock signal, the reference clock signal VCO <n>That is the phase-advanced reference clock signal.

[0096] Figure 3 An embodiment of the phase shift circuit 2 is shown in FIG. Figure 3 In the circuit, NMOS tubes N1 to NMOS tubes N6 serve as a tail current switch part respectively. Figure 3 In Bit <2> 、Bit <1> 、Bit <0> There are three phase shift control bits, phase shift control bit Bit <2> Loaded to the gate end of NMOS tube NM3, the phase shift control bit <1> Loaded to the gate end of NMOS tube N2, the phase shift control bit <0> Loaded to the gate terminal of NMOS tube N1, it can be seen that NMOS tube N1, NMOS tube N2, NMOS tube N3 belong to the same phase shift processing unit, and the phase shift processing unit receives the phase-delayed reference clock signal. <0> When the phase shift control bit is "1", the NMOS tube N1 is in the closed conduction state. <0> When it is "0", the NMOS tube N1 is in the off state, and the phase shift control bit Bit <1> , Phase shift control bit <2> The working situation can be referred to here.

[0097] Figure 3 In the phase shift control bit <2> The inverted phase shift control bit Bit <2> Loaded to the gate end of NMOS tube N4, the phase shift control bit <1> The inverted phase shift control bit Bit <1> Loaded to the gate end of NMOS tube N5, the phase shift control bit <0> After being inverted by inverter X1, the inverted phase shift control bit Bit <0> Loaded to the gate terminal of NMOS tube N6, it can be seen that NMOS tube N4, NMOS tube N5, NMOS tube N6 belong to the same phase shift processing unit, and the phase shift processing unit receives the reference clock signal with advanced phase. <0> When it is "1", it is inverted by the inverter X1 and becomes "0". The NMOS tube N6 is still in the off state. When the phase shift control bit Bit <0> When it is "0", it is inverted by inverter X1 and becomes "1", and the NMOS tube N6 is in the on state.

[0098] Figure 3 In the example shown, each phase shift processing unit includes three phase shift processing branches, and the phase shift circuit 2 includes 6 NMOS transistors as tail current switch units. When working, the 6 tail current switch units in the phase shift circuit 6 must have 3 NMOS transistors in the closed conduction state and 3 NMOS transistors in the open state, that is, only three phase shift processing branches participate in the clock synthesis in the phase shift circuit 2 at the same time.<n+1> , reference clock signal VCO <n>The same voltage-controlled oscillator 10 generates two reference clock signals with different clock phases. Therefore, the frequency of the phase-shifted clock signal generated by clock synthesis is the same as the reference clock signal VCO.<n+1> , reference clock signal VCO <n>Keep the frequency consistent. Figure 1 , Figure 4 and Figure 5 In the figure, Mout is the phase-shifted clock signal.

[0099] In one embodiment of the present invention, when the tail current source adopts a MOS transistor, the conductive channel width-to-length ratios of the MOS transistors adopted by the tail current source in the same phase shift processing unit are different, wherein:

[0100] For the phase shift processing unit receiving the phase-delayed reference clock signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually increases according to the sequence of the phase shift control bits in the phase shift control signal;

[0101] In the phase shift processing section for receiving the phase-advanced reference clock signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually decreases according to the sequence of the phase shift control bits in the phase shift control signal.

[0102] In specific implementation, the tail current source can use a MOS tube. Figure 3 In the embodiment of the phase shift circuit 2 shown in FIG. 1 , the tail current sources all adopt NMOS tubes. In the figure, NMOS tubes N7 to NMOS tubes N12 are all NMOS tubes adopted by the tail current sources. The source terminal of NMOS tube N7 is connected to the drain terminal of NMOS tube N1, and the source terminal of NMOS tube N1 is grounded. The source terminal of NMOS tube N8 is connected to the drain terminal of NMOS tube N2, and the source terminal of NMOS tube N2 is grounded. The source terminal of NMOS tube N9 is connected to the drain terminal of NMOS tube N3, and the source terminal of NMOS tube N3 is grounded. The source terminal of NMOS tube N10 is connected to the drain terminal of NMOS tube N4, and the source terminal of NMOS tube N4 is grounded. The source terminal of NMOS tube N11 is connected to the drain terminal of NMOS tube N5, and the source terminal of NMOS tube N5 is grounded. The source terminal of NMOS tube N12 is connected to the drain terminal of NMOS tube N6, and the source terminal of NMOS tube N6 is grounded.

[0103] Figure 3 In the embodiment, the gate terminals of NMOS tubes N7 to NMOS tubes N12 are connected to bias voltage Vbias, and bias voltage Vbias is provided externally. As can be seen from the above description, the working state of the tail current source is controlled by the tail current switch connected to the tail current source. For example, when NMOS tube N1 is in a closed conduction state, the tail current source formed by NMOS tube N7 is in a working state. For other situations, please refer to the description here.

[0104] Specifically, the width-to-length ratios of the conductive channels used by the tail current sources in the same phase shift processing unit are different. Figure 3 In the example, the width-to-length ratio of the conductive channel of the NMOS tube N7 is M, the width-to-length ratio of the conductive channel of the NMOS tube N8 is 2M, and the width-to-length ratio of the conductive channel of the NMOS tube N9 is 4M. Since the phase shift processing branch where the NMOS tube N7 is located is connected to the phase shift control bit Bit <0> Correspondingly, the phase shift processing branch where the NMOS tube N8 is located is connected to the phase shift control bit Bit <1> Correspondingly, the phase shift processing branch where the NMOS tube N9 is located is connected to the phase shift control bit Bit <2> Correspondingly, according to the sequence of the phase shift control bits in the phase shift control signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually increases.

[0105] Figure 3 In the example, the width-to-length ratio of the conductive channel of the NMOS tube N12 is M, the width-to-length ratio of the conductive channel of the NMOS tube N11 is 2M, and the width-to-length ratio of the conductive channel of the NMOS tube N10 is 4M. Since the phase shift processing branch where the NMOS tube N12 is located is connected to the phase shift control bit Bit <0> Correspondingly, the phase shift processing branch where the NMOS tube N11 is located is connected to the phase shift control bit Bit <1> Correspondingly, the phase shift processing branch where the NMOS tube N10 is located is connected to the phase shift control bit Bit <2> Correspondingly, according to the sequence of the phase shift control bits in the phase shift control signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually decreases.

[0106] It can be seen from the above description that for the phase shift processing unit that receives the phase-lag reference clock signal, according to the bit sequence of the phase shift control bit in the phase shift control signal, the corresponding ratio of the width-to-length ratio of the conductive channel of the MOS tube used by the corresponding tail current source is 1:2:4; for the phase shift processing unit that receives the phase-advanced reference clock signal, according to the bit sequence of the phase shift control bit in the phase shift control signal, the corresponding ratio of the width-to-length ratio of the conductive channel of the MOS tube used by the corresponding tail current source is 4:2:1. Here, the bit sequence of the phase shift control bit in the phase shift control signal can be the order of the phase shift control bit from high to low in the phase shift control signal, such as the above-mentioned phase shift control bit Bit <2> To the phase shift control bit <0> order.

[0107] In a specific implementation, for two phase shift processing branches corresponding to the same phase shift control bit, the tail current sources in the phase shift processing branches use the same type of MOS tubes, and the width-to-length ratios of the conductive channels of the used MOS tubes are consistent.

[0108] In one embodiment of the present invention, in the two phase shift processing units, the input power tubes used in all phase shift differential input units have the same conductive channel width-to-length ratio;

[0109] In the two phase-shift processing sections, the tail current switch sections all use phase-shift control power tubes, the types of the phase-shift control power tubes used in the tail current switch sections are the same, and all the phase-shift control power tubes have the same conductive channel width-to-length ratio.

[0110] From the above description, it can be seen that the phase-shift differential input part includes two input power tubes, and the two input power tubes are generally MOS tubes. In specific implementation, all input power tubes in the phase-shift circuit 2 are of the same type and have the same conductive channel width-to-length ratio. Figure 3 In the embodiment, NMOS tube N13 and NMOS tube N19 constitute two input power tubes in a phase-shift differential input part. The corresponding source terminals of NMOS tube N13 and NMOS tube N19 are connected to the drain terminal of NMOS tube N7. The gate terminal of NMOS tube N13 is connected to the reference clock signal VCO.<n+1> , the gate terminal of NMOS tube N9 is connected to the output terminal of inverter X4. At this time, the reference clock signal VCO<n+1> After being inverted by the inverter X4, it is loaded to the gate terminal of the NMOS tube N19, the drain terminal of the NMOS tube N13 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the power supply VDD, the drain terminal of the NMOS tube N19 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the power supply VDD. Here, the resistor R1, the resistor R2 and the power supply VDD form a passive load.

[0111] Figure 3 In the embodiment, NMOS tube N14 and NMOS tube N20 constitute two input power tubes in a phase-shift differential input part. The corresponding source terminals of NMOS tube N14 and NMOS tube N20 are connected to the drain terminal of NMOS tube N8. The gate terminal of NMOS tube N14 is connected to the reference clock signal VCO.<n+1> , the gate terminal of NMOS tube N20 is connected to the output terminal of inverter X4. At this time, the reference clock signal VCO<n+1> After being inverted by the inverter X4, it is loaded to the gate terminal of the NMOS tube N20, the drain terminal of the NMOS tube N14 is connected to the first end of the resistor R1, and the drain terminal of the NMOS tube N20 is connected to the first end of the resistor R2.

[0112] Figure 3 In the embodiment, NMOS tube N15 and NMOS tube N21 constitute two input power tubes in a phase-shift differential input part. The corresponding source terminals of NMOS tube N15 and NMOS tube N21 are connected to the drain terminal of NMOS tube N10, and the gate terminal of NMOS tube N15 is connected to the reference clock signal VCO.<n+1> , the gate terminal of NMOS tube N21 is connected to the output terminal of inverter X4. At this time, the reference clock signal VCO<n+1> After being inverted by the inverter X4, it is loaded to the gate terminal of the NMOS tube N21, the drain terminal of the NMOS tube N15 is connected to the first end of the resistor R1, and the drain terminal of the NMOS tube N21 is connected to the first end of the resistor R2.

[0113] Figure 3 In the embodiment, NMOS tube N16 and NMOS tube N22 constitute two input power tubes in a phase-shift differential input part. The corresponding source terminals of NMOS tube N16 and NMOS tube N22 are connected to the drain terminal of NMOS tube N11, and the gate terminal of NMOS tube N16 is connected to the reference clock signal VCO. <n>, the gate terminal of NMOS tube N22 is connected to the output terminal of inverter X5. At this time, the reference clock signal VCO <n>After being inverted by the inverter X5, it is loaded to the gate terminal of the NMOS tube N22, the drain terminal of the NMOS tube N16 is connected to the first end of the resistor R1, and the drain terminal of the NMOS tube N22 is connected to the first end of the resistor R2.

[0114] Figure 3 In the embodiment, NMOS tube N17 and NMOS tube N23 constitute two input power tubes in a phase-shift differential input part. The corresponding source terminals of NMOS tube N17 and NMOS tube N23 are connected to the drain terminal of NMOS tube N12, and the gate terminal of NMOS tube N17 is connected to the reference clock signal VCO. <n>, the gate terminal of NMOS tube N23 is connected to the output terminal of inverter X5. At this time, the reference clock signal VCO <n>After being inverted by the inverter X5, it is loaded to the gate terminal of the NMOS tube N23, the drain terminal of the NMOS tube N17 is connected to the first end of the resistor R1, and the drain terminal of the NMOS tube N23 is connected to the first end of the resistor R2.

[0115] Depend on Figure 3 As can be seen from the phase shift circuit 2 described above, when the input power transistors in all phase shift differential input parts have the same conductive channel width-to-length ratio, the magnitude of the tail current determines the contribution of each instantaneous differential input signal.

[0116] As can be seen from the above description, in the phase shift circuit 2, the reference clock signal VCO is received.<n+1> The number of phase shift processing branches in the phase shift processing unit is related to the received reference clock signal VCO <n>The number of phase shift processing branches in the phase shift processing section is consistent. At this time, the corresponding number of phase shift differential input sections and tail current sources in each phase shift processing section is also the same, thereby maintaining the reference clock signal VCO<n+1> , reference clock signal VCO <n>Balance in clock synthesis.

[0117] The tail current source of each phase shift processing branch is connected to the same bias voltage Vbias, and the tail current contribution ratio can be set according to the width-to-length ratio of the conductive channel of the MOS tube used in the tail current source. As mentioned above, the width-to-length ratio of the conductive channel used in the tail current source is 1:2:4. At this time, the tail current contribution ratio in each phase shift processing unit is 1:2:4. The working state of the tail current source is regulated by the tail current switch unit, and the switching state of the tail current switch unit is controlled by the phase shift control signal generated by the Δ-Σ modulator 4.

[0118] Specifically, the clock synthesis method of the phase shift circuit 2 and the Δ-Σ modulator 4 can be used to configure the reference clock signal VCO in the phase shift circuit 2 based on the phase shift control signal of the binary sequence generated by the Δ-Σ modulator 4.<n+1> , reference clock signal VCO <n>The weight is set during clock synthesis so that: the average of the binary sequence phase-shift control signal is equal to the fractional value of the fractional divider 11, wherein the fractional value of the fractional divider 11 is the decimal value corresponding to the fractional division ratio signal Frac<23:0>, that is, the frequency and phase of the phase-shift clock signal, which is equal to the frequency and phase of the expected output clock of the phase-locked loop corresponding to the fractional division ratio signal Frac<23:0>.

[0119] It should be noted that the Δ-Σ modulator 4 can adopt the existing commonly used form. The Δ-Σ modulator 4 can generate a phase shift control signal under the fractional division ratio signal Frac<23:0>. Specifically, the phase shift control signal generated by the Δ-Σ modulator 4 is random, but after a long period of change, the average value of the phase shift control signal generated by the Δ-Σ modulator 4 is the fractional value corresponding to the fractional configuration bit. Therefore, it can be seen that the average value of the phase change of the phase-shifted clock signal will follow the clock phase shift value corresponding to the fractional configuration bit.

[0120] Since the phase shift value of the phase shift circuit 2 is linearly related to the binary sequence given by the delta-sigma modulator 4, the phase shift value of the phase shift circuit 2 specifically refers to the difference between the phase of the phase-shifted clock signal and the corresponding phase of the reference clock signal with a phase lead. Specifically, the phase change range of the phase-shifted clock signal is 0°, 5.625°, 11.25°, 16.875°, 22.5°, 28.125°, 33.75° and 39.375° (based on the reference clock signal VCO <n>The above phase changes correspond to the binary sequences of the phase shift control signals provided by the Δ-Σ modulator 4 as follows: 000, 001, 010, 011, 100, 101, 110 and 111. When the binary sequence corresponding to the phase shift control signal is 000, the phase of the phase shift clock signal is the same as the reference clock signal VCO. <n>The corresponding phase shift value should be 0. At this time, the phase of the phase-shifted clock signal is consistent with the reference clock signal VCO <n>The corresponding phases are the same; when the binary sequence corresponding to the phase-shift control signal is 001, the phase of the phase-shift clock signal is the same as the reference clock signal VCO <n>The corresponding phase shift value should be 5.625°. At this time, the phase of the phase-shifted clock signal lags behind the reference clock signal VCO <n>When the binary sequence corresponding to the phase shift control signal is other than the limit of 5.625°, you can refer to the description here to determine the phase shift clock signal and the reference clock signal VCO <n>The corresponding phase shift value.

[0121] From the above description, it can be seen that when the number m of reference clock signals provided by the voltage controlled oscillator 10 is 8, then among the 8 reference clock signals, the corresponding phase difference between two adjacent reference clock signals is 45°, that is, the reference clock signal VCO <n>With the reference clock signal VCO<n+1> The corresponding phase difference is 45°. The present invention utilizes the binary sequence phase shift control signal and the phase shift circuit 2 to subdivide the phase difference of 45°. As can be seen from the above description, when subdividing, the phase shift clock signal and the reference clock signal VCO <n>The corresponding difference may be 45 / 8=5.625°. For other situations, please refer to the above description.

[0122] It should be noted that when the traditional phase interpolation method is used, the phase variation range is 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315°. It can be seen that the quantization step of the present invention can be one eighth of the quantization step corresponding to the traditional phase interpolation method, that is, compared with the existing phase interpolation method, the quantization step can be effectively reduced. In addition, when the quantization step is set to one eighth of the quantization step corresponding to the traditional phase interpolation method, the corresponding ratio of the width-to-length ratio of the conductive channel of the MOS tube used in the above-mentioned tail current source should adopt the above-mentioned situation.

[0123] It can be understood that, over a long period of time, the division ratio of the fractional divider 11 is obtained by averaging multiple integer division ratios, and the integer division ratio of each clock cycle of the reference clock is different from the expected fractional division ratio. The resulting instantaneous phase error will appear in the clock jitter at the output end of the phase-locked loop in the form of quantization noise, and the minimum value of the instantaneous phase error, that is, the quantization step size, determines the distribution of the quantization noise in the frequency domain.

[0124] As can be seen from the above description, the quantization step of the present invention can be reduced to one eighth of the quantization step corresponding to the traditional phase interpolation method. At this time, the reduction of the quantization step means that the instantaneous phase difference identified by the frequency detector 7 becomes smaller, and the quantized phase noise appears in a higher frequency area. The loop filter 9 has a low-pass characteristic and has a better filtering effect on the high-frequency quantization noise. Therefore, when the fractional frequency divider 11 of the present invention is applied to the phase-locked loop, it can have a lower quantization noise characteristic.

[0125] In one embodiment of the present invention, for the phase-shifted clock signal generated by the phase-shifting circuit, there is:

[0126]

[0127] Among them, Δ yx is the phase difference between the phase of the phase-shifted clock signal and the corresponding phase of the phase-advanced reference clock signal, Δ jz A is the phase difference between the phase of the phase-lag reference clock signal and the corresponding phase of the phase-shift clock signal. 1 is the decimal value corresponding to the phase shift control signal of the binary sequence, A 2 It is a decimal value corresponding to the inverted phase shift control signal of the binary sequence, wherein when the phase shift control signal is inverted, the phase shift control signal is inverted, and an accumulation operation of adding 1 is performed after the inversion.

[0128] Specifically, when the reference clock signal in the clock signal group is provided by the voltage-controlled oscillator 10, and the number m of the reference clock signals in the clock signal group is 8, then in a clock synthesis, if the binary sequence corresponding to the phase-shift control signal is 001, it can be obtained from the above description that the phase difference Δ between the phase of the phase-shift clock signal and the phase leading the corresponding phase of the reference clock signal yx The phase difference between the phase of the phase-lag reference clock signal and the corresponding phase of the phase-shift clock signal is Δ jz It should be 39.375°. At this time, A 1 is 1; negate it to get A 2 Then, we have: after negating 001, we get 110, and the cumulative operation of adding 1 is 111, from which we can get the corresponding decimal A 2 is 7. When the phase shift control signal is in other cases, please refer to the description here, and no examples are given here.

[0129] In one embodiment of the present invention, the configurable frequency divider 3 comprises a dual-mode pre-divider, wherein:

[0130] In the case of integer frequency division, the frequency division count information is determined based on the integer frequency division ratio signal, and the phase-shifted clock signal is divided based on the frequency division count information. After the phase-shifted clock signal is divided, the dual-mode pre-divider generates a high-level frequency-divided clock signal, so as to use the high-level frequency-divided clock signal as the frequency-divided clock signal in a valid state;

[0131] After one clock cycle of the phase-shifted clock signal, the divided clock signal returns to a low level.

[0132] Specifically, the dual-mode prescaler can adopt an existing commonly used form. Figure 5 An embodiment of a dual-mode pre-divider is shown in FIG. 1 . In the figure, the dual-mode pre-divider includes a multi-mode divider 13 and a counter controller 12 . The counter controller 12 generally includes a P counter and an S counter. Figure 5 Int<6:0> is the integer frequency division ratio signal, which is loaded into the counter controller 12. Thereafter, the corresponding maximum count values ​​of the P counter and the S counter can be determined according to the integer frequency division ratio signal. The specific working process is described below by taking a 4 / 5 dual-mode prescaler as an example.

[0133] Figure 5 In the process, the phase-shifted clock signal is loaded into the multi-mode divider 13, and the multi-mode divider 13 outputs a divided clock signal. In the initial state, the divided clock signal FB is at a low level. After determining the corresponding maximum count values ​​of the P counter and the S counter, the phase-shifted clock signal is first divided by five. Each time the frequency is divided by five, the S counter is reduced by one until the S counter returns to zero. After the S counter returns to zero, the frequency division by four begins. Each time the frequency is divided by four, the P counter is reduced by one until the P counter returns to zero. After the P counter returns to zero, the multi-mode divider 13 outputs a high-level divided clock signal. After one clock cycle of the phase-shifted clock signal, the divided clock signal returns to a low level, and a frequency division cycle of a reference clock ends. The corresponding working process can be referred to. Figure 6 Flowchart shown.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A fractional frequency divider with low quantization noise, characterized in that The fractional frequency divider comprises: A signal selector receives a clock signal group, and selects and outputs two reference clock signals with adjacent phases in the clock signal group based on the fractional configuration bit in the fractional frequency division ratio signal, wherein the clock signal group includes a plurality of reference clock signals, and the clock phase difference values ​​of any two adjacent reference clock signals are consistent; A phase shift circuit receives two reference clock signals with adjacent phases output by a signal selector, and performs clock synthesis based on a phase shift control signal loaded by a delta-sigma modulator, so as to synthesize the two reference clock signals with adjacent phases into a phase-shifted clock signal, wherein the frequency of the phase-shifted clock signal is consistent with that of the two reference clock signals with adjacent phases, and the phase of the phase-shifted clock signal is between the corresponding phases of the two adjacent reference clock signals; A configurable frequency divider receives a phase-shifted clock signal from a phase-shifting circuit, performs integer frequency division on the phase-shifted clock signal based on a received integer frequency division ratio signal, and loads a frequency-divided clock signal in a valid state to a Δ-Σ modulator after the integer frequency division, so that the Δ-Σ modulator updates the phase-shifted control signal under the frequency-divided clock signal in a valid state.

2. The fractional frequency divider with low quantization noise according to claim 1, characterized in that: The phase shift circuit includes at least two phase shift processing units, wherein: The two phase shift processing units are adaptively connected so as to respectively receive two reference clock signals output by the signal selector by using the two phase shift processing units, and the phase shift control signal generated by the delta-sigma modulator is simultaneously loaded into the two phase shift processing units; When the phase shift control signal is a binary sequence, each phase shift processing unit includes a plurality of phase shift processing branches, and the number of phase shift processing branches in each phase shift processing unit is not less than the bit width of the phase shift control signal, so that each phase shift control bit in the phase shift control signal corresponds to a phase shift processing branch in each phase shift processing unit; Any phase shift processing branch includes a phase shift differential input section, a tail current source and a tail current switch section, wherein: The phase-shift differential input section is connected to the tail current switch section through a tail current source; All phase-shift differential input parts in the phase-shift circuit are adapted and connected to the passive load; In the phase shift processing section, the phase shift differential input section corresponds to the corresponding received reference clock signal, wherein the reference clock signal is directly loaded into an input power tube in the phase shift differential input section, and the reference clock signal is inverted and loaded into another input power tube in the same phase shift differential input section; In the phase shift processing section, a tail current switch section of a phase shift processing branch corresponds to a phase shift control bit in the phase shift control signal, wherein: For the phase shift processing unit that receives the phase-delayed reference clock signal, each phase shift control bit is directly loaded into the tail current switch unit of the corresponding phase shift processing unit. For the phase shift processing section receiving the phase leading reference clock signal, each phase shift control bit is inverted and then loaded into the tail current switch section in the corresponding phase shift processing section.

3. The fractional frequency divider with low quantization noise according to claim 2, characterized in that: When the tail current source adopts a MOS tube, the conductive channel width-to-length ratios of the MOS tubes adopted by the tail current source in the same phase shift processing unit are different, wherein: For the phase shift processing unit receiving the phase-delayed reference clock signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually increases according to the sequence of the phase shift control bits in the phase shift control signal; In the phase shift processing section for receiving the phase-advanced reference clock signal, the width-to-length ratio of the conductive channel of the MOS tube used in the corresponding tail current source gradually decreases according to the sequence of the phase shift control bits in the phase shift control signal.

4. The fractional frequency divider with low quantization noise according to claim 2, characterized in that: In the two phase-shift processing sections, the input power tubes used in all phase-shift differential input sections have the same conductive channel width-to-length ratio; In the two phase-shift processing sections, the tail current switch sections all use phase-shift control power tubes, the types of the phase-shift control power tubes used in the tail current switch sections are the same, and all the phase-shift control power tubes have the same conductive channel width-to-length ratio.

5. The fractional frequency divider with low quantization noise according to claim 2, characterized in that: For the phase-shifted clock signal generated by the phase-shifting circuit, we have: Among them, Δ yx is the phase difference between the phase of the phase-shifted clock signal and the phase of the corresponding phase of the phase-leading reference clock signal, Δ jz is the phase difference between the phase of the phase-lag reference clock signal and the corresponding phase of the phase-shift clock signal, A1 is the decimal value corresponding to the phase-shift control signal of the binary sequence, and A2 is the decimal value corresponding to the inverted phase-shift control signal of the binary sequence, wherein, when the phase-shift control signal is inverted, the phase-shift control signal is inverted, and an accumulation operation of adding 1 is performed after the inversion.

6. The fractional frequency divider with low quantization noise according to any one of claims 1 to 5, characterized in that: The signal selector includes a first multiplexer and a second multiplexer, wherein: Each reference clock signal in the clock signal group is simultaneously loaded to the corresponding input terminals of the first multiplexer and the second multiplexer; The fractional configuration bits in the fractional frequency division ratio signal are loaded to the corresponding control terminals of the first multiplexer and the second multiplexer, wherein: Based on the fractional configuration bit, the ordinal number n of the reference clock signal is determined, and thereafter, the nth reference clock signal loaded into the first multiplexer is selected and output based on the ordinal number n, and the n+1th reference clock signal loaded into the second multiplexer is selected and output.

7. The fractional frequency divider with low quantization noise according to claim 6, characterized in that: All reference clock signals in the clock signal group are provided by the same voltage-controlled oscillator, and all reference clock signals have the same frequency, where: When the number of reference clock signals in the clock signal group is m, the m reference clock signals are sequentially sorted in the order of 0 to m-1; If the ordinal number n determined by the fractional configuration bit is m-1, the reference clock signal ranked 0 is used as the n+1th reference clock signal.

8. The fractional frequency divider with low quantization noise according to claim 7, characterized in that: The divided clock signal output by the fractional frequency divider is also loaded into a frequency detector, the input end of the frequency detector receives a reference clock signal Fref, the output end of the frequency detector is connected to a charge pump, the output end of the charge pump is connected to a loop filter, and the loop filter is connected to a voltage-controlled oscillator.

9. The fractional frequency divider with low quantization noise according to claim 8, characterized in that: The voltage-controlled oscillator is a ring voltage-controlled oscillator, wherein: When the number m of reference clock signals provided by the voltage-controlled oscillator is 8, then: the reference clock signal VCO with the order of 0 is <0> The phase is 0° and the sequence is 1. <1> The phase is 45° and the reference clock signal VCO is sequenced as 2 <2> The phase is 90° and the sequence is 3 reference clock signal VCO <3> The phase is 135° and the sequence is 4 reference clock signal VCO <4> The phase is 180° and the sequence is 5 reference clock signal VCO <5> The phase is 225° and the sequence is 6 reference clock signal VCO <6> The phase is 270° and the sequence is 7. <7> The phase is 315°.

10. The fractional frequency divider with low quantization noise according to any one of claims 1 to 5, characterized in that: The configurable frequency divider comprises a dual-mode pre-divider, wherein: In the case of integer frequency division, the frequency division count information is determined based on the integer frequency division ratio signal, and the phase-shifted clock signal is divided based on the frequency division count information. After the phase-shifted clock signal is divided, the dual-mode pre-divider generates a high-level frequency-divided clock signal, so as to use the high-level frequency-divided clock signal as the frequency-divided clock signal in a valid state; After one clock cycle of the phase-shifted clock signal, the divided clock signal returns to a low level.

Images