Data processing method and device, equipment and storage medium

Abstract

The invention provides a data processing method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining the state information of a first cache in response to a received request instruction, and determining the state of the first cache according to the state information: the request instruction is used for indicating a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in the network-on-chip, and the target cache is a cache in a second access device for calculating data in the network-on-chip; and when it is detected that the state of the first cache is a non-busy state, writing the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router. According to the invention, unnecessary traffic on the internet can be effectively reduced, and the overall performance of the system can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data processing method, device, electronic device and computer-readable storage medium. Background Art

[0002] In a multi-processor system with shared memory, each processor is equipped with an independent cache to improve system performance. However, multiple caches may store copies of the same data, so when a processor modifies data, it needs to communicate between multiple caches to ensure that the copies of the data in all caches are consistent.

[0003] In related technologies, in order to adapt to different application scenarios and optimize performance, the communication method between multiple caches is complex to implement and difficult to apply flexibly. In addition, the complex communication method significantly increases the debugging and verification costs of the application party, making potential errors increasingly difficult to discover and repair. Summary of the invention

[0004] The embodiments of the present application provide a data processing method, device, electronic device and computer-readable storage medium to solve the problems in the related art.

[0005] In a first aspect, an embodiment of the present application provides a data processing method, the method comprising: In response to the received request instruction, the state information of the first cache is obtained, and the state of the first cache is determined according to the state information: the request instruction is used to instruct the target cache to write the first target data into the first cache, the first cache is a cache in a first access device for storing data in the network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; When it is detected that the state of the first cache is a non-busy state, the first target data stored in the target cache of the second access device is written into the first cache of the first access device through the first router and the second router.

[0006] In a second aspect, an embodiment of the present application provides a data processing device, the device comprising: A first acquisition module is used to obtain state information of a first cache in response to a received request instruction, and determine the state of the first cache according to the state information: the request instruction is used to instruct a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; The first writing module is used to write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router when detecting that the state of the first cache is not busy.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of the first aspect.

[0008] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0009] In the embodiment of the present application, in response to the received request instruction, the state information of the first cache is obtained, and the state of the first cache is determined according to the state information: the request instruction is used to instruct the target cache to write the first target data into the first cache, the first cache is a cache in a first access device for storing data in the on-chip network, the first access device is connected to the first router in the on-chip network, the target cache is a cache in a second access device for calculating data in the on-chip network, and the second access device is connected to the second router in the on-chip network; when it is detected that the state of the first cache is a non-busy state, the first target data stored in the target cache of the second access device is written to the first cache of the first access device through the first router and the second router. In this way, it can be determined whether to write data based on the state information of the first cache, the process is simple and intuitive, unnecessary operations and data transmission can be avoided, thereby effectively reducing unnecessary traffic on the Internet, and the waiting time for data transmission can be reduced, so that data can be more efficiently circulated and updated in the system, thereby improving the overall performance of the system. In addition, while ensuring consistency specifications and performance requirements, a more streamlined operation process can be adopted, reducing the manpower, time and other costs in the development and debugging process, and improving the efficiency and quality of system development.

[0010] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 It is a structural diagram of a multi-core system of a network on chip provided by the background technology of this application; Figure 2 is a flow chart of a data processing method provided in an embodiment of the present application; Figure 3 is a flow chart of another data processing method provided in an embodiment of the present application; Figure 4 It is a flowchart of the execution steps of data processing provided by an embodiment of the present application; Figure 5is a flow chart of another data processing method provided in an embodiment of the present application; Figure 6 is a flowchart of another data processing execution step provided by an embodiment of the present application; Figure 7 is a flow chart of another data processing method provided in an embodiment of the present application; Figure 8 is a flowchart of another data processing execution step provided by an embodiment of the present application; Fig. 9 is a block diagram of a data processing device provided in an embodiment of the present application; Fig.10 is a block diagram of an electronic device according to an exemplary embodiment; Fig.11 is a block diagram of another electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0015] Before introducing the data processing method, device, electronic device and storage medium provided by the present disclosure, the application scenarios involved in each embodiment of the present disclosure are first introduced. The present disclosure can be applied to the scenario of communication between multiple caches in a multi-core processor, and the data processing method provided by the embodiment of the present disclosure can be applied to a system on chip. Among them, the system on chip is a complete electronic system integrated on a single chip, and the electronic system may include multiple functional modules, such as a processor, a memory, various interfaces, an analog circuit, and various digital logic units.

[0016] At present, with the widespread application of multi-core processors and distributed systems, cache consistency has become an important challenge affecting system performance and reliability. In a multi-processor system with shared memory, in order to improve system performance, each processor is usually equipped with an independent cache. Figure 1 As shown, multiple Core nodes work together, where a Core node can be considered as a processor. In a shared memory multi-processor system, each Core node is usually equipped with an independent cache. For example, in a computer processor with multiple cores, Core1 node has its own cache, Core2 node also has its own exclusive cache, etc. They can temporarily store data in their respective caches to speed up data reading and processing.

[0017] Since multiple caches may store copies of the same data, when a processor modifies the data, it needs to communicate through multiple caches to ensure that the copies in all caches are consistent. For example, the value of a variable is stored in the caches of different Core nodes. When one of the Core nodes modifies the data, in order to ensure the accuracy and reliability of the system, the copies of the data in the caches of other Core nodes must also remain consistent, which requires communication through multiple caches. If no corresponding measures are taken, the copies of the data in the caches of different Core nodes will be inconsistent, which will affect the accuracy of subsequent calculations and processing based on this data by the entire system, and in severe cases may even cause system errors and crashes.

[0018] Therefore, in the related art, a cache consistency protocol can be used to implement communication between multiple caches, wherein the cache consistency protocol is used to define multiple types of operations for communication between multiple caches; in order to adapt to different application scenarios and optimize performance, the types and number of domain segments of cache consistency protocol transmission instructions are increasing. Figure 1In the system architecture shown, multiple Core nodes, router nodes and other nodes, such as LLCSF (cache consistency) nodes, Memory nodes, etc., are interconnected to form a complex network. It becomes very difficult to implement communication between multiple caches according to the protocol in a complex network structure. Developers need to consider a large number of instruction types and domain segment settings. It is difficult to easily adapt them to different system configurations and application scenarios. The flexibility is greatly reduced, and the complex communication method significantly increases the debugging and verification costs of the application party, making potential errors increasingly difficult to find and fix.

[0019] In order to solve the above problems, the present disclosure provides a data processing method, device, electronic device and computer-readable storage medium, which can decide whether to write data based on the state information of the first cache. The process is simple and intuitive, and unnecessary operations and data transmission can be avoided, thereby effectively reducing unnecessary traffic on the Internet, and reducing the waiting time for data transmission, so that data can be more efficiently circulated and updated in the system, thereby improving the overall performance of the system. And while ensuring consistency specifications and performance requirements, a more streamlined operation process can be adopted, reducing the manpower, time and other costs in the development and debugging process, and improving the efficiency and quality of system development.

[0020] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0021] Figure 2 is a flow chart of a data processing method provided in an embodiment of the present application, such as Figure 2 As shown, the method is applied to a system on chip, wherein the system on chip is a complete electronic system integrated on a single chip, and the electronic system may include multiple functional modules, such as a processor, a memory, various interfaces, an analog circuit, and various digital logic units.

[0022] The method may include the following steps.

[0023] In step 101, in response to a received request instruction, state information of a first cache is acquired, and a state of the first cache is determined according to the state information.

[0024] Among them, the request instruction is used to instruct the target cache to write the first target data into the first cache, the first cache is a cache in a first access device in the on-chip network for storing data, the first access device is connected to the first router in the on-chip network, and the target cache is a cache in a second access device in the on-chip network for calculating data, and the second access device is connected to the second router in the on-chip network.

[0025] In a multi-core system of an on-chip network, multiple second access devices can be integrated, and the second access devices can be Core nodes. The multiple Core nodes are interconnected and communicated through the on-chip network to achieve data interaction and collaborative work to complete complex computing tasks. The on-chip network also includes a Memory node as the core area for data storage, which provides data reading and writing support for each Core node.

[0026] In this step, if the target cache has a need to write the first target data into the first cache, the target cache can send an electrical signal or a data packet representing the request instruction through the corresponding hardware signal line or the communication protocol of the on-chip network. These signals or data packets will be propagated in the on-chip network according to established routing rules, thereby triggering the system to start the step of obtaining the status information of the first cache.

[0027] The on-chip network may also include a first access device for calculating data. The first cache may be the cache of the first access device. The first access device itself may have corresponding monitoring and control logic, and may be able to perceive in real time the various operations being performed by itself and the resource occupancy status, and then generate status information based on these conditions. The status information may be transmitted in the form of electrical signals, and may be directly transmitted to each target cache in the on-chip network in the form of high or low levels (for example, a high level indicates busy, and a low level indicates idle).

[0028] For example, the first access device can be a Memory node, which has corresponding monitoring and control logic, can perceive various operations and resource occupancy of itself in real time, and then generate and send out mem_busy indication signals according to these conditions. In one possible implementation, this signal can be directly transmitted to each Core node in the form of high and low levels (for example, high level indicates busy, low level indicates idle) through hardware wiring; in another possible implementation, this signal can also follow the communication protocol of the on-chip network, encapsulate the busy status information in the form of a message packet, and then send it to the relevant Core nodes in the system according to the established routing rules, to ensure that each Core node can obtain the busy status information of the Memory node in a timely manner.

[0029] Optionally, there is a corresponding relationship between the status information of the first cache and the status of the first cache. For example, when the status information of the first cache indicates busyness, the status of the first cache is busy; when the status information of the first cache indicates non-busyness, the status of the first cache is non-busy.

[0030] In step 102, when it is detected that the state of the first cache is a non-busy state, the first target data stored in the target cache of the second access device is written into the first cache of the first access device through the first router and the second router.

[0031] Considering that when the state of the first cache is busy, if the data writing operation is performed rashly, it may cause data conflicts, for example, it may cause errors in the data being written or read in the first cache, destroying the consistency of the data, or interfering with the normal cache operation process, thereby affecting the subsequent calculations and processing tasks based on the cache data of the entire system. Therefore, writing the first target data to the first cache when it is determined that the first cache is not busy can ensure that the data writing operation can be performed safely.

[0032] In this step, the first router and the second router are key nodes in the on-chip network responsible for data transmission routing, which are used to build a data transmission channel from the target cache to the first cache. The first target data can start from the target cache of the second access device, forward the data to the appropriate link in the on-chip network through the second router, and then accurately guide the first target data to the location of the first access device through the first router, and finally write it into the first cache of the first access device.

[0033] In some embodiments, the request instruction can be sent to the first cache through the first router and the second router; then, upon receiving the response information sent by the first cache according to the received request instruction, the first target data is sent to the first access device through the first router and the second router, and the first target data is written to the first cache.

[0034] For example, after determining that the first cache is in a non-busy state, the system can start a corresponding data transmission mechanism to read the first target data from the target cache. Then, the first target data can be encapsulated into a data packet suitable for transmission in the on-chip network. In a possible implementation, in addition to the actual first target data, the data packet can also include a target address (i.e., address information of the first cache), a source address (related identification of the second access device, etc.), verification information, etc., so that the accuracy and traceability of the first target data during transmission can be guaranteed. Then, the data packet can be sent to the second router, and the second router can determine the direction and link to be forwarded next according to its internal routing table and a pre-set routing algorithm (such as a shortest path algorithm, a traffic-based routing algorithm, etc.), and forward the data packet to a suitable path so that it is transmitted in the direction of the first router. When the data packet arrives at the first router, the first router also accurately guides the data packet to the first access device according to its own routing mechanism. After the first access device receives the data packet, it can successfully write the first target data into the first cache according to the corresponding unpacking and writing rules.

[0035] In this way, by first detecting the status of the first cache and writing data when it is not busy, the timing of data writing can be reasonably arranged to avoid forced writing when the cache is busy. This can avoid data confusion caused by unreasonable write operations and prevent additional resource consumption caused by data conflicts, ensuring that the data in each cache and related storage area is always consistent and complete.

[0036] By adopting the above technical solution, it is possible to decide whether to write data based on the state information of the first cache. The process is simple and intuitive, and unnecessary operations and data transmission can be avoided, thereby effectively reducing unnecessary traffic on the Internet and the waiting time for data transmission, so that data can flow and update more efficiently in the system, thereby improving the overall performance of the system. In addition, while ensuring consistency specifications and performance requirements, a more streamlined operation process can be adopted, reducing the manpower, time and other costs in the development and debugging process, and improving the efficiency and quality of system development.

[0037] In some embodiments, Figure 3 As shown, the method may further include the following steps.

[0038] In step 201, in response to a received request instruction, state information of a first cache is acquired, and a state of the first cache is determined according to the state information.

[0039] In step 202, when it is detected that the state of the first cache is a busy state, the first target data stored in the target cache of the second access device is sent to the coherent cache through the second router.

[0040] The consistency cache is a cache in a third access device in the network on chip for executing consistency transactions, and the third access device is connected to a second router in the network on chip.

[0041] In this step, if it is determined that the first cache is in a busy state, it can be determined that the first cache is currently performing activities such as data read and write operations, internal data update or replacement, and is temporarily unable to receive new data writes. Therefore, the first target data planned to be written into the first cache can be transmitted to the coherent cache through the second router.

[0042] For example, the first target data can be read from the target cache of the second access device according to the reading rules and storage structure of the target cache, and then the first target data can be encapsulated into a data packet suitable for transmission in the on-chip network. The data packet can contain necessary information, such as the first target data itself, the source address (information identifying the relevant information of the second access device), the target address (pointing to the relevant identifier of the consistency cache in the third access device) and verification information, so as to ensure the accuracy and traceability of the data during the transmission process. Then, the data packet can be sent to the second router, and the second router can determine the forwarding path of the first target data in the on-chip network based on its internal pre-set routing table and routing algorithm (such as the shortest path algorithm based on the destination, etc.), and forward the data packet to the third access device. Finally, the third access device unpacks the received data packet and successfully stores the first target data in its internal consistency cache.

[0043] In this way, in a multi-core system, since data consistency needs to be maintained between different caches, when the first cache is temporarily unable to receive data, the data can be temporarily stored in the consistency cache, which can assist in achieving data consistency coordination between different caches, ensuring that the data in each cache can eventually reach a consistent state in the correct order and rules, and avoiding data inconsistency problems caused by cache busyness and other situations from affecting the normal operation of the entire system.

[0044] In step 203, new status information of the first cache is obtained, and the step of determining the status of the first cache according to the status information is re-executed.

[0045] In step 204, until it is detected that the state of the first cache is a non-busy state, the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device continues.

[0046] In this step, since the busy state of the first cache may change over time, for example, the previous read and write operations may have ended, and its internal maintenance work may have been completed, thus changing to a non-busy state that can receive new data. Therefore, after transferring the first target data to the consistent cache, it is necessary to obtain new status information of the first cache again, and perform the step of determining the status of the first cache based on the status information again. In this way, it is possible to accurately grasp when the first cache can receive data writes, ensuring that the entire data write operation can be performed at an appropriate and safe time.

[0047] The step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device will not be performed until it is detected that the state of the first cache has changed to a non-busy state.

[0048] In some embodiments, Figure 4 As shown, until it is detected that the state of the first cache is not busy, the first target data stored in the consistency cache of the third access device can be sent to the first access device through the first router and the second router; then the first target data can be written into the first cache of the first access device.

[0049] By way of example, the first target data may be written from the source cache (target cache of the second access device) to the final first cache through the first router and the second router.

[0050] This ensures that when the first cache is busy, the system can still coordinate the storage and flow of data in an orderly manner, maintain data consistency and stable operation of the entire on-chip network multi-core system.

[0051] In some embodiments, when the first target data stored in the consistency cache of the third access device is sent to the first access device through the first router and the second router, the remaining memory capacity in the consistency cache can be obtained first; then, when it is determined that the remaining memory capacity is less than or equal to a preset threshold, the first target data stored in the consistency cache can be sent to the first access device through the first router and the second router.

[0052] Optionally, the third access device to which the consistent cache is accessed may include a corresponding monitoring component, which is used to obtain the memory usage of the cache, for example, it may include hardware counters, registers and other components. The hardware counter can count the used memory space accordingly as the data is written and read, and the value of the remaining memory capacity can be obtained by subtracting the used memory capacity from the total memory capacity of the consistent cache. Alternatively, a specific register will be used to store information about the size of the currently used memory space, and the system can calculate the remaining memory capacity by reading the value of the register and combining it with the pre-known total capacity of the consistent cache.

[0053] When the remaining memory capacity in the coherent cache is obtained, the remaining memory capacity is compared with a numerical value of a preset threshold to determine whether the remaining memory capacity in the coherent cache is sufficient to continue storing data.

[0054] Among them, the preset threshold can be a preset indicator pre-set by the on-chip network system based on multiple factors such as the overall performance of the consistent cache, historical data traffic, or expected cache resource reservation. When the remaining memory capacity reaches or is lower than the preset threshold, the memory resources of the consistent cache are already relatively tight. For example, if the total capacity of the consistent cache is 100 storage units, considering that there may be frequent data temporary storage needs in daily operation, in order to ensure that it can cope with a certain number of emergencies, the system may set the preset threshold to 20 storage units, that is, when the remaining memory capacity is less than or equal to 20 storage units, it is considered that the memory resources of the consistent cache are already relatively tight.

[0055] Therefore, when the remaining memory capacity is less than or equal to a preset threshold, the first target data stored in the consistency cache can be sent to the first access device through the first router and the second router.

[0056] For example, the first target data can be read from the consistency cache first, and then the first target data can be encapsulated into a data packet suitable for transmission in the on-chip network. The data packet may include the source address (clearly indicating that the data comes from the consistency cache of the third access device), the target address (pointing to the first access device), verification information and other necessary contents, so as to ensure the accuracy and traceability of data transmission. Subsequently, the data packet will be sent to the first router, which can determine the forwarding path based on its own routing table and routing algorithm, and forward the data packet to the second router, which can further transmit the data packet to the first access device.

[0057] Through the above technical solution, by first obtaining the remaining memory capacity of the consistent cache and then deciding the data sending operation based on the comparison with the preset threshold, the actual situation of the cache memory resources and the overall data processing requirements of the system can be fully considered.

[0058] In some embodiments, Figure 5 As shown, the method may further include the following steps.

[0059] In step 301, the data type of the first target data is obtained.

[0060] Among them, the data type may include a first type and a second type; specifically, the first type of data may refer to data in the cache in the on-chip network that is consistent with the original storage location (such as main memory, disk, etc.), and the second type of data may refer to data that has been modified in the cache in the on-chip network but has not yet been synchronized back to the original storage location (such as main memory, disk, etc.).

[0061] In this step, the first target data in the target cache may be judged first to determine the data type of the first target data in the target cache.

[0062] By way of example, the data type of the first target data in the target cache may be determined in the following manner.

[0063] Method 1: A special flag bit can be set for each data block in the target cache to identify whether the data is the first type of data. When the first target data is written into the target cache, the flag bit can be initialized to 0, indicating that the data has not been modified, that is, the first type of data. When the first target data in the target cache is modified, the corresponding flag bit is set to 1 at the same time, indicating that the data has become the second type of data. Therefore, when determining the data type of the first target data, the value of the corresponding flag bit can be checked. If the flag bit is 1, the data is the second type of data; if the flag bit is 0, it is the first type of data.

[0064] Method 2: A version number may be maintained for the first target data in the target cache and the corresponding data in the main memory. Each time the data is modified, its version number will be incremented, whether in the cache or in the main memory. When it is necessary to determine whether the first target data is the second type of data, the version number of the data in the cache is compared with the version number of the corresponding data in the main memory. If the version number in the cache is greater than the version number in the main memory, it means that the data in the cache has been modified, that is, the second type of data; otherwise, it is the first type of data.

[0065] Method 3: A timestamp can be recorded for the first target data in the target cache and the corresponding data in the main memory respectively. The timestamp records the time when the data was last modified. When determining whether the first target data is the second type of data, the timestamp of the data in the cache is compared with the timestamp of the corresponding data in the main memory. If the timestamp of the data in the cache is updated, it means that the data has been modified in the cache and is the second type of data; if the timestamps of the two are the same, it is the first type of data.

[0066] In step 302, when it is detected that the state of the first cache is a busy state, if it is determined that the data type of the first target data is a specified type, the first target data sent to the coherent cache is marked as first state data.

[0067] The first state data is data inconsistent with the data in the first cache, and the specified type is the second type.

[0068] In this step, when it is detected that the state of the first cache is busy, the state of the first cache may be in the state of executing other data read and write operations, cache maintenance tasks (such as data replacement, update, etc.), and the first cache cannot immediately receive new data write requests.

[0069] And, if Figure 6 As shown, when the data type of the first target data is a data type inconsistent with the data in the first cache, that is, the second type, the first target data originally to be sent to the consistent cache can be marked as first state data.

[0070] The first state data is data inconsistent with the data in the first cache.

[0071] The purpose of doing this is to ensure that in the subsequent processing of the data, whether it is stored in the consistency cache or in the subsequent data transmission and synchronization operations that may be involved, the on-chip network system can determine that the first target data is different from the data state in the first cache, so as to adopt corresponding processing strategies, avoid data conflicts, and ensure data consistency. For example, when the busy state of the first cache is released and the data in the consistency cache needs to be written to the first cache, the system can clearly know that the data needs special processing based on this mark, and it may be necessary to first update or replace the data at the corresponding position in the first cache to ensure the consistency of the final data.

[0072] In step 303, when it is detected that the state of the first cache is a non-busy state, if it is determined that the data type of the first target data is a specified type, the first target data is marked as second state data and stored in the consistency cache of the third access device through the first router and the second router.

[0073] The second state data is data consistent with the data in the first cache.

[0074] In this step, when it is detected that the state of the first cache is not busy and it is determined that the data type of the first target data is a data type consistent with the data in the first cache, that is, the second type, the on-chip network system can mark the first target data as second state data.

[0075] The second state data may be data consistent with the data in the first cache.

[0076] Although the first target data is actually the second type data that has been modified but not synchronized and is inconsistent with the data at the original storage location, it is marked here as second-state data that is consistent with the data in the first cache. This is for associating it with the first cache in the subsequent data processing flow, so as to facilitate accurate writing of it to the first cache at the appropriate time while ensuring maintenance of data consistency.

[0077] Optionally, after marking the first target data as the second state data, the data can be stored in the consistency cache of the third access device through the first router and the second router. The first router and the second router are responsible for data routing and forwarding in the on-chip network, and can ensure that the first target data can be transmitted from the current location to the third access device where the consistency cache is located according to preset routing rules and algorithms.

[0078] The consistency cache is used as a cache in the on-chip network for executing consistency transactions. It can temporarily store the data and further process the data according to the overall data consistency strategy during the subsequent system operation.

[0079] By adopting the above technical solution, by marking the first target data as second state data consistent with the data in the first cache and storing it in the consistent cache, the state of the data can be better tracked and managed. In subsequent processing, whether it is updating the data of the first cache or performing other related cache operations, the consistency of the data between different caches can be ensured based on this mark, avoiding data errors or inconsistencies caused by data state confusion.

[0080] In some embodiments, Figure 7 As shown, the method may further include the following steps.

[0081] In step 401, the second state data in the target cache is obtained.

[0082] The second state data is data consistent with the data in the first cache.

[0083] For example, the target cache is a storage point for data, and the second state data stored in it may be generated or stored according to specific rules in previous operations. For example, during the data processing process of a Core node, the data that needs to be consistent with the first cache after processing is stored in the target cache. Obtaining this part of data provides a basis for subsequent operations such as searching for matching data in the consistency cache and performing consistency detection.

[0084] In step 402, the coherent cache is searched for data that is consistent with the second state data in the target cache.

[0085] The consistency cache is a cache in a third access device in the network on chip for executing consistency transactions, and the third access device is connected to a second router in the network on chip.

[0086] In this step, by searching the coherent cache for data that is consistent with the second state data in the target cache, the on-chip network system can determine whether a copy of the data in the same state already exists. If so, it means that the coherent cache already has data that is consistent with the specific data state in the target cache, so there is no need to transmit the same data from the target cache to the coherent cache again, thereby avoiding repeated data transmission and saving network resources and processing time.

[0087] In step 403, when there is data in the coherent cache point that is consistent with the second state data in the target cache, a consistency check is performed on the cache line data in the coherent cache.

[0088] Alternatively, if Figure 8 As shown, first, when it is determined that the cache line data is in an exclusive state, the cache line data is modified to a shared state, and a first response message is sent to the target cache through the first router and the second router, and the first response message is used to indicate that the target cache does not need to send the second state data in the target cache to the consistency cache; then, when it is determined that the cache line data is in a shared state, the first response message is sent to the target cache through the first router and the second router.

[0089] The exclusive state indicates that a valid copy of the cache line data exists only in the current cache (ie, the coherent cache), while the shared state indicates that multiple caches may simultaneously have copies of the cache line data.

[0090] For example, when it is determined that the cache line data is in an exclusive state, it can be modified to a shared state. This is because if there is the same second-state data as in the target cache, it means that there may be multiple caches that need to share the data, so it is converted to a shared state. Then, the first response information is sent to the target cache through the first router and the second router, informing the target cache that it does not need to send the second-state data stored in it to the consistency cache. Doing so can avoid repeated data transmission, improve system efficiency, and also help maintain data consistency because the consistency cache already has data in the same state.

[0091] If it is determined that the cache line data is already in a shared state, the first response information is also sent to the target cache through the first router and the second router. This means that even if the cache line data is already in a shared state, the target cache does not need to send the same second state data, which further strengthens the maintenance of data consistency and avoids unnecessary data transmission.

[0092] In some embodiments, the coherent cache may also send the second response information to the target cache when there is no data in the coherent cache point that is consistent with the second state data in the target cache.

[0093] The second response information is used to instruct the target cache to send the second state data in the target cache to the coherent cache.

[0094] In this step, the consistency cache sends the second response information to the target cache in order to maintain the consistency of the data in the system. Since the consistency cache lacks data that is consistent with the specific state (second state) in the target cache, in order to ensure the integrity and consistency of the data between the caches, it is necessary to obtain the data from the target cache and fill it into the consistency cache.

[0095] By sending such response information, the target cache is clearly informed of the data transmission task it needs to perform, so that data can be exchanged in an orderly manner between different caches to avoid data inconsistency or data loss.

[0096] Fig. 9 is a block diagram of a data processing device provided in an embodiment of the present application, the device 500 includes: The first acquisition module 501 is used to obtain the state information of the first cache in response to the received request instruction, and determine the state of the first cache according to the state information: the request instruction is used to instruct the target cache to write the first target data into the first cache, the first cache is a cache in a first access device for storing data in the network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; The first writing module 502 is used to write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router when detecting that the state of the first cache is not busy.

[0097] Optionally, the first writing module 502 is used to send the request instruction to the first cache through the first router and the second router; upon receiving the response information sent by the first cache according to the received request instruction, the first target data is sent to the first access device through the first router and the second router, and the first target data is written into the first cache.

[0098] Optionally, the device further comprises: a forwarding module, configured to, when detecting that the state of the first cache is a busy state, send the first target data stored in the target cache of the second access device to a consistency cache through the second router, the consistency cache being a cache in a third access device in the network on chip for executing consistency transactions, the third access device being connected to a second router in the network on chip; The second writing module is used to obtain new status information of the first cache and re-execute the step of determining the status of the first cache according to the status information, until it is detected that the status of the first cache is not busy, and then continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device.

[0099] Optionally, the second writing module is used to send the first target data stored in the consistency cache of the third access device to the first access device through the first router and the second router until it is detected that the state of the first cache is not busy; and write the first target data into the first cache of the first access device.

[0100] Optionally, the second writing module is used to obtain the remaining memory capacity in the consistent cache; when it is determined that the remaining memory capacity is less than or equal to a preset threshold, the first target data stored in the consistent cache is sent to the first access device through the first router and the second router.

[0101] Optionally, the device further comprises: A second acquisition module, used for acquiring the data type of the first target data; A first marking module is used for marking the first target data sent to the coherent cache as first state data if it is determined that the data type of the first target data is a specified type when the state of the first cache is detected to be a busy state; the first state data is data inconsistent with the data in the first cache; The second marking module is used to, when it is detected that the state of the first cache is not busy, if it is determined that the data type of the first target data is a specified type, mark the first target data as second state data, and store it in the consistency cache of the third access device through the first router and the second router. The second state data is data consistent with the data in the first cache.

[0102] Optionally, the device further comprises: A third acquisition module is used to acquire second state data in the target cache, where the second state data is data consistent with the data in the first cache; A search module, configured to search a consistency cache for data consistent with the second state data in the target cache; the consistency cache is a cache in a third access device in the network on chip for executing consistency transactions, and the third access device is connected to a second router in the network on chip; The detection module is used to perform consistency detection on cache line data in the consistency cache when data consistent with the second state data in the target cache exists in the consistency cache point.

[0103] Optionally, the detection module is used to modify the cache line data to a shared state when it is determined that the cache line data is in an exclusive state, and send a first response message to the target cache through the first router and the second router, wherein the first response message is used to indicate that the target cache does not need to send the second state data in the target cache to the consistency cache; and send the first response message to the target cache through the first router and the second router when it is determined that the cache line data is in a shared state.

[0104] Optionally, the device further comprises: A sending module is used for, when there is no data consistent with the second state data in the target cache in the consistency cache point, the consistency cache sends a second response message to the target cache, and the second response message is used to instruct the target cache to send the second state data in the target cache to the consistency cache.

[0105] In summary, in the embodiment of the present application, whether to write data can be determined based on the state information of the first cache. The process is simple and intuitive, and unnecessary operations and data transmission can be avoided, thereby effectively reducing unnecessary traffic on the Internet and the waiting time for data transmission, so that data can be more efficiently transferred and updated in the system, thereby improving the overall performance of the system. In addition, while ensuring consistency specifications and performance requirements, a more streamlined operation process can be adopted, reducing the manpower, time and other costs in the development and debugging process, and improving the efficiency and quality of system development.

[0106] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0108] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0109] An embodiment of the present application provides a data processing device, including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the methods described in one or more of the above embodiments.

[0110] Fig.10 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0111] Reference Fig.10 , the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output interface 612 , a sensor component 614 , and a communication component 616 .

[0112] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0113] The memory 604 is used to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, multimedia, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0114] The power supply component 606 provides power to the various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0115] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0116] The audio component 610 is used to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the electronic device 600 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0117] The input / output interface 612 provides an interface between the processing component 602 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0118] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of the components, such as the display and keypad of the electronic device 600, and the sensor assembly 614 can also detect the position change of the electronic device 600 or a component of the electronic device 600, the presence or absence of contact between the user and the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0119] The communication component 616 is used to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0120] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0121] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of an electronic device 600 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0122] Fig.11 FIG. 7 is a block diagram of another electronic device 700 according to an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Fig.11 , the electronic device 700 includes a processing component 722, which further includes one or more processors, and a memory resource represented by a memory 732, for storing instructions that can be executed by the processing component 722, such as an application. The application stored in the memory 732 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0123] The electronic device 700 may further include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output interface 758. The electronic device 700 may operate based on an operating system stored in the memory 732, such as Windows Server 2000. TM , MacOSX TM , Unix TM , Linux TM , FreeBSD TM or similar.

[0124] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0125] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0126] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A data processing method, characterized in that: The method comprises: In response to the received request instruction, the state information of the first cache is obtained, and the state of the first cache is determined according to the state information: the request instruction is used to instruct the target cache to write the first target data into the first cache, the first cache is a cache in a first access device for storing data in the network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; When it is detected that the state of the first cache is a non-busy state, the first target data stored in the target cache of the second access device is written into the first cache of the first access device through the first router and the second router.

2. The method according to claim 1, characterized in that Writing the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router includes: Sending the request instruction to the first cache through the first router and the second router; Upon receiving response information sent by the first cache according to the received request instruction, the first target data is sent to the first access device through the first router and the second router, and the first target data is written into the first cache.

3. The method according to claim 1, characterized in that: The method further comprises: When it is detected that the state of the first cache is a busy state, the first target data stored in the target cache of the second access device is sent to a coherent cache through the second router, where the coherent cache is a cache in a third access device in the network on chip for executing coherent transactions, and the third access device is connected to a second router in the network on chip; Obtain new status information of the first cache, and re-execute the step of determining the status of the first cache based on the status information, until it is detected that the status of the first cache is not busy, and then continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device.

4. The method according to claim 3, characterized in that Writing the first target data stored in the target cache of the second access device into the first cache of the first access device includes: until it is detected that the state of the first cache is a non-busy state, sending the first target data stored in the coherent cache of the third access device to the first access device through the first router and the second router; The first target data is written into the first cache of the first access device.

5. The method according to claim 4, characterized in that The sending the first target data stored in the coherent cache of the third access device to the first access device through the first router and the second router includes: Obtaining the remaining memory capacity in the coherent cache; When it is determined that the remaining memory capacity is less than or equal to a preset threshold, the first target data stored in the consistency cache is sent to the first access device through the first router and the second router.

6. The method according to claim 3, characterized in that The method further comprises: Acquire the data type of the first target data; In the case where it is detected that the state of the first cache is a busy state, if it is determined that the data type of the first target data is a specified type, the first target data sent to the coherent cache is marked as first state data; the first state data is data inconsistent with the data in the first cache; When it is detected that the state of the first cache is not busy, if it is determined that the data type of the first target data is a specified type, the first target data is marked as second state data and stored in the consistency cache of the third access device through the first router and the second router. The second state data is data consistent with the data in the first cache.

7. The method according to claim 1, characterized in that The method further comprises: Acquire second state data in the target cache, where the second state data is data consistent with the data in the first cache; Searching for data consistent with the second state data in the target cache in a consistent cache; the consistent cache is a cache in a third access device in the on-chip network for executing consistent transactions, and the third access device is connected to a second router in the on-chip network; In the case that data consistent with the second state data in the target cache exists in the consistency cache point, consistency check is performed on cache line data in the consistency cache.

8. The method according to claim 7, characterized in that The performing consistency detection on the cache line data in the consistency cache comprises: When it is determined that the cache line data is in an exclusive state, modifying the cache line data to a shared state, and sending first response information to the target cache through the first router and the second router, wherein the first response information is used to indicate that the target cache does not need to send the second state data in the target cache to the coherent cache; When it is determined that the cache line data is in a shared state, the first response information is sent to the target cache through the first router and the second router.

9. The method according to claim 7, characterized in that: The method further comprises: When there is no data in the consistency cache point that is consistent with the second state data in the target cache, the consistency cache sends a second response message to the target cache, and the second response message is used to instruct the target cache to send the second state data in the target cache to the consistency cache.

10. A data processing device, characterized in that: The device comprises: A first acquisition module is used to obtain state information of a first cache in response to a received request instruction, and determine the state of the first cache according to the state information: the request instruction is used to instruct a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; The first writing module is used to write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router when detecting that the state of the first cache is not busy.

11. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method as claimed in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 9.

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