Method of manufacturing semiconductor memory device

Abstract

A method of manufacturing a semiconductor memory device includes forming a metal seed pattern having a plurality of openings on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; growing a single crystal semiconductor pattern at an interface between the substrate and the metal silicide pattern along a vertical direction, the vertical direction being perpendicular to the substrate; and growing a sacrificial semiconductor pattern in the vertical direction at an interface between the metal silicide pattern and the single crystal semiconductor pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0136223 filed in the Korean Intellectual Property Office on October 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a three-dimensional semiconductor memory device. Background Art

[0004] The demand for miniaturization, multi-function and high performance of electronic products requires high-capacity semiconductor memory devices. Because the integration of conventional two-dimensional semiconductor memory devices is mainly determined by the area occupied by the unit memory cell, improving the integration of two-dimensional semiconductor memory devices is limited by the physical limitations of ultra-high integration semiconductor manufacturing processes. Therefore, as a solution to improve the integration, three-dimensional semiconductor memory devices with multiple memory cells stacked in the vertical direction have attracted attention. Summary of the invention

[0005] The inventive concept provides a method of manufacturing a semiconductor memory device having improved reliability and integration.

[0006] According to some embodiments of the present inventive concept, a method for manufacturing a semiconductor memory device is provided. The method for manufacturing a semiconductor memory device includes: forming a metal seed pattern having a plurality of openings on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; growing a single crystal semiconductor pattern in a vertical direction at an interface between the substrate and the metal silicide pattern, wherein the vertical direction is perpendicular to the substrate; and growing a sacrificial semiconductor pattern in a vertical direction at an interface between the metal silicide pattern and the single crystal semiconductor pattern.

[0007] According to some embodiments of the present inventive concept, a method for manufacturing a semiconductor memory device is provided. The method for manufacturing a semiconductor memory device includes: forming a metal seed pattern on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; forming a eutectic layer of a metal-semiconductor material by heating the metal silicide pattern; and forming a patterned mold stack having a plurality of vertical holes exposing the substrate by alternately growing corresponding single crystal semiconductor patterns among a plurality of single crystal semiconductor patterns and corresponding sacrificial semiconductor patterns among a plurality of sacrificial semiconductor patterns one by one from a bottom surface of the eutectic layer.

[0008] According to some embodiments of the present invention, a method for manufacturing a semiconductor memory device is provided. The method for manufacturing a semiconductor memory device includes: forming a metal seed pattern having a plurality of openings on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; forming a eutectic layer of a metal-semiconductor material by heating the metal silicide pattern; forming a patterned mold stack having a plurality of vertical holes by alternately growing a corresponding single crystal semiconductor pattern in a plurality of single crystal semiconductor patterns and a corresponding sacrificial semiconductor pattern in a plurality of sacrificial semiconductor patterns from the bottom surface of the eutectic layer; at least partially filling the plurality of vertical holes with a sacrificial insulating layer; forming a plurality of recesses by anisotropically etching the patterned mold stack and the sacrificial insulating layer, the plurality of recesses extending into the patterned mold stack and the sacrificial insulating layer in a vertical direction; and forming a buried insulating structure by at least partially filling the plurality of recesses. The plurality of vertical holes have a constant horizontal width regardless of the distance from the substrate, and the plurality of recesses have a tapered shape in which the width narrows toward the top surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is an equivalent circuit diagram showing a cell array of a semiconductor memory device according to some embodiments;

[0011] Figure 2A is a plan view for explaining a semiconductor memory device according to some embodiments;

[0012] Figure 2B It is a semiconductor memory device along Figure 2A A cross-sectional view taken along the line X1-X1';

[0013] Figure 2C yes Figure 2B A magnified view of the area “EX1”;

[0014] Figure 2D It is a semiconductor memory device along Figure 2A A cross-sectional view taken along line X2-X2';

[0015] Figure 3 is a flow chart illustrating a method of manufacturing a semiconductor memory device according to some embodiments;

[0016] Figure 4A , Fig.9A , Fig. 10A and Fig.14A is a plan view for describing a method of manufacturing a semiconductor memory device according to some embodiments; Figure 4B , Figures 5 to 8 , Fig. 9B , Fig. 10B , Figures 11 to 13 , Fig. 14B and Figures 15 to 19 is a cross-sectional view for describing a method of manufacturing a semiconductor memory device according to some embodiments; and

[0017] Fig. 20A and Fig. 20B is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the technical idea of ​​the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof are omitted.

[0019] In this specification, the vertical direction may be defined as the Z direction, and the horizontal direction may be defined as a direction each perpendicular to the Z direction. The first horizontal direction and the second horizontal direction may be defined as directions intersecting each other. The first horizontal direction may be referred to as the X direction, and the second horizontal direction may be referred to as the Y direction. The vertical level may refer to the height level according to the vertical direction (Z direction). The horizontal width of a component may refer to the length of the component in the horizontal direction, and the vertical thickness of a component may refer to the length of the component in the vertical direction (Z direction).

[0020] Figure 1 is a circuit diagram illustrating a semiconductor memory device 10 according to some embodiments.

[0021] Reference Figure 1 , the semiconductor memory device 10 may include a memory cell array SCA. The memory cell array SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC.

[0022] According to some embodiments, each of the plurality of memory cells MC may include a cell transistor TR and a cell capacitor CAP. The cell transistor TR and the cell capacitor CAP may be connected to each other. For example, any one of a source electrode and a drain electrode of the cell transistor TR may be connected to a lower electrode of the cell capacitor CAP.

[0023] According to some embodiments, a plurality of memory cells MC may be repeatedly arranged in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction). Each of the plurality of word lines WL may extend along the second horizontal direction (Y direction) and may be connected to the memory cells MC arranged in the second horizontal direction (Y direction). Each of the plurality of bit lines BL may extend along the vertical direction (Z direction) and may be connected to the memory cells MC arranged in the vertical direction (Z direction). Each of the plurality of bit line bands BLS may extend along the first horizontal direction (X direction) and may be connected to the bit lines BL arranged in the first horizontal direction (X direction).

[0024] At least some of the plurality of memory cells MC may share an upper electrode PE of the cell capacitor CAP. For example, among the plurality of memory cells MC, a first memory cell pair arranged at the same vertical level and connected to different bit lines BL may share one upper electrode PE. According to some embodiments, the upper electrode PE may extend in a vertical direction (Z direction) and may be connected to a plurality of memory cell pairs arranged in the vertical direction (Z direction).

[0025] Figure 2A 1 is a plan view for explaining a semiconductor memory device 10 according to some embodiments. Specifically, Figure 2A Shows Figure 2B A plan view at a first vertical level LV1 is shown. Figure 2B The semiconductor memory device 10 is along Figure 2A A cross-sectional view taken along line X1-X1'. Figure 2C yes Figure 2B Magnified view of area “EX1”. Figure 2D The semiconductor memory device 10 is along Figure 2A A cross-sectional view taken along line X2-X2'.

[0026] Reference FIG. 2A to FIG. 2D The semiconductor memory device 10 may include a substrate 101 and a plurality of memory cells repeatedly arranged along a first horizontal direction (X direction), a second horizontal direction (Y direction) and a vertical direction (Z direction) on the substrate 101. The plurality of memory cells correspond to Figure 1 According to some embodiments, the semiconductor memory device 10 may include a plurality of cell transistors CTR and a plurality of cell capacitors CAP disposed on a substrate 101 .

[0027] According to some embodiments, the substrate 101 may include Si, Ge, or SiGe. In some embodiments, for example, the substrate 101 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0028] The substrate 101 may have a top surface extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction). For example, the top surface of the substrate 101 may have a normal in a vertical direction (Z direction).

[0029] The substrate 101 may include a cell array region and a contact region (not shown). Figure 2A A partial area of ​​the cell array region is shown. In the contact region (not shown), a wiring structure (not shown) connected to a plurality of cell transistors CTR and a plurality of cell capacitors CAP may be arranged, and ends of a plurality of word lines WL may be arranged.

[0030] Although not shown, a peripheral circuit (not shown) and a wiring layer (not shown) connected to the peripheral circuit may be formed on the substrate 101. For example, the peripheral circuit may include a metal oxide semiconductor field effect transistor (MOSFET) including a sub-word line driver, a sense amplifier, etc., but is not limited thereto. A lower insulating layer (not shown) arranged to cover or overlap the peripheral circuit and the wiring layer may be formed on the substrate 101. In other embodiments, the peripheral circuit (not shown) and the wiring layer (not shown) may be arranged on a plurality of cell transistors CTR and a plurality of cell capacitors CAP.

[0031] According to some embodiments, the plurality of cell transistors CTR may include a plurality of transistor bodies 220, a plurality of word lines WL, and a gate dielectric layer 182. According to some embodiments, the plurality of cell capacitors CAP may include a first electrode EL1, a second electrode EL2, and a capacitor dielectric layer DL between the first electrode EL1 and the second electrode EL2. For example, the second electrode EL2 may correspond to Figure 1 The upper electrode PE is shown.

[0032] According to some embodiments, the plurality of transistor bodies 220 may each have a bar shape extending in a first horizontal direction (X direction), and may be repeatedly arranged on the substrate 101 along the first horizontal direction (X direction), the second horizontal direction (Y direction), and the third horizontal direction (Z direction) to be spaced apart from each other. For example, a cell capacitor CAP may be arranged between the transistor bodies 220 spaced apart from each other along the first horizontal direction (X direction), or a second buried insulating layer 196 and a bit line BL may be arranged therebetween. For example, the plurality of transistor bodies 220 may be spaced apart from each other in the second horizontal direction (Y direction) with a first buried insulating layer 162 therebetween. For example, the plurality of transistor bodies 220 may be spaced apart from each other in the vertical direction (Z direction) with an isolation insulating pattern 154 therebetween.

[0033] In some embodiments, the second buried insulating layer 196 and the first buried insulating layer 162 may include any one of silicon oxide, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon, but are not limited to these examples.

[0034] According to some embodiments, one end of each of the plurality of transistor bodies 220 in the first horizontal direction (X direction) may be contact-connected to the bit line BL, and the other end in the first horizontal direction (X direction) may be contact-connected to the cell capacitor CAP. According to some embodiments, at least some portions of both surfaces of each of the plurality of transistor bodies 220 in the vertical direction (Z direction) may be covered by or overlapped with the word line WL, respectively.

[0035] In some embodiments, the plurality of transistor bodies 220 may include undoped semiconductor material and / or doped semiconductor material. For example, the plurality of transistor bodies 220 may include polysilicon.

[0036] In some embodiments, the plurality of transistor bodies 220 may include amorphous metal oxide, polycrystalline metal oxide, a combination of amorphous metal oxide and polycrystalline metal oxide, etc. For example, the plurality of transistor bodies 220 may include at least one of In-Ga based oxide (IGO), In-Zn based oxide (IZO), and In-Ga-Zn based oxide (IGZO).

[0037] According to some embodiments, each of the plurality of transistor bodies 220 may include a first source / drain region 222, a single crystalline channel layer 224, and a second source / drain region 226. For example, the single crystalline channel layer 224 may be arranged between the first source / drain region 222 and the second source / drain region 226 in a first horizontal direction (X direction).

[0038] The first source / drain region 222 may be connected to and in contact with the bit line BL, and the second source / drain region 226 may be connected to the cell capacitor CAP and in contact with the first electrode EL1. Both ends of the single-crystal channel layer 224 in the first horizontal direction (X direction) may contact the first source / drain region 222 and the second source / drain region 226, respectively. In some embodiments, the first source / drain region 222 and the second source / drain region 226 may each include a semiconductor material doped with a high concentration of n-type dopants. In some embodiments, the single-crystal channel layer 224 may include a single-crystal semiconductor material such as Si, SiGe, SiGeC, or SiC.

[0039] In some embodiments, both sides of the single crystal channel layer 224 in the vertical direction (Z direction) may be covered by or overlapped with the corresponding word lines WL. In this case, the cell transistor CTR may have a dual gate shape, in which a word line pair WLP composed of a pair of word lines WL covers one single crystal channel layer 224 or overlaps one single crystal channel layer 224. In other embodiments, the cell transistor CTR may have a full surrounding gate shape, in which one word line WL covers both sides of the single crystal channel layer 224 in the vertical direction (Z direction) and both sides of the second horizontal direction (Y direction), or overlaps with both sides of the single crystal channel layer 224 in the vertical direction (Z direction) and both sides of the second horizontal direction (Y direction), or on both sides of the single crystal channel layer 224 in the vertical direction (Z direction) and both sides of the second horizontal direction (Y direction).

[0040] Reference FIG. 2A to FIG. 2D , each of the plurality of word lines WL may include a first portion PP1 overlapping the plurality of single crystal channel layers 224 and a second portion PP2 extending along the second horizontal direction (Y direction) between two adjacent first portions PP1. In some embodiments, a first horizontal width W1 of the first portion PP1 in the first horizontal direction (X direction) may be greater than a second horizontal width W2 of the second portion PP2 in the first horizontal direction (X direction).

[0041] In some embodiments, the first portions PP1 of the word line pairs WLP may be spaced apart from each other in the vertical direction (Z direction) with the single crystal channel layer 224 and the gate dielectric layer 182 therebetween. In some embodiments, the second portions PP2 of the word line pairs WLP may be spaced apart from each other in the vertical direction (Z direction) with the first buried insulating layer 162 and the gate dielectric layer 182 therebetween. In some embodiments, a plurality of word line pairs WLP may be spaced apart from each other with a plurality of isolation insulating patterns 154 therebetween. In some embodiments, both surfaces of the second portion PP2 of each of the plurality of word lines WL in the first horizontal direction (X direction) may be covered by the first buried insulating layer 162 or overlapped with the first buried insulating layer 162. In some embodiments, the second portions PP2 of the plurality of word lines WL may be covered by the isolation insulating pattern 154 and the first buried insulating layer 162 or overlapped with the isolation insulating pattern 154 and the first buried insulating layer 162 in the vertical direction (Z direction).

[0042] In some embodiments, the horizontal widths of the plurality of word lines WL in the horizontal direction (X direction and / or Y direction) may be constant regardless of the vertical level. For example, the width of the first word line WL arranged closest to the top surface of the substrate 101 according to the first horizontal direction (X direction) may be the same as the width of the second word line WL arranged at a higher vertical level than the first word line WL according to the first horizontal direction (X direction).

[0043] In some embodiments, both side surfaces of the plurality of word lines WL arranged in the vertical direction (Z direction) in the first horizontal direction may be substantially perpendicular to the top surface of the substrate 101. For example, the planar areas of the plurality of word lines WL arranged in the vertical direction (Z direction) are the same regardless of the vertical level and may substantially completely overlap vertically.

[0044] The word line WL of the semiconductor memory device according to the comparative example has a horizontal width that is different according to the vertical level. For example, the word line WL of the comparative example may have a wider horizontal width as it approaches the top surface of the substrate 101. In this case, there may be a problem that the reliability of the semiconductor memory device is deteriorated due to the deviation of the cell transistor CTR attributable to the vertical level. In some embodiments, the width of the multiple word lines WL of the semiconductor memory device 10 according to the horizontal direction (X direction and / or Y direction) may be constant regardless of the vertical level (i.e., the distance from the substrate), thereby improving the operational reliability of the semiconductor memory device 10.

[0045] According to some embodiments, the plurality of bit lines BL may extend in a vertical direction (Z direction) on the substrate 101 and may be spaced apart from each other in a horizontal direction. For example, each of the plurality of bit lines BL may be connected to a first group of the plurality of cell transistors CTR arranged in a vertical direction (Z direction).

[0046] According to some embodiments, a plurality of word lines WL may extend along a second horizontal direction (Y direction) on the substrate 101, and may be spaced apart from each other in a vertical direction (Z direction) and a first horizontal direction (X direction). For example, a plurality of word lines WL may be spaced apart from each other in a vertical direction (Z direction) with an isolation insulating pattern 154 therebetween, and each of the plurality of word lines WL may be connected to a second group of a plurality of cell transistors CTR arranged in a second horizontal direction (Y direction). In some embodiments, the second group of cell transistors CTR may be spaced apart from each other in a second horizontal direction (Y direction) with a first buried insulating layer 162 therebetween.

[0047] In some embodiments, the plurality of bit lines BL and the plurality of word lines WL may each independently include at least one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0048] According to some embodiments, gate dielectric layer 182 may be disposed between the plurality of word lines WL and the plurality of transistor bodies 220. Gate dielectric layer 182 may have a uniform thickness and may have a conformal structure.

[0049] In some embodiments, the gate dielectric layer 182 may include at least one selected from a ferroelectric material and a high-k dielectric material having a higher dielectric constant than silicon oxide. For example, the gate dielectric layer 182 includes at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalum (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). The terms “HfO”, “HfSi”, and “LaO” used in this specification refer to materials formed of elements included in each term, rather than chemical formulas representing a stoichiometric relationship.

[0050] According to some embodiments, the plurality of word lines WL may be spaced apart from the plurality of bit lines BL in the first horizontal direction (X direction) with a plurality of cap spacers 192 therebetween. For example, each of the plurality of cap spacers 192 contacts one end of each of the plurality of word lines WL in the first horizontal direction (X direction) and may at least partially overlap vertically with the first source / drain region 222. According to some embodiments, the first source / drain region 222 may be spaced apart from the plurality of cap spacers 192 with a gate dielectric layer 182 therebetween. In some embodiments, both surfaces of each of the plurality of cap spacers 192 in the vertical direction (Z direction) may be covered by or overlap with the gate dielectric layer 182. In some embodiments, the plurality of cap spacers 192 may include any one of silicon oxide, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon.

[0051] According to some embodiments, the plurality of word lines WL may be spaced apart from the first electrode EL1 of each of the plurality of unit capacitors CAP in the first horizontal direction (X direction) with a plurality of buried spacers 174 therebetween. According to some embodiments, the gate dielectric layer 182 may be disposed between the plurality of buried spacers 174 and the plurality of word lines WL. In some embodiments, the plurality of buried spacers 174 may at least partially overlap vertically with the second source / drain region 226. According to some embodiments, both surfaces of the plurality of buried spacers 174 in the vertical direction (Z direction) may be covered by or overlapped with the spacer liner 172, and the second source / drain region 226 may be spaced apart from the plurality of buried spacers 174 in the vertical direction (Z direction) with a spacer liner 172 therebetween. In some embodiments, the spacer liner 172 may be made of silicon nitride, and the plurality of buried spacers 174 may include any one of silicon oxide, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon.

[0052] In some embodiments, the plurality of capping spacers 192 and the plurality of buried spacers 174 may be arranged at the same vertical level with respect to the substrate as the plurality of word lines WL.

[0053] In some embodiments, a plurality of isolation insulating patterns 154 may be disposed between a plurality of cell transistors CTR spaced apart from each other in the vertical direction (Z direction). For example, each of the plurality of isolation insulating patterns 154 may be disposed between two word lines WL spaced apart from each other in the vertical direction (Z direction).

[0054] In some embodiments, the gate dielectric layer 182 may be disposed between the plurality of isolation insulating patterns 154 and the plurality of word lines WL. In some embodiments, the gate dielectric layer 182 may be disposed between the plurality of isolation insulating patterns 154 and the plurality of capping spacers 192. In some embodiments, the spacer liner 172 may be disposed between the plurality of isolation insulating patterns 154 and the plurality of buried spacers 174.

[0055] According to some embodiments, the first electrode EL1 of each of the plurality of unit capacitors CAP may be connected to the second source / drain region 226. The first electrode EL1 may have a cup shape having a side surface parallel to the first horizontal direction (X direction) and a bottom surface perpendicular to the first horizontal direction (X direction). Figure 2B and Figure 2C As shown, the first electrode EL1 may have a U-shaped horizontal cross-section rotated 90 degrees with respect to the top surface of the substrate, so that a side surface of the first electrode EL1 is parallel to the top surface of the substrate.

[0056] According to some embodiments, the capacitor dielectric layer DL may cover the surface of the first electrode EL1 or overlap the surface of the first electrode EL1. The capacitor dielectric layer DL may have a uniform thickness. Therefore, the capacitor dielectric layer DL may have a conformal shape. The second electrode EL2 may be spaced apart from the first electrode EL1 with the capacitor dielectric layer DL therebetween.

[0057] In some embodiments, among the plurality of memory cells, sub-unit arrays repeatedly arranged in the second horizontal direction (Y direction) and the vertical direction (Z direction) may share one second electrode EL2. In some embodiments, the first sub-unit array and the second sub-unit array may be symmetrically arranged with the second electrode EL2 therebetween. In this case, the first sub-unit array and the second sub-unit array may share the second electrode EL2.

[0058] In some embodiments, the first sub-cell array and the second sub-cell array sharing one second electrode EL2 may constitute one memory cell group. In some embodiments, the first memory cell group may be spaced apart from the second memory cell group with a second buried insulating layer 196 therebetween. For example, a plurality of memory cell groups may be arranged to be spaced apart from each other in a first horizontal direction (X direction).

[0059] Reference Figure 2D In some embodiments, the second buried insulating layer 196 may extend in a vertical direction (Z direction) on the substrate 101. In some embodiments, the horizontal width of the second buried insulating layer 196 in the first horizontal direction (X direction) may increase as it moves away from the top surface of the substrate 101 in the vertical direction (Z direction). For example, the second buried insulating layer 196 may have a tapered shape in which the horizontal width becomes narrower as it approaches the substrate 101 in the vertical direction (Z direction). In some embodiments, the sidewall of the second buried insulating layer 196 may have an inclination relative to the top surface of the substrate 101.

[0060] In some embodiments, the second buried insulating layer 196 may contact the first buried insulating layer 162 in the first horizontal direction (X direction). For example, one side surface of the first buried insulating layer 162 may have a downward slope and may be covered by or overlap the second buried insulating layer 196. In some embodiments, the other side surface of the first buried insulating layer 162 in the first horizontal direction (X direction) may be spaced apart from the second electrode EL2 and have a capacitor dielectric layer DL therebetween. In some embodiments, the other side surface of the first buried insulating layer 162 may have a downward slope. In some embodiments, the second electrode EL2 of the unit capacitor CAP may extend in a vertical direction (Z direction) on the substrate 101, and the horizontal width of the second electrode EL2 in the first horizontal direction (X direction) may increase as the distance from the top surface of the substrate 101 increases.

[0061] In some embodiments, the first electrodes EL1 of the plurality of unit capacitors CAP may be spaced apart from each other in the vertical direction (Z direction) with an intermediate insulating pattern 292 therebetween. In some embodiments, one side surface of each of the plurality of isolation insulating patterns 154 in the first horizontal direction (X direction) may contact a corresponding one of the plurality of intermediate insulating patterns 292. In this case, the other side surface of each of the plurality of isolation insulating patterns 154 in the first horizontal direction (X direction) may contact the bit line BL. In some embodiments, the plurality of intermediate insulating patterns 292 may be spaced apart from the second electrode EL2 with a capacitor dielectric layer DL therebetween. In some embodiments, the plurality of intermediate insulating patterns 292 may include silicon oxide, but are not limited thereto.

[0062] According to some embodiments, the first electrode EL1 and the second electrode EL2 may include a doped semiconductor material, a conductive metal nitride such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride, a metal such as ruthenium, iridium, titanium, or tantalum, or a conductive metal oxide such as iridium oxide or niobium oxide.

[0063] Figure 3 is a flowchart illustrating a method ( S100 ) of manufacturing a semiconductor memory device according to some embodiments. Figure 4A , Fig.9A , Fig. 10A and Fig.14A is a plan view for describing a method of manufacturing a semiconductor memory device according to some embodiments, Figure 4B , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9B , Fig. 10B , Fig.11 , Fig.12 , Fig.13 , Fig. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 is a cross-sectional view for describing a method of manufacturing a semiconductor memory device according to some embodiments. Specifically, Figure 4A , Fig.9A , Fig. 10A and Fig.14A is shown with Figure 2A The corresponding area is the top surface plan, Figure 4B , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9B , Fig. 10B , Fig.11 , Fig.12 , Fig.13 , Fig. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 Shown along with Figure 2A The corresponding part of the cross section taken by the lines X1-X1' and X2-X2'. Figure 3 The flowchart describes a method of manufacturing a semiconductor memory device.

[0064] Reference Figure 3 , Figure 4A and Figure 4B , a metal seed pattern 105 may be formed on a top surface of the substrate 101 ( S110 ).

[0065] In some embodiments, the substrate 101 may include a single crystalline semiconductor material. For example, the substrate 101 may include a semiconductor material such as Si or Ge.

[0066] In some embodiments, the metal seed pattern 105 may be formed by depositing a metal seed layer (not shown) on the top surface of the substrate 101 through a method such as physical vapor deposition (PVD), and then removing a portion of the metal seed layer (not shown). For example, a method of forming a pattern mask (not shown) on the metal seed layer (not shown) to remove the remaining portion except for a portion covered by or overlapped with the mask (not shown) through a lift-off process may be used.

[0067] In some embodiments, the metal seed pattern 105 may have a plurality of first openings op1 and a plurality of second openings op2 exposing the top surface of the substrate 101 .

[0068] In some embodiments, the plurality of first openings op1 and the plurality of second openings op2 may have different widths according to the first horizontal direction (X direction). For example, the plurality of second openings op2 may each have an elliptical plane shape having a major axis in the first horizontal direction (X direction) and a minor axis in the second horizontal direction (Y direction), or a rectangular plane shape having a width in the first horizontal direction (X direction) greater than a width in the second horizontal direction (Y direction).

[0069] In some embodiments, the plurality of first openings op1 may have a smaller width than the plurality of second openings op2 in the first horizontal direction (X direction).For example, the plurality of first openings op1 may have a circular, elliptical, or square planar shape, but is not limited thereto.

[0070] In some embodiments, the plurality of first openings op1 and the plurality of second openings op2 may have the same horizontal width in the second horizontal direction (Y direction).

[0071] In some embodiments, the first opening width ow1 may have a value smaller than the second opening width ow2, the first opening width ow1 being the minimum width between the first opening op1 and the second opening op2 adjacent to each other along the first horizontal direction (X direction), and the second opening width ow2 being the minimum width between two first openings op1 adjacent to each other along the second horizontal direction (Y direction) and / or between two second openings op2 adjacent to each other along the second horizontal direction (Y direction).

[0072] In some embodiments, a plurality of first openings op1 may be arranged to be spaced apart from each other in a horizontal direction (X direction and / or Y direction). In some embodiments, a plurality of first openings op1 may be arranged continuously in a second horizontal direction (Y direction). In some embodiments, two second openings op2 may be arranged between two first openings op1 adjacent to each other in a first horizontal direction (X direction) among a plurality of first openings op1. For example, two second openings op2 and one first opening op1 arranged continuously in a first horizontal direction (X direction) may include a first sub-opening array. The metal seed crystal pattern 105 may have a pattern in which a first sub-opening array is repeatedly arranged in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0073] In some embodiments, the metal seed pattern 105 may include a portion extending in the first horizontal direction (X direction) between the plurality of first openings op1 and the plurality of second openings op2 and a portion extending in the second horizontal direction Y therebetween.

[0074] In some embodiments, the metal seed pattern 105 may include gold (Au), aluminum (Al), silver (Ag), zinc (Zn), titanium (Ti), palladium (Pd), nickel (Ni), cobalt (Co), iron (Fe), indium (In), tungsten (W), and / or combinations thereof.

[0075] In some embodiments, the metal seed pattern 105 may have a first vertical thickness in a vertical direction (Z direction). According to some embodiments, the first vertical thickness may be about 0.01 nm to about 10 nm.

[0076] Reference Figure 3 and Figure 5 , can be obtained from Figure 4A and Figure 4B The resulting metal seed pattern 105 forms a metal silicide pattern 107 (S120). In some embodiments, the metal silicide pattern 107 may be formed at a temperature ranging from about 500°C to about 1500°C.

[0077] For example, the metal seed pattern 105 and a portion of the substrate 101 contacting the metal seed pattern 105 may move and interact with each other through diffusion to form the metal silicide pattern 107 .

[0078] In some embodiments, a bottom surface of the metal silicide pattern 107 may be disposed at a lower vertical level than a top surface of the substrate 101. In some embodiments, the metal silicide pattern 107 may include at least one of silicon (Si) and germanium (Ge) and a metal.

[0079] Reference Figure 3 and Figure 6 ,exist Figure 5 As a result, a single crystalline semiconductor pattern 110 may be formed on a region of the top surface of the substrate 101 vertically overlapping the metal silicide pattern 107 ( S130 ).

[0080] In some embodiments, the single crystalline semiconductor pattern 110 may be formed by exposing the metal silicide pattern 107 to a first reaction gas at a first process temperature. In some embodiments, the metal silicide pattern 107 may be melted at the first process temperature to form a first eutectic layer.

[0081] In some embodiments, the first reaction gas may include a first precursor source. In some embodiments, the first precursor source may include a Si source for forming the single crystalline semiconductor pattern 110. For example, the Si source may include a silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8) and dichlorosilane (SiH 2 Cl 2 ) at least one.

[0082] According to some embodiments, the first eutectic layer may be a metal-semiconductor material eutectic layer. In some embodiments, the first eutectic layer may be a gold (Au)-silicon (Si) eutectic layer.

[0083] In some embodiments, the first eutectic layer can be used as a catalyst in a formation reaction of the single crystalline semiconductor pattern 110. The first precursor source can contact and react with the melted metal silicide pattern 107 (e.g., the first eutectic layer) to form first source atoms (e.g., Si atoms) in the first eutectic layer, and the first source atoms can penetrate into the first eutectic layer to form the single crystalline semiconductor pattern 110 at an interface between the first eutectic layer and the substrate 101.

[0084] In some embodiments, the single crystal semiconductor pattern 110 may be grown on the bottom surface of the first eutectic layer. For example, the single crystal semiconductor pattern 110 may be grown at the interface between the first eutectic layer and the substrate 101 in a direction away from the top surface of the substrate 101 (i.e., a vertical direction (Z direction)). For example, the single crystal semiconductor pattern 110 may be formed by growing a preliminary semiconductor material layer on the top surface of the substrate 101 and then further growing a semiconductor material at the interface between the preliminary semiconductor material layer and the first eutectic layer (i.e., on the bottom surface of the first eutectic layer). For example, the single crystal semiconductor pattern 110 may be formed of single crystal silicon.

[0085] In some embodiments, the ratio of the number of metal atoms to the total number of atoms in the first eutectic layer may be about 0.05 to about 0.5, about 0.1 to about 0.4, about 0.1 to about 0.3, or about 0.1 to about 0.25. In some embodiments, the ratio of silicon (Si) atoms to the total number of atoms in the first eutectic layer may be about 0.6 to about 0.99, about 0.7 to about 0.95, or about 0.8 to about 0.95. When the metal atom content in the first eutectic layer is too much, the growth rate of the single crystal semiconductor pattern 110 may be reduced, and thus pattern imbalance may occur according to the growth in the horizontal direction (X direction and / or Y direction). When the silicon atom content in the first eutectic layer is too much, the temperature for forming the first eutectic layer increases, and the growth rate of the single crystal semiconductor pattern 110 may be reduced.

[0086] In some embodiments, the first process temperature may be about 250° C. to about 1500° C. For example, when the first process temperature is too low, the metal silicide pattern 107 may not form a first eutectic layer and thus may not serve as a catalyst for forming the single crystalline semiconductor pattern 110. For example, when the first process temperature is too high, the reliability of the semiconductor memory device 10 may deteriorate due to diffusion of semiconductor atoms between adjacent substrates 101.

[0087] The first process temperature may vary according to the type and content of the metal atoms and the source atoms. For example, when the metal silicide pattern 107 includes gold (Au), the first process temperature may be about 250°C to about 450°C. For example, when the metal silicide pattern 107 includes aluminum (Al), the first process temperature may be about 450°C to about 650°C. For example, when the metal silicide pattern 107 includes silver (Ag), the first process temperature may be about 750°C to about 950°C. For example, when the metal silicide pattern 107 includes zinc (Zn), the first process temperature may be about 350°C to about 550°C. For example, when the metal silicide pattern 107 includes titanium (Ti), the first process temperature may be about 1250°C to about 1450°C. For example, when the metal silicide pattern 107 includes palladium (Pd), the first process temperature may be about 750°C to about 950°C.

[0088] In some embodiments, the substrate 101 may be configured such that the same crystal plane faces the top surface. In some embodiments, the semiconductor material obtained from the first precursor source may be grown on the substrate 101 in single crystal epitaxial growth, and the single crystal semiconductor pattern 110 may have a constant crystal plane direction and may be uniformly grown in a vertical direction (Z direction). For example, the single crystal semiconductor pattern 110 may have a uniform vertical thickness regardless of the position along the horizontal direction (X direction and / or Y direction) on the substrate 101.

[0089] In some embodiments, the metal silicide pattern 107 may be spaced apart from the substrate 101 with the single crystalline semiconductor pattern 110 therebetween.

[0090] In the method of growing a single crystal semiconductor material according to a comparative example, for example, the single crystal semiconductor material is epitaxially grown on the substrate 101 by a chemical vapor deposition (CVD), a plasma enhanced CVD (PECVD) or an atomic layer deposition (ALD) process. According to some embodiments, the epitaxial growth rate using the metal silicide pattern 107 can be about 1.5 to about 1000 times that of the growth method of the single crystal semiconductor material according to the comparative example. According to some embodiments, because the single crystal semiconductor pattern 110 is epitaxially grown between the substrate 101 and the metal silicide pattern 107, the pattern imbalance problem caused by the growth speed difference according to the crystal plane can be reduced. For example, the single crystal semiconductor pattern 110 can grow in a vertical direction (Z direction) and have a side surface perpendicular to the top surface of the substrate 101.

[0091] According to some embodiments, while the single crystalline semiconductor pattern 110 is grown, impurities may be removed from a partial region of the substrate 101 that is exposed without vertically overlapping the metal silicide pattern 107 .

[0092] In some embodiments, the first reaction gas may further include a first etching composition. In some embodiments, the first etching composition may be used to remove amorphous Si deposited in the remaining regions except the region where the metal silicide pattern 107 is formed on the substrate 101. Under the first reaction gas, the first precursor source may react with the metal silicide pattern 107 to epitaxially grow a single crystalline semiconductor material on a partial region of the substrate (e.g., a region vertically overlapping the metal silicide pattern 107), and form an amorphous semiconductor layer on the top surface of the substrate 101 in other exposed regions of the substrate 101 except the partial region of the substrate 101. For example, the amorphous semiconductor layer may include amorphous Si.

[0093] In some embodiments, the first etching composition may include a compound selected from HCl, Cl 2 , SF 6 , HF and HBr, but not limited thereto.

[0094] According to some embodiments of the method for manufacturing a memory device, other impurities (e.g., amorphous silicon Si) deposited on the substrate 101 can be removed while forming a single crystal semiconductor pattern 110. For example, the first reaction gas may include a first precursor source and a first etching composition to simultaneously form a single crystal semiconductor pattern 110 and remove surrounding impurities. The mechanism of growing some semiconductor materials in some regions while removing semiconductor materials in other regions can be achieved by the difference in growth rate and etching rate of the semiconductor material in each region. For example, the rate at which a single crystal semiconductor material grows on the bottom surface of the metal silicide pattern 107 by the first precursor source may be faster than the rate at which amorphous semiconductor material grows on the substrate 101 around the metal silicide pattern 107. For example, the growth rate of the single crystal semiconductor material may be about 50 times to about 200 times faster than the growth rate of the amorphous semiconductor material. In addition, the rate at which the amorphous semiconductor material is removed by the etching gas may be faster than the rate at which the single crystal semiconductor material is removed. For example, the rate at which the amorphous semiconductor material is removed may be about 5 times to about 50 times the rate at which the single crystal semiconductor material is removed. That is, as a result of a significantly faster growth rate of the single crystal semiconductor material than the removal rate, the single crystal semiconductor pattern 110 may be formed, and as a result of a significantly faster removal rate of the amorphous semiconductor material than the deposition rate, the amorphous semiconductor layer may be removed while being generated. In this specification, the amorphous semiconductor layer or the amorphous semiconductor material may be referred to as an impurity.

[0095] In some embodiments, a volume ratio of the first precursor source to the first etching composition in the first reaction gas may be about 1 to about 5. For example, when the content of the first precursor source is too small, there may be a problem of excessive increase in the removal amount of the single crystalline semiconductor pattern 110. For example, when the content of the first etching composition is too small, there may be a problem of impurities being deposited on the top surface of the substrate 101 around the single crystalline semiconductor pattern 110.

[0096] Reference Figure 3 and Figure 7 ,exist Figure 6 As a result, a sacrificial semiconductor pattern 120 may be formed on the single crystalline semiconductor pattern 110 (S140).

[0097] In some embodiments, the sacrificial semiconductor pattern 120 may be formed by exposing the metal silicide pattern 107 to a second reaction gas at a second process temperature. In some embodiments, the metal silicide pattern 107 may be melted at the second process temperature to form a second eutectic layer.

[0098] In some embodiments, the second reaction gas may include a second precursor source. In some embodiments, the second precursor source may include a Si source and a Ge source for forming the sacrificial semiconductor pattern 120. For example, the Si source may include a silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ) and dichlorosilane (SiH 2 Cl 2 ). For example, the Ge source may include at least one selected from germanium (GeH 4 ), Digermane (Ge 2 H 6 ), propiogermane (Ge 3 H 8 ), butadiene (Ge 4 H 10 ) and dichlorogermane (GeH 2 Cl 2 ) at least one.

[0099] According to some embodiments, the first eutectic layer may be a metal-semiconductor material eutectic layer. In some embodiments, the first eutectic layer may be a gold (Au)-silicon (Si)-germanium (Ge) eutectic layer.

[0100] In some embodiments, the second eutectic layer can be used as a catalyst in the formation reaction of the sacrificial semiconductor pattern 120. The second precursor source can contact and react with the melted metal silicide pattern 107 (e.g., the second eutectic layer) to generate second source atoms including Si atoms and Ge atoms in the second eutectic layer, and the second source atoms can form the sacrificial semiconductor pattern 120 at the interface between the second eutectic layer and the single crystalline semiconductor pattern 110.

[0101] In some embodiments, the sacrificial semiconductor pattern 120 may be grown on the bottom surface of the second eutectic layer. For example, the sacrificial semiconductor pattern 120 may be grown at the interface between the second eutectic layer and the single crystal semiconductor pattern 110 in a direction away from the top surface of the substrate 101 (i.e., a vertical direction (Z direction)). For example, the sacrificial semiconductor pattern 120 may be formed by growing a preliminary sacrificial semiconductor material layer on the top surface of the single crystal semiconductor pattern 110, and then further growing a sacrificial semiconductor material at the interface between the preliminary sacrificial semiconductor material layer and the second eutectic layer (i.e., the bottom surface of the second eutectic layer). For example, the sacrificial semiconductor pattern 120 may be formed of single crystal silicon germanium (SiGe).

[0102] In some embodiments, the ratio of the number of metal atoms in the second eutectic layer to the total number of atoms may be about 0.05 to about 0.5, about 0.1 to about 0.4, about 0.1 to about 0.3, or about 0.1 to about 0.25. In some embodiments, the ratio of the sum of the number of silicon (Si) atoms and germanium (Ge) atoms in the second eutectic layer to the total number of atoms may be about 0.6 to about 0.99, about 0.7 to about 0.95, or about 0.8 to about 0.95. When the metal atom content in the second eutectic layer is too much, the growth rate of the sacrificial semiconductor pattern 120 may be reduced, and thus, pattern imbalance may occur according to the growth in the horizontal direction (X direction and / or Y direction). When the silicon (Si) atom content and the germanium (Ge) atom content in the second eutectic layer are too much, the temperature for forming the second eutectic layer may increase, and the growth rate of the sacrificial semiconductor pattern 120 may be reduced.

[0103] In some embodiments, the second process temperature may be about 150° C. to about 1450° C. In some embodiments, the second process temperature may be lower than the first process temperature for growing the single crystalline semiconductor pattern 110. Therefore, a three-component second eutectic layer including germanium (Ge) may be easily formed, and the sacrificial semiconductor pattern 120 may be rapidly grown in a vertical direction (Z direction) in the presence of the second eutectic layer.

[0104] For example, when the second process temperature is too low, the metal silicide pattern 107 may not form the second eutectic layer and thus may not serve as a catalyst for forming the sacrificial semiconductor pattern 120. For example, when the second process temperature is too high, the reliability of the semiconductor memory device 10 may deteriorate due to diffusion of semiconductor atoms between adjacent substrates 101. For example, the second process temperature may vary depending on the type and content of metal atoms and / or source atoms.

[0105] In some embodiments, the silicon (Si) atomic content and the germanium (Ge) atomic content in the second eutectic layer may be substantially the same. In other embodiments, the silicon (Si) atomic content and the germanium (Ge) atomic content in the second eutectic layer may be different from each other. For example, the silicon (Si) atomic content in the second eutectic layer may be less than the germanium (Ge) atomic content. For example, the silicon (Si) atomic content in the second eutectic layer may be greater than the germanium (Ge) atomic content.

[0106] In some embodiments, the sacrificial semiconductor pattern 120 may be epitaxially grown in a vertical direction (Z direction) on the top surface of the single crystalline semiconductor pattern 110. In some embodiments, the sidewall profile of the sacrificial semiconductor pattern 120 may be substantially the same as the sidewall profile of the single crystalline semiconductor pattern 110 (e.g., perpendicular to the top surface of the substrate 101).

[0107] In some embodiments, the second reaction gas may further include a second etching composition. The role and composition of the second etching composition are the same as those of the first etching composition above. For example, while growing the sacrificial semiconductor pattern 120, impurities may be removed from a portion of the substrate 101 that is exposed and does not vertically overlap with the metal silicide pattern 107.

[0108] Reference Figure 3 and Figure 8 , can be achieved by Figure 7 As a result, the method of growing the single crystal semiconductor pattern 110 and the method of growing the sacrificial semiconductor pattern 120 are alternately performed to form a patterned mold stack PMS ( S150 ).

[0109] In some embodiments, by heating the metal silicide pattern 107 to form a eutectic layer and then exposing the eutectic layer to a first reaction gas containing a Si source, a single crystal semiconductor pattern 110 may be grown on a sacrificial semiconductor pattern 120 formed on the bottom surface of the metal silicide pattern 107. In this operation, the metal silicide pattern 107 may form the above-mentioned first eutectic layer. Thereafter, a sacrificial semiconductor pattern 120 may be formed by being exposed again to a second reaction gas including a Si source and a Ge source. A patterned mold stack PMS may be formed by repeating the above-mentioned process.

[0110] In some embodiments, the plurality of single crystalline semiconductor patterns 110 and the plurality of sacrificial semiconductor patterns 120 may be alternately grown in a vertical direction (Z direction) to be away from the substrate 101 .

[0111] For example, the patterned mold stack PMS may have a structure in which a plurality of single crystalline semiconductor patterns 110 and a plurality of sacrificial semiconductor patterns 120 are alternately stacked one by one on the substrate 101. According to some embodiments, the patterned mold stack PMS may have a plurality of first vertical holes VH1 and a plurality of second vertical holes VH2 exposing a top surface of the substrate 101.

[0112] In some embodiments, the plurality of single crystal semiconductor patterns 110 may include a plurality of first semiconductor patterns 110a and a plurality of second semiconductor patterns 110b having different thicknesses. The plurality of first semiconductor patterns 110a and the plurality of second semiconductor patterns 110b may be arranged alternately one after another in the vertical direction (Z direction). For example, the first semiconductor patterns 110a and the second semiconductor patterns 110b may be alternately arranged on each of the plurality of sacrificial semiconductor patterns 120 spaced apart from each other in the vertical direction (Z direction).

[0113] In other embodiments, the sacrificial semiconductor pattern 120 may be formed on the substrate 101 earlier than the single crystal semiconductor pattern 110. In this case, the patterned mold stack PMS may have a structure in which a plurality of sacrificial semiconductor patterns 120 and a plurality of single crystal semiconductor patterns 110 are sequentially stacked one by one on the substrate 101 in a vertical direction (Z direction).

[0114] In some embodiments, each of the plurality of sacrificial semiconductor patterns 120 and the plurality of single crystal semiconductor patterns 110 may have a thickness of several tens of nm. The first semiconductor pattern 110a may have a first thickness t1, the second semiconductor pattern 110b may have a second thickness t2, and the sacrificial semiconductor pattern 120 may have a third thickness t3. The first thickness t1 may be greater than the second thickness t2. In some embodiments, the first thickness t1 may have a value of about 10 nm or more than the second thickness t2. In some embodiments, the third thickness t3 may have a value less than each of the first thickness t1 and the second thickness t2.

[0115] In other embodiments, each of the plurality of single crystalline semiconductor patterns 110 may be formed to have substantially the same vertical thickness.

[0116] In some embodiments, each of the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 may have a uniform horizontal width regardless of the vertical level relative to the substrate 101. For example, the inner walls of the plurality of first vertical holes VH1 and the inner walls of the plurality of second vertical holes VH2 may be perpendicular to the top surface of the substrate 101. For example, the inner sidewalls of the patterned mold stack PMS define the plurality of vertical holes. The inner sidewalls are perpendicular to the top surface of the substrate.

[0117] According to the method of manufacturing a semiconductor memory device 10 according to a comparative example, a die stack is formed by repeatedly epitaxially growing a plurality of semiconductor layers and a sacrificial layer on a substrate 101, and then the die stack is etched using a patterned etching mask to form a plurality of first and second vertical holes VH1 and VH2. In the process of forming a die stack by repeatedly stacking a plurality of semiconductor layers and a sacrificial layer, as a result of stacking a plurality of large-area planes, lattice defects may occur due to a difference in lattice constants between a first semiconductor material included in the semiconductor layer and a second semiconductor material included in the sacrificial layer. Therefore, during epitaxial growth, warping may occur due to stress caused by atomic dislocations. In addition, the plurality of first and second vertical holes VH1 and VH2 according to the comparative example have a tapered shape in which the horizontal width becomes narrower while approaching the substrate 101. The difference in horizontal width according to the vertical direction (Z direction) causes the word line WL (refer to FIG. 2A to FIG. 2D ) resistance deviation, thereby deteriorating the reliability of the semiconductor memory device 10.

[0118] In contrast, the method of manufacturing the semiconductor memory device 10 according to some embodiments may form a patterned mold stack PMS using a metal induced crystallization method using a metal silicide pattern 107. By growing a single crystal semiconductor pattern 110 and a sacrificial semiconductor pattern 120 selectively patterned on a partial region of the substrate 101, the occurrence of lattice defects due to the lattice constant difference between the first semiconductor material and the second semiconductor material may be reduced. In addition, the single crystal semiconductor pattern 110 and the sacrificial semiconductor pattern 120 are grown in a vertical direction (Z direction), so that the first vertical hole VH1 and the second vertical hole VH2 each have a uniform horizontal width regardless of the vertical level relative to the substrate 101, thereby improving the electrical reliability of the semiconductor memory device 10.

[0119] Reference Fig.9A and Fig. 9B as well as Figure 8 , in from Figure 8 After the metal silicide pattern 107 is removed as a result of the removal of the metal silicide pattern 107 , the sacrificial insulating layer 134 may be at least partially or completely filled in the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 .

[0120] According to some embodiments, the sacrificial insulating layer 134 may include silicon oxide, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, silicon oxynitride containing carbon, or a combination thereof.

[0121] Thereafter, an etching mask layer (not shown) covering or overlapping the patterned mold stack PMS and the sacrificial insulating layer 134 may be formed, and then a first recess R1 and a second recess R2 exposing the substrate 101 through the patterned mold stack PMS and the sacrificial insulating layer 134 may be formed by an anisotropic etching process. The etching mask layer (not shown) may have a plurality of openings corresponding to the first recess R1 and the second recess R2. In some embodiments, the etching mask layer (not shown) may be formed of silicon nitride.

[0122] In some embodiments, each of the first recess R1 and the second recess R2 may extend in the second horizontal direction (Y direction). In some embodiments, each of the first recess R1 and the second recess R2 may have a tapered shape in which a horizontal width becomes narrower while approaching the substrate 101 .

[0123] The first recess R1 may extend in the second horizontal direction (D2 direction) across the other end of each of the plurality of first vertical holes VH1 in the first horizontal direction (X direction) opposite to the plurality of second vertical holes VH2. Portions of the first sacrificial insulating layer 134 filling the plurality of first vertical holes VH1 may be exposed on the inner side surface of the first recess R1.

[0124] The second recess R2 may extend in the second horizontal direction (Y direction) across one end of each of two second vertical holes VH2 adjacent in the first horizontal direction (X direction). Portions of the sacrificial insulating layer 134 filling the plurality of second vertical holes VH2 may be exposed on the inner side surface of the second recess R2.

[0125] Reference Fig. 10A and Fig. 10B as well as Fig.9A and Fig. 9B After forming the buried structure 140 for filling the first recess R1 and the second recess R2, the etching mask layer (not shown) may be removed, and the sacrificial insulating layer 134 for filling the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 may be removed.

[0126] In some embodiments, the buried structure 140 may include a liner 142, a buried layer 144, and a capping layer 146. The liner 142 may conformally cover or overlap the bottom and side surfaces of the first recess R1 and the second recess R2. The buried layer 144 may cover or overlap the liner 142 and at least partially or completely fill the first recess R1. The capping layer 146 may cover or overlap the top surface of the liner 142 and the top surface of the buried layer 144. In some embodiments, the liner 142 and the capping layer 146 may be formed of silicon nitride. In some embodiments, the buried layer 144 may include any one of silicon oxide, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon nitride, and carbon-containing silicon oxynitride.

[0127] Reference Fig.11 as well as Fig. 10A and Fig. 10B , the plurality of sacrificial semiconductor patterns 120 are removed through the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2, thereby forming a plurality of first gaps 110G1 along a vertical direction (Z direction) between the plurality of single crystal semiconductor patterns 110. The plurality of first gaps 110G1 may be formed by removing the plurality of sacrificial semiconductor patterns 120 through an isotropic etching process having an etching selectivity with respect to the substrate 101, the plurality of single crystal semiconductor patterns 110, the liner 142, and the capping layer 146.

[0128] Reference Fig.12 ,exist Fig.11As a result, portions of the plurality of single-crystal semiconductor patterns 110 exposed by the plurality of first vertical holes VH1, the plurality of second vertical holes VH2, and the plurality of first gaps 110G1 may be removed to form a plurality of single-crystal slits 110S. In some embodiments, each of the plurality of single-crystal slits 110S may have a vertical thickness of about 5 nm to about 15 nm. For example, each of the plurality of single-crystal slits 110S may have a vertical thickness of about 10 nm. Fig.12 Each of the plurality of single crystal slits 110S may be formed to have a horizontal width in the second horizontal direction (Y direction) greater than Fig.11 The horizontal width of the plurality of single crystal semiconductor patterns 110 has a small value.

[0129] In some embodiments, the plurality of single crystal slits 110 may be formed by removing a portion of the plurality of single crystal semiconductor patterns 110 through an isotropic etching process having an etching selectivity with respect to the liner 142 and the capping layer 146. In some embodiments, in the process of forming the plurality of single crystal slits 110S, a portion of the substrate 101 exposed to the bottom surface of the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 may also be removed.

[0130] In some embodiments, the plurality of single crystalline semiconductor patterns 110 may be made of the same material as the substrate 101, and Fig.12 In the embodiment, the single crystal semiconductor pattern 110 which is formed at the lowest layer among the plurality of single crystal semiconductor patterns 110 and contacts the substrate 101 is a portion of the substrate 101 and has a structure protruding from the top surface of the substrate 101 .

[0131] In other embodiments, the plurality of single crystalline semiconductor patterns 110 may be formed of a material different from that of the substrate 101 .

[0132] In some embodiments, when the plurality of single crystal semiconductor patterns 110 include a plurality of first semiconductor patterns 110a and a plurality of second semiconductor patterns 110b having different thicknesses, all of the plurality of second semiconductor patterns 110b having relatively smaller thicknesses are removed, and only a portion of the plurality of first semiconductor patterns 110a may remain as a plurality of single crystal slits 110S. In other embodiments, when each of the plurality of single crystal semiconductor patterns 110 has substantially the same thickness, a portion of each of all the plurality of single crystal semiconductor patterns 110 may remain as a plurality of single crystal slits 110S.

[0133] In some embodiments, the plurality of single crystal slits 110S are arranged at different vertical levels with respect to the substrate 101 and may overlap each other in the vertical direction (Z direction).

[0134] In some embodiments, Fig.12As shown, each of the plurality of single crystal slits 110S may include a first portion in contact with the buried structure 140 and a second portion spaced apart from the buried structure 140. For example, the second portion may extend along the second horizontal direction (Y direction) between two first portions adjacent along the second horizontal direction (Y direction), and may be connected to the two first portions. In some embodiments, the second portions of the plurality of single crystal slits 110S may be arranged in a row in the vertical direction (Z direction) and may substantially completely overlap vertically. In some embodiments, the second portions of the plurality of single crystal slits 110S may have the same horizontal width in the first horizontal direction (X direction). In some embodiments, the two sidewalls of each second portion of the plurality of single crystal slits 110S in the first horizontal direction (X direction) may be arranged on a virtual line perpendicular to the substrate 101.

[0135] In some embodiments, the plurality of buried structures 140 may each have a tapered shape in which a horizontal width in a first horizontal direction (X direction) becomes narrower while approaching the top surface of the substrate 101. In some embodiments, a distance between the second portions of the plurality of single crystal slits 110S and the buried structures 140 in the first horizontal direction (X direction) may vary depending on a vertical level relative to the substrate 101. For example, a first distance between a second portion of a first single crystal slit 110S relatively close to the substrate 101 in the vertical direction (Z direction) and an adjacent buried structure 140 may be greater than a second distance between a second portion of a second single crystal slit 110S relatively far from the substrate 101 in the vertical direction (Z direction) and an adjacent buried structure 140.

[0136] As a result of expansion in the horizontal direction by partially removing the plurality of single crystal semiconductor patterns 110, Fig.11 The plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 shown may be formed respectively Fig.12 The plurality of third vertical holes VH3 and the plurality of fourth vertical holes VH4 are shown. By partially removing the plurality of single crystalline semiconductor patterns 110, the plurality of first gaps 110G1 may form a plurality of second gaps 110G2 extending in a vertical direction (Z direction).

[0137] Reference Fig.13 , a plurality of supporting insulating layers 151 covering or overlapping surfaces of the plurality of single crystal slits 110S and a plurality of isolating insulating layers 153 covering or overlapping surfaces of the supporting insulating layers 151 may be formed. The isolating insulating layers 153 may be integrally formed to cover or overlap surfaces of the plurality of supporting insulating layers 151.

[0138] Each of the plurality of supporting insulating layers 151 may be formed to have such a thickness that portions of the supporting insulating layer 151 covering or overlapping each of the plurality of single crystal slits 110S may be spaced apart from each other without contacting each other in the vertical direction (Z direction). Each isolation insulating layer 153 covers or overlaps a surface of each supporting insulating layer 151 and may be filled between portions of two supporting insulating layers 151 adjacent to each other and spaced apart from each other in the vertical direction (Z direction).

[0139] In some embodiments, a supporting insulating layer 151 and an isolating insulating layer 153 may also be formed on each of the exposed surface of the substrate 101 and the exposed surface of the buried structure 140 .

[0140] Reference Fig.14A and Fig. 14B as well as Fig.13 , a portion of each isolation insulating layer 153 may be removed to form a plurality of isolation insulating patterns 154. The plurality of isolation insulating patterns 154 may be arranged between portions of a plurality of supporting insulating layers 151 arranged in a row along a vertical direction (Z direction). Each isolation insulating pattern 154 may be formed so that a horizontal width in a first horizontal direction (X direction) has a value smaller than a width of each supporting insulating layer 151.

[0141] Subsequently, portions of the plurality of supporting insulating layers 151 may be removed to form a plurality of supporting patterns 152. The plurality of supporting patterns 152 may be disposed between the isolation insulating patterns 154 and the plurality of single crystal slits 110S.

[0142] For example, the plurality of support patterns 152 may be formed by removing the remaining portions except for portions of the support insulating layer 151 placed between the isolation insulating pattern 154 and the plurality of single crystal slits 110S.

[0143] Subsequently, a portion of the plurality of single crystal slits 110S may be removed to form a plurality of single crystal bars 110SB arranged in the vertical direction (Z direction) between portions of two adjacent support patterns 152 between the two isolation insulating patterns 154. The plurality of single crystal bars 110SB may extend in the first horizontal direction (X direction) and may have a bar shape having substantially the same thickness in the vertical direction (Z direction).

[0144] Depend on Fig.12 The plurality of third vertical holes VH3 and the plurality of fourth vertical holes VH4 defined by the plurality of single crystal slits 120S shown may be formed by Fig.14A and Fig. 14B The plurality of support patterns 152 shown define a plurality of fifth vertical holes VH5 and a plurality of sixth vertical holes VH6 .

[0145] For example, in the process of forming a plurality of single crystal bars 110SB, Fig.12 A second portion extending in the second horizontal direction (Y direction) and spaced apart from the buried structure 140 in the first horizontal direction (X direction) is removed from the plurality of single crystal slits 110S shown. A third gap 110G3 may be formed in the space from which the second portion is removed. According to some embodiments, the first support pattern 152 and the second support pattern 152 adjacent to each other may be arranged between the two isolation insulating patterns 154 in the vertical direction (Z direction), and the first support pattern 152 and the second support pattern 152 may be spaced apart from each other in the vertical direction (Z direction) with the third gap 110G3 therebetween.

[0146] Reference Fig.15 ,exist Fig.14A and Fig. 14B As a result, a first buried insulating layer 162 can be formed covering or overlapping the structure obtained by stacking a plurality of single crystal strips 110SB, a plurality of support patterns 152 and a plurality of isolation insulating patterns 154 and filling a plurality of fifth vertical holes VH5, a plurality of sixth vertical holes VH6 and a plurality of third gaps 110G3, and then a first mask layer 164 can be formed covering the first buried insulating layer 162 or overlapping the first buried insulating layer 162 and exposing at least a portion of the top surface of the buried structure 140.

[0147] In some embodiments, the first buried insulating layer 162 may include any one of silicon oxide, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon. In some embodiments, the first mask layer 164 may be made of silicon nitride.

[0148] Reference Fig.16 ,exist Fig.15 As a result, the buried structure 140 filling the first recess R1 may be removed, and then a portion of the plurality of support patterns 152 may be removed through the first recess R1 to form a third recess R3.

[0149] In some embodiments, a portion of the first portions of the plurality of support patterns 152 that are in contact with the buried structure 140 in the first horizontal direction (X direction) and a second portion of the plurality of support patterns 152 that extend in the second horizontal direction (Y direction) and are spaced apart from the buried structure 140 in the first horizontal direction (X direction) may be removed.

[0150] In some embodiments, in the process of removing a portion of the plurality of support patterns 152, a portion of the plurality of single crystal bars 110SB and a portion of the plurality of isolation insulating patterns 154 may be placed in the first portion of the plurality of support patterns 152 that remains and is not removed. The remaining portion of the plurality of single crystal bars 110SB and the remaining portion of the plurality of isolation insulating patterns 154 may be exposed in the space from which the portion of the support pattern 152 is removed. In some embodiments, the remaining portion of the plurality of single crystal bars 110SB and the remaining portion of the plurality of isolation insulating patterns 154 may protrude from the remaining first portion of the plurality of support patterns 152 toward the first recess R1 in the first horizontal direction (X direction).

[0151] For example, in a process of removing a portion of the buried structure 140 and the plurality of support patterns 152 , a portion of the first mask layer 164 may also be removed, thereby reducing the height and width.

[0152] Reference Fig.17 ,exist Fig.16 A spacer liner material layer is formed on the resulting exposed surface, a spacer buried material layer is formed covering the spacer liner material layer or overlapping the spacer liner material layer, and then a portion of the spacer liner material layer and a portion of the spacer buried material layer are removed to form a spacer liner 172 covering or overlapping an inner surface of a portion of each space between a plurality of single crystal strips 110SB and a plurality of separation insulation patterns (also referred to as a plurality of isolation insulation patterns 154) adjacent to each other in the vertical direction (Z direction), and a buried spacer 174 filling a portion of each of the spaces.

[0153] In some embodiments, the spacer liner 172 may be made of silicon nitride, and the buried spacer 174 may include any one of silicon oxide, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon.

[0154] Thereafter, a gate dielectric layer 182 covering or overlapping the exposed surface and a word line WL covering or overlapping the gate dielectric layer 182 and filling a portion of the inner portion of the remaining space of the space between the plurality of single crystal strips 110SB and the plurality of isolation insulating patterns 154 are formed. The word line WL may be formed by forming a gate electrode material layer covering or overlapping the gate dielectric layer 182 and filling the third recess R3, and then removing a portion of the gate electrode material layer so that the remaining portion of the gate electrode material layer remains only in a portion of the inner portion of the remaining space of the space between the plurality of single crystal strips 110SB and the plurality of isolation insulating patterns 154.

[0155] In some embodiments, the word line WL may include a conductive barrier layer covering or overlapping the gate dielectric layer 182 and a conductive filling layer covering or overlapping the conductive barrier layer. The conductive barrier layer may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conductive barrier layer may be made of TiN. The conductive filling layer may be formed of doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba, Sr) RuO), CRO (CaRuO), BaRuO, La (Sr, Co) O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some embodiments, the conductive filling layer may include W.

[0156] Then, a plurality of cap spacers 192 may be formed in the vertical direction (Z direction) to at least partially fill the space between the plurality of single crystal strips 110SB and the plurality of isolation insulating patterns 154. One end of each of the plurality of single crystal strips 110SB facing the first recess R1 may be exposed. In some embodiments, each of the plurality of cap spacers 192 may be made of silicon nitride.

[0157] Thereafter, a plurality of first source / drain regions 222 may be formed by implanting impurities into one end of each of the plurality of single crystal strips 110SB exposed through the first recess R1 .

[0158] Thereafter, a conductive material layer conformally covering or overlapping the first recess R1 is formed, and then an etch-back process is performed to expose the substrate 101, thereby forming a conductive line extending in the second horizontal direction (Y direction) in the first recess R1. Thereafter, a portion of the conductive line may be removed to form a plurality of bit lines BL spaced apart from each other in the second horizontal direction (Y direction). According to some embodiments, the plurality of bit lines BL may extend in a vertical direction (Z direction) and may contact the first source / drain regions 222 arranged in the vertical direction (Z direction).

[0159] For example, each of the plurality of bit lines BL may be made of any one of a doped semiconductor material (such as doped silicon and / or doped germanium), a conductive metal nitride (such as titanium nitride and / or tantalum nitride), a metal (such as tungsten, titanium and / or tantalum), and a metal-semiconductor compound (such as tungsten silicide, cobalt silicide and / or titanium silicide).

[0160] Then, a second buried insulating layer 196 at least partially filling the first recess R1 may be formed. In some embodiments, the second buried insulating layer 196 may be formed of silicon oxide.

[0161] Reference Fig.18 , can be obtained from Fig.17 As a result, the first mask layer 164 and a portion of the second buried insulating layer 196 are removed, and the buried structure 140 filling the second recess R2 may be removed. In some embodiments, the plurality of support patterns 152 exposed by the second recess R2 may be removed to form a fourth recess R4 communicating with the second recess R2.

[0162] In the process of forming the fourth recess R4 , the plurality of single crystal bars 110SB and the plurality of isolation insulating patterns 154 may not be removed, and portions of the plurality of single crystal bars 110SB and portions of the plurality of isolation insulating patterns 154 may be exposed through the fourth recess R4 .

[0163] For example, a portion of the plurality of single crystal bars 110SB and a portion of the plurality of isolation insulating patterns 154 may be surrounded by the spacer liner 172 and the buried spacer 174. The remaining portions of the plurality of single crystal bars 110SB and the remaining portions of the plurality of isolation insulating patterns 154 may protrude from the spacer liner 172 and the buried spacer 174 toward the second recess R2 in the first horizontal direction (X direction).

[0164] Reference Fig.19 ,exist Fig.18 As a result, the portions of the plurality of single crystal bars 110SB protruding from the spacer liner 172 and the buried spacer 174 toward the second recess R2 in the first horizontal direction (X direction) may be removed. In some embodiments, the plurality of second source / drain regions 226 may be formed by implanting impurities into the other end of each of the plurality of single crystal bars 110SB exposed via the second recess R2. After forming the plurality of second source / drain regions 226, the remaining portions of the plurality of single crystal bars 110SB may be referred to as a plurality of single crystal channel layers 224. The first source / drain region 222, the single crystal channel layer 224, and the second source / drain region 226 may be referred to together as a transistor body 220. All transistor bodies 220 may be made of a single crystal semiconductor material. For example, each of the first source / drain region 222, the single crystal channel layer 224, and the second source / drain region 226 may be formed of a single crystal semiconductor material. The transistor body 220 , the gate dielectric layer 182 , and the word line WL may constitute a cell transistor CTR.

[0165] Thereafter, a lower electrode material layer may be formed that conformally covers or overlaps the surface exposed in the second recess R2. The lower electrode material layer may conformally cover or overlap the surfaces of the second source / drain region 226, the isolation liner 172, the buried spacer 174, and the isolation insulating pattern 154. Thereafter, a portion of the lower electrode material layer that covers the other end of each of the plurality of isolation insulating patterns 154 facing the second recess R2 or overlaps the other end may be removed to form a plurality of hollow cylindrical first electrodes EL1, wherein the portion facing the second recess R2 in the first horizontal direction (X direction) is open, and the portion facing the second source / drain region 226 is encapsulated.

[0166] In some embodiments, after exposing the surface of the other end of each of the plurality of isolation insulating patterns 154, a portion of the plurality of separation insulating patterns or the plurality of isolation insulating patterns 154 may be removed from the other end. In some embodiments, a portion of the first buried insulating layer 162 defining a partial region of the second recess R2 may be removed. In some embodiments, the plurality of isolation insulating patterns 154 and portions of the first buried insulating layer 162 may be removed by an isotropic etching process.

[0167] Refer to Fig.19 and FIG. 2A to FIG. 2D A capacitor dielectric layer DL conformally covering or overlapping the plurality of first electrodes EL1 and a second electrode EL2 covering or overlapping the capacitor dielectric layer DL and filling the second recess R2 may be formed to form a unit capacitor CAP including the first electrode EL1, the capacitor dielectric layer DL, and the second electrode EL2.

[0168] The capacitor dielectric layer DL may cover at least a portion of the inner surface and the outer surface of each of the plurality of first electrodes EL1 or overlap at least a portion of the inner surface and the outer surface of each of the plurality of first electrodes EL1, each of which has a cylindrical shape. In some embodiments, the capacitor dielectric layer DL may cover the entire inner surface of each of the plurality of first electrodes EL1 having a cylindrical shape or overlap the entire inner surface, and may cover a portion of the outer surface or overlap a portion of the outer surface. In other embodiments, the capacitor dielectric layer DL may cover the entire inner surface of each of the plurality of first electrodes EL1 having a cylindrical shape or overlap the entire inner surface, and may cover the entire outer surface or overlap the entire outer surface. The second electrode EL2 may at least partially fill the interior of each of the plurality of first electrodes EL1 having a cylindrical shape. That is, each of the plurality of first electrodes EL1 may have a U-shaped vertical cross-section rotated 90 degrees, wherein the open portion faces the direction opposite to the second source / drain region 226, that is, the open portion faces the second electrode EL2.

[0169] The first electrode EL1 may include a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the first electrode EL1 may include a high melting point metal layer, such as cobalt, titanium, nickel, tungsten, and / or molybdenum. For example, the first electrode EL1 may include a metal nitride layer, such as a titanium nitride layer, a titanium silicon nitride layer, a titanium aluminum nitride layer, a tantalum nitride layer, a tantalum silicon nitride layer, a tantalum aluminum nitride layer, and / or a tungsten nitride layer.

[0170] The capacitor dielectric layer DL may be formed of at least one selected from a ferroelectric material and a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the capacitor dielectric layer may include at least one of a dielectric material having a perovskite structure and a metal oxide. For example, the capacitor dielectric layer DL includes at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalum (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO) and lead scandium tantalum oxide (PbScTaO).

[0171] The second electrode EL2 can be formed of doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO (((Ba, Sr)RuO), CRO (CaRuO), BaRuO, La (Sr, Co) O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TiAlN, TaSiN or a combination thereof.

[0172] Fig. 20A and Fig. 20B is a cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to other embodiments, and shows a method of manufacturing a semiconductor memory device along Figure 4A The cross-sectional view taken along the line X1-X1' corresponds to the portion.

[0173] Reference Fig. 20A , a mask pattern 102 may be formed on the substrate 101 , and then a metal material may be deposited on the mask pattern 102 and the substrate 101 to form a metal seed layer 105 a .

[0174] In some embodiments, the mask pattern 102 may include a silicon oxide layer formed by a photo process. In some embodiments, the mask pattern 102 may have a pattern shape corresponding to a set of the plurality of first openings op1 and the plurality of second openings op2.

[0175] In some embodiments, the metal seed layer 105a may be formed by physical vapor deposition (PVD) or atomic layer deposition (ALD) processes, but is not limited to the above examples. In some embodiments, the metal seed layer 105a may include a portion in contact with the substrate 101 and a portion in contact with the mask pattern 102.

[0176] Reference Fig. 20B , can be obtained by Fig. 20A As a result, the portion of the metal seed layer 105a disposed on the mask pattern 102 is removed to form a metal seed pattern (not shown). For example, the metal seed pattern may have a Figure 4B The metal seed crystal pattern 105 has a shape corresponding to that of the metal seed crystal pattern 105 .

[0177] In some embodiments, a portion of the metal seed layer 105 a may be removed by a lift-off process, and a metal seed pattern (not shown) as a remaining portion of the metal seed layer 105 a may be disposed in a space defined by the top surface of the substrate 101 and the mask pattern 102 .

[0178] Then, the metal silicide pattern 107 may be formed from the metal seed pattern through a heating process. In some embodiments, a portion of a sidewall of the metal silicide pattern 107 may contact the mask pattern 102 .

[0179] Then, as referenced Figures 6 to 8 As described above, the patterned mold stack PMS may be formed by alternately growing a plurality of single crystal semiconductor patterns 110 and a plurality of sacrificial semiconductor patterns 120 one by one from the metal silicide pattern 107. Thereafter, the patterned mold stack PMS may be formed by referring to FIG. 9A to FIG. 19 The manufacturing method is described to manufacture the semiconductor memory device 10.

[0180] In some embodiments, the mask pattern 102 may be Fig. 10A and Fig. 10B The mask pattern 102 may be removed together with the sacrificial insulating layer 134 in the operation of removing the sacrificial insulating layer 134 described above. Fig. 20B The metal seed layer 105a is removed together with the stripping process described above for removing a portion of the metal seed layer 105a. In this case, a reference Figure 4B A metal seed pattern 105 is depicted.

[0181] While the inventive concept has been particularly shown and described with reference to certain embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising: forming a metal seed pattern having a plurality of openings on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; growing a single crystal semiconductor pattern in a vertical direction at an interface between the substrate and the metal silicide pattern, wherein the vertical direction is perpendicular to the substrate; as well as A sacrificial semiconductor pattern is grown along the vertical direction at an interface between the metal silicide pattern and the single crystalline semiconductor pattern.

2. The method according to claim 1, in, The single crystal semiconductor pattern includes silicon (Si), and Wherein, growing the single crystal semiconductor pattern includes heating the metal silicide pattern under a first reaction gas including a silicon (Si) source.

3. The method according to claim 2, wherein: The metal silicide pattern includes gold (Au), and When the single crystal semiconductor pattern is grown, the metal silicide pattern forms a first eutectic layer of gold (Au)-silicon (Si).

4. The method according to claim 2, wherein: The first reaction gas further includes a first etching composition configured to remove impurities deposited on the substrate.

5. The method according to claim 1, in, The sacrificial semiconductor pattern includes silicon (Si) and germanium (Ge), and Wherein, growing the sacrificial semiconductor pattern includes heating the metal silicide pattern under a second reaction gas including a silicon (Si) source and a germanium (Ge) source.

6. The method according to claim 5, wherein: The metal silicide pattern includes gold (Au), and Wherein, when the sacrificial semiconductor pattern is grown, the metal silicide pattern forms a second eutectic layer of gold (Au)-silicon (Si)-germanium (Ge).

7. The method according to claim 1, wherein: Sidewalls of the single crystalline semiconductor pattern and sidewalls of the sacrificial semiconductor pattern are perpendicular to a top surface of the substrate.

8. The method according to claim 1, further comprising: A patterned mold stack having a plurality of vertical holes is formed by alternately growing corresponding single crystalline semiconductor patterns among a plurality of single crystalline semiconductor patterns and corresponding sacrificial semiconductor patterns among a plurality of sacrificial semiconductor patterns from a bottom surface of the metal silicide pattern.

9. The method according to claim 8, wherein: A horizontal width of each of the plurality of vertical holes is constant regardless of a distance from the substrate in the vertical direction.

10. The method according to claim 8, further comprising: at least partially filling the plurality of vertical holes with a sacrificial insulating layer; as well as forming a plurality of recesses by anisotropically etching the patterned mold stack and the sacrificial insulating layer, the plurality of recesses extending into the patterned mold stack and the sacrificial insulating layer in the vertical direction, The plurality of recesses have a tapered shape in which a horizontal width becomes narrower in the vertical direction toward the substrate.

11. A method for manufacturing a semiconductor memory device, the method comprising: forming a metal seed pattern on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; forming a eutectic layer of metal-semiconductor material by heating the metal silicide pattern; as well as A patterned mold stack having a plurality of vertical holes exposing the substrate is formed by alternately growing corresponding single crystalline semiconductor patterns among a plurality of single crystalline semiconductor patterns and corresponding sacrificial semiconductor patterns among a plurality of sacrificial semiconductor patterns from a bottom surface of the eutectic layer.

12. The method according to claim 11, wherein: Inner sidewalls of the patterned mold stack defining the plurality of vertical holes are perpendicular to a top surface of the substrate.

13. The method according to claim 11, wherein: The plurality of single crystalline semiconductor patterns and the plurality of sacrificial semiconductor patterns are epitaxially grown in a direction away from a top surface of the substrate.

14. The method according to claim 11, wherein: Forming the eutectic layer is performed at a temperature ranging from about 250°C to about 1500°C.

15. The method according to claim 11, wherein: The ratio of the number of atoms of the metal to the total number of atoms in the eutectic layer is from about 0.1 to about 0.

3.

16. The method according to claim 11, in, The plurality of single-crystal semiconductor patterns include silicon (Si), and Wherein, the plurality of sacrificial semiconductor patterns include silicon (Si) and germanium (Ge).

17. A method for manufacturing a semiconductor memory device, the method comprising: forming a metal seed pattern having a plurality of openings on a substrate; forming a metal silicide pattern from the substrate and the metal seed pattern; forming a eutectic layer of metal-semiconductor material by heating the metal silicide pattern; forming a patterned mold stack having a plurality of vertical holes by alternately growing corresponding single crystalline semiconductor patterns among a plurality of single crystalline semiconductor patterns and corresponding sacrificial semiconductor patterns among a plurality of sacrificial semiconductor patterns from a bottom surface of the eutectic layer; at least partially filling the plurality of vertical holes with a sacrificial insulating layer; forming a plurality of recesses by anisotropically etching the patterned mold stack and the sacrificial insulating layer, the plurality of recesses extending into the patterned mold stack and the sacrificial insulating layer in a vertical direction; as well as forming a buried insulating structure in the plurality of recesses, wherein the plurality of vertical holes have a constant horizontal width regardless of a distance from the substrate, and the plurality of recesses have a tapered shape in which a width narrows toward a top surface of the substrate.

18. The method according to claim 17, in, The plurality of single-crystal semiconductor patterns include silicon (Si), Wherein, the plurality of sacrificial semiconductor patterns include silicon (Si) and germanium (Ge), and Among them, forming the patterned mold stack includes, after heating the metal silicide pattern, alternately contacting the metal silicide pattern with a first reaction gas and a second reaction gas, wherein the first reaction gas includes a first silicon (Si) source, and the second reaction gas includes a second silicon (Si) source and a germanium (Ge) source.

19. The method according to claim 17, wherein: The plurality of single crystalline semiconductor patterns and the plurality of sacrificial semiconductor patterns are epitaxially grown in a direction away from the top surface of the substrate.

20. The method according to claim 17, wherein: The ratio of the number of atoms of the metal to the total number of atoms in the eutectic layer is from about 0.1 to about 0.3.

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