Sram memory cell, sram device and method of manufacturing the same

Abstract

The application discloses an SRAM memory unit, an SRAM device and a preparation method thereof, and belongs to the field of semiconductors. In the application, the active regions of NMOS and PMOS are arranged in the optimal directions respectively, then the PMOS is arranged in a sinking mode, so that the active regions of the two kinds of transistors are staggered to improve the heat dissipation capacity. In order to manufacture the above structure, the application designs a corresponding preparation method. In the preparation process, the gate of the pull-up transistor is stepped, so that the gate of the pull-up transistor can be connected with the active region of the transfer gate transistor through a metal silicide technology, thereby greatly reducing the contact resistance, that is, reducing the heat generation of the storage node, thereby improving the performance of the whole device, and the read-write speed is faster than that of the prior art under the same condition.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors and relates to a memory technology, specifically to an SRAM memory cell, an SRAM device, and a method for fabricating the same. Background Technology

[0002] Static Random-Access Memory (SRAM) has advantages such as high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics products (smart cards, digital cameras, multimedia players) and other fields.

[0003] The basic structure of static random access memory (SRAM) is fixed, such as... Figure 1 As shown, taking 6T as an example, the SRAM cell includes transfer gate transistors PG1 and PG2, pull-up transistors PU1 and PU2, and pull-down transistors PD1 and PD2. Pull-up transistors PU1 and PU2 are P-type metal-oxide-semiconductor transistors (PMOS), pull-down transistors PD1 and PD2 are N-type metal-oxide-semiconductor transistors (NMOS), and transfer gate transistors PG1 and PG2 are N-type metal-oxide-semiconductor transistors (NMOS). The gates of transfer gate transistors PG1 and PG2 are connected to and controlled by the word line WL that determines whether to select the SRAM cell. A latch formed by pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2 stores bits, where the complementary values ​​of the bits are stored in the left storage node SNL and the right storage node SNR. Transfer gate transistors PG1 and PG2 are connected to bit line BL and anti-phase line BLB, respectively. Stored bits can be written to or read from the SRAM cell via bit line BL and anti-phase line BLB.

[0004] The sources of pull-up transistors PU1 and PU2 are connected to the power supply voltage / node Vdd; the sources of pull-down transistors PD1 and PD2 are connected to ground Vss. The gates of pull-up transistors PU1 and PD1 are connected to the drains of pull-up transistors PU2 and PD2, with the connection node being the right memory node SNR. The gates of pull-up transistors PU2 and PD2 are connected to the drains of pull-up transistors PU1 and PD1, with the connection node being the left memory node SNL. The source region of the transfer gate transistor PG1 is connected to the bit line BL at the bit line node, and the drain region of the transfer gate transistor PG1 is connected to the left memory node SNL. The source region of the transfer gate transistor PG2 is connected to the anti-phase line BLB (complementary bit line) at the anti-phase line node, and the drain region of the transfer gate transistor PG2 is connected to the right memory node SNR.

[0005] The basic structure and principle of the SRAM cell described above have been determined. However, because six MOS transistors form a highly concentrated memory cell and are interconnected, different layout designs can lead to completely different performance characteristics. For example... Figure 2 The diagram shows a common layout design in the prior art. The channels of the six MOS transistors are arranged vertically in four columns. The transfer gate transistor PG1 and the pull-down transistor PD1 share a source / drain in the first column. The channel of the pull-up transistor PU1 is arranged vertically and forms a separate second column. The channel of the pull-up transistor PU2 is arranged vertically and forms a separate third column. The transfer gate transistor PG2 and the pull-down transistor PD2 share a source / drain in the fourth column. This design is easy to manufacture, but with the improvement of semiconductor manufacturing processes and the shrinking of the physical size of SRAM cells, this design has exposed some defects, such as wasted space, all channels being arranged in one direction, requiring the use of stressed silicon technology to improve the channel carrier mobility, poor heat dissipation, and low device density leading to limited storage capacity, etc.

[0006] Existing technologies have conducted considerable research on SRAM layout design. Chinese patent application CN118714839A discloses an SRAM layout in which the active regions of the transfer gate transistor PG1, pull-down transistor PD1, pull-down transistor PD2, and transfer gate transistor PG2 are arranged on a straight line for source-drain sharing, and the pull-up transistors PU1 and PU2 are arranged on another straight line for source-drain sharing in order to save area. However, since all active regions are oriented in the same direction, complex stress silicon technology is still required to improve the channel carrier migration rate.

[0007] Chinese patent application CN105788628A discloses an SRAM layout in which pull-up transistors PU1 and PU2 share a common source and drain, pull-down transistors PD1 and PD2 share a common source and drain, and transfer gate transistors PG1 and PG2 are set separately. This further saves area and increases the storage capacity per unit area. However, the active region is still in one direction, and complex stress silicon technology is still required to improve the channel carrier migration rate. Furthermore, the heat dissipation problem of the device is not considered.

[0008] Chinese patent application CN101345214A discloses an SRAM layout design in which NMOS devices are set in the first direction (110 crystal orientation) and PMOS devices are set in the second direction (100 crystal orientation) in the SRAM cell, with the angle between the first and second directions being 45 degrees. The MOS transistors are connected in a common way in the prior art. This technology improves the carrier migration rate in the channel region by setting different crystal orientations, which can eliminate the need for stress silicon technology. However, this technology does not consider heat dissipation, and the layout design is not compact, resulting in low layout density.

[0009] In summary, existing SRAM layout designs only improve certain aspects, and there is still much room for improvement in the design. Therefore, it is necessary to redesign the SRAM layout to provide a layout with better overall performance. Summary of the Invention

[0010] One of the objectives of this invention is to provide an SRAM memory cell that improves the carrier mobility in the channel region by setting the active regions of NMOS and PMOS in the (100) crystal orientation and (110) crystal orientation, respectively, and by setting different crystal orientations, and the channels of NMOS and PMOS are staggered in the thickness direction; thereby solving the problems of mutual constraints between SRAM storage density and heat dissipation and low carrier mobility in the prior art.

[0011] Another objective of this invention is to provide a method for fabricating SRAM memory cells, enabling the fabrication of the aforementioned special NMOS and PMOS structures, while also ensuring low contact resistance, thereby improving device performance.

[0012] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0013] On one hand, the present invention provides an SRAM memory cell, wherein the SRAM memory cell includes at least 6 transistors, the 6 transistors being two transfer gate transistors, two pull-up transistors and two pull-down transistors, and the gate of the pull-up transistors and the drain of the transfer gate transistors are connected to form a memory node;

[0014] Two transmission gate transistors and two pull-down transistors have a first type of active region, which is set in a first direction; two pull-up transistors have a second type of active region, which is set in a second direction and is recessed. The first direction and the second direction are two directions with optimal carrier migration rates selected according to the wafer orientation.

[0015] Furthermore, the angle between the first direction and the second direction ranges from 30 to 60 degrees.

[0016] Furthermore, the first direction is the (100) crystal orientation, and the second direction is the (110) crystal orientation.

[0017] Furthermore, the two pull-up transistors share a common source setting.

[0018] Furthermore, the gate of the pull-up transistor is directly connected to the drain of the corresponding transfer gate transistor via metal silicide technology.

[0019] Furthermore, the two transfer gate transistors share the same gate line.

[0020] Furthermore, the pull-up transistor and the pull-down transistor have the same gate width, and the gate width of the transmission gate transistor is greater than the gate width of the pull-up transistor.

[0021] Furthermore, the active region width of the pull-down transistor, the active region width of the transmission gate transistor, and the active region width of the pull-up transistor decrease sequentially.

[0022] Furthermore, two transmission gate transistors and two pull-down transistors are arranged in an array to form a quadrilateral region, and two pull-up transistors are disposed within the quadrilateral region.

[0023] Furthermore, the subsidence of the second type of active region is not less than the channel depth of the first type of active region.

[0024] On the other hand, the present invention provides an SRAM device, including a semiconductor substrate and a plurality of SRAM memory cells formed on the semiconductor substrate. The SRAM memory cells include at least 6 transistors, the 6 transistors being two transfer gate transistors, two pull-up transistors and two pull-down transistors respectively. The gate of the pull-up transistor and the drain of the transfer gate transistor are connected to form a memory node.

[0025] Two transmission gate transistors and two pull-down transistors have a first type of active region, which is set in a first direction; two pull-up transistors have a second type of active region, which is set in a second direction and is recessed. The first direction and the second direction are two directions with optimal carrier migration rates selected according to the wafer orientation.

[0026] On the other hand, the present invention provides a method for fabricating an SRAM device, comprising the following steps:

[0027] Provide semiconductor substrates;

[0028] The active region of each transistor is isolated by an isolation structure;

[0029] The area where the two pull-up transistors are located is etched using an etching process to create a recessed groove.

[0030] Ion implantation technology is used to implant the corresponding type of ions into the active region of each transistor to form the trap region of the first type of active region and the second type of active region.

[0031] The bare gate of each transistor is fabricated, and the bare gate of the pull-up transistor is stepped through an etching process so that the height of the bare gate at the memory node is the same as that of the active region of the transfer gate transistor.

[0032] Sidewalls are fabricated on the bare gate to obtain the gate;

[0033] Fabrication of source and drain electrodes;

[0034] The active region and the top surface of the gate at the memory node are metallized to obtain a metallization layer;

[0035] A metal interconnect layer is fabricated, and six transistors are connected to form an SRAM memory cell.

[0036] Furthermore, the isolation structure adopts an isolation structure with vertical sidewalls.

[0037] Furthermore, during the formation of the recessed groove, the active regions of the two pull-up transistors and their surrounding isolation structures are recessed together.

[0038] Furthermore, the bare gate of each transistor is fabricated, and the bare gate of the pull-up transistor is stepped through an etching process so that the height of the bare gate at the memory node is the same as that of the active region of the transfer gate transistor, including the following steps:

[0039] Photoresist is coated and exposure and development techniques are used to obtain a photoresist pattern that forms the gate shape;

[0040] Etch the gate material outside the photoresist cover;

[0041] Photoresist is applied again, and exposure and development techniques are used to obtain a photoresist pattern that exposes the memory node area;

[0042] The gate material in the memory node region is etched so that the height of the gate material layer at the memory node is the same as the height of the first type of active region.

[0043] Further, the active region and the top surface of the gate at the memory node are silicided to obtain a metal silicide layer, including the following steps:

[0044] Pre-cleaning involves etching away part of the silicon layer at the top of the active region and the gate.

[0045] A nickel-platinum alloy layer is deposited on the pre-cleaned silicon layer surface;

[0046] Deposit a capping layer on a nickel-platinum alloy layer;

[0047] The first rapid thermal annealing is performed to form a high-resistivity metal silicide;

[0048] A second rapid thermal annealing process is performed to form a low-resistivity metal silicide layer.

[0049] Furthermore, during the fabrication of the metal interconnect layer, the left memory node SNL is connected to the drain of the second pull-up transistor and the drain of the second pull-down transistor via metal lines, and the right memory node SNR is connected to the drain of the first pull-up transistor and the drain of the first pull-down transistor via metal lines.

[0050] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0051] This invention creatively positions the NMOS and PMOS in the directions of their respective optimal carrier migration rates (for example, setting the NMOS in the (100) crystal orientation and the PMOS in the (110) crystal orientation), enabling each to achieve its optimal migration rate and obtain excellent device electrical performance without employing stressed silicon technology. Based on this, this invention sinks the second type of active region and sinks the PMOS, so that the channel region of the PMOS is staggered in height from the channel region of the NMOS. The unexpected effect is to achieve excellent heat dissipation. Furthermore, since there are four NMOS transistors and two PMOS transistors, placing the two PMOS transistors with their shared source in the middle of the four NMOS transistors can increase the minimum spacing between the active regions by placing the NMOS and PMOS transistors in different directions using geometric effects. Conversely, the maximum spacing between the four NMOS transistors can be further reduced, thereby further increasing the transistor density and designing high-density SRAM devices. On the basis of the above, this invention achieves excellent heat dissipation by staggering the channels, which disperses the main heat-generating points in space. This solves the heat dissipation problem of high-density memory devices, avoids the impact of device heat on electrical performance, and can further shorten the transistor spacing, thereby setting more SRAM memory cells in a unit area to obtain a larger capacity memory.

[0052] This invention saves area, reduces the number of contact holes, lowers costs, and increases storage density by setting two pull-up transistors to share a common source.

[0053] This invention reduces the use of word lines (WL) by setting two transmission gate transistors to share a gate. Since word lines (WL) need to be powered during reading and writing, reducing the use of word lines (WL) can reduce reading and writing power consumption.

[0054] To fabricate the aforementioned SRAM memory cell with its unique structure, this invention creatively first isolates the active region using an isolation structure, then etches the area containing the second type of active region using an etching process; subsequently, an ion implantation process is used to form the well regions of the first and second types of active regions; then, an etching process is used to form the bare gate, which is stepped up by two etching processes during the formation of the bare gate, making the height of the bare gate at the memory node the same as that of the active region of the transfer gate transistor; this provides the basic conditions for the gate of the pull-up transistor and the active region of the transfer gate transistor to be connected by metal silicide; then, sidewalls are fabricated and the memory node region is metal silicided; then, the source and drain electrodes are fabricated; finally, a metal interconnect layer is prepared to complete the fabrication of the SRAM device. An unexpected effect is that this invention completes the fabrication of the aforementioned unique structure SRAM device through a clever combination of simple and mature processes; and during the fabrication process, the metal silicide technology reduces the connection resistance between the gate of the pull-up transistor and the active region of the transfer gate transistor, thereby enabling the memory node to efficiently and stably store and read / write data, while also ensuring relatively low thermal resistance, achieving unexpected technical results. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of an SRAM memory cell circuit in the prior art.

[0056] Figure 2 This is a layout of SRAM memory cells in the prior art.

[0057] Figure 3 This is a schematic diagram of a cubic crystal plane in the prior art.

[0058] Figure 4 This is a schematic diagram of the SRAM storage cell circuit in Embodiment 1 of the present invention.

[0059] Figure 5 This is the basic layout of the SRAM memory cell in Embodiment 1 of the present invention.

[0060] Figure 6 The layout of adding some metal lines to the SRAM memory cell in Embodiment 1 of the present invention.

[0061] Figure 7 This is a flowchart of the SRAM device fabrication method in Embodiment 3 of the present invention.

[0062] Figure 8 A schematic diagram of a semiconductor substrate is provided in step S100 of embodiment 3 of the present invention.

[0063] Figure 9 This is a schematic diagram of the formation of the first photoresist pattern in step S200 of embodiment 3 of the present invention.

[0064] Figure 10 This is a schematic diagram of forming the isolation groove in step S200 of embodiment 3 of the present invention.

[0065] Figure 11 This is a schematic diagram of the shallow trench isolation structure formed in step S200 of embodiment 3 of the present invention.

[0066] Figure 12 This is a schematic diagram of the formation of the second photoresist pattern in step S300 of embodiment 3 of the present invention.

[0067] Figure 13 This is a top view of step S300 of embodiment 3 of the present invention, which forms the second photoresist pattern.

[0068] Figure 14 This is a schematic diagram of the formation of the sunken groove in step S300 of embodiment 3 of the present invention.

[0069] Figure 15 This is a schematic diagram of the formation of the second type of active region in step S400 of embodiment 3 of the present invention.

[0070] Figure 16 This is a schematic diagram of removing the first hard mask in step S400 of embodiment 3 of the present invention.

[0071] Figure 17 This is a schematic diagram of the formation of the first type of active region in step S400 of embodiment 3 of the present invention.

[0072] Figure 18 This is a schematic diagram of the formation of the gate material layer in step S500 of embodiment 3 of the present invention.

[0073] Figure 19 This is a schematic diagram of the formation of the anti-reflective coating in step S500 of embodiment 3 of the present invention.

[0074] Figure 20 This is a schematic diagram of the formation of the fourth photoresist pattern in step S500 of embodiment 3 of the present invention.

[0075] Figure 21A This is a schematic diagram of forming a bare gate in step S500 of embodiment 3 of the present invention.

[0076] Figure 21B This is a top view of the bare gate formed in step S500 of embodiment 3 of the present invention.

[0077] Figure 22A This is a schematic diagram of the formation of a bare gate step in step S500 of embodiment 3 of the present invention.

[0078] Figure 22B This is a top view of forming a bare gate stepped structure in step S500 of embodiment 3 of the present invention.

[0079] Figure 23 This is a schematic diagram of removing the second hard mask on top of the gate in step S600 of embodiment 3 of the present invention.

[0080] Figure 24 This is a schematic diagram of the formation of the first gate sidewall in step S600 of embodiment 3 of the present invention.

[0081] Figure 25 This is a schematic diagram of the formation of the NLDD region in step S600 of embodiment 3 of the present invention.

[0082] Figure 26 This is a schematic diagram of the gate forming double sidewalls in step S600 of embodiment 3 of the present invention.

[0083] Figure 27 This is a schematic diagram of the formation of the source and drain in step S700 of embodiment 3 of the present invention.

[0084] Figure 28 This is a schematic diagram of the formation of a metal silicide layer in step S800 of embodiment 3 of the present invention.

[0085] Figure 29 This is a schematic diagram of the formation of the barrier layer in step S900 of embodiment 3 of the present invention.

[0086] Figure 30 This is a schematic diagram of the formation of the interlayer dielectric layer in step S900 of embodiment 3 of the present invention.

[0087] Figure 31 This is a schematic diagram of the formation of the contact hole in step S900 of embodiment 3 of the present invention.

[0088] Figure 32 This is a schematic diagram of filling the contact hole in step S900 of embodiment 3 of the present invention.

[0089] in, Figures 8 to 12 , Figures 14 to 21A , Figure 22A , Figures 23 to 32 All Figure 5 Sectional view along the broken line from A1 to A2.

[0090] 100 - P-type silicon substrate; 110 - deep N-well; 120 - first buffer oxide layer; 101 - first hard mask; 102 - first photoresist pattern; 103 - isolation trench; 104 - shallow trench isolation structure; 105 - second photoresist pattern; 106 - sunken trench; 107 - N-well; 108 - third photoresist pattern; 109 - P-well; 111 - NLDD region; 112 - N-type silicon substrate. + area;

[0091] 200 - SRAM memory cell, 201 - first transfer gate transistor, 202 - second transfer gate transistor, 203 - first pull-up transistor, 204 - second pull-up transistor, 205 - first pull-down transistor, 206 - second pull-down transistor, 220 - metal silicide layer;

[0092] 300 - Metal interconnect layer, 301 - Barrier layer, 310 - Metal circuit; 320 - Interlayer dielectric layer, 321 - First ILD thin film, 322 - Second ILD thin film, 323 - Cover layer; 330 - Contact hole; 331 - Contact barrier layer, 332 - Metal connection layer;

[0093] 410 - Gate material layer; 411 - Second buffer oxide layer; 412 - Second hard mask; 413 - Bottom anti-reflective coating; 414 - Fourth photoresist pattern; 415 - Top anti-reflective coating; 416 - Silicon oxide; 420 - Gate oxide layer; 421 - Gate oxide material layer; 430 - Memory node region; 440 - Bare gate; 450 - First gate sidewall; 460 - Second gate sidewall. Detailed Implementation

[0094] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0095] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0096] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0097] Before describing the technical solution of this invention, the prior art related to this invention will be introduced, such as... Figure 3The diagram shows a common cubic crystal system in silicon-based semiconductor substrates. An XYZ coordinate system is established with one endpoint of the cubic crystal as the origin, O. The plane ABCD enclosed by vertices A, B, C, and D of the cube is the (100) crystal direction; the plane ABEF enclosed by vertices A, B, E, and F of the cube is the (110) crystal direction; the plane CEFD enclosed by vertices C, E, F, and D of the cube is the (001) crystal direction; and the plane DFGA enclosed by vertices D, F, G, and A of the cube is the (010) crystal direction. Due to the symmetry of semiconductor crystals, there exist equivalent directions and families of planes. Therefore, the (100) crystal direction has a family of crystal directions, and the carrier migration rates of these family of crystal directions are basically the same. The family of crystal directions of the (100) crystal direction includes the (010) crystal direction and the (001) crystal direction. The (110) crystal orientation also has its own family of crystal orientations, which have essentially the same carrier migration rate. The family of crystal orientations of the (110) crystal orientation includes the (011) crystal orientation, (101) crystal orientation, (-1-10) crystal orientation, (0-1-1) crystal orientation, (-10-1) crystal orientation, (-110) crystal orientation, (0-11) crystal orientation, and (10-1) crystal orientation; from Figure 3 It can be seen that the angle between the (100) crystal orientation and the (110) crystal orientation is 45 degrees.

[0098] The crystal orientations described above are merely examples of silicon-based semiconductor substrates. When other types of substrates are used, different crystal forms have different crystal orientations. However, in general, the carrier migration rates of NMOS and PMOS are different in different crystal orientations, and they often have their own optimal crystal orientations. Moreover, the crystal orientations of the optimal carrier migration rates of NMOS and PMOS generally do not coincide.

[0099] Taking silicon-based semiconductor substrates as an example, electron mobility in silicon crystals is highly correlated with crystal orientation. In the (100) crystal orientation, the effective mass of electrons is the smallest (approximately 0.19m0, where m0 is the free electron mass), resulting in the highest mobility (up to ~1500 cm² / (Vs) in bulk silicon). This orientation can significantly improve the drive current and switching speed of NMOS. Hole mobility reaches its peak in the (110) crystal orientation (approximately ~500 cm² / (Vs) in bulk silicon) because its effective mass is the smallest in this orientation (approximately 0.49m0). Choosing this orientation can optimize the conduction capability and response speed of PMOS.

[0100] Existing technologies also save area by sharing the source and drain of pull-up or pull-down transistors. However, this method of saving area results in an overly compact design of the active area of ​​the SRAM, leading to high heat generation and affecting device performance. This invention, based on the advantages of existing technologies, improves heat dissipation by staggering the active areas, thereby maintaining a high-density, high-performance SRAM device design, and also provides corresponding fabrication processes.

[0101] Example 1: This example provides an SRAM storage unit, such as... Figure 4 The circuit diagram of the SRAM memory cell provided by the present invention is shown below. The SRAM memory cell includes 6 transistors, which are two transmission gate transistors, two pull-up transistors and two pull-down transistors. The gate of the pull-up transistor and the drain of the transmission gate transistor are connected to form a memory node.

[0102] Specifically, the six transistors are the first transmission gate transistor 201, the second transmission gate transistor 202, the first pull-up transistor 203, the second pull-up transistor 204, the first pull-down transistor 205, and the second pull-down transistor 206.

[0103] The source region of the first transmission gate transistor 201 is connected to the bit line BL at the bit line node, and the source region of the second transmission gate transistor 202 is connected to the anti-phase line BLB (complementary bit line) at the anti-phase line node. The two transmission gate transistors share a gate line and are connected to the word line WL.

[0104] See Figure 5 and Figure 6 As shown, Figure 5 and Figure 6 In this diagram, D represents the drain and S represents the source. The first pull-up transistor 203 and the second pull-up transistor 204 share a common source, which is connected to the power supply voltage / node Vdd. The sources of the first pull-down transistor 205 and the second pull-down transistor 206 are connected to ground Vss (GND). The gates of the first pull-up transistor 203 and the first pull-down transistor 205 are connected to the drain of the first transmission gate transistor 201, forming a left storage node SNL at the connection point. This node is then connected to the drains of the second pull-up transistor 204 and the second pull-down transistor 206 via the metal lines 310 of the metal interconnect layer 300. The gates of the second pull-up transistor 204 and the second pull-down transistor 206 are connected to the drain of the second transmission gate transistor 202, forming a right storage node SNR at the connection point. This right storage node SNR is then connected to the drains of the first pull-up transistor 203 and the first pull-down transistor 205 via the metal lines 310 of the metal interconnect layer 300. These six transistors are connected in this manner to form a latch storage bit.

[0105] The read operation of SRAM memory cell 200 relies on the voltage signal difference between two bit lines (BL and BLB). Assuming that the SRAM memory cell stores 0 data, SNL=0 and SNR=1. The test conditions are: BL=BLB=1 and WL=1.

[0106] Under these conditions:

[0107] 1. Since SNL=0 is at a low potential and SNR=1 is at a high potential, the first pull-up transistor 203 is turned on, the first pull-down transistor 205 is turned off, the second pull-up transistor 204 is turned off, and the second pull-down transistor 206 is turned on.

[0108] 2. The complementary bit line BLB potential remains unchanged, but the second pull-down transistor 206 is turned on, causing the current in the bit line BL to flow to ground GND, resulting in a decrease in the potential of the bit line BL.

[0109] Initially, BL=BLB=1. After the BL potential drops, a voltage difference will appear between BL and BLB. This signal will be output through the external amplifier circuit, and the signal reading of SRAM memory cell 200 is completed.

[0110] Write operations of SRAM memory cell 200 are performed by reversing the potentials of SNL and SNR;

[0111] Assuming the SRAM stores 0 data, then SNL=0 and SNR=1.

[0112] The test conditions are as follows:

[0113] BL=1, BLB=0, WL=1

[0114] Under these conditions:

[0115] 1. Since SNL=0 is at a low potential and SNR=1 is at a high potential, the first pull-up transistor 203 is turned on, the first pull-down transistor 205 is turned off, the second pull-up transistor 204 is turned off, and the second pull-down transistor 206 is turned on.

[0116] 2. Since BLB=0 and WL=1, the second transfer gate transistor 202 is turned on, and the SNR potential of the right storage node gradually decreases.

[0117] 3. The decrease in the SNR potential of the right storage node causes the second pull-up transistor 204 to turn on and the second pull-down transistor 206 to turn off. Under the power supply Vdd, the SNL potential of the left storage node rises.

[0118] 4. The SNL potential of the left storage node rises, causing the first pull-down transistor 205 to turn on and the first pull-up transistor 203 to turn off, thus completing the data flip.

[0119] The SRAM memory cell 200 is in a holding operation: the first transfer gate transistor 201 and the second transfer gate transistor 202 are turned off, and no modifications are made to the internal circuitry.

[0120] The test conditions are as follows:

[0121] BL=BLB=1, WL=0;

[0122] Under these conditions

[0123] When the first transfer gate transistor 201 and the second transfer gate transistor 202 are turned off, the bit line BL and the complementary bit line BLB cannot modify the data held in the memory node.

[0124] This invention provides a layout design for the aforementioned SRAM memory cells, such as... Figure 5 As shown, Figure 5 In this study, the active regions of all transistors are divided into two categories according to the transistor type: the first category of active regions and the second category of active regions.

[0125] The channels of the two transmission gate transistors (first transmission gate transistor 201 and second transmission gate transistor 20) and the two pull-down transistors (first pull-down transistor 205 and second pull-down transistor 206) are configured as a first type of active region, and the first type of active region is configured in a first direction; the channels of the two pull-up transistors (first pull-up transistor 203 and second pull-up transistor 204) are configured as a second type of active region, and the second type of active region is configured in a second direction. The second type of active region is recessed, wherein the first direction and the second direction are two directions with optimal carrier migration rates selected according to the wafer orientation.

[0126] For example, the first type of active region is NMOS (N-Metal-Oxide-Semiconductor), and the second type of active region is PMOS (P-Metal-Oxide-Semiconductor). Taking silicon-based semiconductors as an example, the carriers of NMOS are electrons, which have the best migration rate in the (100) crystal direction, and the carriers of PMOS are holes, which have the best migration rate in the (110) crystal direction. Therefore, the first direction is set to the (100) crystal direction and the second direction is set to the (110) crystal direction. In silicon crystal, the angle between the (100) crystal direction and the (110) crystal direction is 45 degrees. In the layout design, taking the horizontal direction as the (100) crystal direction as an example, the first direction is set to the horizontal direction and the second direction is set to the direction with an angle of 45 degrees to the horizontal direction.

[0127] This invention creatively positions NMOS and PMOS transistors along their respective optimal carrier migration rates, enabling them to achieve their best migration rates and achieving excellent device electrical performance without employing stressed silicon technology. Building upon this, the invention further recesses the second type of active region; for example, in the above embodiment, the PMOS transistor is recessed, causing its channel region to be offset from that of the NMOS transistor in height. An unexpected effect is that by spatially dispersing the main heat-generating points through this channel offsetting, the invention achieves excellent heat dissipation, preventing device heating from affecting electrical performance. Furthermore, it can further shorten the transistor spacing, thereby allowing for more SRAM memory cells to be placed within a unit area, resulting in a larger capacity memory.

[0128] It should be noted that the angle between the first and second directions is not fixed at 45 degrees, but can vary within the range of 30-60 degrees. For different types of substrates, the crystal form may be different, and the optimal crystal orientation may also be different. Therefore, the angle between the first and second directions may also be different. Specifically, the first and second directions need to be determined according to the substrate type and crystal orientation.

[0129] In some embodiments, the two pull-up transistors share a common source and are connected to the power supply Vdd through the common source. For example, in the above embodiment, the first pull-up transistor 203 and the second pull-up transistor 204 share a common source, which can further reduce the PMOS area, thereby making more SRAM memory cells 200 in a unit area of ​​substrate. At the same time, by sharing the source, one contact hole and corresponding metal line are reduced, which reduces the process difficulty.

[0130] In some embodiments, such as Figure 5 As shown, two transmission gate transistors and two pull-down transistor arrays are distributed at the four corners to form a quadrilateral area, and two pull-up transistors are set in the quadrilateral area. Through this relative positioning, the six transistors are more compactly distributed in the SRAM memory cell. Under the same process technology, the transistor density can be increased, which means the storage capacity per unit area can be increased.

[0131] Since there are four NMOS transistors and two PMOS transistors (two pull-up transistors), placing the two PMOS transistors with their shared source in the middle of the four NMOS transistors can increase the minimum spacing between the active regions by using geometric effects to place the NMOS and PMOS transistors in different directions. Conversely, the minimum spacing between the four NMOS transistors can be further reduced, thereby further increasing the transistor density and designing high-density SRAM devices. However, in designing high-density SRAM devices, this approach is difficult to dissipate heat because the two PMOS transistors are located in the middle of the four NMOS transistors and are highly clustered. Therefore, although this design increases the storage density, its poor heat dissipation capability leads to poor long-term operational stability of the device. This invention creatively places the PMOS transistors at the bottom, so that the channels of the PMOS and NMOS transistors are staggered, avoiding the heat source of the NMOS transistors (mainly the channel) from enveloping the heat source of the PMOS transistors, thereby improving the heat dissipation capability of the PMOS transistors. Unexpectedly, this invention achieves better actual heat dissipation effect. Simulation verification shows that the temperature is greatly reduced during use, thus enabling the creation of high-stability, high-density SRAM devices.

[0132] In some embodiments, the gate of the pull-up transistor is directly connected to the drain of the corresponding transmission gate transistor via metal silicide technology. The gate of the pull-up transistor and the active region of the transmission gate transistor are connected to form a memory node, which is defined as memory node region 430. For example, the gate of the pull-up transistor is arranged with different height steps, so that the gate of the pull-up transistor is at the same height as the drain of the transmission gate transistor, allowing them to be connected via a metal silicide layer 220. For instance, the gate of the first pull-up transistor 203 is connected to the drain of the first transmission gate transistor 201 via the metal silicide layer 220, and the gate of the second pull-up transistor 204 is connected to the drain of the second transmission gate transistor 202 via the metal silicide layer 220. Metal silicide technology can greatly reduce contact resistance. Actual measurements show that the contact resistance of existing contact hole connection technologies is generally around 10 ohms. -4 The above; however, this invention directly uses metal silicide layers for connection, and the contact resistance is generally 10. -7 -10 -8 Therefore, the contact resistance of this invention is 3-4 orders of magnitude lower, which can significantly reduce heat generation and improve device performance.

[0133] In some embodiments, the gates of the pull-up transistor and the pull-down transistor are connected by a gate line to reduce transmission resistance. For example, the gate of the first pull-up transistor 203 and the gate of the first pull-down transistor 205 are connected by the same gate line; the gate of the second pull-up transistor 204 and the gate of the second pull-down transistor 206 are connected by the same gate line to reduce heat generation during the read, write and storage processes of the SRAM memory cell 200.

[0134] In some embodiments, two transfer gate transistors share the same gate line. Controlling the two transfer gate transistors through the same gate line can reduce the use of word lines (WL), thereby saving area and reducing process complexity.

[0135] In some embodiments, such as Figure 5 As shown, the gate width L3 of the pull-up transistor is the same as the gate width L2 of the pull-down transistor, and the gate width L1 of the transfer gate transistor is greater than the gate width L3 of the pull-up transistor, i.e., L1>L2=L3. By setting the gate width L3 of the pull-up transistor and the gate width L2 of the pull-down transistor to be the same, the change rates of the left storage node SNL and the right storage node SNR are consistent during the data storage process of the SRAM memory cell, thereby improving storage efficiency. Since the word line WL is in a high potential state during the read and access process, the gate of the transfer gate transistor is in a powered state for most of the time during SRAM use. By setting the gate width L1 of the transfer gate transistor to be greater than the gate width L3 of the pull-up transistor, the gate heat generation of the transfer gate transistor is reduced during the read and access process, thereby greatly reducing the operating temperature of the SRAM memory. Generally, L1 can be 10-30% larger than L2. The value within this range is a balance between electrical performance and area.

[0136] In some embodiments, such as Figure 5 As shown, the active region width W2 of the pull-down transistor, the active region width W1 of the transmission gate transistor, and the active region width W3 of the pull-up transistor decrease sequentially, i.e., W2>W1>W3. This invention, by setting the active region width W3 of the pull-up transistor to be smaller than the active region width W1 of the transmission gate transistor, ensures that the current of the pull-up transistor is less than the current of the transmission gate transistor during data storage, thereby guaranteeing a smooth decrease in the potential of the right storage node SNR and achieving efficient data storage. This invention, by setting the active region width W2 of the pull-down transistor to be greater than the active region width W1 of the transmission gate transistor, ensures that the current of the pull-down transistor is greater than the current of the transmission gate transistor during signal reading, thereby guaranteeing a sufficiently large potential difference between BL and BLB for accurate reading.

[0137] Generally speaking, W2 should be about 10-40% larger than W1, and W1 should be about 10-40% larger than W3. This ratio range represents a balance between the overall device performance and area of ​​the SRAM memory cell.

[0138] In some embodiments, the subsidence of the second type of active region is not less than the channel depth of the first type of active region. More preferably, the subsidence of the second type of active region is exactly equal to the channel depth of the first type of active region, which can both meet the heat dissipation requirements and reduce the manufacturing difficulty.

[0139] In some embodiments, such as Figure 6 As shown, the left memory node SNL is connected to the drain of the second pull-down transistor 206 and the drain of the second pull-up transistor 204 through the metal interconnect 310 of the metal interconnect layer; the right memory node SNR is connected to the drain of the first pull-down transistor 205 and the drain of the first pull-up transistor 203 through another metal interconnect 310 of the metal interconnect layer; the complete connection of the SRAM memory cell 200 is achieved through the metal interconnect layer 300. The present invention minimizes the connection of the metal interconnect layer through the above design, thereby reducing the heat generation of the entire device and improving the device's operational stability and electrical performance.

[0140] Example 2: This example provides an SRAM device, in which the SRAM memory cell 200 from Example 1 is fabricated on a semiconductor substrate. Common semiconductor substrates include silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, gallium oxide, etc. Substrates are also divided into P-type substrates and N-type substrates, such as P-type silicon substrates and N-type silicon substrates. They can also be bulk silicon substrates or silicon-on-insulator (SOI) substrates; the appropriate selection is made according to the specific needs.

[0141] Example 3: As Figure 7 As shown, this embodiment provides a method for fabricating an SRAM device, including the following steps:

[0142] S100, provides semiconductor substrates;

[0143] S200: The active region of each transistor is isolated by an isolation structure;

[0144] S300: The area where the two pull-up transistors are located is etched using an etching process to form a recessed groove.

[0145] S400: Ion implantation process is used to implant the corresponding type of ions into the active region of each transistor to form the trap region of the first type of active region and the second type of active region.

[0146] S500: Prepare the bare gate of each transistor, and use an etching process to step up the bare gate of the pull-up transistor so that the height of the bare gate at the memory node is the same as the height of the active region of the transfer gate transistor.

[0147] S600. Sidewall fabrication is performed on the bare gate to obtain the gate;

[0148] S700, fabrication of source and drain electrodes;

[0149] S800: The active region and the top surface of the gate are metallized to obtain a metallization layer;

[0150] S900: Fabricate a metal interconnect layer and connect 6 transistors to form an SRAM memory cell.

[0151] In step S100, the silicon substrate can be a common substrate in the prior art. In this embodiment, the semiconductor substrate is a P-type silicon substrate 100, and a deep N-well 110 (DWN) is fabricated in the P-type silicon substrate 100, such as... Figure 8 As shown; the specific method is as follows:

[0152] S110. A first buffer oxide layer 120 is prepared on a P-type silicon substrate 100;

[0153] For example, a first buffer oxide layer 120 of a certain thickness is formed on a P-type silicon substrate 100 using a furnace tube process. The first buffer oxide layer 120 is located between the silicon substrate and the hard mask layer. It is used to alleviate the high tensile stress of silicon nitride and to optimize the shallow trench isolation structure. The thickness is generally related to the process node. The actual thickness is determined by stress model simulation and defect detection data. A balance needs to be struck between protecting the silicon interface and process controllability. This can be achieved according to existing technologies. For example, in mature processes, the thickness can be 15-30nm, and in advanced nodes (28nm and below), the thickness can be 5-10nm. For example, the material of the first buffer oxide layer 120 is silicon oxide.

[0154] S120, a deep N-well 110 is formed by ion implantation process;

[0155] First, photoresist is coated on a P-type silicon substrate 100, and then photolithography is performed using a mask (to define the deep N-well region).

[0156] After development, a photoresist window is left in the area where the deep N-well 110 needs to be formed, while other areas are covered by photoresist.

[0157] High-energy N-type dopant ions (typically phosphorus or arsenic) are implanted into the silicon substrate through a photoresist window. During implantation, the energy, dose, angle, and depth can be selected to obtain a deep N-well 110 that meets the requirements. Figure 8 As shown, Figure 8 for Figure 5 Sectional view along the broken line from A1 to A2. Figure 8 The middle dashed line is Figure 5 The boundary line between the gate line of the first pull-up transistor 203 and the active region of the first transfer gate transistor 201.

[0158] For example, the implanted ion is P, the implantation energy is 3.0 MeV, and the implantation dose is 1.60E12cm. -2 Implantation angle scheme: 2 / 0 / 1; injection depth: determined by the structural size and process advancement of the SRAM cell, for example, it can be 2000 angstroms.

[0159] Preferably, the ion implantation distribution follows a Gaussian distribution. Multi-energy, multi-dose, multi-stage implantation can make the ion distribution more uniform, and annealing can be performed after implantation to improve the quality of the obtained deep N-well.

[0160] In step S200, the active region of each transistor is isolated by an isolation structure. Specifically, the active region can be isolated by a shallow trench isolation structure 104 (STI), as follows:

[0161] S210. A first hard mask 101 is deposited on the first buffer oxide layer 120. Common materials for the first hard mask 101 include Si3N4, TiN, TaN, and W.

[0162] S220, Coat the photoresist, then expose and develop to obtain the first photoresist pattern 102, as shown. Figure 9 As shown, the window of the first photoresist pattern 102 is a shallow trench isolation structure 104;

[0163] S230. Isolation grooves 103 (forming STI grooves) are obtained by dry etching. After removing the first photoresist pattern 102, as shown... Figure 10 As shown;

[0164] In some embodiments, after the isolation trench is fabricated, it is further processed by RTP (Rapid Thermal Annealing) process. On the one hand, it performs corner rounding, which reduces the concentration of electric field by rounding the sharp corners on both sides of STI. On the other hand, it can repair the damage to the active region (AA) on the sidewall of the isolation trench caused by dry etching.

[0165] In some embodiments, reactive ion etching (RIE) or atomic layer etching (ALE) is used to obtain isolation trenches with vertical sidewalls, which facilitates subsequent process fabrication, especially for the sinking of type II active regions.

[0166] S240. Fill the isolation trench with isolation material and flatten it on the first hard mask 101 to obtain a shallow trench isolation structure 104, such as... Figure 11 As shown;

[0167] The isolation material can be common isolation materials such as silicon dioxide. For example, TEOS (tetraethoxysilane) is deposited using a high aspect ratio process (HARP) to fill the isolation trenches to a height higher than the first hard mask 101.

[0168] The porous TEOS is transformed into dense SiO2 by a heat treatment process (RTP) to form an insulating material layer.

[0169] The isolation material layer is planarized using a CMP process and then deposited onto the first hard mask 101 to obtain a shallow trench isolation structure 104 (STI). Figure 11 As shown.

[0170] In step S300, the area where the two pull-up transistors are located is etched using an etching process to form a recessed groove 106, including the following steps:

[0171] S310, apply photoresist, then expose and develop to obtain the second photoresist pattern 105, as shown. Figure 12 As shown, the window of the second photoresist pattern 105 is the area where the two pull-up transistors are located, including the second type of active region and the shallow trench isolation structure 104 around it, as shown in the top view. Figure 13 As shown;

[0172] S320, an etching process is used to etch and form a recessed groove 106. After removing the second photoresist pattern 105, as shown... Figure 14 As shown; during the etching process, by selecting the etching solution and etching parameters, the etching rates of the first hard mask 101, the first buffer oxide layer 120, the shallow trench isolation structure 104, and the deep N-well 110 can be made the same, so that the regions where the two pull-up transistors are located are basically lowered at the same height; in order to further improve the etching quality, the first hard mask 101 and the first buffer oxide layer 120 can be etched first, and then the shallow trench isolation structure 104 and the deep N-well 110 can be etched simultaneously, so that the regions where the two pull-up transistors are located are etched down simultaneously, and the etching depth of the recessed groove 106 is greater than or equal to the channel design depth of the first type of active region, that is, greater than or equal to the depth of the NMOS channel. In actual processes, the depth can be selected as 200~500 angstroms.

[0173] In S400, an ion implantation process is used to implant the appropriate type of ions into the active region of each transistor, including the following steps;

[0174] S410, N-type ions are directly injected into the regions where the two pull-up transistors are located to obtain N-well 107, forming a type II active region, such as Figure 15 As shown; since other areas are blocked by the shallow trench isolation structure 104 or the first hard mask 101, N-type ions can only be injected into the active region of the pull-up transistor. No photolithography process is required. Phosphorus (P) or arsenic (As) ions are generally selected. The injection can be carried out in three steps, with different depths injected respectively.

[0175] S420, Remove the remaining first hard mask 101 by an etching process (such as wet etching), as follows: Figure 16 As shown;

[0176] S430, Coat photoresist, then expose and develop to obtain third photoresist pattern 108. The window of third photoresist pattern 108 is the active area where the transmission gate transistor and pull-down transistor are located.

[0177] S440. By implanting P-type ions into the active regions of the transmission gate transistor and the pull-down transistor, a P-well 109 is obtained, forming a first-type active region, such as... Figure 17 As shown, the third photoresist pattern 108 and the first buffer oxide layer 120 are then removed to complete the definition of the active regions of NMOS and PMOS.

[0178] S500: Fabricate the bare gate 440 of each transistor, and use an etching process to step up the bare gate 440 of the pull-up transistor so that the height of the bare gate 440 at the memory node is the same as the height of the active region of the transfer gate transistor. The result is as follows: Figure 22A As shown, the specific steps include:

[0179] S510, deposit gate material and planarize it to obtain gate material layer 410, as shown. Figure 18 As shown, the specific steps include:

[0180] S511, Deposit gate oxide material layer 421;

[0181] The gate oxide layer 421 can be made of silicon dioxide, silicon oxynitride, high-k dielectric (such as HfO2), etc. In this embodiment, it is silicon dioxide, which is formed by thermal oxidation process and has a thickness of 20~30 angstroms.

[0182] S512. Deposit gate material. The gate material is a common gate material in the prior art, such as polysilicon, metal gate, work function layer, etc. In this embodiment, polysilicon is used. After planarization, a gate material layer 410 is obtained, such as... Figure 18 As shown.

[0183] S520. A hard mask layer is prepared on the gate material layer 410;

[0184] A second buffer oxide layer 411 is deposited on the gate material layer 410. The material of the second buffer oxide layer 411 is the same as that of the first buffer oxide layer 120, and the function is basically the same.

[0185] A second hard mask 412 is deposited on the second buffer oxide layer 411 to obtain a hard mask layer; the material and function of the second hard mask 412 are the same as those of the first hard mask 101.

[0186] S530. The gate shapes of the first type of active region and the second type of active region are etched using an etching process. The specific steps are as follows:

[0187] S531, Deposit an anti-reflective coating on the second hard mask 412;

[0188] For example, a bottom anti-reflective coating 413 (BARC) is deposited on the second hard mask 412.

[0189] S532, apply photoresist and deposit top anti-reflective coating 415 (TARC), such as Figure 19 As shown;

[0190] S533, then exposure and development are performed to obtain the fourth photoresist pattern 414. The fourth photoresist pattern 414 exactly covers the gates of all transistors, that is, the window is the area outside the gates of all transistors, such as... Figure 20 As shown;

[0191] S534. Etching is performed using an etching process with a high selectivity etching solution. This ensures that the gate oxide layer 421 in the first type of active region (excluding the gate) is completely etched, while the gate material layer 410 in the second type of active region (excluding the gate) is also completely etched. The specific etching solution formulation is determined based on the selectivity ratio, a common technique in the prior art. The selectivity ratio of the gate material layer 410 to the gate oxide layer 421 is 10-50:1, specifically determined by the respective thicknesses of the gate material layer 410 and the gate oxide layer 421. For example, if the thickness of the gate oxide layer 421 is 20 angstroms and the thickness of the gate material layer 410 in the recessed area of ​​the second type of active region is 200 angstroms, then the etching ratio needs to be 10:1. The etching solution formulation is selected based on this etching ratio and the respective material types. After etching, the gate oxide layer 420 is formed just below the gate material layer 410 in the first type of active region. After removing the fourth photoresist pattern 414 and the bottom anti-reflective coating 413, the shape is as follows... Figure 21A As shown, it can be seen that the gate of the second type of active region is stepped at the boundary with the first type of active region (at the memory node), as shown in the top view. Figure 21B As shown.

[0192] In another embodiment, if the gate oxide material layer 421 in the area outside the gate of the first type of active region is just etched and the gate material layer 410 in the area outside the gate of the second type of active region is not yet etched, the photolithography process can be used again to cover and protect the first type of active region with photoresist, and the gate material layer 410 and gate oxide material layer 421 in the area outside the gate of the second type of active region can be etched.

[0193] S540. Coat the photoresist again, then expose and develop to obtain the fifth photoresist pattern (not shown in the figure). The window of the fifth photoresist pattern is part of the gate of the second type active region at the boundary with the first type active region (memory node).

[0194] The gate height is reduced by etching, making the gate height of a portion of the second type of active region flush with the active region height of the first type of active region, forming the memory node region 430. The fifth photoresist pattern is removed by ashing, and residues, the second hard mask 412, and the second buffer oxide layer 411 are removed by wet cleaning, resulting in the bare gate 440. Figure 22A As shown, the top view is as follows Figure 22B As shown.

[0195] S600. Sidewall fabrication is performed on the bare gate 440 to obtain the gate, including the following steps:

[0196] S610, First gate sidewalls 450 are fabricated on both sides of the bare gate 440, such as Figure 24 As shown.

[0197] For example, it includes the following steps;

[0198] S611. Using ROX process (Recessed Oxide Isolation), silicon oxide 416 is formed on the sidewall of the bare gate 440;

[0199] S612, Remove the second hard mask 412 at the top of the gate, as shown. Figure 23 As shown;

[0200] In this embodiment, a hot phosphoric acid wet etching process is used to precisely remove the second hard mask 412 on top of the gate.

[0201] S613. Deposit a sidewall material layer, wherein the sidewall material layer comprises any one of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. For example, silicon nitride is preferred in this invention.

[0202] S614. Anisotropic etching is used to remove the sidewall material layer and the second buffer oxide layer 411 in the top and surrounding areas of the gate, resulting in the first gate sidewall 450. Figure 24 As shown;

[0203] Specifically, anisotropic etching is achieved using dry etching (plasma etching); the etching gas for etching Si3N4 is a mixture of CF4 / CHF3 / O2 (selective ratio Si3N4:SiO2 ≥ 10:1). The etching gas for etching SiO2 is C4F8 / CHF3 / Ar (selective ratio SiO2:Si ≥ 20:1).

[0204] S620. The NMOS transistor connection and PMOS transistor connection of the first type active region and the second type active region are respectively prepared by ion implantation process;

[0205] For example, the connection between NMOS transistors and PMOS transistors is fabricated using LDD technology, and the specific method is as follows:

[0206] S621. Coat with NMOS photoresist and expose the first type of active region by exposure and development;

[0207] S622, Perform ion implantation to form NLDD region 111 (N-type lightly doped drain), obtaining NMOS transistor connection, such as Figure 25 As shown;

[0208] This invention provides an implantation method that uses sequential implantation of Ge, C, In, B (pockect), N, P, and As elements to a certain depth to form an NLDD region.

[0209] This embodiment provides an exemplary injection parameter as follows:

[0210] Ge element ion implantation parameters: energy 15 keV, dose 3.0E14, implantation angle scheme 0 / 0 / 4 (tilt angle / rotation angle / dose coefficient, the same applies below), implantation depth 131 angstroms;

[0211] C element ion implantation parameters: energy 10 keV, dose 3.0E14, implantation angle scheme 0 / 0 / 4, implantation depth 260 angstroms;

[0212] The implantation of Ge and C ions breaks up the silicon in the substrate, allowing for better control of the implantation depth;

[0213] In ion implantation parameters: energy 65 keV, dose 6.0E12, implantation angle scheme 37 / 90 / 2, implantation depth 480 angstroms;

[0214] Boolean ion implantation parameters: energy 9 keV, dose 3.4E13, implantation angle scheme 37 / 90 / 2, implantation depth 362 angstroms;

[0215] Pocket ion implantation, where the ion junction is deeper than the channel, prevents source-drain interconnection.

[0216] Nitrogen ion implantation parameters: energy 8 keV, dose 10E15, implantation angle scheme 0 / 0 / 4, implantation depth 200 angstroms; nitrogen implantation can improve the reliability of time-dependent dielectric breakdown (TDDB) for NMOS.

[0217] P element ion implantation parameters: 2 keV, dose 7.74E13, implantation angle scheme 0 / 0 / 4, implantation depth 28 angstroms;

[0218] As ion implantation parameters: energy 2 keV, concentration 8.69E14, implantation angle scheme 0 / 0 / 4, implantation depth 20 angstroms. The junction depth in the NLDD region is shallower than the channel to prevent the HCI effect (hot carrier injection effect).

[0219] It should be noted that the above parameters are for illustrative purposes only and can be adjusted according to the actual application of the device and the level of advancement in the manufacturing process.

[0220] S623, Coat with PMOS photoresist, and expose the second type of active region by exposure and development;

[0221] S624, Ion implantation is performed to form a PLDD region ( Figure 25 (Not shown in the image), the PMOS transistor connection is obtained.

[0222] This invention provides an injection method in which Ge, AS (pockect, pocket ion implantation), and BF2 are sequentially injected to a certain depth to form a PLDD region.

[0223] This embodiment provides an exemplary injection parameter as follows:

[0224] Ge ion implantation parameters: energy 15keV, dose 3.0E14, implantation angle scheme 0 / 0 / 4, implantation depth 131 angstroms; implanting Ge ions disperses the silicon in the substrate, allowing for better control of the implantation depth.

[0225] As ion implantation parameters: energy 50 keV, dose 1.8E13, implantation angle scheme 30 / 0 / 4, implantation depth 322 angstroms; pocket ion implantation, the ion junction depth is deeper than the channel to prevent source-drain interconnection.

[0226] BF2 injection parameters: dose 1.6 keV, dose 1.01E15, implantation angle scheme 0 / 0 / 4, implantation depth 80 angstroms; the junction depth in the PLDD region is shallower than that in the channel to prevent HCI effect (hot carrier injection effect).

[0227] It should be noted that the above parameters are for illustrative purposes only and can be adjusted according to the actual application of the device and the level of advancement in the manufacturing process.

[0228] In other embodiments, a second gate sidewall may be formed on both sides of the gate. An example of this invention is provided below:

[0229] S630, a second gate sidewall 460 is formed on both sides of the first gate sidewall 450; as shown in... Figure 26 As shown.

[0230] S631 uses ROX process (Recessed Oxide Isolation) to deposit silicon oxide;

[0231] S632. Deposit a sidewall material layer, wherein the sidewall material layer comprises any one of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. For example, silicon nitride is preferred in this invention.

[0232] S633. Anisotropic etching is used to remove the sidewall material layer and silicon oxide in the top and surrounding areas of the gate, resulting in the second gate sidewall 460, thus obtaining a dual-spacer gate. Figure 26 As shown;

[0233] Specifically, anisotropic etching is achieved using dry etching (plasma etching); the etching gas for etching Si3N4 is a mixture of CF4 / CHF3 / O2 (selective ratio Si3N4:SiO2 ≥ 10:1). The etching gas for etching SiO2 is C4F8 / CHF3 / Ar (selective ratio SiO2:Si ≥ 20:1).

[0234] In S700, the fabrication of the source and drain includes the following steps:

[0235] By using a heavy ion doping process, N-type N-type MOSFETs are obtained by heavy doping in the source and drain regions. + Region 112, heavy doping is performed in the source and drain regions of the PMOS to obtain P + area( Figure 27 (not shown in the image), to obtain the corresponding source and drain electrodes, and use photolithography to cover the areas that do not need to be doped.

[0236] In some embodiments, N + The region is mainly injected with P, GE, P, As, and F at a certain depth in sequence. + The region is mainly injected with Ge, B, and BF2 to a certain depth, and then subjected to peak annealing at a certain temperature, such as around 1050℃, mainly to fix the injected ions within a certain region.

[0237] In S800, the active region and the top surface of the gate are metallized to obtain a metallized layer, as shown in the figure. Figure 28 As shown, the main steps are as follows:

[0238] S810. Remove the photoresist left from the previous process, and then deposit a barrier layer to cover the areas where metal silicide does not need to be formed. The barrier layer can be a combination of silicon oxide and silicon nitride, and can be formed by first depositing and then etching. The areas where metal silicide needs to be formed are the exposed active area and the top of the gate.

[0239] S820, pre-cleaning, etching away part of the silicon layer at the top of the active region and the gate (the substrate silicon of the active region and the polysilicon exposed at the top of the gate are collectively referred to as the silicon layer).

[0240] For example, SiCoNi (typically a vapor phase etching technique based on HF / ethanol or other formulations) is used to remove the native oxide layer on the silicon (Si) surface; approximately 60 angstroms (6 nanometers) thick silicon layer is etched away, and the etching thickness can be 20-80 angstroms, depending on the actual needs;

[0241] S830, Deposit a nickel-platinum alloy layer on the pre-cleaned silicon layer surface;

[0242] Physical vapor deposition (PVD, such as sputtering) is typically used.

[0243] The thickness is approximately 120 angstroms (12 nanometers), but can be 40-160 angstroms, depending on the specific requirements.

[0244] The main functions of platinum are as follows:

[0245] Lower the temperature at which disilicides form;

[0246] Suppressing nickel diffusion into polysilicon gates and source / drain areas;

[0247] Improve the morphological stability of nickel silicides on narrow lines to prevent junction leakage and contact resistance degradation;

[0248] Reduce bridging issues in nickel silicides.

[0249] S840, depositing a capping layer on a nickel-platinum alloy layer;

[0250] For example, the capping layer is made of titanium nitride (TiN) and is approximately 50 angstroms (5 nanometers) thick; its function is as follows:

[0251] To prevent nickel from being oxidized during subsequent heat treatment.

[0252] As a diffusion barrier layer, it restricts the excessive diffusion of metal atoms (especially nickel) into silicon or the upper dielectric.

[0253] It helps maintain the stress state of the thin film and improves its thermal stability.

[0254] It provides a relatively inert surface, which facilitates subsequent processing.

[0255] S850, First Rapid Thermal Annealing (First RTP) is performed to form high-resistivity metal silicide;

[0256] For example, the first rapid thermal annealing conditions are: 290°C for 30 seconds;

[0257] At this lower temperature, the nickel-platinum alloy (NiPt) begins to react with the underlying silicon (Si) in a solid state, forming a nickel-rich silicide Ni2PtSi (Ni-rich phAse, N2P). Ni2PtSi has a high resistivity, so a second rapid thermal annealing is required.

[0258] S860, second rapid thermal annealing (RTP), forms a low-resistance metal silicide layer, which connects the gate of the pull-up transistor to the active region of the transfer transistor in the memory node with low resistance.

[0259] The nickel-rich silicide Ni2PtSi formed in the previous step is converted into the silicon-rich NiPtSi2 (Si-rich phAse).

[0260] For example, the thickness of the formed NiPtSi2 is about 200 angstroms (20 nanometers), which is a typical target thickness. The actual thickness depends on the initial metal thickness and reaction conditions, and can generally vary between 100 and 300 Å.

[0261] The silicon-rich phase NiPtSi2 is the final desired low resistivity phase (C54 crystal structure), which has good thermal stability and contact properties.

[0262] The temperature (typically in the range of 650°C - 850°C, depending on the process node, material system, and design goals) and time control of the second rapid thermal annealing are crucial. Too low a temperature will prevent the phase transition from completing, while too high a temperature may lead to excessive silicide growth or increased junction depth.

[0263] S870, selective removal of residual nickel-platinum alloy (NiPt), capping layer, and barrier layer that did not participate in the silicide reaction, completes the preparation of metal silicide, yielding metal silicide layer 220, such as... Figure 28 As shown.

[0264] Wet chemical etching is used to remove residual nickel-platinum alloy (NiPt), capping layer and barrier layer, typically using mixed acid solutions (such as SPM / HPM, or specific formulations based on HNO3 / HCl / HF, also known as Selective NickelEtch).

[0265] The NiPt alloy, TiN capping layer, and barrier layer are etched away in a specific etching solution, while the NiPtSi silicide already formed on the silicon surface is removed. 2 The exposed dielectric layers, such as silicon dioxide (SiO2) or silicon nitride (SiN), have high corrosion resistance.

[0266] In S900, a metal interconnect layer 300 is fabricated using a metal interconnect process. The left memory node SNL is connected to the drain of the second pull-down transistor 206 and the drain of the second pull-up transistor 204 through the metal line 310 of the metal interconnect layer 300. The right memory node SNR is connected to the drain of the first pull-down transistor 205 and the drain of the first pull-up transistor 203 through the metal line 310 of the metal interconnect layer 300. The complete connection of the SRAM memory cell 200 is achieved through the metal interconnect layer 300. The present invention minimizes the connection of the metal interconnect layer 300 through the above design, thereby reducing the heat generation of the entire device and improving the device's operational stability and electrical performance.

[0267] In addition, it is necessary to bring out the six transistors through metal interconnection technology, which can be achieved using existing technology and has no impact on the technical implementation of this invention. Therefore, this invention will not describe it in detail.

[0268] The specific steps in S900 are as follows:

[0269] S910, A barrier layer 301 of a certain thickness is deposited using CVD technology, such as... Figure 29 As shown, the material of the barrier layer 301 can be SiN, and the thickness can be selected in the range of 200~330 angstroms.

[0270] S920, interlayer dielectric layer 320 (ILD), deposition is performed in multiple stages, and an exemplary process is as follows:

[0271] Step 1: Using HARP (High Aspect Ratio Process) technology, deposit a certain thickness of TEOS (Tetraethylorthosilicate)-based silicon dioxide (SiO2) to obtain the first ILD film 321. The thickness can be selected as needed, and can be in the range of 200-2000 angstroms. An example selection is 1100 angstroms.

[0272] HARP (High Aspect Ratio Process) has excellent gap-filling ability; HARP TEOS (typically O3-based sub-atmospheric pressure chemical vapor deposition, SA-CVD) is specifically designed to fill narrow and deep high aspect ratio structures, effectively filling gaps without creating voids or seams.

[0273] The HARP process exhibits conformality, providing excellent step coverage.

[0274] The HARP process can perform substrate coverage, serving as the base layer of the ILD, covering and electrically isolating the underlying active devices and wiring structures (including the NiPtSi silicide formed above).

[0275] Step 2: Deposit PE TEOS (Plasma Enhanced TEOS) as a thicker second ILD film 322 using CD CVD (Chemical Deposition Chemical Vapor Deposition) technology, with a thickness of 2000 angstroms-4000 angstroms, for example, 3600 angstroms.

[0276] CD CVD technology enables high-speed deposition, with a deposition rate significantly higher than that of HARP (SA-CVD) technology, making it suitable for rapidly constructing thick dielectric layers.

[0277] CD CVD process has better density; PE TEOS is denser than O3-based SA-CVD TEOS.

[0278] The ILD film deposited by the CD CVD process is the basis for planarization. This thicker PE TEOS layer is the host layer that provides the main material for subsequent chemical mechanical polishing (CMP) planarization.

[0279] Step 3: Grind the ILD flat using chemical mechanical polishing (CMP);

[0280] By utilizing the synergistic effect of chemical etching and mechanical polishing, the raised areas on the wafer surface are ground away, ultimately resulting in a very flat surface, creating conditions for photolithography.

[0281] Step 4: Deposit a capping layer 323 on the planarized ILD surface to obtain an interlayer dielectric layer 320, such as... Figure 30 As shown;

[0282] TEOS SiO2 was deposited using PECVD TEOS; the thickness was approximately 600 angstroms (60 nanometers), typically 400-800 angstroms.

[0283] Protect the newly planarized, clean ILD surface from contamination or minor scratches that may result from subsequent processes (such as storage and transportation).

[0284] S930, etched contact hole 330 (contact)

[0285] First, photoresist is applied, and the position of contact hole 330 is defined by exposure and development.

[0286] Then, a dry etching process is used to open the contact hole 330, such as... Figure 31 As shown;

[0287] S940, filler contact hole 330;

[0288] The residual material from etching the CT hole (contact) is cleaned by using a wet cleaning process, and then a titanium metal layer and a titanium nitride metal layer are deposited sequentially as a contact barrier layer 331;

[0289] The titanium metal layer serves as an adhesion / contact layer, increasing the adhesion of the titanium nitride metal layer, preventing peeling, and reducing contact resistance; the thickness is 80-120 angstroms, with 100 angstroms being an example.

[0290] The titanium nitride metal layer serves as a diffusion barrier layer 301 / adhesion layer. TiN exhibits excellent adhesion to tungsten (W), which is beneficial for the nucleation and deposition of metallic W. At the same time, it avoids the formation of defects by the reaction of WF6 with Ti during the W deposition process. The thickness of the titanium nitride metal layer is 30-70 angstroms, with 50 angstroms being an example.

[0291] Continue depositing a black metal layer as a metal bonding layer 332. The black metal layer needs to fill the entire contact hole 330.

[0292] The contact hole 330 lead was fabricated using CMP planarization. Figure 32 As shown.

[0293] S950. The metal layer is fabricated to obtain the metal interconnect layer 300. The metal interconnect process is specifically used in the prior art, which has no impact on the technical problem solved by the present invention, and will not be described in detail here.

[0294] This invention creatively isolates the active region using an isolation structure, then etches the area containing the second type of active region using an etching process. Next, an ion implantation process forms the well regions of the first and second types of active regions. Then, an etching process forms the bare gate, which is stepped up by two etching operations during formation, ensuring the bare gate at the memory node is at the same height as the active region of the transfer gate transistor. This provides the foundation for connecting the gate of the pull-up transistor and the active region of the transfer gate transistor via metal silicide. Afterwards, sidewalls are fabricated and the memory node region is metal silicided, followed by source and drain fabrication. Finally, a metal interconnect layer is prepared to complete the SRAM device fabrication. The unexpected effect is that this invention completes the fabrication of the aforementioned special structure SRAM device using a simple and mature process. Furthermore, during fabrication, the metal silicide technology reduces the connection resistance between the gate of the pull-up transistor and the active region of the transfer gate transistor, enabling the memory node to efficiently and stably store and read / write data while maintaining relatively low thermal resistance, achieving a significant technical effect.

[0295] The above embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Although the invention has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications, or equivalent substitutions of the technical solutions of the invention do not depart from the spirit and scope of the invention and should be covered within the scope of the claims of the invention.

Claims

1. A method for fabricating an SRAM device, the SRAM device comprising a semiconductor substrate and a plurality of SRAM memory cells formed on the semiconductor substrate, wherein the SRAM memory cells comprise at least 6 transistors, the 6 transistors being two transfer gate transistors, two pull-up transistors and two pull-down transistors respectively, the gate of the pull-up transistors and the drain of the transfer gate transistors being connected to form a memory node; Two transmission gate transistors and two pull-down transistors have a first type of active region, which is configured in a first direction; two pull-up transistors have a second type of active region, which is configured in a second direction and is recessed, wherein the first direction and the second direction are two directions with optimal carrier migration rates selected according to the wafer orientation; characterized in that... The preparation method includes the following steps: Provide semiconductor substrates; The active region of each transistor is isolated by an isolation structure; The area where the two pull-up transistors are located is etched using an etching process to create a recessed groove. Ion implantation technology is used to implant the corresponding type of ions into the active region of each transistor to form the trap region of the first type of active region and the second type of active region. The bare gate of each transistor is fabricated, and the bare gate of the pull-up transistor is stepped through an etching process so that the height of the bare gate at the memory node is the same as that of the active region of the transfer gate transistor. Sidewalls are fabricated on the bare gate to obtain the gate; Fabrication of source and drain electrodes; The active region and the top surface of the gate at the memory node are metallized to obtain a metallization layer; A metal interconnect layer is fabricated, and six transistors are connected to form an SRAM memory cell.

2. The method of claim 1, wherein the SRAM device is formed by: The two pull-up transistors share a common source setting, and the two transfer gate transistors share the same gate line.

3. The method of claim 2, wherein the SRAM device is formed by: The pull-up transistor and the pull-down transistor have the same gate width, and the gate width of the transmission gate transistor is greater than the gate width of the pull-up transistor.

4. The method of claim 1, wherein the SRAM device is formed by: The active region widths of the pull-down transistor, the transmission gate transistor, and the pull-up transistor decrease sequentially.

5. The method of claim 1, wherein the SRAM device is formed by: Two transmission gate transistors and two pull-down transistors are arranged in an array to form a quadrilateral region, and two pull-up transistors are disposed within the quadrilateral region.

6. The method for fabricating the SRAM device according to claim 1, characterized in that, The subsidence of the second type of active region is not less than the channel depth of the first type of active region.

7. The method for fabricating the SRAM device according to claim 1, characterized in that, The isolation structure adopts a vertical sidewall isolation structure.

8. The method for fabricating the SRAM device according to claim 1, characterized in that, When forming the recessed groove, the active regions of the two pull-up transistors and their surrounding isolation structure are recessed together.

9. The method for fabricating the SRAM device according to claim 1, characterized in that, Fabricating the bare gate of each transistor and stepping the bare gate of the pull-up transistor using an etching process, so that the bare gate at the memory node has the same height as the active region of the transfer gate transistor, includes the following steps: Photoresist is coated and exposure and development techniques are used to obtain a photoresist pattern that forms the gate shape; Etch the gate material outside the photoresist cover; Photoresist is applied again, and exposure and development techniques are used to obtain a photoresist pattern that exposes the memory node area; The gate material in the memory node region is etched so that the height of the gate material layer at the memory node is the same as the height of the first type of active region.

10. The method for fabricating the SRAM device according to claim 1, characterized in that, The active region and the top surface of the gate at the memory node are silicided to obtain a metal silicide layer, including the following steps: Pre-cleaning involves etching away part of the silicon layer at the top of the active region and the gate. A nickel-platinum alloy layer is deposited on the pre-cleaned silicon layer surface; Deposit a capping layer on a nickel-platinum alloy layer; The first rapid thermal annealing is performed to form a high-resistivity metal silicide; A second rapid thermal annealing process is performed to form a low-resistivity metal silicide layer.

11. The method for fabricating the SRAM device according to claim 1, characterized in that, During the fabrication of the metal interconnect layer, the left memory node SNL is connected to the drain of the second pull-up transistor and the drain of the second pull-down transistor via metal lines, and the right memory node SNR is connected to the drain of the first pull-up transistor and the drain of the first pull-down transistor via metal lines.

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