Formation method of semiconductor structure and deposition equipment

Abstract

The invention discloses a forming method of a semiconductor structure and deposition equipment. The forming method comprises the following steps: providing a substrate; deposition treatment is carried out on the substrate to form a grid layer, and the deposition treatment comprises the steps of carrying out multiple times of pre-deposition treatment, and forming a seed crystal layer on the substrate; and after multiple pre-deposition treatments are completed, a polycrystalline layer is formed on the seed crystal layer through main deposition treatments by taking the seed crystal layer as a growth basis. According to the embodiment of the invention, the seed crystal layer is formed through multiple times of pre-deposition treatment, so that the number of crystal grains in the seed crystal layer is relatively large, the coverage area of the seed crystal layer is relatively large, and the distance between adjacent crystal grains in the seed crystal layer is relatively small correspondingly, so that in the step of main deposition treatment, the thickness of the seed crystal layer is relatively small; when the polycrystalline layer is grown on the template with the crystal grains in the crystal seed layer as the growth basis, the crystal grains of the formed polycrystalline layer are small, the probability of forming holes in the polycrystalline layer is correspondingly reduced, the quality of the gate layer is further improved, and the performance of the semiconductor structure is correspondingly improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure and a deposition device. Background Art

[0002] At present, Flash memory, also known as flash memory, has become the mainstream of non-volatile memory (NVM). According to different structures, flash memory can be divided into two types: NOR Flash and NAND Flash. The main feature of flash memory is that it can keep the stored information for a long time without power supply, and it has the advantages of high integration, fast access speed, easy erasure and rewriting, so it has been widely used in many fields such as microcomputers and automation control.

[0003] Compared with NAND Flash, although NOR Flash has relatively slow erase and write speeds, its read speed is very fast, so it is widely used in automotive electronics, camera optical compensation, Bluetooth headsets and other fields.

[0004] However, the performance of NOR Flash still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure and a deposition device to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; performing a deposition process on the substrate to form a gate layer, the deposition process comprising: performing multiple pre-deposition processes to form a seed layer on the substrate; after completing the multiple pre-deposition processes, using the seed layer as a growth basis, forming a polycrystalline layer on the seed layer through a main deposition process.

[0007] Optionally, the pre-deposition treatment step includes: vacuuming the reaction chamber; after the vacuuming treatment, introducing a purge gas into the reaction chamber to perform a purge treatment, and making the gas flow value of the purge gas reach a stable state; after completing the purge treatment, introducing a pre-deposition reaction gas into the reaction chamber, and making the gas flow value of the pre-deposition reaction gas reach a stable state to form a seed layer on the substrate; the main deposition treatment step includes: introducing a main deposition reaction gas into the reaction chamber to form the polycrystalline layer with the seed layer as the growth basis.

[0008] Optionally, during the process of introducing the pre-deposition reaction gas into the reaction chamber, the first carrier gas is also introduced into the reaction chamber; during the process of introducing the main deposition reaction gas into the reaction chamber, the second carrier gas is also introduced into the reaction chamber.

[0009] Optionally, the first carrier gas includes an inert gas or nitrogen; the second carrier gas includes an inert gas or nitrogen.

[0010] Optionally, the purge gas includes an inert gas or nitrogen.

[0011] Optionally, the material of the gate layer includes polysilicon; the pre-deposition reaction gas includes one or more of SiH4, Si2H6, Si2Cl6 and SiH2Cl2; and the main deposition reaction gas includes one or more of SiH4, Si2H6, Si2Cl6 and SiH2Cl2.

[0012] Optionally, the pre-deposition reaction gas is the same as the main deposition reaction gas.

[0013] Optionally, the step of introducing pre-deposition reaction gas into the reaction chamber includes: opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller in sequence to introduce the pre-deposition reaction gas into the reaction chamber; after the gas flow of the pre-deposition reaction gas reaches a stable state, closing the pre-valve of the flow controller and the flow controller.

[0014] Optionally, the steps of sequentially opening the pre-valve of a flow controller for supplying reaction gas and the flow controller include: opening the pre-valve of the flow controller and keeping the flow controller in a closed state until the pre-deposition reaction gas reaches a stable state; after the pre-deposition reaction gas reaches a stable state, opening the flow controller.

[0015] Optionally, in the pre-deposition treatment step, the time for introducing the pre-deposition reaction gas into the reaction chamber is equal to the time required for the gas flow value of the pre-deposition reaction gas to reach a target value from an initial value.

[0016] Optionally, in the step of the pre-deposition treatment, the gas flow rate range of the pre-deposition reaction gas is 70 standard ml / min to 150 standard ml / min; the temperature of the pre-deposition treatment is 580 degrees Celsius to 620 degrees Celsius; the reaction pressure of the pre-deposition treatment is 0.1 mTorr to 0.4 mTorr; in the step of the main deposition treatment, the gas flow rate range of the main deposition reaction gas is 70 standard ml / min to 150 standard ml / min; the temperature of the main deposition treatment is 580 degrees Celsius to 620 degrees Celsius; the reaction pressure of the main deposition treatment is 0.1 mTorr to 0.4 mTorr.

[0017] Optionally, the target value of the gas flow rate of the pre-deposition reaction gas is greater than the target value of the gas flow rate of the main deposition reaction gas; the temperature of the pre-deposition process is greater than the temperature of the main deposition process; the reaction pressure of the pre-deposition process is greater than the reaction pressure of the main deposition process; the acceleration of the gas flow rate of the pre-deposition reaction gas from an initial value to a target value is a first acceleration; the acceleration of the gas flow rate of the main deposition reaction gas from an initial value to a target value is a second acceleration, and the second acceleration is less than the first acceleration.

[0018] Optionally, during the pre-deposition treatment, the pre-deposition reaction gas is introduced into the reaction chamber by opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller; after completing the last pre-deposition treatment, the pre-valve of the flow controller for supplying the reaction gas and the flow controller are kept open, and the main deposition treatment is performed successively.

[0019] Optionally, the pre-deposition treatment is performed 5 to 20 times.

[0020] Optionally, after completing multiple pre-deposition processes, the total thickness of the seed layer along the normal direction of the top surface of the substrate is 5 angstroms to 20 angstroms.

[0021] Optionally, the deposition process includes a low pressure chemical vapor deposition process.

[0022] Optionally, in the step of providing a substrate, the substrate includes a storage area, and a groove is formed in the substrate of the storage area; a first deposition process is performed on the substrate of the storage area to form a gate layer, and the gate layer is used as a floating gate material layer, and the floating gate material layer is located in the substrate of the storage area and the groove, wherein in the step of forming a seed layer on the substrate in the first deposition process, the seed layer covers the inner wall of the groove and the substrate outside the groove, and in the step of forming a polycrystalline layer on the substrate, the polycrystalline layer covers the seed layer and fills the groove; after the first deposition process is performed on the substrate of the storage area, it also includes: patterning the floating gate material layer to form a floating gate on the substrate of the storage area; forming an inter-gate dielectric layer on the floating gate; forming a control gate on the inter-gate dielectric layer; the step of forming a control gate on the inter-gate dielectric layer includes: performing a second deposition process to form another gate layer on the inter-gate dielectric layer to serve as a control gate material layer; patterning the control gate material layer to form a control gate located above the floating gate in the storage area.

[0023] Optionally, in the step of providing the substrate, the substrate further includes a logic area; and in the step of forming a control gate located above the floating gate in the storage area, a logic area gate is also formed on the substrate of the logic area.

[0024] Optionally, in the deposition treatment step, reaction gas is introduced into the reaction chamber through multiple gas passages, the ends of the multiple gas passages are directed toward the substrate and are located at different heights of the reaction chamber, and the height values ​​of the ends of the respective gas passages are an arithmetic progression.

[0025] Correspondingly, an embodiment of the present invention also provides a deposition device for executing the formation method described in the embodiment of the present invention to perform deposition processing on a substrate, including: a reaction chamber; a plurality of gas injectors located in the reaction chamber, the gas injectors being used to introduce reaction gas into the interior of the reaction chamber, the plurality of gas injectors being separately arranged, and the outlet ends of the plurality of gas injectors being located at different height positions in the reaction chamber.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a deposition process is performed on the substrate to form a gate layer, and the deposition process step includes: performing multiple pre-deposition processes to form a seed layer on the substrate, and after completing the multiple pre-deposition processes, using the seed layer as a growth basis, a polycrystalline layer is formed on the substrate through a main deposition process. Since the seed layer is formed through multiple pre-deposition processes, the number of grains in the seed layer is large, and the area covered by the seed layer is large, and accordingly, the distance between adjacent grains in the seed layer is small, so that in the step of the main deposition process, when the polycrystalline layer is grown using the grains in the seed layer as a template for the growth basis, the grains of the formed polycrystalline layer are also small, which correspondingly reduces the probability of forming holes in the polycrystalline layer, thereby improving the quality of the gate layer, and correspondingly improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 6 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0029] Figure 7 A comparison diagram of the distribution of failed core particles in the CP test after one pre-deposition treatment and after multiple pre-deposition treatments;

[0030] Figure 8 The distribution of gas injectors of a deposition device in a reaction chamber. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, NOR Flash has a very fast reading speed, and is therefore widely used in automotive electronics, camera optical compensation, Bluetooth headsets, and other fields. Moreover, for NOR Flash, more parallel structures can enable it to read data more quickly and randomly. However, at present, the performance of NOR Flash is limited by the quality of its gate layer formation and cannot be further improved.

[0032] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; performing a deposition process on the substrate to form a gate layer, the deposition process comprising: performing multiple pre-deposition processes to form a seed layer on the substrate; after completing the multiple pre-deposition processes, using the seed layer as a growth basis, forming a polycrystalline layer on the seed layer through a main deposition process.

[0033] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a deposition process is performed on the substrate to form a gate layer, and the deposition process step includes: performing multiple pre-deposition processes to form a seed layer on the substrate, and after completing the multiple pre-deposition processes, using the seed layer as a growth basis, a polycrystalline layer is formed on the substrate through a main deposition process. Since the seed layer is formed through multiple pre-deposition processes, the number of grains in the seed layer is large, and the area covered by the seed layer is large, and accordingly, the distance between adjacent grains in the seed layer is small, so that in the step of the main deposition process, when the polycrystalline layer is grown using the grains in the seed layer as a template for the growth basis, the grains of the formed polycrystalline layer are also small, which correspondingly reduces the probability of forming holes in the polycrystalline layer, thereby improving the quality of the gate layer, and correspondingly improving the performance of the semiconductor structure.

[0034] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0036] Figure 7 This is a situation where the crystal grains cover the substrate after the pre-deposition process.

[0037] refer to Figure 1 , providing a substrate 100.

[0038] The substrate 100 provides a process operation basis for the formation process of a semiconductor structure, wherein the semiconductor structure includes a planar transistor or a three-dimensional transistor (eg, a fin field effect transistor).

[0039] In this embodiment, the semiconductor structure is a planar transistor as an example, that is, the channel is a planar channel. In other embodiments, the semiconductor structure is a fin field effect transistor, and the channel is a fin.

[0040] In this embodiment, the base 100 includes a substrate 101 .

[0041] It should be noted that the substrate 101 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0042] In this embodiment, in the step of providing the substrate 100 , the substrate 100 includes a storage area i, and a groove 105 is formed in the substrate of the storage area i.

[0043] The storage area i is used to form a storage device.

[0044] In this embodiment, the storage area i is used to form a Flash memory as an example. Flash memory belongs to a non-volatile storage device. As an example, the storage area i is used to form a Nor Flash memory.

[0045] The trench 105 is used to provide a space for the subsequent formation of a gate layer.

[0046] In this embodiment, the base 100 further includes an initial isolation structure 115 located in the substrate 101 , and the isolation structure 115 and the substrate 101 form the trench 105 .

[0047] The initial isolation structure 115 is used to provide a process basis for subsequently forming an isolation structure.

[0048] In this embodiment, in the step of providing the substrate 100 , the substrate 100 includes a channel region (not labeled) and an isolation region (not labeled) located between adjacent channel regions, and an initial isolation structure 115 is formed in the substrate 101 of the isolation region.

[0049] The channel region is used to form a memory device. The isolation region is used to form an initial isolation structure 115.

[0050] Specifically, the material of the initial isolation structure 115 is an insulating material. As an example, the material of the initial isolation structure 115 is silicon oxide.

[0051] It should be noted that the steps of forming the initial isolation structure 115 include: forming a patterned layer (not shown) on the substrate 101, the patterned layer exposing the top surface of the substrate 101 in the isolation area; using the patterned layer as a mask, patterning the substrate 101, and forming an isolation groove in the substrate 101 (not shown); forming an isolation material layer (not shown) filling the isolation groove and covering the patterned layer; planarizing the isolation material layer, removing the isolation material layer higher than the patterned layer, and retaining the isolation material layer located in the isolation groove as the initial isolation structure 115.

[0052] It should be further explained that after forming the initial isolation structure 115 , the formation method further includes: removing the patterned layer.

[0053] Therefore, in this embodiment, the top of the initial isolation structure 115 is higher than the top of the substrate 101 .

[0054] In this embodiment, in the step of providing the substrate 100 , a tunneling oxide layer (TOX) 120 is formed on the substrate 101 of the storage area i.

[0055] Specifically, a tunneling oxide layer 120 is formed on the substrate 100 of the storage region i between adjacent initial isolation structures 115 .

[0056] The tunneling oxide layer 120 is used to isolate the floating gate formed subsequently from the substrate 100 . The tunneling oxide layer 120 is also used to provide a tunneling channel for electrons from the substrate 100 to the floating gate.

[0057] As an example, the material of the tunnel oxide layer 120 is silicon oxide.

[0058] In this embodiment, in the step of providing the substrate 100, the substrate 100 further includes a logic area ii.

[0059] The logic area ii is used to form a logic device.

[0060] Correspondingly, in this embodiment, an initial isolation structure 115 is also formed in the substrate 101 of the logic area ii.

[0061] Correspondingly, in this embodiment, a tunneling oxide layer 120 is also formed on the substrate 100 of the logic region ii.

[0062] refer to Figure 2 , a deposition process is performed on the substrate 100 to form a gate layer 130, and the deposition process includes: performing multiple pre-deposition processes to form a seed layer 131 on the substrate 100; after completing the multiple pre-deposition processes, using the seed layer 131 as a growth basis, through a main deposition process, a polycrystalline layer 132 is formed on the seed layer 131.

[0063] Since the seed layer 131 is formed through multiple pre-deposition treatments, the seed layer 131 has a larger number of grains and a larger area covered by the seed layer 131. Accordingly, in the seed layer 131, the distance between adjacent grains is smaller. As a result, in the main deposition step, when the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth, the grains of the formed polycrystalline layer 132 are also smaller, which reduces the probability of forming holes in the polycrystalline layer 132, thereby improving the quality of the gate layer 130 and the performance of the semiconductor structure.

[0064] For example, combined with reference Figure 7 , Figure 7 A comparison chart of the distribution of failed cores in a CP (Chip Probing) test corresponding to a single pre-deposition process and multiple pre-deposition processes. Figure 7 (a) is the distribution diagram of failed core particles in CP test after one pre-deposition treatment; Figure 7 (b) is the distribution diagram of CP failed core particles obtained after three pre-deposition treatments; the gray part is the part with normal yield, and the black part is the part with yield loss.

[0065] It can be seen that after multiple pre-deposition treatments, the yield damage of the wafer is reduced, that is, the yield is improved.

[0066] It can be understood that the seed layer 131 is formed through multiple pre-deposition processes, and the polycrystalline layer 132 is formed through main deposition processes. The polycrystalline layer 132 and the seed layer 131 constitute the gate layer 130, and both the seed layer 131 and the polycrystalline layer 132 are polycrystalline structures.

[0067] In this embodiment, the material of the gate layer 130 includes polysilicon.

[0068] Silicon is a commonly used material in the semiconductor manufacturing field and is relatively easy to obtain. In addition, polysilicon has a wide temperature tolerance range, which is conducive to the semiconductor manufacturing process.

[0069] In this embodiment, the steps of the pre-deposition treatment include: vacuuming the reaction chamber; after the vacuuming treatment, introducing a purge gas into the reaction chamber to perform a purge treatment, and making the gas flow value of the purge gas reach a stable state; after the purge treatment is completed, introducing a pre-deposition reaction gas into the reaction chamber, and making the gas flow value of the pre-deposition reaction gas reach a stable state to form a seed layer on the substrate.

[0070] The reaction chamber is evacuated to achieve the pressure requirement of the deposition reaction.

[0071] Before the pre-deposition reaction, a purge gas is introduced into the reaction chamber to perform a purge process to remove residual gas in the reaction chamber, which is beneficial to reducing the influence of the residual gas on the pre-deposition reaction. In addition, the purge process is completed when the gas flow value of the purge gas reaches a stable state.

[0072] The purging process is completed only after the gas flow value of the purging gas reaches a stable state. This is beneficial to reducing the probability of the gas in the reaction chamber transforming from a laminar state to a turbulent state when the pre-deposition reaction gas is subsequently introduced, thereby facilitating a more uniform distribution of the pre-deposition reaction gas and reducing the probability of defect enrichment in the seed layer 131.

[0073] It should be noted that when the gas flow value reaches the target value, the gas flow value reaches a stable state. Therefore, the gas flow value of the purge gas reaches a stable state, which means that the gas flow value of the purge gas reaches the target value.

[0074] Specifically, the purge gas includes an inert gas.

[0075] Inert gas has low reactivity and is not easy to react chemically with other substances. The purge gas includes inert gas, which is conducive to reducing the influence of purge gas on pre-deposition reaction. As an example, the purge gas includes helium. In other embodiments, the purge gas may also include nitrogen.

[0076] The pre-deposition reaction gas is a precursor gas required for a pre-deposition reaction, and the seed layer 131 is formed on the substrate 100 by causing the precursor gas to undergo a chemical reaction.

[0077] A pre-deposition reaction gas is introduced into the reaction chamber and the gas flow rate of the pre-deposition reaction gas reaches a stable state, so that the acceleration of the gas flow rate of the pre-deposition reaction gas from the initial value to the target value is utilized, and the pre-deposition reaction gas is diffused in the reaction chamber, so that the grains in the seed layer 131 can be formed more evenly on the surface of the substrate 100, and the seed layer 131 has a larger number of grains.

[0078] In this embodiment, the step of introducing the pre-deposition reaction gas into the reaction chamber includes: opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller in sequence to introduce the pre-deposition reaction gas into the reaction chamber; after the gas flow of the pre-deposition reaction gas reaches a stable state (that is, the pre-deposition reaction gas reaches the target value), closing the pre-valve of the flow controller and the flow controller.

[0079] Here, sequentially opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller means opening the pre-valve of the flow controller for supplying the reaction gas and then opening the flow controller.

[0080] After opening the pre-valve of the flow controller for supplying the reaction gas, the flow controller is then opened to introduce the pre-deposition reaction gas into the reaction chamber. This is beneficial for the pre-deposition reaction gas in the reaction chamber to have a higher gas pressure, temperature, gas flow value and gas flow acceleration value at the moment after the flow controller is opened, thereby facilitating the uniform distribution of the pre-deposition reaction gas in the reaction chamber, further facilitating the uniform formation of the grains in the seed layer 131 on the surface of the substrate 100, and also facilitating further increasing the number of grains in the seed layer 131.

[0081] Specifically, the steps of sequentially opening the pre-valve of a flow controller for supplying reaction gas and the flow controller include: opening the pre-valve of the flow controller and keeping the flow controller in a closed state until the pre-deposition reaction gas reaches a stable state; after the pre-deposition reaction gas reaches a stable state, opening the flow controller.

[0082] Keeping the flow controller closed until the pre-deposition reaction gas reaches a stable state, and then opening the flow controller can easily reduce the probability of the gas in the reaction chamber transforming from a laminar state to a turbulent state, thereby further improving the uniformity of diffusion of the pre-deposition reaction gas in the reaction chamber, which is correspondingly beneficial for making the grains in the seed layer 131 more evenly formed on the surface of the substrate 100, and is also beneficial for reducing the probability of defect enrichment in the seed layer 131.

[0083] As an example, after the front valve of the flow controller is opened, the pre-deposition reaction gas reaches a stable state after 5 seconds or more.

[0084] In this embodiment, in the step of the pre-deposition treatment, the time for introducing the pre-deposition reaction gas into the reaction chamber is equal to the time required for the gas flow value of the pre-deposition reaction gas to reach the target value from the initial value.

[0085] The time for introducing the pre-deposition reaction gas into the reaction chamber is equal to the time required for the gas flow value of the pre-deposition reaction gas to reach the target value from the initial value, which is beneficial to fully utilizing the gas flow acceleration during the time period when the gas flow value of the pre-deposition reaction gas reaches the target value from the initial value, so that the pre-deposition reaction gas diffuses in the reaction chamber.

[0086] As an example, the initial value of the gas flow rate of the pre-deposition reaction gas is 0.

[0087] It should be noted that the time required for introducing the pre-deposition reaction gas into the reaction chamber until the gas flow rate of the pre-deposition reaction gas reaches a stable state should not be too short or too long. If the time required for introducing the pre-deposition reaction gas into the reaction chamber until the gas flow rate of the pre-deposition reaction gas reaches a stable state is too short, the reaction time of the pre-deposition reaction gas is too short, which may lead to poor quality and coverage of the seed layer 131 formed on the substrate 100; if the time required for introducing the pre-deposition reaction gas into the reaction chamber until the gas flow rate of the pre-deposition reaction gas reaches a stable state is too long, the reaction time of the pre-deposition reaction gas is too long, which may lead to large grains in the seed layer 131, and correspondingly, when the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth, the grains of the formed polycrystalline layer 132 are also large, which may lead to unsatisfactory effect of reducing the formation of holes in the polycrystalline layer 132. Therefore, in this embodiment, the time required for introducing the pre-deposition reaction gas into the reaction chamber until the gas flow of the pre-deposition reaction gas reaches a stable state is 15 seconds to 60 seconds.

[0088] In this embodiment, in the step of the pre-deposition treatment, the gas flow rate range of the pre-deposition reaction gas is 70 standard ml / min to 120 standard ml / min; the temperature of the pre-deposition treatment is 580 degrees Celsius to 620 degrees Celsius; and the reaction pressure of the pre-deposition treatment is 0.1 mTorr to 0.4 mTorr.

[0089] It should be noted that the gas flow rate of the pre-deposition reaction gas should not be too small or too large. If the gas flow rate of the pre-deposition reaction gas is too small, it is easy to make the acceleration of the gas flow value of the pre-deposition reaction gas from the initial value to the target value too small, so that the diffusion speed of the pre-deposition reaction gas in the reaction chamber is slow, and then the effect of improving the uniform formation of the grains in the seed layer 131 on the surface of the substrate 100 is not ideal. If the gas flow rate of the pre-deposition reaction gas is too large, it is easy to make the reaction speed of the pre-deposition reaction gas faster, which increases the difficulty of controlling the grain size in the seed layer 131, so that the grains are easy to be larger, and correspondingly, it is easy to make the polycrystalline layer 132 formed when the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth basis. Therefore, in this embodiment, the gas flow rate of the pre-deposition reaction gas ranges from 70 standard ml / min to 120 standard ml / min.

[0090] It should also be noted that the temperature of the pre-deposition treatment should not be too low or too high. If the temperature of the pre-deposition treatment is too low, an amorphous structure is easily formed, resulting in poor quality of the seed layer 131, and correspondingly, poor quality of the polycrystalline layer 132; if the temperature of the pre-deposition treatment is too high, the reaction speed of the pre-deposition reaction gas is easy to be fast, which increases the difficulty of controlling the grain size in the seed layer 131, and thus easily makes the grains larger. Therefore, in this embodiment, the temperature of the pre-deposition treatment is 580 degrees Celsius to 620 degrees Celsius.

[0091] It is also necessary to explain that the reaction pressure of the pre-deposition treatment should not be too small or too large. If the reaction pressure of the pre-deposition treatment is too small, it is easy for the reaction pressure of the pre-deposition treatment to be difficult to meet the process requirements, resulting in poor quality of the seed layer 131; if the reaction pressure of the pre-deposition treatment is too large, it is easy for the reaction speed of the pre-deposition reaction gas to be faster, increasing the difficulty of controlling the grain size in the seed layer 131, thereby easily making the grains in the seed layer 131 larger. Therefore, in this embodiment, the reaction pressure of the pre-deposition treatment is 0.1 mTorr to 0.4 mTorr.

[0092] In this embodiment, during the pre-deposition process, the pre-deposition reaction gas is introduced into the reaction chamber by opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller.

[0093] After the last pre-deposition process is completed, the front valve of the flow controller for supplying the reaction gas and the flow controller are kept in an open state, and the main deposition process is performed successively.

[0094] After completing the last pre-deposition treatment, the pre-valve of the flow controller used to supply the reaction gas during the pre-deposition treatment and the flow controller are kept in an open state, and the main deposition treatment is performed successively, that is, the steps of vacuuming and purging the reaction chamber are omitted, which is beneficial to reducing process steps, simplifying the process flow, and saving process costs.

[0095] In this embodiment, the material of the gate layer 130 includes polysilicon. Accordingly, the pre-deposition reaction gas includes silicon element. As an example, the pre-deposition reaction gas includes SiH4.

[0096] SiH4 has a high reaction temperature and is easy to form polysilicon, which is beneficial to improving the quality of the seed layer 131. In other embodiments, the pre-deposition reaction gas may also include Si2H6, Si2Cl6 and SiH2Cl2.

[0097] In this embodiment, during the process of introducing the pre-deposition reaction gas into the reaction chamber, the first carrier gas is also introduced into the reaction chamber.

[0098] In the process of introducing the pre-deposition reaction gas into the reaction chamber, the first carrier gas is also introduced into the reaction chamber, which is beneficial to forming a stable and uniform atmosphere of the pre-deposition reaction gas in the reaction chamber, and is also beneficial to making the surface of the substrate 100 fully and evenly contact with the surrounding pre-deposition reaction gas, thereby facilitating that the grains in the seed layer 131 can be formed more evenly on the surface of the substrate 100.

[0099] Moreover, in the process of introducing the pre-deposition reaction gas into the reaction chamber, the first carrier gas is also introduced into the reaction chamber, which is beneficial to adjust the distribution of the grains on the surface of the substrate 100, further improve the uniformity of the distribution of the grains in the seed layer 131 on the surface of the substrate 100, and can also blow away the excess reaction gas on the surface of the substrate 100, reducing the probability of forming larger grains.

[0100] Specifically, the first carrier gas includes an inert gas.

[0101] The inert gas has low reactivity and is not easy to react chemically with other substances. The first carrier gas includes the inert gas, which is beneficial to the influence on the pre-deposition reaction.

[0102] In a specific embodiment, the first carrier gas includes helium. Helium has a relatively small relative molecular weight, and is not easy to blow away the pre-deposition reaction gas. In addition, helium has a high thermal conductivity and a large diffusion coefficient, which is conducive to the pre-deposition reaction gas forming the grains in the seed layer 131 through chemical reaction, and it is easy to make the distribution of the grains in the seed layer 131 on the substrate 100 more uniform. In other embodiments, the first carrier gas may also include nitrogen.

[0103] In this embodiment, the first carrier gas and the purge gas are both helium.

[0104] The first carrier gas and the purge gas are both helium, which is not easy to introduce impurities that affect the maintenance cycle of the machine, nor is it easy to affect other properties of the product.

[0105] It should be noted that the number of pre-deposition treatments should not be too few or too many. If the number of pre-deposition treatments is too few, it is easy to increase the number of grains in the seed layer 131, and it is also easy to increase the coverage area of ​​the seed layer 131. The effect of reducing the distance between adjacent grains is not good, and it is easy to reduce the effect of forming holes in the polycrystalline layer 132. If the number of pre-deposition treatments is too many, it is easy to reduce the process efficiency. Therefore, in this embodiment, the number of pre-deposition treatments is 5 to 20 times.

[0106] It should also be noted that after completing multiple pre-deposition processes, the total thickness of the seed layer 131 along the normal direction of the top surface of the substrate should not be too small or too large. If the total thickness of the seed layer 131 is too small, it is easy to increase the coverage area of ​​the seed layer 131, and the effect of reducing the distance between adjacent grains is not good; if the total thickness of the seed layer 131 is too large, it is easy to cause too many pre-deposition processes, thereby reducing the process efficiency, or it is easy to cause the time of a single pre-deposition process to be too long, thereby reducing the effect of reducing the grains in the seed layer 131, and the effect of reducing the grains in the polycrystalline layer 132 is not good. Therefore, in this embodiment, after completing multiple pre-deposition processes, the total thickness of the seed layer 131 along the normal direction of the top surface of the substrate 100 is 5 angstroms to 20 angstroms.

[0107] In this embodiment, the main deposition process comprises: introducing a main deposition reaction gas into a reaction chamber to form the polycrystalline layer 132 based on the seed layer 131 .

[0108] The main deposition reaction gas is a precursor gas required for a main deposition reaction, and the polycrystalline layer 132 is formed on the seed layer 131 by causing a chemical reaction in the precursor gas.

[0109] In this embodiment, in the step of the main deposition treatment, the gas flow range of the main deposition reaction gas is 70 standard ml / min to 150 standard ml / min; the temperature of the main deposition treatment is 580 degrees Celsius to 620 degrees Celsius; and the reaction pressure of the main deposition treatment is 0.1 mTorr to 0.4 mTorr.

[0110] It should be noted that the gas flow rate of the main deposition reaction gas should not be too small or too large. If the gas flow rate of the main deposition reaction gas is too small, the main deposition reaction time is likely to be too long, affecting the process efficiency; if the gas flow rate of the main deposition reaction gas is too large, the reaction speed of the main deposition reaction gas is likely to be faster, increasing the difficulty of controlling the grain size in the polycrystalline layer 132, thereby easily making the effect of reducing the formation of holes in the polycrystalline layer 132 unsatisfactory. Therefore, in this embodiment, the gas flow rate of the main deposition reaction gas ranges from 70 standard ml / min to 150 standard ml / min.

[0111] It should also be noted that the temperature of the main deposition process should not be too low or too high. If the temperature of the main deposition process is too low, an amorphous structure is easily formed, resulting in poor quality of the polycrystalline layer 132; if the temperature of the main deposition process is too high, the reaction speed of the main deposition reaction gas is likely to be faster, increasing the difficulty of controlling the grain size in the polycrystalline layer 132, thereby easily making the effect of reducing the formation of holes in the polycrystalline layer 132 unsatisfactory. Therefore, in this embodiment, the temperature of the main deposition process is 580 degrees Celsius to 620 degrees Celsius.

[0112] It is also necessary to explain that the reaction pressure of the main deposition process should not be too small or too large. If the reaction pressure of the main deposition process is too small, it is easy for the reaction pressure of the main deposition process to be difficult to meet the process requirements, resulting in poor quality of the polycrystalline layer 132; if the reaction pressure of the main deposition process is too large, it is easy for the reaction speed of the main deposition reaction gas to be faster, increasing the difficulty of controlling the grain size in the polycrystalline layer 132, thereby easily making the effect of reducing the formation of holes in the polycrystalline layer 132 unsatisfactory. Therefore, in this embodiment, the reaction pressure of the main deposition process is 0.1 mTorr to 0.4 mTorr.

[0113] Accordingly, in this embodiment, the main deposition reaction gas includes silicon. As an example, the main deposition reaction gas includes SiH4.

[0114] The reason why the main deposition reaction gas includes SiH4 is similar to the reason why the pre-deposition reaction gas includes SiH4, which will not be described again. In other embodiments, the main deposition reaction gas may also include Si2H6, Si2Cl6 and SiH2Cl2.

[0115] In this embodiment, the pre-deposition reaction gas is the same as the main deposition reaction gas.

[0116] The pre-deposition reaction gas is the same as the main deposition reaction gas, which makes it easy to reduce the difference between the pre-deposition process and the main deposition process, thereby facilitating reducing the process complexity of the deposition process.

[0117] In this embodiment, during the process of introducing the main deposition reaction gas into the reaction chamber, the second carrier gas is also introduced into the reaction chamber.

[0118] In the process of introducing the main deposition reaction gas into the reaction chamber, a second carrier gas is also introduced into the reaction chamber, which is beneficial to forming a stable and uniform pre-deposition reaction gas atmosphere in the reaction chamber, and is convenient for uniformly forming the polycrystalline layer 132 on the surface of the seed layer 131, thereby helping to improve the quality of the polycrystalline layer 132 and further reduce the grain size of the polycrystalline layer 132.

[0119] Specifically, the second carrier gas includes an inert gas. The reason why the second carrier gas includes an inert gas is similar to the reason why the first carrier gas includes an inert gas, and will not be repeated again.

[0120] As an example, the second carrier gas includes helium; the reason why the second carrier gas includes helium is similar to the reason why the first carrier gas includes helium, and will not be repeated again; accordingly, the second carrier gas and the first carrier gas are both helium, and the first carrier gas and the second carrier gas are both helium, which is not easy to introduce impurities that affect the maintenance cycle of the machine, nor is it easy to affect other performances of the product. In other embodiments, the second carrier gas may also include nitrogen.

[0121] It should be noted that the target value of the gas flow rate of the pre-deposition reaction gas is greater than the target value of the gas flow rate of the main deposition reaction gas, so that the speed of the pre-deposition reaction is faster, and the grain size in the seed layer 131 can be further reduced, so that in the main deposition process, when the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth, the grain size in the polycrystalline layer 132 is further reduced. Therefore, in this embodiment, the target value of the gas flow rate of the pre-deposition reaction gas is greater than the target value of the gas flow rate of the main deposition reaction gas.

[0122] The temperature of the pre-deposition process is higher than the temperature of the main deposition process, so that the pre-deposition reaction speed is faster, and the grain size in the seed layer 131 can be further reduced, so that in the step of the main deposition process, when the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth, the grain size in the polycrystalline layer 132 is further reduced. Therefore, in this embodiment, the temperature of the pre-deposition process is higher than the temperature of the main deposition process.

[0123] It should also be noted that, since in the step of the main deposition process, the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth, the quality of the seed layer 131 is also better than that of the polycrystalline layer 132. The reaction pressure of the pre-deposition process is greater than the reaction pressure of the main deposition process, which facilitates the quality of the grains in the seed layer 131 to be better, so that in the step of the main deposition process, when the polycrystalline layer 132 is grown using the grains in the seed layer 131 as a template for growth, the quality of the polycrystalline layer 132 is also better. Therefore, in this embodiment, the reaction pressure of the pre-deposition process is greater than the reaction pressure of the main deposition process.

[0124] It is further necessary to explain that the acceleration of the gas flow rate of the pre-deposition reaction gas from the initial value to the target value is the first acceleration; the acceleration of the gas flow rate of the main deposition reaction gas from the initial value to the target gas value is the second acceleration, and the second acceleration is less than the first acceleration, that is, the first acceleration is larger, which is convenient for making the pre-deposition reaction gas diffuse better in the reaction chamber, so that the grains in the seed layer 131 can be more evenly formed on the surface of the substrate 100, and the seed layer 131 has a larger number of grains, which is conducive to further improving the quality of the seed layer 131. Therefore, in this embodiment, the second acceleration is less than the first acceleration.

[0125] In this embodiment, in the deposition process, reaction gas is introduced into the reaction chamber through multiple gas passages, the ends of the multiple gas passages are directed toward the substrate and are located at different heights of the reaction chamber, and the height values ​​of the ends of the respective gas passages are an arithmetic progression.

[0126] In the deposition process, reaction gas is introduced into the reaction chamber through multiple gas passages, and the ends of the multiple gas passages are located at different heights of the reaction chamber, so that when there are multiple wafers in the reaction chamber, the distribution of the reaction gas in the reaction chamber is more uniform, that is, the distribution of the reaction gas at the position of each wafer is more consistent, which is beneficial to improve the uniformity of the thickness of each gate layer 130 formed by the deposition process.

[0127] In this embodiment, along the arrangement direction of the multiple gas passages, the height values ​​of the ends of the multiple gas passages increase or decrease in sequence, which can easily reduce the degree of transformation of the gas from laminar flow to turbulent flow, thereby further improving the uniformity of the distribution of the reaction gas in the reaction chamber, and further making the thickness uniformity of each gate layer 130 formed by the deposition process better.

[0128] Specifically, the height values ​​of the ends of the gas passages are an arithmetic progression, that is, in the direction perpendicular to the bottom of the reaction chamber, there is a reaction gas outlet at the same interval, thereby ensuring a high uniformity of the deposition thickness at each height position and improving the uniformity of the thermal budget.

[0129] As an example, the deposition device is a furnace tube device. It should be noted that when the furnace tube device is used for deposition processing, the furnace tube device usually performs deposition processing on multiple wafers at the same time, that is, there are multiple wafers in the furnace tube, and the multiple wafers are located at different heights of the furnace tube device.

[0130] In this embodiment, the deposition process includes a low pressure chemical vapor deposition (LPCVD) process.

[0131] The low pressure chemical vapor deposition process has a high step coverage capability and a good filling capability. As an example, the low pressure chemical vapor deposition process includes a vertical furnace low pressure chemical vapor deposition process. The vertical furnace low pressure chemical vapor deposition process has a high process efficiency.

[0132] In this embodiment, a first deposition process is performed on the substrate 100 of the storage area i to form a gate layer 130, the gate layer 130 is used as a floating gate material layer, and the floating gate material layer is located in the substrate 100 of the storage area i and the groove 105, wherein in the first deposition process, in the step of forming a seed layer 131 on the substrate 100, the seed layer 131 covers the inner wall of the groove 105 and the substrate 100 outside the groove 105, and in the step of forming a polycrystalline layer 132 on the substrate 100, the polycrystalline layer 132 covers the seed layer 131 and fills the groove 105;

[0133] The floating gate material layer is used to provide a process basis for the subsequent formation of a floating gate.

[0134] The seed layer 131 covers the inner wall of the groove 105 (i.e., the side wall and bottom of the groove 105) and the substrate 100 outside the groove 105, so that the polycrystalline layer 132 can grow with the seed layer 131 as a template for growth; moreover, the seed layer 131 covers the inner wall of the groove 105, so that the polycrystalline layer 132 can fill the groove 105.

[0135] The polycrystalline layer 132 completely fills the groove, which helps to reduce the probability of forming holes in the polycrystalline layer 132, thereby improving the quality of the gate layer 130 and correspondingly improving the performance of the semiconductor structure.

[0136] It should be noted that, in the present embodiment, in the step of providing the substrate 100, the substrate 100 also includes a logic area ii. Accordingly, in the step of performing the first deposition process on the substrate 100 of the storage area i and forming the gate layer 130, the gate layer 130 is also formed on the substrate 100 of the logic area ii. Wherein, in the step of forming the seed layer 131 on the substrate 100 in the first deposition process, the seed layer 131 also covers the inner wall of the groove 105 of the logic area ii and the substrate 100 of the logic area ii outside the groove 105 of the logic area ii, and in the step of forming the polycrystalline layer 132 on the substrate 100, the polycrystalline layer 132 covers the seed layer 131 of the logic area ii and fills the groove 105 of the logic area ii.

[0137] refer to Figures 3 to 6 , and continue to refer to Figure 2 In this embodiment, after the first deposition process is performed on the substrate 100 of the storage area i, it also includes: patterning the floating gate material layer to form a floating gate 133 on the substrate 100 of the storage area i; forming an inter-gate dielectric layer 134 on the floating gate 133; and forming a control gate 135 on the inter-gate dielectric layer 134.

[0138] Among them, in order to clearly show the semiconductor structure, Figure 6 A shallow trench isolation structure is schematically shown in FIG.

[0139] The floating gate 133 is used as a unit structure for storing data in the memory device.

[0140] The control gate 135 is used to control the opening and closing of the transistor channel of the storage region i.

[0141] The inter-gate dielectric layer 134 is used to isolate the control gate 135 from the floating gate 133 .

[0142] The floating gate 133 , the inter-gate dielectric layer 134 , and the control gate 135 constitute a storage gate 136 .

[0143] It should be noted that after the first deposition process, before the floating gate material layer is patterned, the floating gate material layer of the storage area i and the logic area ii is planarized with the top of the initial isolation structure 115 as the stop position, and the floating gate material layer above the top of the initial isolation structure 115 (such as Figure 3 shown).

[0144] It should also be noted that the step of patterning the floating gate material layer includes: etching the initial isolation structure 115 of the storage area i, removing the initial isolation structure 115 above the top of the storage area i substrate 100, and the remaining floating gate material layer of the storage area i serves as the floating gate 133.

[0145] It should be further explained that the step of forming the inter-gate dielectric layer 134 includes: forming the inter-gate dielectric layer 134 on the floating gate 133; wherein the inter-gate dielectric layer 134 is also formed on the substrate 100 of the storage area i between adjacent floating gates 133, and on the floating gate material layer of the logic area ii remaining after the planarization process (such as Figure 4 shown).

[0146] In a specific embodiment, the inter-gate dielectric layer 134 is an oxide-nitride-oxide (ONO) stacked structure, including a first inter-gate dielectric layer (not labeled) covering the floating gate 133, a second inter-gate dielectric layer (not labeled) covering the first inter-gate dielectric layer, and a third inter-gate dielectric layer (not labeled) covering the second inter-gate dielectric layer. Accordingly, the material of the first inter-gate dielectric layer is silicon oxide, the material of the second inter-gate dielectric layer is silicon nitride, and the material of the third inter-gate dielectric layer is silicon oxide. The ONO structure has good corrosion resistance and compactness, can play a good role in protecting the floating gate 133, and the inter-gate dielectric layer 134 has a better effect of isolating the control gate 135 and the floating gate 133. In other embodiments, the inter-gate dielectric layer can also be a single-layer structure.

[0147] It is further necessary to explain that, before forming the control gate 135, the formation method also includes: removing the gate dielectric layer 134 of the logic area ii, the remaining floating gate material layer of the logic area ii, the tunneling oxide layer 120 of the logic area ii, and removing the initial isolation structure 115 above the top of the substrate 100 of the logic area ii, and the remaining initial isolation structure 115 of the logic area ii and the storage area i is used as a shallow trench isolation (STI) structure 116 for achieving isolation between different devices; after forming the shallow trench isolation structure 116, a gate dielectric layer 117 is formed on the substrate 100 of the logic area ii.

[0148] The gate dielectric layer 117 is used to isolate a gate and a channel to be formed subsequently.

[0149] The material of the gate dielectric layer 117 includes one or more of HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 .

[0150] As an example, the floating gate 133 and the control gate 135 are both made of polysilicon.

[0151] In this embodiment, the step of forming the control gate 135 on the inter-gate dielectric layer 134 includes: performing a second deposition process to form another gate layer 130 on the inter-gate dielectric layer 134 to serve as a control gate material layer (such as Figure 5 ); patterning the control gate material layer to form a control gate 135 (as shown) located above the floating gate 133 in the storage region i; Figure 6 shown).

[0152] A control gate material layer is first formed, and then the control gate material layer is patterned to form a control gate 135 located above the floating gate 133 in the storage region i, which is conducive to reducing the difficulty of forming the control gate 135 .

[0153] It should be noted that the step of forming the control gate material layer includes: in the process of forming another gate layer 130 on the gate dielectric layer 134, the other gate layer 130 also covers the top of the gate dielectric layer 117 and the top of the shallow trench isolation structure 116 of the logic area ii.

[0154] It should also be noted that in the step of forming the control gate 135 located above the floating gate 133 in the storage area i, a logic gate 137 is also formed on the substrate 100 in the logic area ii.

[0155] Generally, the memory device needs to be compatible with the embedded standard logic device. For an embedded semiconductor device, it is usually divided into a logic area ii and a storage area i. The logic area ii usually includes logic devices, and the storage area i includes memory devices.

[0156] The logic gate 137 is used to control the opening and closing of the transistor channel of the logic area ii.

[0157] In the step of forming the control gate 135 located above the floating gate 133 in the storage area i, a logic gate 137 is also formed on the substrate 100 in the logic area ii, which is beneficial to reduce process steps, simplify the process flow, and combine with the existing process.

[0158] As an example, the materials of the control gate 135 and the logic gate 137 both include polysilicon.

[0159] Continue to refer Figure 6 In this embodiment, after the storage area i gate 136 and the logic gate 137 are formed, the formation method further includes: forming a sidewall structure 140 on the sidewalls of the storage area i gate 136 and the sidewalls of the logic gate 137; after the sidewall structure 140 is formed, a pocket ion implantation region 150 and a source-drain doping region 151 are formed in the substrate 100 on both sides of the storage area i gate 136, and a pocket ion implantation region 150 and a source-drain doping region 151 are formed in the substrate 100 on both sides of the logic gate 137.

[0160] Correspondingly, the present invention also provides a deposition device. Figure 8 The distribution of gas injectors of a deposition device in a reaction chamber.

[0161] refer to Figure 8, and combined with reference Figures 1 to 7 The deposition device is used to execute the formation method described in the above-mentioned embodiment to perform deposition processing on a substrate, including: a reaction chamber 1; a plurality of gas injectors 2, which are located in the reaction chamber 1, and the gas injectors are used to introduce reaction gas into the reaction chamber 1, and the plurality of gas injectors are separately arranged, and the outlet ends of the plurality of gas injectors 2 face the substrate and are located at different height positions in the reaction chamber, and the height values ​​of each gas injector are an arithmetic progression.

[0162] A deposition process is performed in the reaction chamber 1; as an example, the deposition equipment is a furnace tube equipment.

[0163] It should be noted that when a furnace tube device is used for deposition processing, the furnace tube device usually performs deposition processing on multiple wafers at the same time, that is, there are multiple wafers in the furnace tube, and the multiple wafers are located at different heights of the furnace tube device.

[0164] The plurality of gas injectors 2 are separately arranged, and the outlet ends of the plurality of gas injectors 2 are oriented toward the substrate 100 , so as to form a seed layer 131 on the substrate during the deposition process.

[0165] The outlet ends of the multiple gas injectors 2 are directed toward the substrate and are located at different heights of the reaction chamber 1, so that when there are multiple wafers in the reaction chamber, it is beneficial to make the distribution of the reaction gas in the reaction chamber more uniform, that is, it is beneficial to make the distribution of the reaction gas at the position of each wafer in the reaction chamber more consistent, thereby facilitating the improvement of the uniformity of the thickness of each gate layer 130 formed by the deposition process.

[0166] In this embodiment, along the arrangement direction of the multiple gas passages, the height values ​​of each of the gas injectors increase or decrease in sequence, which can easily reduce the degree of transformation of the gas from laminar flow to turbulent flow, thereby further improving the uniformity of the distribution of the reaction gas in the reaction chamber, and further making the thickness uniformity of each gate layer 130 formed by the deposition process better.

[0167] Specifically, the height values ​​of each gas injector are an arithmetic progression, that is, in the direction perpendicular to the bottom of the furnace tube device, there is an outlet end of a gas injector at the same interval, thereby ensuring a high uniformity of the deposition thickness at each height position and improving the uniformity of the thermal budget.

[0168] In this embodiment, the deposition device further comprises a flow controller and a pre-valve of the flow controller. The flow controller and the pre-valve of the flow controller are used to supply the reaction gas.

[0169] Specifically, the pre-deposition reaction gas is introduced into the reaction chamber by opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller in sequence to introduce the pre-deposition reaction gas into the reaction chamber 1; after the gas flow of the pre-deposition reaction gas reaches a stable state, the pre-valve of the flow controller and the flow controller are closed.

[0170] Here, sequentially opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller means opening the pre-valve of the flow controller for supplying the reaction gas and then opening the flow controller.

[0171] After opening the pre-valve of the flow controller for supplying the reaction gas, the flow controller is then opened to introduce the pre-deposition reaction gas into the reaction chamber 1. This is beneficial for the pre-deposition reaction gas in the reaction chamber 1 to have a higher gas pressure, temperature, gas flow value and gas flow acceleration value at the moment after the flow controller is opened, thereby facilitating the uniform distribution of the pre-deposition reaction gas in the reaction chamber 1, further facilitating the uniform formation of the grains in the seed layer 131 on the surface of the substrate 100, and also facilitating further increasing the number of grains in the seed layer 131.

[0172] Specifically, the steps of sequentially opening the pre-valve of the flow controller for supplying the gas required for the deposition reaction and the flow controller include: opening the pre-valve of the flow controller for supplying the gas required for the deposition reaction, and keeping the flow controller in a closed state until the pre-deposition reaction gas reaches a stable state; after the pre-deposition reaction gas reaches a stable state, opening the flow controller.

[0173] Keeping the flow controller closed until the pre-deposition reaction gas reaches a stable state, and then opening the flow controller can easily make the pre-deposition reaction gas in the reaction chamber 1 have a higher gas pressure, temperature, gas flow value and gas flow acceleration value at the moment after the flow controller is opened, thereby further improving the uniformity of diffusion of the pre-deposition reaction gas in the reaction chamber 1.

[0174] As an example, after the front valve of the flow controller is opened, the pre-deposition reaction gas reaches a stable state after 5 seconds or more.

[0175] For the description of the method for forming the semiconductor structure, please refer to the detailed description of the aforementioned embodiment, which will not be repeated in this embodiment.

[0176] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include providing a substrate; Performing a deposition process on the substrate to form a gate layer, the deposition process comprising: performing multiple pre-deposition processes to form a seed layer on the substrate; After completing multiple pre-deposition processes, a polycrystalline layer is formed on the seed layer through a main deposition process with the seed layer as a growth basis.

2. The method for forming a semiconductor structure according to claim 1, wherein: The steps of the pre-deposition treatment include: Performing vacuum treatment on the reaction chamber; After the vacuuming process, a purge gas is introduced into the reaction chamber to perform a purge process, and a gas flow value of the purge gas reaches a stable state; After the purging process is completed, a pre-deposition reaction gas is introduced into the reaction chamber, and the gas flow rate of the pre-deposition reaction gas is made to reach a stable state, so as to form a seed layer on the substrate; The steps of the main deposition process include: A main deposition reaction gas is introduced into the reaction chamber to form the polycrystalline layer with the seed layer as a growth basis.

3. The method for forming a semiconductor structure according to claim 2, wherein: In the process of introducing the pre-deposition reaction gas into the reaction chamber, the first carrier gas is also introduced into the reaction chamber; During the process of introducing the main deposition reaction gas into the reaction chamber, the second carrier gas is also introduced into the reaction chamber.

4. The method for forming a semiconductor structure according to claim 3, wherein: The first carrier gas includes an inert gas or nitrogen; the second carrier gas includes an inert gas or nitrogen.

5. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that: The purge gas includes an inert gas or nitrogen.

6. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that: The material of the gate layer includes polysilicon; the pre-deposition reaction gas includes one or more of SiH4, Si2H6, Si2Cl6 and SiH2Cl2; the main deposition reaction gas includes one or more of SiH4, Si2H6, Si2Cl6 and SiH2Cl2.

7. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that: The pre-deposition reaction gas is the same as the main deposition reaction gas.

8. The method for forming a semiconductor structure according to claim 2, wherein: The step of introducing the pre-deposition reaction gas into the reaction chamber comprises: sequentially opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller to introduce the pre-deposition reaction gas into the reaction chamber; after the gas flow of the pre-deposition reaction gas reaches a stable state, closing the pre-valve of the flow controller and the flow controller.

9. The method for forming a semiconductor structure according to claim 8, wherein: The steps of sequentially opening the pre-valve of a flow controller for supplying reaction gas and the flow controller include: opening the pre-valve of the flow controller and keeping the flow controller in a closed state until the pre-deposition reaction gas reaches a stable state; After the pre-deposition reaction gas reaches a stable state, the flow controller is turned on.

10. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that: In the step of the pre-deposition treatment, the time for introducing the pre-deposition reaction gas into the reaction chamber is equal to the time required for the gas flow value of the pre-deposition reaction gas to reach the target value from the initial value.

11. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that: In the step of the pre-deposition treatment, the gas flow rate of the pre-deposition reaction gas ranges from 70 standard ml / min to 150 standard ml / min; the temperature of the pre-deposition treatment is 580 degrees Celsius to 620 degrees Celsius; The reaction pressure of the pre-deposition treatment is 0.1 mTorr to 0.4 mTorr; In the step of the main deposition process, the gas flow rate of the main deposition reaction gas ranges from 70 standard ml / min to 150 standard ml / min; the temperature of the main deposition process is 580 degrees Celsius to 620 degrees Celsius; The reaction pressure of the main deposition process is 0.1 mTorr to 0.4 mTorr.

12. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that: The target value of the gas flow rate of the pre-deposition reaction gas is greater than the target value of the gas flow rate of the main deposition reaction gas; The temperature of the pre-deposition process is greater than the temperature of the main deposition process; The reaction pressure of the pre-deposition process is greater than the reaction pressure of the main deposition process; The acceleration of the gas flow of the pre-deposition reaction gas from an initial value to a target value is a first acceleration; the acceleration of the gas flow of the main deposition reaction gas from an initial value to a target value is a second acceleration, and the second acceleration is smaller than the first acceleration.

13. The method for forming a semiconductor structure according to claim 2, wherein: During the pre-deposition treatment, the pre-deposition reaction gas is introduced into the reaction chamber by opening the pre-valve of the flow controller for supplying the reaction gas and the flow controller; After the last pre-deposition process is completed, the front valve of the flow controller for supplying the reaction gas and the flow controller are kept in an open state, and the main deposition process is performed successively.

14. The method for forming a semiconductor structure according to claim 1, wherein: The number of the pre-deposition treatment is 5 to 20 times.

15. The method for forming a semiconductor structure according to claim 1, wherein: After completing multiple pre-deposition processes, the total thickness of the seed layer along the normal direction of the top surface of the substrate is 5 angstroms to 20 angstroms.

16. The method for forming a semiconductor structure according to claim 1, wherein: The deposition process includes a low pressure chemical vapor deposition process.

17. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the substrate includes a storage area, and a groove is formed in the substrate of the storage area; Performing a first deposition process on the substrate of the storage area to form a gate layer, the gate layer is used as a floating gate material layer, and the floating gate material layer is located in the substrate of the storage area and the groove, wherein in the first deposition process, in the step of forming a seed layer on the substrate, the seed layer covers the inner wall of the groove and the substrate outside the groove, and in the step of forming a polycrystalline layer on the substrate, the polycrystalline layer covers the seed layer and fills the groove; After performing a first deposition process on the substrate of the storage area, the method further includes: patterning the floating gate material layer to form a floating gate on the substrate of the storage area; forming an inter-gate dielectric layer on the floating gate; and forming a control gate on the inter-gate dielectric layer; The step of forming a control gate on the inter-gate dielectric layer includes: performing a second deposition process to form another gate layer on the inter-gate dielectric layer to serve as a control gate material layer; and patterning the control gate material layer to form a control gate located above the floating gate in the storage area.

18. The method for forming a semiconductor structure according to claim 17, wherein: In the step of providing the substrate, the substrate further includes a logic area; In the step of forming a control gate located above the floating gate in the storage area, a logic area gate is also formed on the substrate of the logic area.

19. The method for forming a semiconductor structure according to claim 1, wherein: In the deposition process, reaction gas is introduced into the reaction chamber through multiple gas passages, the ends of the multiple gas passages are directed toward the substrate and are located at different heights of the reaction chamber, and the height values ​​of the ends of the respective gas passages are an arithmetic progression.

20. A deposition device, characterized in that: Used to perform the forming method according to any one of claims 1 to 19 to perform a deposition process on a substrate, the deposition device comprising: a reaction chamber; A plurality of gas injectors are located in the reaction chamber, and the gas injectors are used to introduce reaction gas into the interior of the reaction chamber. The plurality of gas injectors are separately arranged, and the outlet ends of the plurality of gas injectors face the substrate and are located at different height positions in the reaction chamber. The height values ​​of the respective gas injectors are an arithmetic progression.

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