Power semiconductor device

Abstract

The invention provides a power semiconductor device. The power semiconductor device comprises a P-type substrate, a P-type epitaxial layer, an N-type well region, a P-type body region, a first P-type heavily doped region, a first N-type heavily doped region, a second N-type heavily doped region, a gate oxide layer, a first oxide layer, a polycrystalline silicon control gate electrode, a polycrystalline silicon separation embedded gate electrode and a single-layer floating field plate, the source metal covers the surfaces of the first P-type heavily doped region and the first N-type heavily doped region, and the drain metal covers the surface of the second N-type heavily doped region. Single-layer floating field plates at equal intervals are introduced on an isolation oxide layer based on an STI process, surface electric field distribution is smoothed, a high-peak electric field and a strong collision ionization rate introduced by an STI corner and a separation embedded gate are reduced, the hot carrier effect of the device is improved, and meanwhile, the floating field plates can assist depletion, so that a current path is far away from the surface of the device, and the device performance is improved. The number of carriers generated on the surface of the device is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and in particular relates to a power semiconductor device. Background Art

[0002] Lateral Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOSFET) has the advantages of easy integration, fast switching speed, high input impedance, and good thermal stability, and is widely used in power integrated circuits (PIC). Due to its high compatibility with CMOS logic processes, shallow trench isolation (STI) technology has gradually replaced local oxidation isolation (LOCOS) technology to become the mainstream LDMOS device isolation technology.

[0003] The isolation oxide layer formed based on STI technology will introduce two sharp corners at its bottom, where strong electric fields and high collision ionization rates are likely to occur, increasing the energy and number of hot carriers and aggravating the hot carrier effect. These hot carriers are injected into the oxide layer under the action of the electric field, which, on the one hand, breaks the valence bonds near the interface to form interface states, and on the other hand, causes the carriers to be captured by oxide layer traps to become oxide layer trap charges, which will lead to degradation of device performance and reduced reliability. At present, there is a method of using a separated embedded gate structure to reduce the peak electric field at the STI corner, but the separated embedded gate bottom and end will also introduce new electric field peaks, which will degrade device reliability. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention proposes a power semiconductor device, aiming to reduce the high peak electric field and high collision ionization rate introduced by the separated embedded gate while maintaining the device's withstand voltage level, and further reduce the peak electric field and collision ionization rate at the STI corner.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A power semiconductor device comprises: a P-type substrate 1, a P-type epitaxial layer 2 located above the P-type substrate 1, an N-type well region 3 and a P-type body region 4 located inside the P-type epitaxial layer 2, a first P-type heavily doped region 5 and a first N-type heavily doped region 6 located on the surface of the P-type body region 4, a second N-type heavily doped region 7 located on the right side surface of the N-type well region 3, a gate oxide layer 8 and a first oxide layer 9 located on the surface of the P-type epitaxial layer 2, a left side of the gate oxide layer 8 being tangent to a right side of the first N-type heavily doped region 6, a right side of the gate oxide layer 8 extending and ending at a left boundary of the first oxide layer 9, a polysilicon control gate electrode 10 located above the gate oxide layer 8 and the first oxide layer 9, a polysilicon separation embedded gate electrode 11 located inside and on the surface of the first oxide layer 9, a single-layer floating field plate 12 or a double-layer floating field plate 20 located above the first oxide layer 9, the first P-type heavily doped region 5 and the first N-type heavily doped region 6 being short-circuited by a source metal 13, and the second N-type heavily doped region 7 being connected to a drain metal 14.

[0007] As a preferred embodiment, the single-layer floating field plate 12 includes a plurality of sections of polysilicon sub-field plates, and the distances between the polysilicon sub-field plates are equal.

[0008] As a preferred embodiment, the polysilicon separation embedded gate electrode 11 is individually connected to a potential lead, to which a negative voltage, a positive voltage or a ground potential is applied.

[0009] As a preferred embodiment, the double-layer floating field plate 20 is composed of a first layer of field plates and a second layer of field plates, wherein the second layer of field plates is located above the first layer of field plates, each layer of field plates includes a plurality of polysilicon sub-field plates at equal distances, and the upper and lower layers of field plates are staggered and the upper and lower overlapping areas between each segment are kept consistent.

[0010] As a preferred embodiment, the polysilicon sub-field plate located at the device drain end in the second layer of the double-layer floating field plate 20 is closer to the device drain end than the polysilicon sub-field plate located at the device drain end in the first layer of the field plate;

[0011] As a preferred embodiment, the polysilicon subfield plate located at the device drain end in the first field plate of the double-layer floating field plate 20 is closer to the device drain end than the polysilicon subfield plate located at the device drain end in the second field plate.

[0012] As a preferred embodiment, the polysilicon subfield plate near the source end in the second field plate of the double-layer floating field plate 20 is short-circuited with the source metal 13 , and the polysilicon subfield plate near the drain end in the second field plate of the double-layer floating field plate 20 is short-circuited with the drain metal 14 .

[0013] As a preferred embodiment, the polysilicon subfield plate near the source end in the first layer of the double-layer floating field plate 20 is short-circuited with the source metal 13 , and the polysilicon subfield plate near the drain end in the first layer of the double-layer floating field plate 20 is short-circuited with the drain metal 14 .

[0014] As a preferred embodiment, a second P-type doping region 30 is disposed below the first oxide layer 9 , and the second P-type doping region 30 surrounds a corner of the first oxide layer 9 .

[0015] As a preferred embodiment, a segmented third P-type doping region 31 is set below the first oxide layer 9, the third P-type doping region 31 close to the source side surrounds the corner of the first oxide layer 9, and the doping concentration of the third P-type doping region 31 decreases from the source side to the drain side.

[0016] As a preferred embodiment, the first oxide layer 9 is in a discontinuous distribution;

[0017] As a preferred embodiment, there is a low-K dielectric layer 40 inside the first oxide layer 9 , and the relative dielectric constant of the low-K dielectric layer is lower than the relative dielectric constant of the first oxide layer 9 .

[0018] The beneficial effects of the present invention are as follows: the present invention introduces a floating polysilicon field plate with equal spacing above the isolation oxide layer based on the STI process to smooth the surface electric field distribution, effectively weaken the new high peak electric field and high collision ionization rate introduced at the bottom corner of the embedded part of the separation embedded gate and the end of the separation gate close to the drain side, thereby improving the hot carrier effect of the device; the floating polysilicon field plate can assist the surface depletion of the device, so that the current path is away from the device surface, the number of carriers generated by surface collision ionization is reduced, and the reliability of the device is improved; the floating polysilicon field plate can introduce a new electric field peak, compensate for the reduction of the electric field peak at the STI corner and the separation embedded gate corner, and the breakdown voltage of the device remains unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a traditional LDMOS longitudinal cross-section structure;

[0020] Figure 2 It is a structural schematic diagram of Example 1;

[0021] Figure 3 Schematic diagram of electric field distribution in Example 1;

[0022] Figure 4 Schematic diagram of collision ionization rate distribution in Example 1;

[0023] Figure 5 It is a structural schematic diagram of Example 2;

[0024] Figure 6 It is a structural schematic diagram of Example 3;

[0025] Figure 7 It is a structural schematic diagram of Example 4;

[0026] Figure 8 It is a structural schematic diagram of Example 5;

[0027] Fig. 9 It is a structural schematic diagram of Example 6;

[0028] Fig.10 is a schematic structural diagram of Example 7;

[0029] Fig.11 It is a structural schematic diagram of Example 8;

[0030] Fig.12 is a schematic structural diagram of Example 9;

[0031] Fig.13 is a schematic structural diagram of Example 10;

[0032] Fig.14 is a schematic structural diagram of Example 11;

[0033] 1 is a P-type substrate, 2 is a P-type epitaxial layer, 3 is an N-type well region, 4 is a P-type body region, 5 is a first P-type heavily doped region, 6 is a first N-type heavily doped region, 7 is a second N-type heavily doped region, 8 is a gate oxide layer, 9 is a first oxide layer, 10 is a polysilicon control gate electrode, 11 is a polysilicon separated embedded gate electrode, 12 is a single-layer floating field plate, 13 is a source metal, 14 is a drain metal, 20 is a double-layer floating field plate, 30 is a second P-type doped region, 31 is a third P-type doped region, and 40 is a low-K dielectric layer. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] The present invention introduces a floating polysilicon field plate with equal spacing above an isolation oxide layer based on an STI process to smooth the surface electric field distribution, effectively weaken the new high peak electric field and high collision ionization rate introduced at the bottom corner of the embedded part of the separation embedded gate and the end of the separation gate close to the drain side, thereby improving the hot carrier effect of the device; the floating polysilicon field plate can assist the surface depletion of the device, so that the current path is away from the device surface, the number of carriers generated by surface collision ionization is reduced, and the reliability of the device is improved; the floating polysilicon field plate can introduce a new electric field peak, compensate for the reduction of the electric field peak at the STI corner and the separation embedded gate corner, and the breakdown voltage of the device remains unchanged.

[0036] Example 1

[0037] like Figure 2As shown, the device structure of this embodiment includes: a P-type substrate 1, a P-type epitaxial layer 2 located above the P-type substrate 1, an N-type well region 3 and a P-type body region 4 located inside the P-type epitaxial layer 2, a first P-type heavily doped region 5 and a first N-type heavily doped region 6 located on the surface of the P-type body region 4, a second N-type heavily doped region 7 located on the right side surface of the N-type well region 3, a gate oxide layer 8 and a first oxide layer 9 located on the surface of the P-type epitaxial layer 2, the left side of the gate oxide layer 8 is tangent to the right side of the first N-type heavily doped region 6, the right side of the gate oxide layer 8 extends and stops at the left boundary of the first oxide layer 9, a polysilicon control gate electrode 10 is located above the gate oxide layer 8 and the first oxide layer 9, a polysilicon separation embedded gate electrode 11 is located inside and on the surface of the first oxide layer 9, a single-layer floating field plate 12 is located above the first oxide layer 9, the first P-type heavily doped region 5 and the first N-type heavily doped region 6 are short-circuited by a source metal 13, and the second N-type heavily doped region 7 is connected to a drain metal 14.

[0038] This example works like this:

[0039] A polysilicon floating field plate with equal spacing is introduced above the isolation oxide layer of the conventional separated embedded gate LDMOS device. Figure 3 and Figure 4 To capture the device electric field distribution diagram and collision ionization rate distribution diagram close to the STI surface, it can be seen from the figure that a new electric field peak can be introduced under the polysilicon floating field plate to smooth the electric field distribution on the device surface, effectively reducing the high peak electric field introduced by the separated embedded gate, reducing the collision ionization level of hot carriers, and improving the hot carrier effect of the device; the new electric field peak introduced by the polysilicon floating field plate compensates for the electric field reduced by the STI corner and the separated embedded gate, so that the breakdown voltage of the device remains unchanged; the polysilicon field plate can assist in depleting the device surface, so that the carrier path is away from the interface between the silicon and the oxide layer, the number of carriers on the device surface is reduced, and the hot carrier effect of the device is improved.

[0040] Example 2

[0041] like Figure 5 As shown, the present invention is basically the same as Example 1, except that a second P-type doping region 30 is provided below the first oxide layer 9, and the second P-type doping region 30 surrounds the corner of the first oxide layer 9. The advantage is that the doping concentration of the drift region can be increased and the on-resistance of the device can be reduced without reducing the withstand voltage level of the device; at the same time, the introduction of the second P-type doping region can keep the current path away from the STI corner and the interface between the silicon and the oxide layer, thereby improving the reliability of the device.

[0042] Example 3

[0043] like Figure 6As shown, the present invention is basically the same as Example 1, except that: a segmented third P-type doping region 31 is arranged below the first oxide layer 9, and the third P-type doping region 31 near the source side surrounds the corner of the first oxide layer 9, and the doping concentration of the third P-type doping region 31 decreases from the source side to the drain side. The advantage is that the doping concentration of the third P-type doping region near the source side is higher, which can effectively reduce the peak electric field of the main junction, and the third P-type doping concentration near the drain side is lower, which can avoid the introduction of a peak electric field at the drain end, causing the device to break down prematurely, thereby increasing the device breakdown voltage; at the same time, the introduction of the third P-type doping region can keep the current path away from the STI corner and the interface between silicon and the oxide layer, thereby improving the reliability of the device.

[0044] Example 4

[0045] like Figure 7 As shown, the present invention is basically the same as Example 1, except that the first oxide layer 9 is in a discontinuous distribution. Its advantage is that the isolation oxide layer based on the STI process is formed by etching and then depositing, and its interface quality is poor. The isolation oxide layer is segmented, which can make the oxide layer area formed by thermal oxidation larger and the oxide layer area formed by etching and then depositing smaller, thereby improving the interface quality between silicon and oxide layer and improving the reliability of the device; at the same time, the corners of the multi-segment isolation oxide layer can introduce new electric field peaks, smooth the electric field distribution on the device surface, and improve the hot carrier effect of the device.

[0046] Example 5

[0047] like Figure 8 As shown, the present invention is basically the same as Example 1, except that: a low-K dielectric layer 40 exists inside the first oxide layer 9, and the relative dielectric constant of the low-K dielectric layer is lower than the relative dielectric constant of the first oxide layer 9. The advantage is that the low-K dielectric layer can increase the equivalent thickness of the isolation oxide layer, reduce the electric field peak introduced by the STI corner and the separation embedded gate, and improve the hot carrier effect of the device.

[0048] Example 6

[0049] like Fig. 9 As shown, the present invention is basically the same as Example 1, except that: the single-layer floating field plate 12 is replaced by a double-layer floating field plate, the double-layer floating field plate 20 is located above the first oxide layer 9, and the double-layer floating field plate 20 is composed of a first layer field plate and a second layer field plate, wherein the second layer field plate is located above the first layer field plate, each layer of field plates includes a plurality of polysilicon sub-field plates with equal distances, and the upper and lower layers of field plates are staggered and the upper and lower overlapping areas between each segment are kept consistent;

[0050] The polysilicon sub-field plate located at the drain end of the device in the second field plate of the double-layer floating field plate 20 is closer to the drain end of the device than the polysilicon sub-field plate located at the drain end of the device in the first field plate. Among them, the polysilicon sub-field plate near the source end in the second field plate of the double-layer floating field plate 20 is short-circuited with the source metal 13, and the polysilicon sub-field plate near the drain end in the second field plate of the double-layer floating field plate 20 is short-circuited with the drain metal 14. Its advantage is that the surface electric field distribution is more uniform, further reducing the electric field peak introduced by the STI corner and the separated embedded gate, and improving the hot carrier effect of the device.

[0051] Example 7

[0052] like Fig.10 As shown, the present invention is basically the same as Example 6, except that the polysilicon sub-field plate located at the drain end of the device in the first layer of the double-layer floating field plate 20 is closer to the drain end of the device than the polysilicon sub-field plate located at the drain end of the device in the second layer of the field plate. Among them, the polysilicon sub-field plate near the source end in the first layer of the double-layer floating field plate 20 is short-circuited with the source metal 13, and the polysilicon sub-field plate near the drain end in the first layer of the double-layer floating field plate 20 is short-circuited with the drain metal 14. Its advantage is that the surface electric field distribution is more uniform, further reducing the electric field peak introduced by the STI corner and the separated embedded gate, and improving the hot carrier effect of the device.

[0053] Example 8

[0054] like Fig.11 As shown, the present invention is basically the same as Example 6, except that a second P-type doping region 30 is provided below the first oxide layer 9, and the second P-type doping region 30 surrounds the corner of the first oxide layer 9. The advantage is that the doping concentration of the drift region can be increased and the on-resistance of the device can be reduced without reducing the withstand voltage level of the device; at the same time, the introduction of the second P-type doping region can keep the current path away from the STI corner and the interface between the silicon and the oxide layer, thereby improving the reliability of the device.

[0055] Example 9

[0056] like Fig.12 As shown, the present invention is basically the same as Example 6, except that: a segmented third P-type doping region 31 is arranged below the first oxide layer 9, and the third P-type doping region 31 near the source side surrounds the corner of the first oxide layer 9, and the doping concentration of the third P-type doping region 31 decreases from the source side to the drain side. The advantage is that the doping concentration of the third P-type doping region near the source side is higher, which can effectively reduce the peak electric field of the main junction, and the third P-type doping concentration near the drain side is lower, which can avoid the introduction of a peak electric field at the drain end, causing the device to break down prematurely, thereby increasing the device breakdown voltage; at the same time, the introduction of the third P-type doping region can keep the current path away from the STI corner and the interface between silicon and the oxide layer, thereby improving the reliability of the device.

[0057] Example 10

[0058] like Fig.13 As shown, the present invention is basically the same as Example 6, except that the first oxide layer 9 is in a discontinuous distribution. Its advantage is that the isolation oxide layer based on the STI process is formed by etching and then depositing, and its interface quality is poor. The isolation oxide layer is segmented, which can make the oxide layer area formed by thermal oxidation larger and the oxide layer area formed by etching and then depositing smaller, thereby improving the interface quality between silicon and oxide layer and improving the reliability of the device; at the same time, the corners of the multi-segment isolation oxide layer can introduce new electric field peaks, smooth the electric field distribution on the device surface, and improve the hot carrier effect of the device.

[0059] Embodiment 11

[0060] like Fig.14 As shown, the present invention is basically the same as Example 6, except that: a low-K dielectric layer 40 exists inside the first oxide layer 9, and the relative dielectric constant of the low-K dielectric layer is lower than the relative dielectric constant of the first oxide layer 9. The advantage is that the low-K dielectric layer can increase the equivalent thickness of the isolation oxide layer, reduce the electric field peak introduced by the STI corner and the separation embedded gate, and improve the hot carrier effect of the device.

[0061] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power semiconductor device, characterized in that include: A P-type substrate (1), a P-type epitaxial layer (2) located above the P-type substrate (1), an N-type well region (3) and a P-type body region (4) located inside the P-type epitaxial layer (2), a first P-type heavily doped region (5) and a first N-type heavily doped region (6) located on the surface of the P-type body region (4), a second N-type heavily doped region (7) located on the right side surface of the N-type well region (3), a gate oxide layer (8) and a first oxide layer (9) located on the surface of the P-type epitaxial layer (2), a left side of the gate oxide layer (8) being tangent to a right side of the first N-type heavily doped region (6), and a gate oxide layer ( 8) extends to the right side and stops at the left boundary of the first oxide layer (9), the polysilicon control gate electrode (10) is located on the gate oxide layer (8) and the first oxide layer (9), the polysilicon separation embedded gate electrode (11) is located inside and on the surface of the first oxide layer (9), the single-layer floating field plate (12) or the double-layer floating field plate (20) is located above the first oxide layer (9), the first P-type heavily doped region (5) and the first N-type heavily doped region (6) are short-circuited by the source metal (13), and the second N-type heavily doped region (7) is connected to the drain metal (14).

2. A power semiconductor device according to claim 1, characterized in that: The single-layer floating field plate (12) comprises a plurality of sections of polysilicon sub-field plates, and the distances between the polysilicon sub-field plates are equal.

3. A power semiconductor device according to claim 1, characterized in that: The polysilicon separation embedded gate electrode (11) is connected to a potential lead-out separately, and negative voltage, positive voltage or ground potential is applied thereto.

4. A power semiconductor device according to claim 1, characterized in that: The double-layer floating field plate (20) is composed of a first layer of field plates and a second layer of field plates, wherein the second layer of field plates is located above the first layer of field plates, each layer of field plates includes a plurality of polysilicon sub-field plates at equal distances, and the upper and lower layers of field plates are staggered and arranged to keep the upper and lower overlapping areas of each segment consistent.

5. A power semiconductor device according to claim 4, characterized in that: The polysilicon sub-field plate located at the device drain end in the second layer of the double-layer floating field plate (20) is closer to the device drain end than the polysilicon sub-field plate located at the device drain end in the first layer of the field plate; Or the polysilicon sub-field plate located at the device drain end in the first layer of the double-layer floating field plate (20) is closer to the device drain end than the polysilicon sub-field plate located at the device drain end in the second layer of the field plate.

6. A power semiconductor device according to claim 4 or 5, characterized in that: The polysilicon sub-field plate close to the source end in the second field plate of the double-layer floating field plate (20) is short-circuited with the source metal (13), and the polysilicon sub-field plate close to the drain end in the second field plate of the double-layer floating field plate (20) is short-circuited with the drain metal (14).

7. A power semiconductor device according to claim 4 or 5, characterized in that: The polysilicon sub-field plate close to the source end in the first field plate of the double-layer floating field plate (20) is short-circuited with the source metal (13), and the polysilicon sub-field plate close to the drain end in the first field plate of the double-layer floating field plate (20) is short-circuited with the drain metal (14).

8. A power semiconductor device according to claim 1, 6 or 7, characterized in that: A second P-type doping region (30) is arranged below the first oxide layer (9), and the second P-type doping region (30) surrounds a corner of the first oxide layer (9).

9. A power semiconductor device according to claim 1 or 6 or 7, characterized in that: A segmented third P-type doping region (31) is arranged below the first oxide layer (9), the third P-type doping region (31) close to the source side surrounds the corner of the first oxide layer (9), and the doping concentration of the third P-type doping region (31) decreases from the source side to the drain side.

10. A power semiconductor device according to claim 1 or 6 or 7, characterized in that: The first oxide layer (9) is distributed discontinuously; And / or a low-K dielectric layer (40) exists inside the first oxide layer (9), and the relative dielectric constant of the low-K dielectric layer is lower than the relative dielectric constant of the first oxide layer (9).

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