An Asymmetric Groove-Gate Silicon Carbide VDMOS and Its Manufacturing Method

Abstract

The present invention provides an asymmetric trench-gated silicon carbide VDMOS and a manufacturing method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a blocking layer, etching, and performing ion implantation to form a masking layer, a P-type well region, and an N-type source region; reforming the blocking layer, etching, and etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; reforming the blocking layer, etching, depositing metal to form a gate metal layer; reforming the blocking layer, etching the blocking layer to form a via hole, and etching the drift layer to the upper side of the freewheeling region, and depositing metal to form a source metal layer; removing the blocking layer to complete the manufacturing, which can effectively reduce the conduction loss of the body diode of the device, improve the reverse recovery speed of the device, improve the gate reliability of the device, and improve the reliability of the source large current impact.

Description

Technical Field

[0001] The present invention relates to an asymmetric trench-gate silicon carbide VDMOS and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS (vertical double-diffused metal-oxide-semiconductor field effect transistor) is a typical representative of silicon carbide power devices. Due to its excellent performance, it has been widely used in many high-tech fields such as electric vehicles, aerospace, and power conversion. However, different application scenarios have different emphases on the performance requirements of silicon carbide power VDMOS. Generally speaking, its core requirements mainly focus on the following aspects:

[0003] 1. Lower on-resistance: In high-power applications, such as the electric drive system of electric vehicles and power conversion equipment, the on-resistance of the device is directly related to the energy conversion efficiency and system heating. A lower on-resistance can significantly reduce the energy loss during conduction, improve the overall energy efficiency, thereby extending the driving range of electric vehicles or reducing the heat dissipation requirements of power conversion equipment.

[0004] 2. Faster switching speed: Fast switching ability is crucial for high-frequency power electronic devices. In the aerospace field, high-frequency switching power supplies and pulse power systems require fast response and high-precision control to achieve efficient energy distribution and conversion. The fast switching characteristics of silicon carbide VDMOS can effectively reduce the switching loss, improve the dynamic performance and power density of the system.

[0005] 3. Higher reliability:

[0006] Gate reliability: In complex working environments, such as high temperature, high humidity, and high voltage shock, etc., the reliability of the gate is a key factor affecting the device life. The high thermal stability and chemical stability of silicon carbide materials enable its gate structure to remain stable under extreme conditions, thereby extending the service life of the device.

[0007] Drain voltage shock reliability: In a power conversion system, the device may be subjected to voltage spikes and transient shocks. The high breakdown voltage characteristics and fast recovery ability of silicon carbide VDMOS enable it to withstand these shocks, reducing the risk of device damage caused by voltage overshoot.

[0008] 4. Lower body diode conduction loss: In many applications, such as the motor drive of electric vehicles and renewable energy conversion systems, the conduction loss of the body diode directly affects the overall efficiency of the system. By optimizing the device structure, silicon carbide VDMOS effectively reduces the conduction loss of the body diode, while improving the reverse recovery speed and reducing the energy retention and loss in the diode. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide an asymmetric trench-gate silicon carbide VDMOS and a preparation method thereof, which can effectively reduce the conduction loss of the body diode of the device, improve the reverse recovery speed of the device, improve the gate reliability of the device, and improve the source maximum current impact reliability of the device.

[0010] In the first aspect, the present invention provides a preparation method of an asymmetric trench-gate silicon carbide VDMOS, including the following steps:

[0011] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the silicon carbide substrate to form a drift layer;

[0012] Step 2: Inject ions into the drift layer to form a freewheeling region;

[0013] Step 3: Form a barrier layer on the drift layer, etch the barrier layer to form a through hole, and inject ions to form a masking layer;

[0014] Step 4: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and inject ions to form a P-type well region;

[0015] Step 5: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and inject ions to form an N-type source region;

[0016] Step 6: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer and the masking layer to form a groove, and oxidize to form an insulating dielectric layer;

[0017] Step 7: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and deposit metal to form a gate metal layer;

[0018] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the freewheeling region, deposit metal to form a source metal layer; remove the barrier layer to complete the preparation.

[0019] In the second aspect, the present invention provides an asymmetric trench-gate silicon carbide VDMOS, which is prepared by using the preparation method of an asymmetric trench-gate silicon carbide VDMOS described in the first aspect.

[0020] The advantages of the present invention are as follows:

[0021] First, the masking layer of the present invention wraps the area below the trench-gate insulating dielectric layer, which can effectively improve the gate reliability of the device;

[0022] Second, the masking layer of the present invention is also directly connected to the source metal layer, forming an ohmic contact with the source metal layer. The pn junction formed by it and the freewheeling region can effectively increase the area of the body pn junction diode of the device, and effectively improve the freewheeling ability of the body diode of the device;

[0023] Third, the freewheeling regions of the present invention are respectively connected to the source metal layer on the left and right sides, forming a Schottky diode between the source metal layer and the freewheeling region, which can effectively reduce the conduction voltage drop of the body diode of the device;

[0024] Fourth, the cathode distribution position of the Schottky diode of the present invention is the same as that of the cathode of the pn junction. However, the reverse recovery of the Schottky diode is faster and the conduction voltage drop is lower. Therefore, in general, the device has the characteristic of fast recovery. In extreme cases, under the condition of a large current from the source to the drain, the pn junction diode assists in conduction, which can effectively improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0026] Figure 1 It is a schematic diagram of an asymmetric trench-gated silicon carbide VDMOS of the present invention.

[0027] Figure 2 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 1 .

[0028] Figure 3 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 2 .

[0029] Figure 4 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 3 .

[0030] Figure 5 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 4 .

[0031] Figure 6 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 5 .

[0032] Figure 7 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 6 .

[0033] Figure 8 It is a process cross-section of an asymmetric trench-gated silicon carbide VDMOS of the present invention Figure 7 .

[0034] Figure 9 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 8 。

[0035] Figure 10 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 9 。

[0036] Figure 11 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 10 。 Specific embodiments

[0037] To facilitate understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant accompanying drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be denoted as the second element, component, region, layer or part.

[0040] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Therefore, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. In addition, the device can also include other orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0041] As used herein, the singular forms of "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0042] As Figures 1 to 11 shown, an embodiment of the present application provides a method for preparing an asymmetric trench-gate silicon carbide VDMOS, including the following steps:

[0043] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially grow on the silicon carbide substrate 1 to form a drift layer 2;

[0044] Step 2: Inject ions into the drift layer 2 to form a freewheeling region 3, and the ion implantation energy is 100 - 400 kev;

[0045] Step 3: Form a barrier layer 8 on the drift layer 2, etch the barrier layer 8 to form a through hole, and perform ion implantation to form a masking layer 33, and the ion implantation energy is 100 - 330 kev;

[0046] Step 4: Remove the original barrier layer, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation to form a P-type well region 31, and the ion implantation energy is 200 - 300 kev;

[0047] Step 5: Remove the original barrier layer, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation to form an N-type source region 32, and the ion implantation energy is 100 - 200 kev;

[0048] Step 6: Remove the original barrier layer, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the drift layer 2 and the masking layer 33 to form a groove 34, and oxidize to form an insulating dielectric layer 4;

[0049] Step 7: Remove the original barrier layer, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit metal to form a gate metal layer 5;

[0050] Step 8: Remove the original barrier layer, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the drift layer 2 to the upper side of the freewheeling region 3, deposit metal to form a source metal layer 6; remove the barrier layer 8 to complete the preparation.

[0051] In this embodiment, preferably, the width of the P-type well region 31 is greater than the width of the N-type source region 32.

[0052] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2, and the freewheeling region 3 are all N-type, and the masking layer 33 is P-type.

[0053] In this embodiment, preferably, the upper sides of the N-type source region 32, the freewheeling region 3, and the masking layer 33 are in the same plane.

[0054] In this embodiment, preferably, the doping concentration of the freewheeling region 3 is greater than the doping concentration of the drift layer 2.

[0055] In this embodiment, preferably, the doping concentration of the masking layer 33 is greater than the doping concentration of the freewheeling region 3.

[0056] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0057] Silicon carbide substrate 1;

[0058] Drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0059] Freewheeling region 3, the lower side of the freewheeling region 3 is connected to the upper side of the drift layer 2; a P-type well region 31, an N-type source region 32, a masking layer 33, and a groove 34 are provided in the freewheeling region 3; the lower side of the N-type source region 32 is connected to the upper side of the P-type well region 31; the P-type well region 31 and the N-type source region 32 are located on one side of the groove 34; the masking layer 33 is located below the groove 34 and on the other side;

[0060] Insulating dielectric layer 4, the lower part of the insulating dielectric layer 4 is arranged in the groove 34, and the lower side surface of the insulating dielectric layer 4 is connected to the masking layer 33; the outer side surfaces of the insulating dielectric layer 4 are respectively connected to the N-type source region 32, the P-type well region 31 and the masking layer 33; a trench 41 is arranged in the insulating dielectric layer 4;

[0061] Gate metal layer 5, the gate metal layer 5 is arranged in the trench 41;

[0062] Source metal layer 6, the source metal layer 6 is respectively connected to the freewheeling region 3, the N-type source region 31 and the masking layer 33;

[0063] And a drain metal layer 7, the drain metal layer 7 is connected to the silicon carbide substrate 1.

[0064] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2e18 cm -3 , the doping concentration of the N-type drift layer 2 is 1e16 cm -3 , the doping concentration of the N-type freewheeling region 3 is 1e17 cm -3 , the doping concentration of the P-type masking layer 33 is 1e18 cm -3 , the doping concentration of the P-type well region 31 is 5e17 cm -3 , the material of the insulating dielectric layer 4 can be one or a combination of several of silicon dioxide, aluminum nitride, hafnium dioxide, and the doping concentration of the N-type source region 32 is 2e18 cm -3 ; the doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 7 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse breakdown voltage and the on-resistance of the device; the doping concentration of the N-type freewheeling region 3 is to reduce the on-resistance of the device and form a Schottky metal rather than an ohmic contact with the source metal layer 6 to form a Schottky substrate diode inside the device; the doping concentration of the P-type masking layer 33 is to suppress the electric field concentration at the gate corner of the device and suppress the influence of the drain voltage impact on the gate of the device. The P-type masking layer 33 forms an ohmic contact with the source metal layer 6 to form a pn junction bulk diode inside the device. The doping concentration of the N-type source region 32 is to form an ohmic contact with the source metal layer 6 and reduce the contact resistance.

[0065] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 15 - 25 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the N-type freewheeling region 3 under the P-type masking layer 33 is 200 nm, the thickness of the N-type freewheeling region 3 under the P-type well region 31 is 300 nm, and the thickness of the N-type freewheeling region 3 under the source metal layer 6 is 900 nm; the width of the contact surface between the N-type freewheeling region 3 on one side of the N-type source region 32 and the source metal layer 6 is 500 nm; the width of the N-type freewheeling region 3 beside the P-type well region 31 is 100 nm; the width of the contact surface between the N-type freewheeling region 3 on one side of the P-type masking layer 33 and the source metal layer 6 is 200 nm, ensuring that when a positive voltage is applied to the drain of the device, this region is a space charge region, guaranteeing the turn-off characteristics of the device; the N-type freewheeling region 3 under the P-type masking layer 33 can effectively shield the capacitance effect of the gate on the drain, reduce the gate-drain charge of the device, improve the switching speed of the device, and at the same time guide the carriers from one side of the device to other regions of the device, avoiding current concentration inside the device and reducing the on-resistance of the device; the thickness of the P-type masking layer 33 under the insulating dielectric layer 4 is 100 nm, which is to protect the gate of the device and suppress the breakdown problem caused by electric field concentration at the gate corner. The bottom thickness of the insulating dielectric layer 4 is 50 nm, the thickness of the N-type source region 32 is 300 nm, and the thickness of the P-type well region 31 is 300 nm;

[0066] The P-type masking layer 33 of the device is directly connected to the source metal layer 6, forming an ohmic contact with the source metal layer 6. The pn junction formed by it and the N-type freewheeling region 3 can effectively increase the area of the body pn junction diode of the device, effectively improving the freewheeling ability of the body diode of the device; the N-type freewheeling region 3 of the device is connected to the source metal layer 6 on both the left and right sides respectively, forming a Schottky diode between the source metal layer 6 and the N-type freewheeling region 3, which can effectively reduce the on-voltage drop of the body diode of the device. The cathode distribution position of the Schottky diode of the device is the same as that of the cathode of the pn junction, but the reverse recovery of the Schottky diode is faster and the on-voltage drop is lower. Therefore, generally, the device has the characteristics of fast recovery. In extreme cases, when there is a large current condition from the source to the drain of the device, the pn junction diode conducts electricity to assist, which can improve the source current freewheeling ability of the device. This structure can effectively improve the reliability of the large source current in the off state of the device.

[0067] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope protected by the claims of the present invention.

Claims

1. A preparation method of an asymmetric trench-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the silicon carbide substrate to form a drift layer; Step 2: Inject ions into the drift layer to form a freewheeling region; Step 3: Form a blocking layer on the drift layer, etch the blocking layer to form a through hole, and inject ions to form a masking layer; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and inject ions to form a P-type well region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and inject ions to form an N-type source region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer and the masking layer to form a groove, and oxidize to form an insulating dielectric layer; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal to form a gate metal layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to the upper side of the freewheeling region, deposit metal to form a source metal layer; remove the blocking layer to complete the preparation; The lower side of the freewheeling region is connected to the upper side of the drift layer; the freewheeling region is provided with a P-type well region, an N-type source region, a masking layer, and a groove; the lower side of the N-type source region is connected to the upper side of the P-type well region; the P-type well region and the N-type source region are located on one side of the groove; the masking layer is located below the groove and on the other side; The lower part of the insulating dielectric layer is arranged in the groove, and the lower side of the insulating dielectric layer is connected to the masking layer; the outer side of the insulating dielectric layer is respectively connected to the N-type source region, the P-type well region, and the masking layer; the insulating dielectric layer is provided with a trench; The gate metal layer is arranged in the trench; The source metal layer is respectively connected to the freewheeling region, the N-type source region, and the masking layer.

2. The manufacturing method of an asymmetric trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the P-type well region is greater than the width of the N-type source region.

3. The manufacturing method of an asymmetric trench-gate silicon carbide VDMOS according to claim 1, wherein: The silicon carbide substrate, the drift layer, and the freewheeling region are all N-type, and the masking layer is P-type.

4. The manufacturing method of an asymmetric trench-gate silicon carbide VDMOS according to claim 1, wherein: The upper sides of the N-type source region, the freewheeling region, and the masking layer are located on the same plane.

5. The manufacturing method of an asymmetric trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the freewheeling region is greater than the doping concentration of the drift layer.

6. The manufacturing method of an asymmetric trench-gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the masking layer is greater than the doping concentration of the freewheeling region.

7. An asymmetric trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of Claims 1 to 6.

Images