A trench-gate silicon carbide VDMOS with a trench source and a preparation method thereof

Abstract

The present invention provides a trench-gate silicon carbide VDMOS with a trench source and a preparation method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer, etching, and ion implanting to form a low-resistance region and a first protrusion; reforming the blocking layer, etching, and ion implanting to form a first well region and a second protrusion; reforming the blocking layer, etching, and ion implanting to form a P-type source region and a P-type well region; reforming the blocking layer, etching, and oxidizing to form an insulating dielectric layer, where a trench is provided in the insulating dielectric layer; reforming the blocking layer, etching, and depositing metal to form a gate metal layer and a source metal layer, and removing the blocking layer to complete the preparation; solving the problem of the gate reliability of the trench gate, and not requiring an additional electrode to be led out, improving the freewheeling ability of the body diode, and reducing the on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to a trench-gate silicon carbide VDMOS with a trench source and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the requirements for device performance focus on different aspects in different fields. Generally speaking, the overall requirements include higher breakdown voltage capability, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage shock reliability, short-circuit reliability, etc.), and lower conduction loss of the body diode.

[0003] In addition, for trench top-gate devices, electric field concentration is likely to occur at the corners of the gate insulating medium, leading to gate breakdown. Generally, there are two solutions. One is to adopt a P-type shielding region structure to suppress gate breakdown, but the introduction of P-type doping will affect the on-resistance of the device. The other is to adopt a deep trench P-type well region. However, due to the relatively high potential of the P-type well region, it is necessary to draw out the potential from the edge of the P-type well region, which will increase the complexity of the device structure and packaging. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a trench-gate silicon carbide VDMOS with a trench source and a preparation method thereof, which solves the gate reliability problem of the trench gate, does not require an additional electrode to be drawn out, improves the freewheeling ability of the body diode, and reduces the on-resistance of the device.

[0005] In the first aspect, the present invention provides a preparation method of a trench-gate silicon carbide VDMOS with a trench source, including the following steps:

[0006] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0007] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a low-resistance region and a first protrusion;

[0008] Step 3: Remove the original blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a first well region and a second protrusion;

[0009] Step 4: Remove the original blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the first well region to form a P-type source region;

[0010] Step 5: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a via hole, perform ion implantation on the drift layer to form a second well region, and the P-type well region includes the first well region and the second well region;

[0011] Step 6: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a via hole, perform ion implantation on the second well region to form an N-type source region;

[0012] Step 7: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a via hole, etch the first well region and the drift layer, and then oxidize to form an insulating dielectric layer with grooves therein;

[0013] Step 8: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a via hole, and deposit metal to form a gate metal layer;

[0014] Step 9: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a via hole, and etch the P-type source region, and then deposit metal to form a first source metal region;

[0015] Step 10: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a via hole, and etch the P-type well region and the N-type source region, and then deposit metal to form a second source metal region. The source metal layer includes the first source metal region and the second source metal region. Remove the blocking layer to complete the preparation.

[0016] In a second aspect, the present invention provides a trench-gate silicon carbide VDMOS with a trench source, and the silicon carbide VDMOS is prepared by using the preparation method of a trench-gate silicon carbide VDMOS with a trench source described in the first aspect.

[0017] The advantages of the present invention are as follows:

[0018] First, when the drain of the device of the present invention bears a large voltage, a pn junction is formed between the drift layer and the P-type well region to achieve voltage resistance; when the device withstands voltage, the distribution of the space charge region in the P-type well region in the pn junction is distributed away from the gate corner direction of the P-type well region, avoiding the problem of high electric field breakdown at the gate corner of the device;

[0019] Second, when the device of the present invention bears the drain voltage, the potential of the P-type well region is lower than that of the device gate through the source metal layer, so as to realize the diffusion of the pn junction electric field to the two P-type well regions on both sides, improving the voltage resistance ability; and a P-type source region is provided to reduce the potential of the P-type well region;

[0020] Third, the P-type source region of the present invention forms a pn junction body diode of the device, increasing the contact area between the body diode and the N-type region and improving the freewheeling ability of the body diode;

[0021] IV. A low-resistance region is constructed below the P-type well region of the present invention. Without affecting the function of the device source, the resistance at the edge of the device is reduced after the device is turned on, so that the device current expands towards the edge, achieving the purpose of reducing the total on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0023] Figure 1 It is a schematic diagram of a trench-gate silicon carbide VDMOS with a trench source according to the present invention.

[0024] Figure 2 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 1 .

[0025] Figure 3 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 2 .

[0026] Figure 4 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 3 .

[0027] Figure 5 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 4 .

[0028] Figure 6 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 5 .

[0029] Figure 7 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 6 .

[0030] Figure 8 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 7 .

[0031] Figure 9 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 8 .

[0032] Figure 10 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 9 .

[0033] Figure 11 It is a process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present inventionFigure 10 。

[0034] Figure 12 Process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 One.

[0035] Figure 13 Process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 Two.

[0036] Figure 14 Process cross-section of a trench-gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 Three. Detailed implementation manners

[0037] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part.

[0040] Spatial relationship terms such as "under", "below", "underlying", "beneath", "above", "overlying", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that, in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "over" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0041] As used herein, the singular forms of "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprising" or "having" specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0042] As Figures 1 to 14 shown, an embodiment of the present application provides a method for preparing a trench-gate silicon carbide VDMOS with a trench source, including the following steps:

[0043] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 109; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0044] Step 2: Form a blocking layer 110 above the drift layer 102, etch the blocking layer 110 to form a through hole, and perform ion implantation on the drift layer 102 to form a low-resistance region 103 and a first protrusion 1021;

[0045] Step 3: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, and perform ion implantation on the drift layer 102 to form a first well region 111 and a second protrusion 1022;

[0046] Step 4: Remove the original blocking layer 110, reform the blocking layer 110, etch the blocking layer 110 to form a through hole, and perform ion implantation on the first well region 111 to form a P-type source region 105;

[0047] Step 5: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, perform ion implantation on the drift layer 102 to form a second well region 112, and the P-type well region 104 includes a first well region 111 and a second well region 112;

[0048] Step 6: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, perform ion implantation on the second well region 112 to form an N-type source region 1041;

[0049] Step 7: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, etch the first well region 111 and the drift layer 102, and then oxidize to form an insulating dielectric layer 106, and a trench 1061 is provided in the insulating dielectric layer 106;

[0050] Step 8: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, and deposit metal to form a gate metal layer 107;

[0051] Step 9: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, and etch the P-type source region 105, and then deposit metal to form a first source metal region 1081;

[0052] Step 10: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, and etch the P-type well region 104 and the N-type source region 1041, and then deposit metal to form a second source metal region 1082. The source metal layer 108 includes a first source metal region 1081 and a second source metal region 1082. Remove the barrier layer 110 to complete the preparation.

[0053] In this embodiment, preferably, a first opening (not shown in the figure) is provided on the P-type well region 104, and the P-type source region 105 is disposed in the first opening; a second opening (not shown in the figure) is provided on the P-type source region 105, and the lower part of the source metal layer 108 is disposed in the second opening.

[0054] In this embodiment, preferably, the lower side surface of the gate metal layer 107 is flush with the upper side surface of the second protrusion 1022.

[0055] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the low-resistance region 103.

[0056] In this embodiment, preferably, the doping concentration of the P-type well region 104 is less than the doping concentration of the P-type source region 105.

[0057] Such as Figure 1As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0058] A silicon carbide substrate 101,

[0059] A drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; a first protrusion 1021 is provided on the drift layer 102, a second protrusion 1022 is provided on the first protrusion 1021, and a groove 10221 is provided on the second protrusion 1022;

[0060] A low-resistance region 103, the lower side of the low-resistance region 103 is connected to the upper side of the drift layer 102, and the inner side of the low-resistance region 103 is connected to the outer side of the first protrusion 1021;

[0061] A P-type well region 104, the P-type well region 104 is connected to the upper side of the low-resistance region 103, the upper side of the drift layer 102, the upper side of the first protrusion 1021, the outer side of the second protrusion 1022, and the upper side of the second protrusion 1022; an N-type source region 1041 is provided on the P-type well region 104;

[0062] A P-type source region 105, the P-type source region 105 is connected to the P-type well region 104;

[0063] An insulating dielectric layer 106, the lower part of the insulating dielectric layer 106 is disposed in the groove 10221, and the outer side of the insulating dielectric layer 106 is respectively connected to the P-type well region 104 and the N-type source region 1041; a trench 1061 is provided in the insulating dielectric layer 106;

[0064] A gate metal layer 107, the gate metal layer 107 is disposed in the trench 1061;

[0065] A source metal layer 108, the source metal layer 108 is respectively connected to the P-type source region 105, the P-type well region 104, and the N-type source region 1041;

[0066] And a drain metal layer 109, the drain metal layer 109 is connected to the lower side of the silicon carbide substrate 101.

[0067] In another embodiment of the present invention, the silicon carbide substrate 101, the drift layer 102, and the low-resistance region 103 are all N-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18 cm -3 , the doping concentration of the drift layer 102 is 6-10e16 cm -3 , the doping concentration of the low-resistance region 103 is 1-5e17 cm -3 , the doping concentration of the P-type well region 104 is 6-10e16 cm -3, the doping concentration of the P-type source region 105 is 1-5e19 cm -3 , the material of the insulating dielectric layer 106 can be silicon dioxide, and the doping concentration of the N-type source region 1041 is 2-8e18 cm -3 ; the doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 109 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device; the doping concentration of the P-type well region 104 is to achieve the breakdown voltage of the pn junction structure of the device when the drain of the device bears a high voltage; the doping concentration of the P-type source region 105 is to reduce the potential difference between the source metal layer 108 of the device and the P-type well region 104 and ensure the low potential of the P-type well region 104 of the device; the doping concentration of the N-type low-resistance region 103 is to reduce the resistivity at the edge of the device, distribute the current in the JFET region of the device to the edge, and reduce the on-resistance of the device; the doping concentration of the N-type source region 1041 is to reduce the source contact resistance of the device and reduce the on-resistance of the device;

[0068] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to form a low-resistance ohmic contact with the drain metal layer 109 and reduce the on-resistance of the device. The thickness of the N-type drift layer 102 is 50-100 μm and is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device; the thickness of the second source metal region 1082 is 300 nm, the thickness of the first source metal region is 1.4 μm, the thickness of the P-type source region 105 located below the first source metal region 1081 is 200 nm, and the thickness of the P-type source region 105 located below the second source metal region 1082 is 1.3 μm, and the width is 200 nm; the thickness of the P-type well region 104 directly below the first source metal region 1081 is 1 μm, and the thickness of the P-type well region 104 located below the second source metal region 1082 is 2.3 μm; the thickness of the P-type well region 104 directly below the N-type source region 1041 is 100 nm, the thickness of the N-type source region 1041 is 200 nm, the width of the N-type source region 1041 of the device is 500 nm, the total width of the P-type well region 104 is 2 μm, the width of the insulating dielectric layer 106 is 50% of the device structure width, the gate metal thickness is 600 nm, the bottom thickness of the insulating dielectric layer 106 is 200 nm, the thickness of the N-type low-resistance region 103 is 1 μm, and the width is 800 nm-1 μm, which is to prevent the N-type low-resistance region 103 from affecting the function of the P-type well region 104 above it;

[0069] In this embodiment, the source metal layer 108 and the P-type well region 104 of the device extend into the device through the trench. When the drain of the device bears a large voltage, a pn junction is formed between the N-type drift layer 102 and the P-type well region 104 of the device to achieve voltage withstand, and the problem of breakdown due to high electric field at the corner of the device gate is avoided; when the device bears the drain voltage, it is necessary to ensure that the potential of the P-type well region 104 of the device is lower than that of the device gate, so as to realize the diffusion of the pn junction electric field from the longitudinal direction to the P-type well region 104 regions on the left and right sides, and a first source metal region 1081 is constructed to balance the potential of the P-type well region 104 of the device; in order to reduce the potential of the P-type well region 104, a P-type source region 105 is prepared.

[0070] In addition to reducing the potential, the P-type source region 105 also forms the pn junction body diode of the device, increases the contact area between the body diode and the N-type region, and improves the freewheeling ability of the body diode.

[0071] In this embodiment, an N-type low-resistance region 103 is constructed. After the device is turned on, the resistance at the edge of the device is reduced on the basis of not affecting the function of the device source, so that the device current expands to the edge, achieving the purpose of reducing the total on-resistance.

[0072] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative only and not used to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a trench-gate silicon carbide VDMOS with a trench source, characterized in that: The steps are as follows: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a low-resistance region and a first protrusion; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a first well region and a second protrusion; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the first well region to form a P-type source region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a second well region. The P-type well region includes the first well region and the second well region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the second well region to form an N-type source region; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, etch the first well region and the drift layer, and then oxidize to form an insulating dielectric layer. Grooves are provided in the insulating dielectric layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and etch the P-type source region, and then deposit metal to form a first source metal region; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, and etch the P-type well region and the N-type source region, and then deposit metal to form a second source metal region. The source metal layer includes the first source metal region and the second source metal region. Remove the blocking layer to complete the preparation; The lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a first protrusion is provided on the drift layer, a second protrusion is provided on the first protrusion, and a groove is provided on the second protrusion; The lower side of the low-resistance region is connected to the upper side of the drift layer, and the inner side of the low-resistance region is connected to the outer side of the first protrusion; The P-type well region is connected to the upper side of the low-resistance region, the upper side of the drift layer, the upper side of the first protrusion, the outer side of the second protrusion, and the upper side of the second protrusion; an N-type source region is provided on the P-type well region; The P-type source region is connected to the P-type well region; The lower part of the insulating dielectric layer is provided in the groove, and the outer side of the insulating dielectric layer is respectively connected to the P-type well region and the N-type source region; grooves are provided in the insulating dielectric layer; The gate metal layer is provided in the groove; The source metal layer is respectively connected to the P-type source region, the P-type well region, and the N-type source region.

2. The manufacturing method of a trench gate silicon carbide VDMOS with a trench source according to claim 1, characterized in that: A first opening is provided on the P-type well region, and the P-type source region is provided in the first opening; a second opening is provided on the P-type source region, and the lower part of the source metal layer is provided in the second opening.

3. The manufacturing method of a trench-gate silicon carbide VDMOS with a trench source according to claim 1, wherein: The lower side of the gate metal layer is flush with the upper side of the second protrusion.

4. The manufacturing method of a trench-gate silicon carbide VDMOS with a trench source according to claim 1, characterized in that: The doping concentration of the drift layer is less than that of the low-resistance region.

5. The manufacturing method of a trench-gate silicon carbide VDMOS with a trench source according to claim 1, characterized in that: The doping concentration of the P-type well region is less than that of the P-type source region.

6. A trench-gate silicon carbide VDMOS with a trench source, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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