Manufacturing method of double-gate SOI device

Abstract

The invention relates to a manufacturing method of a double-gate SOI (Silicon On Insulator) device, which comprises the following steps of: 1) forming back gate oxide and a back gate on a first substrate, and planarizing the surface of the first substrate; 2) performing hydrogen ion implantation based on an intelligent stripping technology to form a hydrogen-rich layer; 3) reversing the first substrate and bonding the first substrate with a second substrate wafer; 4) performing wafer stripping to obtain an SOI substrate with a back gate; 5) preparing an SOI device, including a front-end process and a rear-end process; the first substrate at least comprises a P + substrate layer and a P-epitaxial layer, and the P-epitaxial layer of the first substrate is located on the surface of the first substrate; the hydrogen-rich layer formed in the step (2) is located on the P + substrate layer of the first substrate, and the remaining part of the P + substrate layer of the first substrate is removed after wafer stripping is carried out in the step (4), and the surface of the top silicon layer of the SOI substrate of the obtained back grid is free of a step structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a dual-gate SOI device. Summary of the invention

[0002] Silicon-On-Insulator (SOI) introduces a buried oxide layer between the top silicon layer and the back substrate, which not only achieves the isolation of n and p devices and eliminates the parasitic latch-up effect of bulk silicon CMOS; it also achieves the isolation of the device layer from the substrate layer, reduces parasitic capacitance, improves the short channel effect and subthreshold characteristics, and reduces the static power consumption of the circuit. It has significant advantages in the fields of high frequency, low voltage, low power consumption and radiation resistance.

[0003] Dual-gate SOI evolved from single-gate SOI, which can further suppress the short channel effect and reduce leakage current. It has a flexible and adjustable back bias, which can realize the flexibility of device performance regulation, thereby obtaining high-performance device characteristics. However, the traditional dual-gate SOI preparation process is very complicated, and there are great difficulties in the ion doping of the back gate and the realization of back gate silicide. In addition, the cost of SOI wafers remains high, which also limits its scale.

[0004] Recently, the manufacturing process of dual-gate SOI has attempted to introduce smart peeling technology and wafer bonding technology to simplify the process flow and reduce production costs.

[0005] The process flow is summarized as follows: (1) A back gate oxide and a back gate are formed on the substrate 1, and the surface of the substrate 1 is planarized.

[0006] (2) Based on the smart stripping technology, hydrogen ion implantation is performed to form a hydrogen-rich layer.

[0007] (3) Invert substrate 1 and perform wafer bonding with substrate 2.

[0008] (4) Wafer peeling is performed to obtain an SOI substrate with a back gate.

[0009] (5) Preparation of SOI devices, including front-end process and back-end process.

[0010] However, the above dual-gate SOI process has at least one major problem: after step (2) is completed, there is a step in the hydrogen-rich layer, which is specifically manifested as the depth of the hydrogen-rich layer under the back gate is less than the depth of the hydrogen-rich layer under the oxide layer, and the step height difference is close to the gate thickness. After step (4) is completed, a step structure is also formed on the surface of the top silicon layer.

[0011] Therefore, the top silicon layer needs to be flattened, otherwise it will affect the processing of subsequent processes. However, due to the large height difference of the steps and the absence of an etching or grinding stop layer, it is difficult to eliminate the step height difference using wet or chemical mechanical polishing methods. Even if a multi-step chemical mechanical polishing method is used, it is difficult to obtain a flat surface.

[0012] Some methods are to form a step structure opposite to the aforementioned hydrogen-rich layer by patterning the oxide layer after step (1) is completed, thereby obtaining a hydrogen-rich layer with consistent depth, and to flatten the step structure of the oxide layer after step (2) is completed. However, this requires an additional photomask and multiple process steps, and after step (4) is completed, a chemical mechanical polishing process is still required. Summary of the invention

[0013] The present invention provides a method for manufacturing a double-gate SOI device, wherein the surface of the top silicon layer of the SOI substrate of the obtained back gate has no step structure.

[0014] The technical solution of the present invention: A method for manufacturing a dual-gate SOI device, the method comprising: 1) forming a back-gate oxide and a back-gate on a first substrate, and planarizing the surface of the first substrate; 2) performing hydrogen ion implantation based on a smart stripping technique to form a hydrogen-rich layer; 3) inverting the first substrate and bonding it to a second substrate wafer; 4) performing wafer stripping to obtain an SOI substrate with a back-gate; 5) preparing an SOI device, including a front-end process and a back-end process; the first substrate at least comprises a P+ substrate layer and a P-epitaxial layer, the P-epitaxial layer of the first substrate being located on its surface; in step 2), the formed hydrogen-rich layer is located on the P+ substrate layer of the first substrate; in step 4), after performing wafer stripping, removing the remaining portion of the P+ substrate layer of the first substrate.

[0015] The above technical solution is further refined. In step 4), a hydrofluoric acid-nitric acid-acetic acid solution is used to perform wet etching to remove the remaining portion of the P+ substrate layer of the first substrate.

[0016] The above technical solution is further refined. In step 4), after removing the remaining portion of the P-epitaxial layer of the first substrate, a planarization process is performed.

[0017] The above technical solution is further refined, the doping concentration of the P+ substrate is 10 19 cm -3 The doping concentration of the P-epitaxial layer is 10 13 -10 15 cm -3 The thickness of the P-epitaxial layer is orders of magnitude greater than the thickness of the top silicon layer of the SOI substrate having the back gate.

[0018] The above technical solution is further refined. In step 3), before the first substrate and the second substrate wafer are bonded, a second oxide layer is formed on the surface of the second substrate. After the first substrate and the second substrate wafer are bonded, the first oxide layer and the second oxide layer formed on the surface of the first substrate when the surface of the first substrate is flattened in step 1) constitute a buried oxide layer of the SOI substrate with a back gate.

[0019] The above technical solution is further refined. In step 3), low-temperature bonding is adopted when the first substrate and the second substrate wafer are bonded; in step 4), a smart stripping process is adopted when the wafer is stripped; and the bonding temperature is lower than the smart stripping process temperature.

[0020] The above technical solution is further refined, and the etching selectivity ratio of the hydrofluoric acid-nitric acid-acetic acid solution to the P+ substrate layer and the P- epitaxial layer is greater than 80:1.

[0021] The invention has the advantages of reasonable design and simple structure. The P+ substrate layer / P-epitaxial layer is selected as the first substrate, so that the hydrogen-rich layer with a step structure is formed in the P+ substrate layer. The step structure of the P+ substrate layer is removed by utilizing the large etching selectivity of the hydrofluoric acid-nitric acid-acetic acid solution to the P+ substrate layer and the P-epitaxial layer. Only one wet etching process needs to be added to obtain a surface of the top silicon layer of the SOI substrate of the back gate without a step structure. The method simplifies the process flow and reduces the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings show only preferred embodiments. Various features in the drawings are not drawn to scale and the sizes of various features may be changed arbitrarily. These are not considered to be limitations of the present invention.

[0023] Figure 1 It is a cross-sectional view of a dual-gate SOI device according to an embodiment of the present application.

[0024] Figure 2 is a cross-sectional view of a first substrate according to an embodiment of the present application.

[0025] Figure 3 It is a cross-sectional view of a first oxide layer formed on a first substrate according to an embodiment of the present application.

[0026] Figure 4 It is a cross-sectional view of a hydrogen-rich layer formed on a first substrate according to an embodiment of the present application.

[0027] Figure 5 is a cross-sectional view of a second substrate according to an embodiment of the present application.

[0028] Figure 6 It is a cross-sectional view of an embodiment of the present application after the wafer bonding process.

[0029] Figure 7It is a cross-sectional view of an embodiment of the present application after the intelligent stripping process.

[0030] Figure 8 FIG. 4 is a cross-sectional view of an SOI wafer according to an embodiment of the present application.

[0031] Fig. 9 It is a cross-sectional view after forming an interconnection structure according to an embodiment of the present application.

[0032] Fig.10 This is an embodiment of the present application. Fig. 9 Cross-sectional view along line A-A'. DETAILED DESCRIPTION

[0033] In order to make the content and technical advantages of the present invention clearer and easier to understand, the content of the present invention will be fully described below in conjunction with specific embodiments and related drawings. Those skilled in the art should understand that this is only presented as a preferred embodiment, rather than limiting the scope of protection of the present invention. It should be understood that the present invention is not limited to some specific embodiments, that is, some of the specific embodiments described are only part of the embodiments of the present invention, rather than all of the embodiments. Any changes and modifications made by those skilled in the art based on the content are within the scope of protection of the present invention.

[0034] like Figure 1 As shown, a dual-gate SOI device includes: an SOI substrate with a back gate composed of a second substrate 200, a buried oxide layer 202, a back gate 103 and the back gate oxide 102, and a top silicon layer 101, an isolation structure 301, a positive gate oxide 302, a positive gate 303, a sidewall 304, a source and a drain 305, a metal silicide 306, and an interconnection structure composed of a contact plug 308 and a metal interconnection layer 310; the buried oxide layer 202 is located above the second substrate 200, the back gate 103 and the back gate oxide 102 are located in the buried oxide layer 202, and the back gate 103 is located in the back gate oxide 102, the top surface of the back gate oxide 102 is flush with the top surface of the buried oxide layer 202, the top silicon layer 101 is located above the buried oxide layer 202 and the back gate oxide 102, the bottom surface of the isolation structure 301 is placed in the buried oxide layer 202, and the top surface is higher than or flat with the top surface of the top silicon layer 101, the positive gate oxide 302 is located above the top silicon layer 101, the positive gate 303 is located above the positive gate oxide 302, the sidewalls 304 are located on both sides of the positive gate oxide 302 and the positive gate 303, and the source and drain 305 are located in the top silicon layer 101 on both sides of the positive gate 303; the thickness of the top silicon layer 101 is between 40-1000nm.

[0035] like Figure 2-Figure 10 As shown, the manufacturing method of the above dual-gate SOI device is described in detail below in conjunction with the embodiments and drawings.

[0036] refer to Figure 2, providing a first substrate 100, wherein the first substrate 100 comprises a P+ substrate layer 100A and a P- epitaxial layer 100B, and the first substrate 100 is, for example, silicon, germanium, silicon germanium or any other suitable semiconductor material. Alternatively, the first substrate 100 is a silicon epitaxial wafer, and the doping concentration ratio of the P+ substrate layer 100A to the P- epitaxial layer 100B is higher than 10 4 , with a flush interface between them.

[0037] refer to Figure 3 , a back gate oxide 102 is formed on the P-epitaxial layer 100B. The material of the back gate oxide 102 can be silicon oxide, silicon nitride or silicon oxynitride, etc., and the formation method can be wet and / or dry thermal oxidation, in-situ water vapor generation and other processes. The back gate oxide 102 contains at least one thickness of gate oxide, and the thickness is between 4-20nm. Alternatively, the back gate oxide 102 is silicon oxide, and the formation method is wet and / or dry thermal oxidation, and the growth temperature is between 700-900℃. Alternatively, the back gate oxide 102 is silicon oxynitride. Specifically, silicon oxide is formed first and then a nitridation process is performed. The nitridation process includes but is not limited to thermal treatment nitridation, plasma nitridation, etc. When the back gate oxide 102 contains two or more thicknesses of gate oxide, the back gate oxide 102 is processed in order from high to low thickness, including but not limited to thin film deposition, photolithography, etching and other processes.

[0038] A back gate 103 is formed on the back gate oxide 102. The material of the back gate 103 can be doped or undoped amorphous or polycrystalline silicon, or other conductive materials such as metals, and its thickness is between 40-100nm. The specific formation method includes but is not limited to low-pressure chemical vapor deposition, photolithography, dry etching, ashing and degumming, ion doping, annealing and other processes. The patterning process of the back gate 103 also includes patterning the back gate oxide 102. Alternatively, the back gate 103 is doped amorphous or polycrystalline silicon deposited by low-pressure chemical vapor deposition. When the doping type is N-type, P-type ion doping is required for the PMOS region, and the amorphous or polycrystalline silicon in the PMOS region is reversed from N-type to P-type through impurity compensation; when the doping type is P-type, N-type ion doping is required for the NMOS region, and the amorphous or polycrystalline silicon in the NMOS region is reversed from P-type to N-type through impurity compensation. Alternatively, the back gate 103 is undoped amorphous or polycrystalline silicon deposited by low-pressure chemical vapor deposition. N-type doping is performed on the NMOS region and P-type doping is performed on the PMOS region, or N-type doping is performed only on the NMOS region.

[0039] A first oxide layer 104 is deposited on the back gate 103 and the P-epitaxial layer 100B by a deposition method such as plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, etc., and the deposition thickness is between 200-400nm; then, a chemical mechanical polishing process is performed to form a flat surface, and the top surface of the first oxide layer 104 is 40-100nm higher than the top surface of the back gate 103.

[0040] refer to Figure 4 , hydrogen ion implantation or hydrogen and helium ion co-implantation is performed on the front side of the first substrate 100, with an implantation energy of 40-100 keV, to form a hydrogen-rich layer 106 inside the P+ substrate layer 100A.

[0041] It should be pointed out that hydrogen and helium ions have stronger penetration power in the oxide layer than in amorphous or polycrystalline silicon. Therefore, as a result, there are steps in the hydrogen-rich layer 106. Specifically, the depth of the hydrogen-rich layer below the back gate 103 is less than the depth of the hydrogen-rich layer below the first oxide layer 104. The step height difference is between 40-100nm, which is close to the thickness of the back gate 103.

[0042] It should also be noted that the top surface of the step of the hydrogen rich layer 106 is 10-30 nm below the P- / P+ interface.

[0043] refer to Figure 5 , provide a second substrate 200, which may be silicon, germanium, silicon germanium or any other suitable semiconductor material.

[0044] A second oxide layer 201 is formed on the second substrate 200 by wet and / or dry thermal oxidation, chemical vapor deposition, etc. The thickness of the second oxide layer 201 is between 10-20 nm.

[0045] refer to Figure 6 , flip the first substrate 100 so that the first oxide layer 104 faces downward and contacts face-to-face with the second oxide layer 201 on the second substrate 200, and perform a wafer bonding process.

[0046] Before wafer bonding, wafer cleaning and surface activation processes are performed on the surface of the first oxide layer 104 and the surface of the second oxide layer 201 .

[0047] It should be pointed out that since the hydrogen-rich layer 106 will form bubbles in the silicon wafer at 300°C, the wafer bonding process is a low-temperature direct bonding process, including but not limited to wafer cleaning, wafer surface activation, wafer pre-bonding and annealing, and the wafer bonding temperature is lower than 300°C.

[0048] After wafer bonding, the first oxide layer 104 and the second oxide layer 201 together form a buried oxide layer 202 .

[0049] refer to Figure 7, an intelligent stripping process is performed on the bonded wafer. Specifically, the annealing temperature is increased to 300-400°C, a bubble layer is formed in the hydrogen-rich layer 106, and microcracks are generated along the hydrogen-rich layer 106 due to the increase in the bubble layer, thereby achieving wafer stripping of the P+ substrate layer 100A along the hydrogen-rich layer 106. The wafer structure after stripping is from bottom to top: a second substrate 200, a buried oxide layer 202, a P- epitaxial layer 100B, and a P+ substrate layer 107 with a step structure.

[0050] After completing smart stripping, a high-temperature annealing process is also implemented to enhance the wafer bonding strength. The annealing temperature is between 900-1100℃.

[0051] The P+ substrate layer 107 with a step structure is wet-etched by using a single-wafer rotary spray method and a hydrofluoric acid-nitric acid-acetic acid solution (HNA solution) as an etching solution. The wet etching stops at the P-epitaxial layer 100B. The HNA solution is used for the P+ (10 19 cm -3 ) and P-(10 15 cm -3 ) has an etching selectivity greater than 80:1. The high etching selectivity ensures that while the P+ substrate layer 107 with a step structure is removed, there is less etching loss on the P- epitaxial layer 100B.

[0052] It should be understood that after the wet etching is completed, the step structure on the P+ substrate layer 107 is transferred to the P- epitaxial layer 100B, but the step height difference is reduced from 40-100 nm to a few nm level.

[0053] Furthermore, at least one chemical mechanical polishing process is performed to eliminate the step height difference and improve the surface roughness on the one hand, and to reduce the thickness of the P-epitaxial layer 100B to the same thickness as the top silicon layer 101 on the other hand. It should be noted that after the P-epitaxial layer 100B is thinned, it is called the top silicon layer 101.

[0054] Optionally, when performing a multi-pass chemical mechanical polishing process, a wet etching process is further performed before performing the second and subsequent chemical mechanical polishing processes.

[0055] refer to Figure 8 After the above processes, an SOI wafer supported by the first substrate 200 and having a back gate oxide 102 , a back gate 103 , a buried oxide layer 202 and a top silicon layer 101 is obtained.

[0056] refer to Fig. 9 and Fig.10 , an isolation structure 301 is formed in the top silicon layer 101, such as shallow trench isolation or local oxidation isolation, and the isolation structure is used to prevent electrical interference between adjacent devices.

[0057] Taking shallow trench isolation as an example, a hard mask layer (not shown) is deposited on the top silicon layer 101. The material may be silicon nitride. Then, photolithography and etching processes are implemented. The etching is divided into at least two steps. The first step is to use photoresist as a mask to etch the hard mask layer and stop at the top silicon layer 101. The second step is to use the hard mask layer as a mask to etch the top silicon layer 101 and stop at the buried oxide layer 202 to form an isolation trench. The bottom surface of the isolation trench is lower than the interface between the top silicon layer 101 and the buried oxide layer 202.

[0058] An insulating medium is filled in the isolation trench. The material may be silicon oxide or the like. The formation method may be high-density plasma chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition. Chemical mechanical polishing is performed and stops at the hard mask layer. Wet etching is performed to remove the hard mask layer on the top silicon layer 101.

[0059] Before removing the hard mask layer by wet etching, a wet etching is further performed to adjust the height of the top surface of the isolation structure 301 , so that the top surface of the isolation structure 301 is higher than or level with the top surface of the top silicon layer 101 .

[0060] An N-well and a P-well are formed in the top silicon layer 101, and an N-type impurity, which may be P or As, is doped in the N-well region, and a P-type impurity, which may be B, is doped in the P-well region. Specific processes include but are not limited to photolithography, ion implantation, ashing and degumming, etc. Alternatively, the N-well and the P-well are not formed to avoid the random impurity fluctuation effect, so as to maintain a stable threshold voltage and avoid the degradation of carrier mobility.

[0061] A positive gate oxide 302 is formed on the top silicon layer 101. The material may be silicon oxide, silicon nitride or silicon oxynitride, etc. The formation method may be wet and / or dry thermal oxidation, low pressure chemical vapor deposition, in-situ water vapor generation and other processes. The positive gate oxide 302 contains at least one thickness of gate oxide, and the thickness is between 4-20nm. Optionally, the positive gate oxide 302 is silicon oxide, and the formation method is wet and / or dry thermal oxidation, and the growth temperature is between 700-900°C. Alternatively, the positive gate oxide 302 is silicon oxynitride. Specifically, silicon oxide is formed first and then a nitridation process is performed. The nitridation process includes but is not limited to thermal treatment nitridation, plasma nitridation and the like. When the positive gate oxide 302 contains two or more thicknesses of gate oxide, the positive gate oxide 302 is processed in order from high to low thickness, including but not limited to thin film deposition, photolithography, etching and other processes.

[0062] A positive gate 303 is formed on the positive gate oxide 302 . The positive gate 303 and the back gate 103 are made of the same material and formed by the same process, including but not limited to deposition, photolithography, etching, ion implantation, etc. The patterning process of the positive gate 303 also includes patterning the positive gate oxide 302 .

[0063] A sidewall 304 is formed on the side of the positive gate 303. The material may be a double-layer structure of silicon oxide / silicon nitride or a triple-layer structure of silicon oxide / silicon nitride / silicon oxide. The formation method includes low-pressure chemical vapor deposition and anisotropic plasma etching.

[0064] The source and drain 305 are formed in the top silicon layer 101 on both sides of the sidewall 304 by an ion implantation process, wherein the source, drain and gate of the NMOS device are heavily doped with N-type, such as As or P; and the source, drain and gate of the PMOS device are heavily doped with P-type, such as B or In. Optionally, before forming the source and drain 305 structure, a source and drain extension structure is also formed. Optionally, a raised source / drain process is used to form the source and drain 305 in the top silicon layer 101 on both sides of the sidewall 304, wherein the source and drain of the NMOS device are SiC epitaxial layer with in-situ N-type doping, such as As or P; and the source and drain of the PMOS device are SiGe epitaxial layer with in-situ P-type doping, such as B or In.

[0065] The lattice damage is repaired and the doped ions are activated by a spike rapid thermal process, with an annealing temperature between 1000-1100°C and an annealing time between 0.5-2s. Alternatively, in addition to the spike rapid thermal process, a millisecond laser annealing process is also used.

[0066] A metal silicide 306 is formed on the back gate 103, the positive gate 303, the source and the drain 305. Two patterning processes are used. The first patterning process opens the metallization area of ​​the back gate 103. After depositing a layer of oxide, the second patterning process opens the metallization area of ​​the back gate 103, the positive gate 303, the source and the drain 305. The formation of the metal silicide 306 includes: depositing a layer of metal, such as titanium, cobalt, nickel; depositing a layer of titanium nitride; performing a rapid thermal annealing to form metal silicide; and wet etching to remove unreacted metal. Optionally, before the metal silicide process, amorphization ion implantation is also performed to amorphize the surface of the source and drain 305 to reduce the reaction temperature of the metal silicide.

[0067] Furthermore, an interlayer dielectric layer 307 is formed, and the interlayer dielectric layer 307 at least includes an etching stop layer located at the bottom layer and a dielectric layer at the upper layer. The material of the etching stop layer can be silicon nitride, and the material of the dielectric layer can be silicon oxide. A chemical mechanical polishing process is implemented to flatten the surface of the interlayer dielectric layer 307, and the vertical distance between the top surface of the interlayer dielectric layer 307 and the top surface of the top silicon layer 101 is between 0.3-0.5μm.

[0068] A contact plug 308 is formed inside the interlayer dielectric layer 307, including a contact plug 308A connected to the back gate 103, and a contact plug 308B connected to the positive gate 303, the source and the drain 305. The formation process includes: a patterning process; depositing an adhesion layer (not shown), such as titanium / titanium nitride; filling a conductive material, such as a metal material such as tungsten; a chemical mechanical polishing process, etc. Optionally, the patterning process of the contact plug 308 includes two times, the first patterning process is only for the contact plug 308A, and its etching stops inside the interlayer dielectric layer 307, and the second patterning process is for the contact plugs 308A and 308B, and its etching first stops at the etching barrier layer, and then etches the etching barrier layer and stops at the metal silicide 306.

[0069] A metal interconnection structure 310 is formed in the interlayer dielectric layer 307 and the intermetallic dielectric layer 309 on the contact plug 308 , including multiple metal layers and conductive plugs between two adjacent metal layers. The metal interconnection structure 310 is connected to the contact plug 308 .

[0070] It should be understood that in the above-mentioned specific embodiments, the terms used when describing the specific embodiments of the present invention, such as "upper", "lower", "front", "back", "side", "vertical" and other terms describing the orientation or position relationship, only refer to the orientation or position relationship in the drawings, and do not indicate or imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation.

[0071] In addition, it should be understood that when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention for the convenience of explanation, the structures in the accompanying drawings are not drawn according to general proportions, and are partially enlarged, deformed and simplified. Therefore, it should be avoided to understand this as a limitation of the present invention.

Claims

1. A method for manufacturing a dual-gate SOI device, the method comprising: 1) forming a back gate oxide and a back gate on a first substrate, and planarizing the surface of the first substrate; 2) Based on the smart stripping technology, hydrogen ion implantation is performed to form a hydrogen-rich layer; 3) The first substrate is reversed and bonded to the second substrate wafer; 4) Wafer peeling is performed to obtain an SOI substrate with a back gate; 5) Preparing an SOI device, including a front-end process and a back-end process; characterized in that the first substrate at least comprises a P+ substrate layer and a P-epitaxial layer, and the P-epitaxial layer of the first substrate is located on its surface; In step 2), the formed hydrogen-rich layer is located on the P+ substrate layer of the first substrate; In step 4), after wafer stripping, the remaining portion of the P+ substrate layer of the first substrate is removed.

2. The method for manufacturing a dual-gate SOI device according to claim 1, characterized in that: In step 4), a hydrofluoric acid-nitric acid-acetic acid solution is used to perform wet etching to remove the remaining portion of the P+ substrate layer of the first substrate.

3. The method for manufacturing a dual-gate SOI device according to claim 1, characterized in that: In step 4), after removing the remaining portion of the P+ substrate layer of the first substrate, a planarization process is performed.

4. The method for manufacturing a dual-gate SOI device according to claim 1, characterized in that: The doping concentration of the P+ substrate is 10 19 cm -3 The doping concentration of the P-epitaxial layer is 10 13 -10 15 cm -3 The thickness of the P-epitaxial layer is orders of magnitude greater than the thickness of the top silicon layer of the SOI substrate having the back gate.

5. The method for manufacturing a dual-gate SOI device according to claim 1, characterized in that: In step 3), before the first substrate is bonded to the second substrate wafer, a second oxide layer is formed on the surface of the second substrate. After the first substrate is bonded to the second substrate wafer, the first oxide layer and the second oxide layer formed on the surface of the first substrate when the surface of the first substrate is planarized in step 1) constitute a buried oxide layer of the SOI substrate with a back gate.

6. The method for manufacturing a dual-gate SOI device according to claim 1, characterized in that: In step 3), low temperature bonding is used when bonding the first substrate and the second substrate wafer; In step 4), a smart stripping process is used when stripping the wafer; The bonding temperature is lower than the smart peel process temperature.

7. The method for manufacturing a dual-gate SOI device according to claim 2, characterized in that: The etching selectivity ratio of the hydrofluoric acid-nitric acid-acetic acid solution to the P+ substrate layer and the P- epitaxial layer is greater than 80:1.

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