Semiconductor device and apparatus

Abstract

The invention discloses a semiconductor device and an apparatus. A semiconductor device according to the present invention comprises: a semiconductor element including a cell array and a plurality of wirings; and a semiconductor component including a plurality of pads connected to the semiconductor component including the cell array. A first row pad connected to a row wiring connected to the first cell and the second cell, a second row pad connected to a row wiring connected to the third cell and the fourth cell and a column pad connected to a column wiring connected to the first cell and the third cell are arranged such that a straight line connecting the first row pad and the column pad intersects a straight line connecting the second row pad and the column pad.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 202010563480.8, application date June 19, 2020, and titled “Semiconductor Devices and Equipment”. Technical Field

[0002] The present invention relates to a semiconductor device including a plurality of semiconductor components. Background Art

[0003] If a semiconductor component including a cell array overlaps with another semiconductor component electrically connected to the cell array, the semiconductor device may have higher performance, may be reduced in size, or may have higher integration.

[0004] Japanese Patent Application Laid-Open No. 2010-225927 discloses a solid-state imaging device in which a first chip including a plurality of pixels and a second chip including a plurality of pixel driving circuits and stacked over the first chip are electrically connected to each other via connection pads.

[0005] The study of the arrangement of the connection pads in Japanese Patent Application Laid-Open No. 2010-225927 is insufficient, and there is a need to improve the characteristics and yield of wiring between chips. Summary of the invention

[0006] The present invention provides a technology that contributes to increasing the value of a semiconductor device.

[0007] According to a first aspect of the present invention, a semiconductor device is provided, which includes: a first semiconductor component including a cell array and a plurality of wirings; and a second semiconductor component including a plurality of pads connected to the first semiconductor component. The first semiconductor component and the second semiconductor component overlap each other. The cell array includes a plurality of cells arranged in a first direction and a second direction intersecting the first direction. A plurality of pads are arranged on a plane along the first direction and the second direction to overlap with the cell array. The plurality of cells include a first cell, a second cell arranged adjacent to the first cell in the first direction, a third cell arranged adjacent to the first cell in the second direction, and a fourth cell arranged adjacent to the third cell in the first direction and adjacent to the second cell in the second direction. The plurality of wirings include a first wiring connected to the first cell and the second cell, a second wiring connected to the third cell and the fourth cell, and a third wiring connected to the first cell and the third cell. The plurality of pads include a first pad connected to the first wiring, a second pad connected to the second wiring, and a third pad connected to the third wiring. The first pad, the second pad, and the third pad are arranged so that a straight line connecting the first pad and the third pad intersects a straight line connecting the second pad and the third pad.

[0008] According to a second aspect of the present invention, there is provided a semiconductor device, which includes: a first semiconductor component including a cell array and a plurality of wirings; and a second semiconductor component including a pad array connected to the first semiconductor component. The first semiconductor component and the second semiconductor component overlap each other. The cell array includes a plurality of cells arranged in a matrix. The pad array includes a plurality of pads arranged in a matrix to overlap with the cell array. The plurality of wirings include a plurality of row wirings each connected to two or more cells in the same cell row of the cell array and arranged in the corresponding cell rows of the cell array, and a plurality of column wirings each connected to two or more cells in the same cell column of the cell array and arranged in the corresponding cell columns of the cell array. A first row pad connected to a first row wiring among the plurality of row wirings and a second row pad connected to a second row wiring among the plurality of row wirings are arranged in different pad columns of the pad array.

[0009] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A semiconductor device is schematically shown.

[0011] Figure 1B A semiconductor device is schematically shown.

[0012] Figure 2A A semiconductor device is schematically shown.

[0013] Figure 2B A semiconductor device is schematically shown.

[0014] Figure 3A A semiconductor device is schematically shown.

[0015] Figure 3B A semiconductor device is schematically shown.

[0016] Figure 4A A semiconductor device is schematically shown.

[0017] Figure 4B A semiconductor device is schematically shown.

[0018] Figure 5A A semiconductor device according to an example is schematically illustrated.

[0019] Figure 5B A semiconductor device according to an example is schematically illustrated.

[0020] Figure 5C A semiconductor device according to an example is schematically illustrated.

[0021] Fig. 6AA semiconductor device according to a first example is schematically shown.

[0022] Figure 6B A semiconductor device according to a first example is schematically shown.

[0023] Figure 6C A semiconductor device according to a first example is schematically shown.

[0024] Fig. 7A A semiconductor device according to a second example is schematically shown.

[0025] Figure 7B A semiconductor device according to a second example is schematically shown.

[0026] Figure 7C A semiconductor device according to a second example is schematically shown.

[0027] Fig. 8A A semiconductor device according to a third example is schematically shown.

[0028] Figure 8B A semiconductor device according to a third example is schematically shown.

[0029] Figure 8C A semiconductor device according to a third example is schematically shown.

[0030] Fig.9A A semiconductor device according to a fourth example is schematically shown.

[0031] Fig. 9B A semiconductor device according to a fourth example is schematically shown.

[0032] Fig. 9C A semiconductor device according to a fourth example is schematically shown.

[0033] Fig. 10A A semiconductor device according to a fifth example is schematically shown.

[0034] Fig. 10B A semiconductor device according to a fifth example is schematically shown.

[0035] Fig. 10C A semiconductor device according to a fifth example is schematically shown.

[0036] Fig.11 Semiconductor devices and equipment are schematically shown. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments for implementing the present invention will be described with reference to the accompanying drawings. In the following description and the accompanying drawings, common components in multiple drawings are assigned common reference numerals. Therefore, such common components are described by cross-referencing the accompanying drawings, and the description of the components assigned common reference numerals will be appropriately omitted.

[0038] Figure 1A is a schematic cross-sectional view of a semiconductor device 930, and Figure 1B is a schematic plan view of a semiconductor device 930. Figure 1A As shown in , the semiconductor device 930 includes a semiconductor component 101 and a semiconductor component 201. The semiconductor component 101 includes a semiconductor layer 100 and a wiring structure 110 above the semiconductor layer 100. The wiring structure 110 of the semiconductor component 101 includes a plurality of conductive layers and an insulating member 120 at the periphery of the plurality of conductive layers, the plurality of conductive layers including a conductive layer 10, a conductive layer 20, and a conductive layer 30. The semiconductor component 201 includes a semiconductor layer 200 and a wiring structure 210 above the semiconductor layer 200. The wiring structure 210 of the semiconductor component 201 includes a plurality of conductive layers including a conductive layer 40 and an insulating member 220 at the periphery of the plurality of conductive layers. In this example, the semiconductor component 101 and the semiconductor component 201 are bonded to each other at a bonding surface 300.

[0039] like Figure 1B As shown in , the semiconductor component 101 includes a cell array 1234. The cell array 1234 extends in the X direction and the Y direction. The Y direction intersects the X direction. Although the Y direction is orthogonal to the X direction in this example, the Y direction may be inclined relative to the X direction.

[0040] like Figure 1A As shown in , the semiconductor component 201 overlaps the semiconductor component 101 in the Z direction. The Z direction intersects the X direction and the Y direction. Although the Z direction is orthogonal to the X direction and the Y direction in this example, the Z direction may be inclined relative to the X direction and the Y direction.

[0041] like Figure 1B As shown in , the cell array 1234 includes cell 1, cell 2, cell 3, and cell 4. Cell 1 and cell 2 are arranged side by side in the X direction. Cell 1 and cell 3 are arranged side by side in the Y direction. Cell 3 and cell 4 are arranged side by side in the X direction. Cell 2 and cell 4 are arranged side by side in the Y direction. A group of multiple cells arranged in the X direction will be referred to as a cell row, and a group of multiple cells arranged in the Y direction will be referred to as a cell column.

[0042] Each cell in the cell array 1234 includes at least one semiconductor element. The semiconductor element herein is generally a transistor, and may also be a diode or a thyristor. In addition, the semiconductor element is not limited to an active element, and may be a passive element such as a resistor or a capacitor. Cell 1 includes a semiconductor element 61, cell 2 includes a semiconductor element 62, cell 3 includes a semiconductor element 63, and cell 4 includes a semiconductor element 64. Semiconductor elements 61, 62, 63, and 64 may have substantially equivalent functions. Cell 1 also includes a semiconductor element 71, cell 2 also includes a semiconductor element 72, cell 3 also includes a semiconductor element 73, and cell 4 also includes a semiconductor element 74. Semiconductor elements 71, 72, 73, and 74 may have, but are not limited to, substantially equivalent functions. Semiconductor elements 61, 62, 63, and 64 may have, but are not limited to, functions different from semiconductor elements 71, 72, 73, and 74.

[0043] The semiconductor component 101 includes a plurality of wirings. The wiring connecting at least two cells included in the same cell row will be referred to as row wiring, and the wiring connecting at least two cells included in the same cell column will be referred to as column wiring. The plurality of wirings consisting of row wiring and column wiring will be referred to as matrix wiring. The plurality of wirings (matrix wiring) of the semiconductor component 101 include row wiring 11, row wiring 12, column wiring 21, and column wiring 22. The row wiring 11 is connected to cell 1 and cell 2. The row wiring 12 is connected to cell 3 and cell 4. The column wiring 21 is connected to cell 1 and cell 3. The column wiring 22 is connected to cell 2 and cell 4. The column wiring 22 may also be connected to cell 2 and another cell arranged next to cell 2 in the Y direction instead of cell 4. That is, a certain cell row includes cell 1 and cell 2 connected via row wiring 11, and another cell row includes cell 3 and cell 4 connected via row wiring 12. In addition, a certain cell column includes cell 1 and cell 3 connected via column wiring 21, and another cell column includes cell 2 and cell 4 connected via column wiring 22.

[0044] The connection between the cells and the wiring will be described in more detail. The row wiring 11 is shared by the semiconductor element 61 of the cell 1 and the semiconductor element 62 of the cell 2. The row wiring 12 is shared by the semiconductor element 63 of the cell 3 and the semiconductor element 64 of the cell 4. The column wiring 21 is shared by the semiconductor element 71 of the cell 1 and the semiconductor element 73 of the cell 3. The column wiring 22 is shared by the semiconductor element 72 of the cell 2 and the semiconductor element 74 of the cell 4.

[0045] For example, a common signal is input to semiconductor elements 61 and 62 through row wiring 11, and a common signal is input to semiconductor elements 63 and 64 through row wiring 12. In addition, for example, signals from semiconductor elements 71 and 73 are output to column wiring 21, and signals from semiconductor elements 72 and 74 are output to column wiring 22. In the following description, for convenience, a signal is input to a cell through a row wiring, and a signal from a cell is output to a column wiring. However, a signal may be input to a cell through a column wiring, and a signal from a cell may be output to a row wiring.

[0046] The semiconductor component 201 includes a pad array 4321. In the pad array 4321, a large number of conductive pads are arranged in the XY plane. The pad array 4321 includes a plurality of conductive pads arranged to overlap with the cell array 1234 in the XY plane. Each of the plurality of conductive pads arranged to overlap with the cell array 1234 in the XY plane will be referred to as an overlapping pad. In addition to the plurality of overlapping pads arranged to overlap with the cell array 1234 in the XY plane, a large number of conductive pads in the pad array 4321 may also include at least one non-overlapping pad arranged not to overlap with the cell array 1234. All conductive pads in the pad array 4321 may be arranged to overlap with the cell array 1234.

[0047] The plurality of overlapping pads in the semiconductor component 201 include row pads 41, row pads 42, column pads 43, and column pads 44. The row pads 41, row pads 42, column pads 43, and column pads 44 are arranged to overlap with the cell array 1234 in the Z direction where the semiconductor component 101 and the semiconductor component 201 overlap each other. The row pad 41 is connected to the row wiring 11. The row pad 42 is connected to the row wiring 12. The column pad 43 is connected to the column wiring 21. The column pad 44 is connected to the column wiring 22. The row pad 41 and the column pad 43 can be arranged side by side in one of the X direction and the Y direction (in the Y direction in this example). In addition, the row pad 42 and the column pad 44 can be arranged side by side in the other of the X direction and the Y direction (in the X direction in this example). However, since the plurality of pads of the pad array may be arranged independently of arrangement of cells of the cell array, the pads need not be arranged in the direction in which the cells are arranged and, for example, row pads and column pads may be arranged obliquely relative to cell columns and cell rows.

[0048] More specifically, semiconductor component 201 includes circuit 51, circuit 52, circuit 53, and circuit 54. Row pad 41 is connected to circuit 51, row pad 42 is connected to circuit 52, column pad 43 is connected to circuit 53, and column pad 44 is connected to circuit 54.

[0049] The semiconductor component 101 includes a pad array. In the pad array, a large number of conductive pads are arranged in an XY plane. The pad array includes a plurality of conductive pads arranged to overlap with the cell array 1234 in the XY plane. Each of the plurality of conductive pads arranged to overlap with the cell array 1234 in the XY plane will be referred to as an overlapping pad. A large number of conductive pads in the pad array may also include at least one non-overlapping pad arranged not to overlap with the cell array 1234 in addition to a plurality of overlapping pads arranged to overlap with the cell array 1234 in the XY plane. All conductive pads in the pad array may be arranged to overlap with the cell array 1234.

[0050] The plurality of overlapping pads in the semiconductor component 101 include a row pad 31, a row pad 32, a column pad 33, and a column pad 34. The row pad 31, the row pad 32, the column pad 33, and the column pad 34 are arranged to overlap with the cell array 1234 in the Z direction in which the semiconductor component 101 and the semiconductor component 201 overlap each other. The row pad 31 is connected to the row wiring 11. The row pad 32 is connected to the row wiring 12. The column pad 33 is connected to the column wiring 21. The column pad 34 is connected to the column wiring 22.

[0051] Row pads 31 and row pads 41 are electrically connected to each other, row pads 32 and row pads 42 are electrically connected to each other, column pads 33 and column pads 43 are electrically connected to each other, and column pads 34 and column pads 44 are electrically connected to each other. Therefore, as described above, row pads 41 are connected to row wiring 11, row pads 42 are connected to row wiring 12, column pads 43 are connected to column wiring 21, and column pads 44 are connected to column wiring 22. In addition, circuit 51 is connected to row wiring 11 via row pads 41 and row pads 31, and circuit 52 is connected to row wiring 12 via row pads 42 and row pads 32. In addition, circuit 53 is connected to column wiring 21 via column pads 43 and column pads 33, and circuit 54 is connected to column wiring 22 via column pads 44 and column pads 34.

[0052] In this example, row pads 41 and 42 and column pads 43 and 44 are directly bonded to corresponding row pads 31 and 32 and column pads 33 and 34 at bonding surface 300, respectively. Row pads 41 and 42 and column pads 43 and 44 can be bonded to row pads 31 and 32 and column pads 33 and 34 by metal bonds. Suitable materials for such conductive pads directly bonded by metal bonds include copper, gold and alloys thereof, or can be any conductive material other than copper or gold. Alternatively, bumps such as solder can be provided between row pads 41 and 42 and column pads 43 and 44 and row pads 31 and 32 and column pads 33 and 34, and row pads 41 and 42 and column pads 43 and 44 can be bonded to row pads 31 and 32 and column pads 33 and 34 via bumps. In this example, the insulating member 120 of the wiring structure 110 is directly bonded to the insulating member 220 of the wiring structure 210 at the bonding surface 300. The insulating member 120 and the insulating member 220 may be bonded by covalent bonds. Suitable materials for such insulating members directly bonded by covalent bonds include silicon oxide and silicon nitride, or may be any insulating material other than silicon oxide or silicon nitride. Alternatively, an adhesive such as a resin may be provided between the insulating member 120 and the insulating member 220, and the insulating member 120 and the insulating member 220 may be bonded by the adhesive.

[0053] Pad array 4321 may include dummy pads that are not connected to a circuit in semiconductor component 201 or a circuit in semiconductor component 101. Dummy pads included in pad array 4321 may be bonded to dummy pads in pad array included in semiconductor component 101. Providing dummy pads is advantageous in terms of increasing uniformity of bonding surface 300 and mechanical and / or electrical reliability of bonding between components.

[0054] This embodiment is characterized by the arrangement of row pads 41 and 42 and column pads 43 and 44. Since row pads 31 and 32 are bonded to row pads 41 and 42, the arrangement of row pads 31 and 32 is substantially the same as the arrangement of row pads 41 and 42. Furthermore, since column pads 33 and 34 are bonded to column pads 43 and 44, the arrangement of column pads 33 and 34 is substantially the same as the arrangement of column pads 43 and 44. Therefore, the description of the arrangement of row pads 31 and 32 and column pads 33 and 34 will be omitted.

[0055] The row pads 41, the row pads 42, and the column pads 43 are arranged so that the straight line A connecting (passing through) the row pads 41 and the column pads 43 in the XY plane perpendicular to the Z direction intersects with the straight line B connecting (passing through) the row pads 42 and the column pads 43. The row pads 41, the row pads 42, and the column pads 44 are arranged so that the straight line C connecting (passing through) the row pads 41 and the column pads 44 in the XY plane perpendicular to the Z direction intersects with the straight line D connecting (passing through) the row pads 42 and the column pads 44. It should be noted that each of the straight lines A, B, C, and D is a straight line connecting (passing through) the row pads connected to the row wiring and the column pads connected to the column wiring. In addition, it should also be noted that the row wiring and the column wiring to which the two pads for any one of the straight lines A, B, C, and D are connected (passed through) are connected in the same unit. For example, the row pad 41 and the column pad 43 for the straight line A are respectively connected to the row wiring 11 and the column wiring 21 connected in the same unit 1. For example, the row pad 42 and the column pad 43 for the straight line B are respectively connected to the row wiring 12 and the column wiring 21 connected in the same unit 3. This arrangement of three pads defined by straight line A and straight line B or three pads defined by straight line C and straight line D will be referred to as a triangular arrangement, because if the three pads constituting the triangular arrangement are connected to each other, a triangle is formed. This triangle is typically but not limited to a right triangle, or may be an equilateral triangle or an isosceles triangle. Note that the row pad 41, the column pad 43 and the column pad 44 also have a triangular arrangement, and the row pad 42, the column pad 43 and the column pad 44 also have a triangular arrangement. By adopting a triangular arrangement, multiple overlapping pads can be arranged in a good manner.

[0056] For example, the discussion will be Figure 1BDifferent cases where row pads 42 are arranged above cell 3. In this case, if column pads 43 are arranged above cell 3, the interval between column pads 43 and row pads 42 can be very short. Alternatively, if column pads 43 are not arranged above cell 3, non-overlapping pads replacing column pads 43 need to be arranged at positions that do not overlap with cell array 1234. Although column pads 43 can be arranged above cell 4, this situation increases the wiring path between column pads 43 and column wiring 21, thereby increasing wiring resistance or wiring capacitance and causing RC delay. In contrast, by shifting row pads 42 relative to row pads 41 in the X direction, that is, by changing the position of row pads 42 to be above cell 4 to the right of cell 3, rather than above cell 3, column pads 43 can be arranged above cell 3. Note that since row pads 42 are connected to row wiring 12, the wiring path between row pads 42 and row wiring 12 does not increase even if row pads 42 are shifted in the X direction. By adopting the triangular arrangement in this way, the row pads 41 and 42 and the column pads 43 and 44 overlapping the cell array 1234 can be appropriately arranged. That is, the wiring paths between the row pads 41 and 42 and the column pads 43 and 44 and the row wirings 11 and 12 and the column wirings 21 and 22 can be reduced, respectively, and the intervals between the row pads 41 and 42 and the column pads 43 and 44 can also be increased.

[0057] The row pads 41, the row pads 42, the column pads 43, and the column pads 44 are arranged so that the straight line E connecting the row pads 41 and the row pads 42 in the XY plane perpendicular to the Z direction passes between the column pads 43 and the column pads 44. In a similar manner, the row pads 41, the row pads 42, the column pads 43, and the column pads 44 are arranged so that the straight line F connecting the column pads 43 and the column pads 44 in the XY plane perpendicular to the Z direction passes between the row pads 41 and the row pads 42. Such an arrangement of the row pads 41, the row pads 42, the column pads 43, and the column pads 44 defined by the straight line E and / or the straight line F will be referred to as a cross arrangement.

[0058] This cross arrangement can improve the performance of the semiconductor device. One of the advantages of the cross arrangement is that it can prevent the spacing between the row pads 41 and 42 and the column pads 43 and 44 from being very small. If the spacing between the row pads 41 and 42 and the column pads 43 and 44 can be prevented from being very small, the yield can be improved and the parasitic capacitance can be reduced. Another advantage of the cross arrangement is that it can suppress the increase in the length of the wiring path from the row pads 41 and 42 or the column pads 43 and 44 to the row wiring 11 and 12 or the column wiring 21 and 22. Another advantage of the cross arrangement is that it can prevent the wiring path from the row pads 41 and 42 or the column pads 43 and 44 to the row wiring 11 and 12 or the column wiring 21 and 22 from becoming complicated. If the increase in the wiring path length can be suppressed or the wiring path can be prevented from becoming complicated, the yield can be improved and the RC delay of the wiring can be reduced.

[0059] For example, in Figure 1B In the example, if the column pad 44 arranged at the position overlapping with the cell 2 is moved to the position overlapping with the cell 3, the straight line E does not pass between the column pad 43 and the column pad 44. That is, the cross arrangement is no longer satisfied. In this case, since the column pad 43 and the column pad 44 overlap with the cell 3, Figure 1B Compared with the case in FIG. 4 , the interval between column pad 43 and column pad 44 is reduced. This may generate a short circuit or crosstalk between column pad 43 and column pad 44. Figure 1B Compared with the case of the column pad 44 moved to the position overlapping the cell 3, the distance from the column wiring 22 is greater. This increases the wiring path length from the column pad 44 to the column wiring 22, or complicates the wiring path.

[0060] Although referenced Figure 1B The cell array 1234 having two rows and two columns is described, but the number of cells included in the cell array 1234 may be any number. Figure 2A and Figure 2B A cell array 1234 having three rows and three columns is described. Row wiring 11, row wiring 12, and row wiring 13 corresponding to the cell rows and column wiring 21, column wiring 22, and column wiring 23 corresponding to the cell columns are provided. The connection of the row wiring 11 and 12 and the column wiring 21 and 22 to the cells and pads can be as Figure 1BThe connections shown in are substantially the same, and therefore, a detailed description thereof is omitted. Cells 5, 6, and 05 are arranged in the X direction, and row wiring 13 is connected to cells 5, 6, and 05. Cells 01, 02, and 03 are arranged in the Y direction, and column wiring 23 is connected to cells 01, 02, and 03. Cell 01 and cell 1 are arranged side by side in the X direction, and cell 02 and cell 2 are arranged side by side in the X direction. Row pad 41 is connected to row wiring 11, row pad 42 is connected to row wiring 12, and row pad 45 is connected to row wiring 13. Column pad 43 is connected to column wiring 21, column pad 44 is connected to column wiring 22, and column pad 47 is connected to column wiring 23. In addition, row pads 41, 42, and 45 and column pads 43, 44, and 47 are arranged to overlap with different cells.

[0061] exist Figure 2A , straight line E passes between column pad 43 and column pad 44, and straight line E passes between column pad 43 and column pad 47. In addition, straight line G connecting (passing through) row pad 42 and row pad 45 passes through column pad 43 and column pad 47. Straight line G connecting (passing through) row pad 42 and row pad 45 also passes through column pad 44 and column pad 47.

[0062] exist Figure 2A , row pads 41, 42, and 45 are not arranged linearly. That is, row pad 41 is away from the straight line G connecting (passing through) row pad 42 and row pad 45, row pad 42 is away from the straight line connecting (passing through) row pad 41 and row pad 45, and row pad 45 is away from the straight line E connecting (passing through) row pad 41 and row pad 42. Such an arrangement of row pads 41, 42, and 45 will be referred to as a nonlinear arrangement.

[0063] like Figure 2A As shown in , row pads 41, 42, and 45 are arranged in cells 1, 4, and 5, respectively, so that row pads 41, 42, and 45 have a nonlinear arrangement. Therefore, since it is impossible to arrange column pads 43 connected to column wiring 21 in the shortest wiring path in cells 1 and 4, and column pads 43 are arranged in cell 3, the arrangement of column pads 43 has a degree of freedom of 1. Figure 2A The column pad 44 connected to the column wiring 22 is arranged in the unit 2, but can also be arranged in the unit 6, so the arrangement of the column pad 44 has 2 degrees of freedom. Figure 2A Column pad 47 connected to column wiring 23 is arranged in cell 03, but may be arranged in cell 01 or cell 05, so the arrangement of column pad 47 has 3 degrees of freedom. Thus, the degrees of freedom of column pads 43, 44, and 47 are 1×2×3=6.

[0064] exist Figure 2B, row pads 41, 42, and 45 are arranged linearly. Row pad 42 is located between row pad 41 and row pad 45, and a straight line connecting (passing through) row pad 41 and row pad 45 also passes through row pad 42. This arrangement of row pads 41, 42, and 45 will be referred to as a linear arrangement. By using a linear arrangement for the arrangement of row pads 41, 42, and 45, the degree of freedom of arrangement of column pads 43, 44, and 47 is increased.

[0065] like Figure 2B As shown in FIG, row pads 41, 42 and 45 are arranged in cells 1, 4 and 05, respectively, so that row pads 41, 42 and 45 have a linear arrangement. Figure 2B The column pad 43 connected to the column wiring 21 is arranged in the cell 5, but can also be arranged in the cell 3, so the arrangement of the column pad 43 has two degrees of freedom. Figure 2B The column pad 44 connected to the column wiring 22 is arranged in the cell 2, but can also be arranged in the cell 6, so the arrangement of the column pad 44 has two degrees of freedom. Figure 2B Column pad 47 connected to column wiring 23 is arranged in unit 03, but can also be arranged in unit 01, so the arrangement of column pad 47 has two degrees of freedom. Therefore, the number of degrees of freedom of column pads 43, 44 and 47 is 2×2×2=8, which is higher than the case of adopting nonlinear arrangement.

[0066] Reference Figure 3A and Figure 3B A cell array 1234 having four rows and four columns is described. Row wiring 11, row wiring 12, row wiring 13, and row wiring 14 are provided corresponding to the cell rows. Cells 7, 8, 07, and 08 are arranged in the X direction, and row wiring 14 is connected to cells 7, 8, 07, and 08. Cells 02, 04, 06, and 08 are arranged in the Y direction, and column wiring 24 is connected to cells 02, 04, 06, and 08. Row pad 46 is connected to row wiring 14, and column pad 48 is connected to column wiring 24. In addition, row pads 41, 42, 45, and 46 and column pads 43, 44, 47, and 48 are arranged to overlap different cells.

[0067] exist Figure 3A In the arrangement shown, row pads 41 and 42 and column pads 43 and 44 are in a cross arrangement. Row pads 41, 45 and 46 have a linear arrangement, and row pad 42 is arranged away from (deviation from) a straight line connecting (passing through) any two of row pads 41, 45 and 46. Column pads 44, 47 and 48 have a linear arrangement, and column pad 43 is arranged away from (deviation from) a straight line connecting (passing through) any two of column pads 44, 47 and 48.

[0068] Also in Figure 3BIn the arrangement shown, row pads 41 and 42 and column pads 43 and 44 have a cross arrangement. Likewise, row pads 45 and 46 and column pads 47 and 48 have a cross arrangement. Row pads 41, 42, 45 and 46 have a linear arrangement, and column pads 43, 44, 47 and 48 have a linear arrangement.

[0069] exist Figure 1B , Figure 2B and Figure 3B In the arrangement in , for each row pad, the distance from two or more cells (e.g., cells 1, 3, 5, and 7) on the same cell column to the row pads (e.g., row pads 41, 42, 45, and 46) connected to these cells is different. Therefore, for each cell row, the length of the wiring path from the cell column to the row pad can be different. As a result, for each cell row, the delay amount of the signal input to the cell through the row wiring can be different. If a large number of row pads are arranged linearly, then the variation in the length of the wiring path from the cell column to the row pad increases. For example, in Figure 2B In the arrangement in , the distance from cell 5 to row pad 45 is substantially twice the distance from cell 3 to row pad 42, and cell 3 and cell 5 belong to the same cell column. Figure 3B In the arrangement in , the distance from cell 07 to row pad 46 is substantially three times the distance from cell 01 to row pad 41, and cell 01 and cell 07 belong to the same cell column. Figure 2A and Figure 3A By adopting a nonlinear arrangement for row pads 41, 42, 45, and 46, as in the arrangement in FIG. 4, the variation in the wiring path length from the cell column to the row pad can be reduced. Figure 2A and Figure 3A , the distances from two or more cells (eg, cells 1, 5, and 7) on the same cell column to several row pads (eg, row pads 41, 45, and 46) connected to these cells are equal.

[0070] Figure 4A and Figure 4B The arrangement shown in Figure 3A and Figure 3BThe difference between the arrangement shown in is that a plurality of row wirings are arranged on each cell row and / or a plurality of column wirings are arranged on each cell column. With respect to the row wirings, cells 1, 2, 01, and 02 belonging to the same cell row are connected to the row wiring 11 and are also connected to the row wiring 16. More specifically, the row wiring 11 is connected to the first type of semiconductor element 60 included in cell 1 and the first type of semiconductor element 60 included in cell 2. In addition, the row wiring 16 is connected to the second type of semiconductor element (not shown) included in cell 1 and the second type of semiconductor element (not shown) included in cell 2. The row wiring 11 is a signal line for transmitting a first type of signal, and the row wiring 16 is a signal line for transmitting a second type of signal. A plurality of overlapping pads include a row pad 41 and a row pad 91, the row pad 41 being a connection pad connected to the row wiring 11 as a signal line, and the row pad 91 being a connection pad connected to the row wiring 16 as a signal line. The same applies to other row wirings. Cells 3, 4, 03, and 04 belonging to the same cell row are connected to the row wiring 12 and are also connected to the row wiring 17. Cells 5, 6, 05, and 06 belonging to the same cell row are connected to row wiring 13 and are also connected to row wiring 18. Cells 7, 8, 07, and 08 belonging to the same cell row are connected to row wiring 14 and are also connected to row wiring 19. Row pad 92 is connected to row wiring 17, row pad 95 is connected to row wiring 18, and row pad 96 is connected to row wiring 19.

[0071] Regarding the column wiring, although cells 1, 5, 3, and 7 belong to the same cell column, cells 1 and 3 are connected to column wiring 21, and cells 5 and 7 are connected to column wiring 26. Similarly, cells 6 and 8 are connected to column wiring 27, cells 05 and 07 are connected to column wiring 28, and cells 06 and 08 are connected to column wiring 29. Column pad 93 is connected to column wiring 26 connected to cells 5 and 7, column pad 94 is connected to column wiring 27 connected to cells 6 and 8, column pad 97 is connected to column wiring 28 connected to cells 05 and 07, and column pad 98 is connected to column wiring 29 connected to cells 06 and 08.

[0072] exist Figure 4B In the arrangement of , row pad 41 is located between column pads 43 and 94 and row pad 91, row pad 45 is located between column pads 44 and 93 and row pad 95, row pad 92 is located between column pads 47 and 48 and row pad 42, and row pad 96 is located between column pads 97 and 98 and row pad 46. In this way, when the column pads are arranged on one side of either of the two row pads connected to the same cell row, the arrangement of the column pads is unbalanced, thereby increasing the influence of fixed pattern noise. Figure 4AIn the layout, column pad 44 is located between row pad 41 and row pad 91, column pad 97 is located between row pad 45 and row pad 95, column pad 94 is located between row pad 42 and row pad 92, and column pad 47 is located between row pad 46 and row pad 96. In this way, by arranging each column pad between two row pads connected to the same unit row, the layout of the column pads can reduce the imbalance.

[0073] In Figure 4A and Figure 4B In the layout, the straight line connecting column pad 43 and column pad 93, which are connected to different column wirings, is defined as straight line O, the distance between straight line O and row pad 41 is defined as distance P, the distance between straight line O and row pad 42 is defined as distance Q, and the distance between row pad 41 and row pad 42 is defined as distance R. If the difference between distance P and distance Q is greater than distance R (R < |P - Q|), then the difference in the wiring path lengths from two units 1 and 3 connected to the same column wiring 21 to the corresponding row pads 41 and 42 increases. In this case, the delay amounts of the signals transmitted through the row wirings of units 1 and 3 are different, thereby increasing the variation in the outputs of units 1 and 3. In contrast, in Figure 4A and Figure 4B In the layout, the difference between distance P and distance Q is less than distance R (|P - Q| < R). This can reduce the difference in the wiring path lengths from two units 1 and 3 connected to the same column wiring 21 to the corresponding row pads 41 and 42. Therefore, the difference in the delay amounts of the signals transmitted through the row wirings of units 1 and 3 can be reduced, and the variation in the outputs of units 1 and 3 can be reduced. Although in Figure 4B In the layout, the difference between distance P and distance Q is approximately of distance R Figure 4A in the layout, distance P is equal to distance Q, and the difference between them is zero. In addition, distance P and distance Q can be less than distance R (P < R, Q < R). In Figure 4B In the layout, although distance Q is less than distance R, distance P is greater than distance R. Therefore, variations may occur in the outputs of units 1 and 3. In contrast, in Figure 4A In the layout, since distance Q and distance P are less than distance R, the variation in the outputs of units 1 and 3 can be reduced.

[0074] In addition, the distance between the straight line O and the row pad 45 is defined as distance S, the distance between the straight line O and the row pad 46 is defined as distance T, and the distance between the row pad 45 and the row pad 46 is defined as distance U. Similar to the distances P, Q, and R, the difference between the distance S and the distance T can be less than the distance U (|S - T| < U), the difference between the distance S and the distance T can be less than or equal to half of the distance U (|S - T| ≤ U / 2), and the distances S and T can be less than the distance U (S < U, T < U). This can reduce the possibility of variations in the outputs of the cell 05 connected to the row pad 45 and the cell 7 connected to the row pad 46.

[0075] In addition, the difference between the distance S and the distance T can be less than the distance R (|S - T| < R), the difference between the distance S and the distance T can be less than or equal to half of the distance R (|S - T| ≤ R / 2), and the distances S and T can be less than the distance R (S < R, T < R). In addition, the difference between the distance P and the distance Q can be less than the distance U (|P - Q| < U), the difference between the distance P and the distance Q can be less than or equal to half of the distance U (|P - Q| ≤ U / 2), and the distances P and Q can be less than the distance U (P < U, Q < U). This can reduce the possibility of variations in the outputs of the column pad 43 through the column wiring 21 and the column pad 93 through the column wiring 26. For example, in Figure 4A the arrangement shown, the distances S and T are approximately half of the distance R, and the distances P and Q are less than or equal to one-fourth of the distance U.

[0076] Although the straight line O in this document is defined by using the column pads 43 and 93, the straight line O can be any straight line connecting two column pads corresponding to two column wirings, where each column wiring connects two or more cells belonging to the same cell column. In other words, each of the two column pads used to define the straight line corresponding to the straight line O is connected to at least one cell belonging to the same cell column. Therefore, the row pads 41 and 42 and / or the row pads 45 and 46 can be arranged relative to the straight line connecting the column pad 44 and the column pad 94 to satisfy the above relationships between the distances P, Q, R, S, T, and U. The same applies to the straight line connecting the column pad 47 and the column pad 97 and the straight line connecting the column pad 48 and the column pad 98.

[0077] The row pads 41, 42, 45, and 46 connected to the row wirings 11, 12, 13, and 14 have been described in this document. Similarly, the row pads 91, 92, 95, and 96 connected to the row wirings 16, 17, 18, and 19 can be arranged to satisfy the above relationships between the distances P, Q, R, S, T, and U so that the distance differences from the straight line corresponding to the straight line O do not increase.

[0078] The type of cells constituting the cell array 1234 is appropriately set according to the purpose of the semiconductor device 930. For example, the cell may be a pixel cell. The cell array 1234 composed of pixel cells may capture or display an image. The pixel cell for capturing an image may include a photoelectric conversion element.

[0079] The photoelectric conversion element can be a photodiode, a photogate, a component in which a photoelectric conversion film is sandwiched between a pair of electrodes, etc. The pixel unit displaying the image can include an optical element. The optical element can be an electroluminescent (EL) element, a cathode luminescent (CL) element, a liquid crystal element, a mirror element, etc. For example, the unit can be a memory unit. The unit array 1234 composed of memory cells operates as a memory. The memory unit can be a static random access memory (SRAM) unit, a dynamic random access memory (DRAM) unit, or a flash memory unit.

[0080] One of the row wiring and the column wiring may be a signal line (drive signal line) for transmitting a drive signal for driving the unit. The drive signal line is usually connected to the gate of the transistor included in the unit and controls the operation timing of the unit. If the unit is a memory unit, the drive signal line is a word line. The other of the row wiring and the column wiring may be a signal line (information signal line) for transmitting an information signal including information processed in the unit. The information signal line is usually connected to the source or drain of the transistor included in the unit. If the unit is a pixel unit, the information signal is a pixel signal, and the pixel signal may represent a signal level according to the charge generated by the photoelectric conversion element or a signal level according to the brightness level of the display element. If the unit is a memory unit, the information signal line is a bit line for reading data recorded on the memory unit or writing data to the memory unit.

[0081] Furthermore, the row wiring and / or the column wiring are not limited to wiring for transmitting signals whose signal levels change over time, but may be wiring (potential supply line) for supplying a fixed potential to be used as a power supply potential, a ground potential, or a reference potential.

[0082] The circuit in the semiconductor component 201 connected to the information signal line of the semiconductor component 101 may be an information processing circuit. The circuit in the semiconductor component 201 connected to the drive signal line of the semiconductor component 101 may be a drive circuit for generating a drive signal.

[0083] Example

[0084] Now, configurations common to the following first to fifth examples will be described. Figure 5AA semiconductor device according to an example is schematically shown. In a cell array 1234 of a semiconductor component 101, cells 102 are arranged in a matrix. Multiple cells on the same cell column are connected via column wiring 103, and signals from the cells 102 are output through the column wiring 103. Multiple cells on the same cell row are connected via row wiring 104, and signals are input to the cells 102 through the row wiring 104. Each of the multiple row wirings 104 is connected to two or more cells on the same cell row of the cell array 1234, and is provided for the corresponding cell row of the cell array 1234. Each of the multiple column wirings 103 is connected to two or more cells on the same cell column of the cell array 1234, and is provided for the corresponding cell column of the cell array 1234.

[0085] exist Figure 5B In the semiconductor component 201 in the embodiment, at least a control circuit 202 and a processing circuit 203 are arranged. The control circuit 202 outputs a driving signal for driving the cell 102, and the processing circuit 203 processes a signal output from the cell 102. By stacking the semiconductor component 101 and the semiconductor component 201, a stacked semiconductor device is formed. In addition, the control circuit 202 is connected to the corresponding row wiring 104, and the processing circuit 203 that processes a signal output from the cell 102 is connected to the corresponding column wiring 103.

[0086] Figure 5C An example of a configuration of a unit 102 is shown. The unit 102 includes a photodiode PD as a photoelectric conversion element, a transfer transistor M2 that transfers the charge of the photodiode PD to a detection node FD formed by a floating diffusion, and a reset transistor M1 that resets the detection node FD. The detection node FD is connected to the gate of the amplifier transistor M3, and the power supply voltage is supplied to the amplifier transistor M3 and the reset transistor M1. The selection transistor M4 is connected to the source of the amplifier transistor M3, and the selection transistor M4 is connected to the column wiring 103. The drive signals as the reset signal PRES, the transfer signal PTS, and the selection signal PSEL are input from the control circuit 202 to the gates of the reset transistor M1, the transfer transistor M2, and the selection transistor M4 through a plurality of signal lines included in the row wiring 104. The power supply potential VDD is supplied to the reset transistor M1 and the amplifier transistor M3 from the power supply potential supply line as the row wiring. Although an example in which a pixel unit includes four transistors has been described herein, the selection transistor M4 can be omitted and three transistors can be used, or, in addition to the four transistors, transistors that implement various additional functions can be added.

[0087] First example

[0088] Fig. 6A and Figure 6BThe relationship between the row wirings 104_1 to 104_3 corresponding to the control circuit 202_1 and the row pads 302_1 to 302_3 connected to the row wirings 104_1 to 104_3 is shown. Fig. 6A and Figure 6B The relationship between the column wiring 103_1 corresponding to the processing circuit 203 and the column pad 301 connected to the column wiring 103_1 is also shown. In the pad array 4321, the column pads 301 and / or the row pads 302 are arranged in a matrix. The pad array 4321 includes a plurality of pads arranged in a matrix to overlap with the cell array 1234. The columns arranged with the column pads 301 and / or the row pads 302 are referred to as pad columns, and the rows arranged with the column pads 301 and / or the row pads 302 are referred to as pad rows. Fig. 6A , Figure 6B and Figure 6C A plurality of pad rows including the (M+1)th row and a plurality of pad columns including the Nth column are shown. In the semiconductor component 101, a single column wiring 103_1 is arranged in each cell column. The matrix wiring includes a plurality of row wirings 104, each row wiring 104 being connected to two or more cells in the same cell row. Three row wirings 104_1, 104_2, and 104_3 are arranged in each cell row. The plurality of pads include several row pads 302_1, 302_2, and 302_3 connected to the plurality of row wirings 104_1, 104_2, and 104_3, respectively. The row wiring 104_1 is used to transmit a reset signal PRES and is connected to the gate of the reset transistor M1 of the cell 102. The row wiring 104_2 is used to transmit a selection signal PSEL and is connected to the gate of the selection transistor M4 of the cell 102. The row wiring 104_3 is used to transmit a transfer signal PTS and is connected to the gate of the transfer transistor M2 of the cell 102.

[0089] exist Figure 6C In , the position of the row pad corresponding to each cell row is represented by "r", "s" and "t". Figure 6C In , "r" represents, for example, the position of the row pad 302_1 connected to the row wiring 104_1, "s" represents, for example, the position of the row pad 302_2 connected to the row wiring 104_2, and "t" represents, for example, the position of the row pad 302_3 connected to the row wiring 104_3. Figure 6C , the position of the column pad corresponding to each cell column is indicated by “o”.

[0090] In the semiconductor component 201, as the control circuit 202, a plurality of (v) control circuits 202_1 to 202_v corresponding to each row are arranged at the same pitch as the pitch of the unit row. The column pad 301 is a pad for connecting to the column wiring 103_1 of the processing circuit 203. The row pads 302_1 to 302_3 are pads for connecting to the row wiring 104_1 to 104_3 of the control circuit 202_1. For each unit, the number of column pads 301 and row pads 302 may be one. The pad array 4321 may include a dummy pad that is not a row pad 302 or a column pad 301. In Figure 6B In FIG. 1 , a dummy pad may be disposed in a pad row or pad column not represented by any one of “r”, “s”, “t”, and “o”.

[0091] The arrangement of the column pads 301 will be described. The column pads 301 are arranged in each unit column and are arranged for each column wiring 103. Fig. 6A and Figure 6B , except in the (N-2)th column, the column pad 301 provided for each column wiring 103 is not denoted by reference numeral 301. Therefore, Figure 6C Reference will be made for detailed pad arrangement. In order to suppress image quality degradation, the correspondence between the group (cell row, cell column) of the cells 102 arranged in the semiconductor component 101 and the peripheral circuit can be maintained. Therefore, the column wiring 103 in each cell column is connected to the processing circuit 203 of the semiconductor component 201 in the corresponding cell column. Therefore, the column pad 301 can be arranged above the control circuit 202. In addition, it is desirable that the wiring path lengths from the processing circuit 203 of the semiconductor component 201 to the column pad 301 are equal.

[0092] The arrangement of the row pads 302_1 to 302_3 will be described. The row pads 302_1 to 302_3 are arranged in each unit row and are arranged for each row wiring 104. The row pads 302_1 to 302_3 in the Mth row are connected to a certain row wiring 104 among the plurality of row wirings 104, and the row pads 302_1 to 302_3 in rows other than the Mth row are connected to other row wirings 104 among the plurality of row wirings 104. Fig. 6A and Figure 6B , except in the (M-2)th row, the row pads 302_1 to 302_3 provided for each unit row are not denoted by reference numerals 302_1 to 302_3. Figure 6CReference will be made to the detailed pad arrangement. If the column pads 301 are not arranged above the control circuit 202, the row pads 302_1 to 302_3 in each row can be arranged in all rows and the Nth to (N+2)th columns of the pad array 4321. However, in this example, the column pads 301 are arranged above the control circuit 202. That is, the column pads 301 are arranged in the Mth row, Nth column to the Mth row, (N+2)th column of the pad array 4321. Therefore, since it is impossible to arrange the row pads 302_1 to 302_3 in the Mth row, Nth column to the Mth row, (N+2)th column, the row pads 302_1 to 302_3 in the Mth row are arranged in the (N+3)th to (N+5)th columns to avoid the Nth to (N+2)th columns. That is, row pads 302_1 to 302_3 are discontinuous between the (N+2)th column and the (N+3)th column, and the pad row in which row pads 302_1 to 302_3 are arranged is shifted. In this way, row pads 302_1 to 302_3 in the Mth row and row pads 302_1 to 302_3 in rows other than the Mth row are arranged in different pad columns (the (N+3)th to (N+5)th columns and the Nth to (N+2)th columns) of pad array 4321.

[0093] With the above configuration, the column pads 301 and the row pads 302_1 to 302_3 can be arranged to overlap with the cell array 1234 in a plan view. In addition, the column wiring 103_1 of the semiconductor component 101 and the processing circuit 203 of the semiconductor component 201 can be connected in a good manner via the column pads 301. In addition, the row wirings 104_1 to 104_3 of the semiconductor component 101 and the control circuit 202 of the semiconductor component 201 can be connected via the row pads 302_1 to 302_3.

[0094] Column pads 301 are arranged in the (M+1)th row, (N+3)th column to the (M+1)th row, (N+5)th column of pad array 4321. Since it is impossible to arrange column pads 301 in the (N+3)th column to the (N+5)th column of M-th row, column pads 301 in the (N+3)th column to the (N+5)th column are arranged in the (M+1)th row, (N+3)th column to the (M+1)th row, (N+5)th column to avoid the M-th row. In this way, in the (N+3)th to (N+5)th pad columns of pad array 4321 including row pads 302_1 to 302_3 in the M-th row, column pads 301 (in the (M+1)th row) connected to cells to which row pads 302_1 to 302_3 in the M-th row are connected are arranged. Furthermore, in the Nth to (N+2)th pad columns including the row pads 302_1 to 302_3 in the rows other than the Mth row, the column pads 301 connected to the cells to which the row pads 302_1 to 302_3 in the rows other than the Mth row are connected are arranged.

[0095] The above example shows the following situation: as the control circuit 202, the control circuits 202_1 to 202_v corresponding to each row are arranged at the same spacing as the spacing of the unit row. However, the control circuits 202_1 to 202_v corresponding to each row of the control circuit 202 can be arranged alternatively at a spacing different from the spacing of the unit row in a relationship where the number of column pads 301 and row pads 302_1 to 302_3 is less than or equal to one per unit spacing. In addition, although the above example shows a situation where the row wiring is three row wirings 104_1 to 104_3 and the column wiring is a single column wiring 103_1, the present invention is not limited to this relationship. The arrangement in this example is an example, and the discontinuous positions of the column pads 301 and the row pads 302_1 to 302_3 are not limited to the positions shown in this example.

[0096] Second example

[0097] Will refer to 7A to 7C A second example is described. 7A to 7C In, with FIG. 6A to FIG. 6C Corresponding parts are denoted by the same reference numerals, and description thereof will be omitted. Fig. 7A , Figure 7B and Figure 7C The relationship between Fig. 6A , Figure 6B and Figure 6C The relationship between them is basically the same.

[0098] In the second example, the column pads 301 are arranged to be shifted by one row in each pad column. Therefore, the wiring to the column pads 301 connecting the processing circuit 203 and the corresponding column wiring 103_1 is simple. In the first example, a plurality of wirings connecting the processing circuit 203 and the corresponding column wiring 103_1 need to be arranged in each control circuit 202_1 to 202_v corresponding to each row arranged in the control circuit 202. In addition, the control circuits 202_1 to 202_v corresponding to each row arranged in the control circuit 202 need to be arranged in a plurality of rows.

[0099] The arrangement of row pads 302_1 to 302_3 will be described. The row pads 302 in rows other than the Mth to (M+2)th rows are arranged in the Nth to (N+2)th columns. In the second example, the column pads 301 are arranged in the Mth row, Nth column, the (M+1)th row, (N+1)th column, and the (M+2)th row, (N+2)th column of the pad array 4321. Therefore, since it is impossible to arrange any row pads 302_1 to 302_3 in the Mth row, Nth column, the (M+1)th row, (N+1)th column, and the (M+2)th row, (N+2)th column, at least one of the row pads 302_1 to 302_3 in each of the Mth to (M+2)th rows needs to be shifted to a pad column other than the Nth to (N+2)th columns. Therefore, in the Mth to (M+2)th rows, row pads 302_3 are arranged in the (N+3)th column.

[0100] The above example shows the following situation: as the control circuit 202, the control circuits 202_1 to 202_v corresponding to each row are arranged at the same spacing as the spacing of the unit row. However, the control circuits 202_1 to 202_v corresponding to each row of the control circuit 202 can be arranged alternatively at a spacing different from the spacing of the unit row in a relationship where the number of column pads 301 and row pads 302_1 to 302_3 is less than or equal to one per unit spacing. In addition, although the above example shows a situation where the row wiring is three row wirings 104_1 to 104_3 and the column wiring is a single column wiring 103_1, the present invention is not limited to this relationship. The arrangement in this example is an example, and the discontinuous positions of the column pads 301 and the row pads 302_1 to 302_3 are not limited to the positions shown in this example.

[0101] Third Example

[0102] Reference FIG. 8A to FIG. 8C A third example is described. FIG. 8A to FIG. 8C In, with FIG. 6A to FIG. 6C Corresponding parts are denoted by the same reference numerals, and description thereof will be omitted. Fig. 8A , Figure 8B and Figure 8C The relationship between Fig. 6A , Figure 6B and Figure 6C The relationship between them is basically the same.

[0103] In the third example, as column wirings, two column wirings 103_1 and 103_2 are provided in the same unit column. Therefore, pads for the column wirings 103_1 and 103_2 corresponding to the processing circuit 203 are column pads 301_1 and 301_2. Figure 8C In , the position of the column pads corresponding to each cell column is represented by "a" and "b". Figure 8CIn FIG. 1 , “a” represents, for example, a position of a column pad 301_1 connected to the column wiring 103_1 , and “b” represents, for example, a position of a column pad 301_2 connected to the column wiring 103_2 .

[0104] The arrangement of the column pads 301_1 and 301_2 will be described. In order to suppress image quality degradation, the correspondence relationship between the group of cells 102 arranged in the semiconductor component 101 and the peripheral circuit can be maintained. Therefore, the column wirings 103_1 and 103_2 in each cell column are connected to the processing circuit 203 of the semiconductor component 201 in the corresponding cell column. Therefore, the column pads 301_1 and 301_2 can be arranged above the control circuit 202.

[0105] The arrangement of row pads 302_1 to 302_3 will be described. Row pads 302_1 to 302_3 are arranged in each unit row. If column pads 301_1 and 301_2 are not arranged above control circuit 202, row pads 302_1 to 302_3 in each row may be arranged in all rows and in Nth to (N+2)th columns. However, in this example, column pads 301_1 and 301_2 are arranged above control circuit 202. That is, column pads 301_1 and 301_2 are arranged in Mth row, Nth column to Mth row, (N+2)th column and (M+1)th row, Nth column to (M+1)th row, (N+2)th column. Therefore, since it is impossible to arrange the row pads 302_1 to 302_3 in the Mth row, Nth column to the Mth row, (N+2)th column and the (M+1)th row, Nth column to the (M+1)th row, (N+2)th column, the row pads 302_1 to 302_3 in the Mth row and the (M+1)th row are arranged in the (N+3)th to (N+5)th columns to avoid the Nth to (N+2)th columns. That is, the row pads 302_1 to 302_3 are arranged to be shifted to the (N+3)th to (N+5)th columns in the pad rows (two pad rows, the Mth row and the (M+1)th row) whose number is equal to the number (two) of the column wirings 103.

[0106] With the above configuration, the column pads 301_1 and 301_2 and the row pads 302_1 to 302_3 can be arranged to overlap with the cell array 1234. In addition, the column wirings 103_1 and 103_2 of the semiconductor component 101 and the processing circuit 203 of the semiconductor component 201 can be connected via the column pads 301_1 and 301_2. In addition, the row wirings 104_1 to 104_3 of the semiconductor component 101 and the control circuit 202 of the semiconductor component 201 can be connected via the row pads 302_1 to 302_3. The above example shows the following case: as the control circuit 202, the control circuits 202_1 to 202_v corresponding to the respective rows are arranged at the same pitch as the pitch of the cell rows. However, the control circuits 202_1 to 202_v corresponding to the respective rows of the control circuit 202 may alternatively be arranged at a pitch different from the pitch of the cell rows in a relationship in which the number of column pads 301_1 and 301_2 and row pads 302_1 to 302_3 is less than or equal to one per cell pitch. In addition, although the above example shows a case where the row wiring is three row wirings 104_1 to 104_3 and the column wiring is two column wirings 103_1 and 103_2, the present invention is not limited to this relationship. The arrangement in this example is an example, and the discontinuous positions of the column pads 301_1 and 301_2 and the row pads 302_1 to 302_3 are not limited to the positions shown in this example.

[0107] Fourth Example

[0108] Reference 9A to 9C A fourth example is described. 9A to 9C In, with FIG. 6A to FIG. 6C Corresponding parts are denoted by the same reference numerals, and description thereof will be omitted. Fig.9A , Fig. 9B and Fig. 9C The relationship between Fig. 6A , Figure 6B and Figure 6C The relationship between them is basically the same.

[0109] In the fourth example, six connection lines as column wirings 103_1 to 103_6 are provided in the same column as the column wiring 103. Furthermore, six column pads 301_1 to 301_6 connect the processing circuit 203 and the six column wirings 103_1 to 103_6.

[0110] The cells connected to the row pads 302_1 to 302_3 in the (M+m)th row and the cells connected to the row pads 302_1 to 302_3 in the (M+m+6)th row are connected to the same column wiring 103_m. Herein, m is any number from 1 to 6. The cells connected to the row pads 302_1 to 302_3 in the (M+1)th row (m=1) and the cells connected to the row pads 302_1 to 302_3 in the (M+7)th row (m=1) are connected to the same column wiring 103_1 (m=1). The cells connected to the row pads 302_1 to 302_3 in the (M+2)th row (m=2) and the cells connected to the row pads 302_1 to 302_3 in the (M+8)th row (m=2) are connected to the same column wiring 103_2 (m=2). The cells connected to the row pads 302_1 to 302_3 in the (M+3)th row (m=3) and the cells connected to the row pads 302_1 to 302_3 in the (M+9)th row (m=3) are connected to the same column wiring 103_3 (m=3). The cells connected to the row pads 302_1 to 302_3 in the (M+4)th row (m=4) and the cells connected to the row pads 302_1 to 302_3 in the (M+10)th row (m=4) are connected to the same column wiring 103_4 (m=4). The cells connected to the row pads 302_1 to 302_3 in the (M+5)th row (m=5) and the cells connected to the row pads 302_1 to 302_3 in the (M+11)th row (m=5) are connected to the same column wiring 103_5 (m=5). The cells connected to the row pads 302_1 to 302_3 in the (M+6)th row (m=6) and the cells connected to the row pads 302_1 to 302_3 in the (M+12)th row (m=6) are connected to the same column wiring 103_6 (m=6).

[0111] exist Fig. 9C In FIG. 1 , the positions of the column pads 301_1 to 301_6 connected to the respective column wirings 103_1 to 103_6 are indicated by “a”, “b”, “c”, “d”, “e”, and “f”. Fig. 9C In , "c" indicates, for example, the position of the column pad 301_3 connected to the column wiring 103_3, and "d" indicates, for example, the position of the column pad 301_4 connected to the column wiring 103_4. Fig. 9C In FIG. 1 , “e” represents, for example, the position of the column pad 301_5 connected to the column wiring 103_5, and “f” represents, for example, the position of the column pad 301_6 connected to the column wiring 103_6.

[0112] The arrangement of the column pads 301_1 to 301_6 and the row pads 302_1 to 302_3 in this example will be described.

[0113] The row pads 302_1 to 302_3 connected to the row wirings 104_1 to 104_3 corresponding to the same cell row are arranged in the same pad row. For example, in the (M+1)th row, the row pads 302_1 to 302_3 are arranged in the Nth to (N+2)th columns. In the (M+6)th row, the row pads 302_1 to 302_3 are arranged in the (N+5)th to (N+7)th columns.

[0114] The row pads 302_1 to 302_3 in several (two in this example) pad rows are arranged in the same pad column. In addition, the arrangement of the row pads 302_1 to 302_3 in a pad row is repeated in every seven pad rows (with six rows as a cycle). For example, in the (M+7)th row, as in the (M+1)th row, the row pads 302_1 to 302_3 are arranged in the Nth to (N+2)th columns. In the (M+12)th row, as in the (M+6)th row, the row pads 302_1 to 302_3 are arranged in the (N+5)th to (N+7)th columns.

[0115] Column pads 301_1 to 301_6 connected to column wirings 103_1 to 103_6 corresponding to the same cell column are arranged in the same pad column. For example, in the Nth column, column pads 301_1 to 301_3 are arranged in the (M+2)th to (M+4)th rows, and column pads 301_4 to 301_6 are arranged in the (M+8)th to (M+10)th rows. In the (N+1)th column, column pads 301_1 to 301_3 are arranged in the (M+3)th to (M+5)th rows, and column pads 301_4 to 301_6 are arranged in the (M+9)th to (M+11)th rows. In the (N+5)th column, column pads 301_1 to 301_3 are arranged in the (M+7)th to (M+9)th rows, and column pads 301_4 to 301_6 are arranged in the (M+1)th to (M+3)th rows.

[0116] Column pads 301_1 to 301_6 in several (two in this example) pad columns are arranged in the same pad row. In addition, the arrangement of column pads 301_1 to 301_6 in a pad column is repeated in every seven pad columns (with six columns as a cycle). For example, in the (N+6)th and (N+12)th columns, as in the Nth column, column pads 301_1 to 301_3 are arranged in the (M+2)th to (M+4)th rows, and column pads 301_4 to 301_6 are arranged in the (M+8)th to (M+10)th rows. In the (N+7)th column, as in the (N+1)th column, column pads 301_1 to 301_3 are arranged in the (M+3)th to (M+5)th rows, and column pads 301_4 to 301_6 are arranged in the (M+9)th to (M+11)th rows. In this way, row pads 302_1 to 302_3 are arranged in the same pad column in the (M+1)th and (M+7)th rows, in the (M+2)th and (M+8)th rows, in the (M+3)th and (M+9)th rows, in the (M+4)th and (M+10)th rows, in the (M+5)th and (M+11)th rows, and in the (M+6)th and (M+12)th rows.

[0117] Now, attention is paid to row wirings 104 to which row pads 302 arranged in the same pad column are connected. Among cells connected to such row wirings 104, cells belonging to the same cell column are connected to the same column wiring 103.

[0118] More specifically, attention is paid to two row wirings 104_1 to which row pads 302_1 arranged in the (M+m)th row and the (M+m+6)th row in the same (N+m-1)th column are connected. Among cells connected to such two row wirings 104_1, several cells belonging to the same cell column are connected to the same column wiring 103_m.

[0119] In the example of m=1, attention is paid to two row wirings 104_1 to which row pads 302_1 arranged in the (M+1)th row and the (M+7)th row in the same Nth column are connected. Among cells connected to such two row wirings 104_1, several cells belonging to the same cell column are connected to the same column wiring 103_1.

[0120] Similarly, in the example of m=2, attention is paid to several row wirings 104_1 to which row pads 302_1 arranged in the (M+2)th row and the (M+8)th row in the same (N+1)th column are connected. Among the cells connected to such two row wirings 104_1, several cells belonging to the same cell column are connected to the same column wiring 103_2.

[0121] In other words, if attention is paid to several cells connected to the same column wiring 103, the row pads 302 connected to several row wirings 104 corresponding to such several cells are arranged in the same pad column.

[0122] More specifically, if attention is paid to two cells connected to the same column wiring 103_m, the row pad 302_1 in the (M+m)th row and the row pad 302_1 in the (M+m+6)th row are connected to two row wirings 104_m corresponding to the two cells. The row pad 302_1 in the (M+m)th row and the row pad 302_1 in the (M+m+6)th row are arranged in the same (N+m)th column.

[0123] In the example of m=1, if attention is paid to two cells connected to the same column wiring 103_1, the row pad 302_1 in the (M+1)th row and the row pad 302_1 in the (M+7)th row are connected to two row wirings 104_1 corresponding to the two cells. The row pad 302_1 in the (M+1)th row and the row pad 302_1 in the (M+7)th row are arranged in the same Nth column.

[0124] Similarly, in the example of m=2, if attention is paid to two cells connected to the same column wiring 103_2, the row pad 302_1 in the (M+2)th row and the row pad 302_1 in the (M+8)th row are connected to two row wirings 104_1 corresponding to the two cells. The row pad 302_1 in the (M+2)th row and the row pad 302_1 in the (M+8)th row are arranged in the same (N+1)th column.

[0125] Furthermore, in the example of m=6, if attention is paid to two cells connected to the same column wiring 103_6, the row pad 302_1 in the (M+6)th row and the row pad 302_1 in the (M+12)th row are connected to two row wirings 104_1 corresponding to the two cells. The row pad 302_1 in the (M+6)th row and the row pad 302_1 in the (M+12)th row are arranged in the same (N+6)th column.

[0126] In this way, by arranging several row pads 302 connected to several row wirings 104 in the same pad column, wherein the several row wirings 104 are connected to several cells connected to the same column wiring 103, the difference in the wiring path length from the several row pads 302 to the several cells can be reduced. Therefore, the difference in the operation of the several cells connected to the same row wiring 104 can be reduced, and the variation in the output of the several cells can be reduced.

[0127] This is consistent with the reference Figure 4AThat is, the straight line O corresponds to one unit column. In addition, the arrangement of several rows of pads 302 corresponding to the same column wiring 103 in the same pad column corresponds to a decrease in the difference between the distance P and the distance Q or the difference between the distance S and the distance T.

[0128] Furthermore, if attention is paid to several column pads 301 arranged in the same pad column, the wiring path length from the cell connected to each column pad 301 to the corresponding row pad 302 differs depending on the pad row in which the column pad 301 is arranged.

[0129] More specifically, attention is paid to two column pads 301_m and 301_n arranged in the same (N+m-1)th column. In this article, n is any number different from m from 1 to 6. The row pad 302_m corresponding to the cell connected to the column pad 301_m is arranged in the (M+m)th row in the (N+m-1)th column. The row pad 302_1 corresponding to the cell connected to the column pad 301_n is arranged in the (M+n)th row in the (N+n-1)th column. In this article, the wiring path length from the cell connected to the column pad 301_2 to the row pad 302_1 in the (M+n)th row in the (N+n-1)th column is referred to as the length J, and the wiring path length from the cell connected to the column pad 301_1 to the row pad 302_1 in the (M+m)th row in the (N+m-1)th column is referred to as the length K. The length J is longer than the length K by |nm| pad columns.

[0130] As an example of m=1 and n=2, attention is paid to two column pads 301_1 and 301_2 arranged in the same N column. Row pad 302_1 corresponding to a cell connected to column pad 301_1 is arranged in the (M+1)th row in the Nth column.

[0131] The row pads 302_1 corresponding to the cells connected to the column pads 301_2 are arranged in the (M+2)th row in the (N+1)th column. Therefore, the wiring path length from the cells connected to the column pads 301_2 to the row pads 302_1 in the (M+2)th row in the (N+1)th column is longer by one pad column than the wiring path length from the cells connected to the column pads 301_1 to the row pads 302_1 in the (M+1)th row in the Nth column.

[0132] As an example of m=1 and n=6, attention is paid to two column pads 301_1 and 301_6 arranged in the same N column. Row pad 302_1 corresponding to the cell connected to column pad 301_1 is arranged in the (M+1)th row in the Nth column.

[0133] The row pad 302_6 corresponding to the cell connected to the column pad 301_2 is arranged in the (M+6)th row in the (N+5)th column. Therefore, the wiring path length from the cell connected to the column pad 301_2 to the row pad 302_1 in the (M+2)th row in the (N+1)th column is five pad columns longer than the wiring path length from the cell connected to the column pad 301_1 to the row pad 302_1 in the (M+1)th row in the Nth column.

[0134] The row pads 302_1 to 302_3 are arranged in the same pattern in every seven pad rows (in a cycle of six rows). In addition, the row pads 302_1 to 302_3 in the (M+2)th and (M+8)th rows corresponding to the row wiring 104 are arranged in the same pad column (the (N+1)th to (N+3)th columns), wherein the row wiring 104 is connected to two cells connected to the same column wiring 103 (e.g., column wiring 103_1).

[0135] More specifically, in each of the (M+2)th and (M+8)th rows, similarly, row pad 302_1 is arranged in the (N+1)th column, row pad 302_2 is arranged in the (N+2)th column, and row pad 302_3 is arranged in the (N+3)th column.

[0136] The row pads 302_1 to 302_3 connected to the cells connected to the column wirings 103_1 to 103_6 are arranged in different pad columns. Therefore, in each cell row in the six-row cycle, for each of the column wirings 103_1 to 103_6, the wiring path lengths from the row pads 302_1 to 302_3 to the cells are different. Therefore, fixed pattern noise in the six-row cycle may be generated. For example, in the row connected to the column wiring 103_1, if the row pads 302_1 are arranged in the same column, then in each row in the six-row cycle, the path lengths of the signal lines (row wirings 104_1) for transmitting the reset signal PRES are different, and fixed pattern noise in the six-row cycle may be generated. However, this fixed pattern noise in the six-row cycle can be eliminated by performing a predetermined correction process using a signal from a correction unit (e.g., an optical black unit) formed in the periphery of the cell array.

[0137] Although the above example has shown the case of three row wirings 104_1 to 104_3 and six column wirings 103_1 to 103_6, the present invention is not limited to this relationship.

[0138] Fifth example

[0139] Will refer to FIG. 10A to FIG. 10C A fifth example is described. In the fifth example, descriptions of parts that are substantially the same as those in the fourth example will be omitted. Note that Fig. 10A , Fig. 10B and Fig. 10C The relationship between Fig.9A , Fig. 9B and Fig. 9C The relationship between them is basically the same.

[0140] The arrangement of the column pads 301_1 to 301_6 and the row pads 302_1 to 302_3 in this example will be described.

[0141] As in the fourth example, row pads 302_1 to 302_3 connected to row wirings 104_1 to 104_3 corresponding to the same cell row are arranged in the same pad row.

[0142] The row pads 302_1 to 302_3 in a plurality of (six in this example) pad rows are arranged in the same pad column. In addition, the arrangement of the row pads 302_1 to 302_3 in a pad row is repeated in every other pad row (in two rows as a cycle). For example, in the (M+1), (M+3), (M+5), (M+7), (M+9) and (M+11) rows, the row pads 302_1 to 302_3 are arranged in the N, (N+2) and (N+4) columns. In addition, in the (M+2), (M+4), (M+6), (M+8), (M+10) and (M+12) rows, the row pads 302_1 to 302_3 are arranged in the (N+1), (N+3) and (N+5) columns.

[0143] As in the fourth example, the column pads 301_1 to 301_6 connected to the column wirings 103_1 to 103_6 corresponding to the same cell column are arranged in the same pad column.

[0144] Column pads 301_1 to 301_6 in a plurality of (six in this example) pad columns are arranged in the same pad row. In addition, the arrangement of column pads 301_1 to 301_6 in a pad column is repeated in every other pad column (with two columns as a cycle). For example, in the (N), (N+2), (N+4), (N+6), (N+8), (N+10), and (N+12) columns, column pads 301_1 to 301_6 are arranged in the (M+1), (M+3), (M+5), (M+7), (M+9), and (M+11) rows. In the (N+1), (N+3), (N+5), (N+7), (N+9) and (N+11)th columns, column pads 301_1 to 301_6 are arranged in the (M+2), (M+4), (M+6), (M+8), (M+10) and (M+12)th rows.

[0145] Also in this example, for the same reason as in the fourth example, fixed pattern noise in a two-line period may be generated. As in the fourth example, the fixed pattern noise can be eliminated by performing a predetermined correction process. In addition, since the fixed pattern noise has a two-line period, the fixed pattern noise has a high spatial frequency, and compared with the fourth example, image quality degradation can be suppressed. Therefore, the correction process is not always necessary.

[0146] Although the above example has shown the case of three row wirings 104_1 to 104_3 and six column wirings 103_1 to 103_6 , this example similarly applies as long as the number of column wirings is one or any even number.

[0147] The above-described embodiments may be modified appropriately without departing from the spirit of the present invention.

[0148] Now, refer to Fig.11 The equipment 9191 including the semiconductor device 930 is described in detail. The semiconductor device 930 may include a semiconductor device 910 having the semiconductor layer 100 as described above and a package 920 accommodating the semiconductor device 910. The package 920 may include a substrate on which the semiconductor device 910 is fixed and a cover formed of, for example, glass and facing the semiconductor device 910. The package 920 may also include a bonding member such as a bonding wire or a bump that connects a terminal provided on the substrate and a terminal provided on the semiconductor device 910.

[0149] The equipment 9191 may include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. For example, the optical device 940 is a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. For example, the control device 950 is a semiconductor device such as an application specific integrated circuit (ASIC).

[0150] The processing device 960 processes a signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a central processing unit (CPU) or an ASIC for configuring an analog front end (AFE) or a digital front end (DFE). The display device 970 is an EL display device or a liquid crystal display device that displays information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0151] The mechanical device 990 includes a movable unit or a propulsion unit such as a motor or an engine. The equipment 9191 displays a signal output from the semiconductor device 930 on the display device 970, or transmits a signal to the outside by using a communication device (not shown) included in the equipment 9191. Therefore, the equipment 9191 may include a storage device 980 or a processing device 960 in addition to a storage circuit or an algorithm circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on a signal output from the semiconductor device 930.

[0152] In addition, the device 9191 is applicable to electronic equipment such as an information terminal (e.g., a smart phone or a wearable terminal) or a camera (e.g., a lens interchangeable camera, a compact camera, a video camera, or a surveillance camera) having an image capture function. The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, or shuttering. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 to prevent blurring.

[0153] Equipment 9191 may also be a transport equipment such as a vehicle, a ship, or an airplane. The mechanical device 990 in the transport equipment may be used as a mobile device. Equipment 9191 used as transport equipment is suitable for transporting semiconductor devices 930, or for assisting and / or automatically driving (operation) by using an image capture function. The processing device 960 for assisting and / or automatically driving (operation) may perform processing for operating the mechanical device 990 used as a mobile device based on information obtained by the semiconductor device 930. Alternatively, equipment 9191 may be medical equipment such as an endoscope, measurement equipment such as a distance measurement sensor, analysis equipment such as an electron microscope, or office equipment such as a copier.

[0154] According to this embodiment, the characteristics of the wiring between the semiconductor component 101 and the semiconductor component 201 can be improved. Therefore, the value of the semiconductor device can be increased. In this article, the increase in value corresponds to at least any one of the addition of functions, improvement of performance, improvement of characteristics, increase in reliability, increase in yield, reduction in environmental load, reduction in cost, reduction in size, and reduction in weight.

[0155] Therefore, by using the semiconductor device according to this embodiment for equipment, the value of the equipment can also be increased. For example, the semiconductor device can be mounted on transportation equipment, and high performance can be obtained when the transportation equipment captures external images or measures external environments. Therefore, for manufacturing and selling transportation equipment, the decision to mount the semiconductor device according to this embodiment on the transportation equipment is conducive to improving the performance of the transportation equipment.

[0156] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor component including a cell array and a plurality of wirings; as well as a second semiconductor component including a plurality of pads connected to the first semiconductor component, The unit array includes a plurality of units arranged in a first direction and a second direction intersecting the first direction, wherein the plurality of pads are arranged on a plane along a first direction and a second direction to overlap with the unit array, The plurality of units include a first unit, a second unit and a third unit. The first unit, the second unit and the third unit are arranged in sequence along the first direction. Wherein, the plurality of wirings include: a first wiring connected to the first unit; a second wiring connected to the first unit and the third unit; and A third wiring, connected to a third unit, Wherein, the plurality of pads include: A first pad connected to a first wiring; a second pad connected to a second wiring; and a third pad connected to a third wiring, and The first pad, the second pad and the third pad are arranged in sequence along the first direction.

2. The semiconductor device according to claim 1, in, The second semiconductor component also includes: control circuit, control unit array; and A processing circuit processes the signal output from the cell array, The first unit is connected to the control circuit through the first pad and the first wiring. wherein the first unit and the third unit are connected to the processing circuit via the second pad and the second wiring, and The third unit is connected to the control circuit through a third pad and a third wiring.

3. The semiconductor device according to claim 2, in, The plurality of units include a fourth unit and a fifth unit, The fourth unit, the first unit and the fifth unit are arranged in sequence along the second direction. wherein the fourth unit and the fifth unit are connected to the first wiring, and The fourth unit and the fifth unit are connected to the control circuit through the first pad and the first wiring.

4. The semiconductor device according to claim 3, in, The plurality of wirings include: a fourth wiring connected to a fourth unit; and A fifth wiring connected to a fifth unit, Wherein, the plurality of pads include: a fourth pad connected to a fourth wiring and arranged to overlap with the fourth cell; and a fifth pad connected to a fifth wiring and arranged to overlap with the fifth unit, and The fourth pad, the first pad and the fifth pad are arranged in sequence along the second direction.

5. The semiconductor device according to claim 4, in, The first unit is connected to the control circuit through a fourth pad and a fourth wiring, and The first unit is connected to the control circuit through a fifth pad and a fifth wiring.

6. The semiconductor device according to claim 4, in, The first wiring, the third wiring, the fourth wiring, and the fifth wiring are arranged in the second direction, and Among them, the second wiring is arranged in the first direction.

7. The semiconductor device according to claim 2, in, The plurality of units also includes a sixth unit, The first unit, the sixth unit, the second unit and the third unit are arranged in sequence along the first direction. The plurality of wirings further include a sixth wiring connected to a sixth unit. wherein the plurality of pads further includes a sixth pad connected to a sixth wiring and arranged to overlap with the sixth unit, and The first pad, the sixth pad, the second pad and the third pad are arranged in sequence along the first direction.

8. The semiconductor device according to claim 7, in, The sixth unit is connected to the processing circuit through a sixth pad and a sixth wiring.

9. The semiconductor device according to claim 7, in, The first wiring and the third wiring are arranged in the second direction, and Among them, the second wiring and the sixth wiring are arranged in the first direction.

10. The semiconductor device according to claim 2, in, The second unit is connected to the second wiring, and The second unit is connected to the processing circuit through the second pad and the second wiring.

11. The semiconductor device according to claim 2, in, The control circuit transmits a first signal to the first unit through the first pad and the first wiring, and transmits a third signal to the third unit through the third pad and the third wiring, The first signal and the third signal are control signals of the same type.

12. The semiconductor device according to claim 2, in, The control circuit transmits a first signal to the first unit through the first pad and the first wiring, and transmits a third signal to the third unit through the third pad and the third wiring, The first signal and the third signal are control signals of different types.

13. The semiconductor device according to claim 11, in, The first signal and the third signal are transmitted at different timings from each other.

14. The semiconductor device according to claim 1, in, The first pad is arranged to overlap with the first unit, wherein the second pad is arranged to overlap with the second unit, The third pad is arranged to overlap with the third unit.

15. The semiconductor device according to claim 1, in, The first wiring crosses the second wiring, and The third wiring crosses the second wiring.

16. The semiconductor device according to claim 1, in, At least one of the plurality of cells does not have any of the plurality of pads at a position overlapping with the at least one cell.

17. The semiconductor device according to claim 1, in, Each of the plurality of cells includes a photoelectric conversion element.

18. An apparatus, characterized in that: include: The semiconductor device according to claim 1; as well as At least one of the following: Optical devices, corresponding to semiconductor devices; A controller for controlling a semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device that displays information obtained from the semiconductor device; a storage device storing information obtained from the semiconductor device; as well as A mechanical device that operates based on information obtained from a semiconductor device.

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